[qemu.git] / include / hw / i386 / pc.h

#ifndef HW_PC_H
#define HW_PC_H

#include "qemu-common.h"
#include "exec/memory.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"

#include "qemu/range.h"
#include "qemu/bitmap.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"

/* PC-style peripherals (also used by other machines).  */

typedef struct PcPciInfo {
    Range w32;
    Range w64;
} PcPciInfo;

#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
#define ACPI_PM_PROP_S4_VAL "s4_val"
#define ACPI_PM_PROP_SCI_INT "sci_int"
#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"

struct PcGuestInfo {
    bool has_pci_info;
    bool isapc_ram_fw;
    hwaddr ram_size;
    unsigned apic_id_limit;
    bool apic_xrupt_override;
    uint64_t numa_nodes;
    uint64_t *node_mem;
    uint64_t *node_cpu;
    FWCfgState *fw_cfg;
    bool has_acpi_build;
};

/* parallel.c */
static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
{
    DeviceState *dev;
    ISADevice *isadev;

    isadev = isa_try_create(bus, "isa-parallel");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "index", index);
    qdev_prop_set_chr(dev, "chardev", chr);
    if (qdev_init(dev) < 0) {
        return false;
    }
    return true;
}

bool parallel_mm_init(MemoryRegion *address_space,
                      hwaddr base, int it_shift, qemu_irq irq,
                      CharDriverState *chr);

/* i8259.c */

extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon, const QDict *qdict);
void irq_info(Monitor *mon, const QDict *qdict);

/* Global System Interrupts */

#define GSI_NUM_PINS IOAPIC_NUM_PINS

typedef struct GSIState {
    qemu_irq i8259_irq[ISA_NUM_IRQS];
    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;

void gsi_handler(void *opaque, int n, int level);

/* vmport.c */
typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);

static inline void vmport_init(ISABus *bus)
{
    isa_create_simple(bus, "vmport");
}

void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);

/* pc.c */
extern int fd_bootchk;

void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);

void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);

PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
                                ram_addr_t above_4g_mem_size);

#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)

static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
{
    if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
        return 1ULL << 62;
    } else {
        return pci_hole64_size;
    }
}

void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
                        uint64_t pci_hole64_size);

FWCfgState *pc_memory_init(MemoryRegion *system_memory,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           ram_addr_t below_4g_mem_size,
                           ram_addr_t above_4g_mem_size,
                           MemoryRegion *rom_memory,
                           MemoryRegion **ram_memory,
                           PcGuestInfo *guest_info);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
                          ISADevice **rtc_state,
                          ISADevice **floppy,
                          bool no_vmport);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                  const char *boot_device,
                  ISADevice *floppy, BusState *ide0, BusState *ide1,
                  ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);

typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);

void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);

/* acpi_piix.c */

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int kvm_enabled, FWCfgState *fw_cfg);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);

/* hpet.c */
extern int no_hpet;

/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
                    ISABus **isa_bus, qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size,
                    hwaddr pci_hole_start,
                    hwaddr pci_hole_size,
                    ram_addr_t above_4g_mem_size,
                    MemoryRegion *pci_memory,
                    MemoryRegion *ram_memory);

PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);

/* vga.c */
enum vga_retrace_method {
    VGA_RETRACE_DUMB,
    VGA_RETRACE_PRECISE
};

extern enum vga_retrace_method vga_retrace_method;

int isa_vga_mm_init(hwaddr vram_base,
                    hwaddr ctrl_base, int it_shift,
                    MemoryRegion *address_space);

/* ne2000.c */
static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
{
    DeviceState *dev;
    ISADevice *isadev;

    qemu_check_nic_model(nd, "ne2k_isa");

    isadev = isa_try_create(bus, "ne2k_isa");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "iobase", base);
    qdev_prop_set_uint32(dev, "irq",    irq);
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);
    return true;
}

/* pc_sysfw.c */
void pc_system_firmware_init(MemoryRegion *rom_memory,
                             bool isapc_ram_fw);

/* pvpanic.c */
uint16_t pvpanic_port(void);

/* e820 types */
#define E820_RAM        1
#define E820_RESERVED   2
#define E820_ACPI       3
#define E820_NVS        4
#define E820_UNUSABLE   5

int e820_add_entry(uint64_t, uint64_t, uint32_t);

#define PC_COMPAT_1_6 \
        {\
            .driver   = "e1000",\
            .property = "mitigation",\
            .value    = "off",\
        },{\
            .driver   = "qemu64-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "qemu32-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(3),\
        },{\
            .driver   = "i440FX-pcihost",\
            .property = "short_root_bus",\
            .value    = stringify(1),\
        },{\
            .driver   = "q35-pcihost",\
            .property = "short_root_bus",\
            .value    = stringify(1),\
        }

#define PC_COMPAT_1_5 \
        PC_COMPAT_1_6, \
        {\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "any_layout",\
            .value    = "off",\
        },{\
            .driver = TYPE_X86_CPU,\
            .property = "pmu",\
            .value = "on",\
        },{\
            .driver   = "i440FX-pcihost",\
            .property = "short_root_bus",\
            .value    = stringify(0),\
        },{\
            .driver   = "q35-pcihost",\
            .property = "short_root_bus",\
            .value    = stringify(0),\
        }

#define PC_COMPAT_1_4 \
        PC_COMPAT_1_5, \
        {\
            .driver   = "scsi-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-disk",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-drive",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
        },{\
            .driver   = "virtio-blk-pci",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "virtio-serial-pci",\
            .property = "vectors",\
            /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
            .value    = stringify(0xFFFFFFFF),\
        },{ \
            .driver   = "virtio-net-pci", \
            .property = "ctrl_guest_offloads", \
            .value    = "off", \
        },{\
            .driver   = "e1000",\
            .property = "romfile",\
            .value    = "pxe-e1000.rom",\
        },{\
            .driver   = "ne2k_pci",\
            .property = "romfile",\
            .value    = "pxe-ne2k_pci.rom",\
        },{\
            .driver   = "pcnet",\
            .property = "romfile",\
            .value    = "pxe-pcnet.rom",\
        },{\
            .driver   = "rtl8139",\
            .property = "romfile",\
            .value    = "pxe-rtl8139.rom",\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "romfile",\
            .value    = "pxe-virtio.rom",\
        },{\
            .driver   = "486-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(0),\
        }

#define PC_COMMON_MACHINE_OPTIONS \
    .default_boot_order = "cad"

#define PC_DEFAULT_MACHINE_OPTIONS \
    PC_COMMON_MACHINE_OPTIONS, \
    .hot_add_cpu = pc_hot_add_cpu, \
    .max_cpus = 255

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
87ecb68b PB	2	#define HW_PC_H
376253ec AL	3
376253ec AL	4	#include "qemu-common.h"
022c62cb	5	#include "exec/memory.h"
0d09e41a PB	6	#include "hw/isa/isa.h"
0d09e41a PB	7	#include "hw/block/fdc.h"
1422e32d	8	#include "net/net.h"
0d09e41a	9	#include "hw/i386/ioapic.h"
376253ec	10
3459a625	11	#include "qemu/range.h"
b20c9bd5 MT	12	#include "qemu/bitmap.h"
	13	#include "sysemu/sysemu.h"
	14	#include "hw/pci/pci.h"
3459a625	15
87ecb68b PB	16	/* PC-style peripherals (also used by other machines). */
87ecb68b PB	17
3459a625 MT	18	typedef struct PcPciInfo {
	19	Range w32;
	20	Range w64;
	21	} PcPciInfo;
	22
f854ecc7 MT	23	#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
	24	#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
	25	#define ACPI_PM_PROP_S4_VAL "s4_val"
	26	#define ACPI_PM_PROP_SCI_INT "sci_int"
	27	#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
	28	#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
	29	#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
	30	#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
	31	#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
	32
3459a625	33	struct PcGuestInfo {
f8c457b8	34	bool has_pci_info;
6dd2a5c9	35	bool isapc_ram_fw;
b20c9bd5 MT	36	hwaddr ram_size;
	37	unsigned apic_id_limit;
	38	bool apic_xrupt_override;
	39	uint64_t numa_nodes;
	40	uint64_t *node_mem;
	41	uint64_t *node_cpu;
3459a625	42	FWCfgState *fw_cfg;
72c194f7	43	bool has_acpi_build;
3459a625 MT	44	};
3459a625 MT	45
87ecb68b	46	/* parallel.c */
48a18b3c	47	static inline bool parallel_init(ISABus bus, int index, CharDriverState chr)
defdb20e	48	{
4a17cc4f AF	49	DeviceState *dev;
4a17cc4f AF	50	ISADevice *isadev;
defdb20e	51
4a17cc4f AF	52	isadev = isa_try_create(bus, "isa-parallel");
4a17cc4f AF	53	if (!isadev) {
73531538 BS	54	return false;
73531538 BS	55	}
4a17cc4f AF	56	dev = DEVICE(isadev);
	57	qdev_prop_set_uint32(dev, "index", index);
	58	qdev_prop_set_chr(dev, "chardev", chr);
	59	if (qdev_init(dev) < 0) {
defdb20e BS	60	return false;
	61	}
	62	return true;
	63	}
	64
63858cd9	65	bool parallel_mm_init(MemoryRegion *address_space,
a8170e5e	66	hwaddr base, int it_shift, qemu_irq irq,
defdb20e	67	CharDriverState *chr);
87ecb68b PB	68
	69	/* i8259.c */
	70
9aa78c42	71	extern DeviceState *isa_pic;
48a18b3c	72	qemu_irq i8259_init(ISABus bus, qemu_irq parent_irq);
10b61882	73	qemu_irq kvm_i8259_init(ISABus bus);
9aa78c42 JK	74	int pic_read_irq(DeviceState *d);
9aa78c42 JK	75	int pic_get_output(DeviceState *d);
84f2d0ea WX	76	void pic_info(Monitor mon, const QDict qdict);
84f2d0ea WX	77	void irq_info(Monitor mon, const QDict qdict);
87ecb68b	78
b881fbe9	79	/* Global System Interrupts */
96051119	80
b881fbe9	81	#define GSI_NUM_PINS IOAPIC_NUM_PINS
845773ab	82
b881fbe9	83	typedef struct GSIState {
43a0db35	84	qemu_irq i8259_irq[ISA_NUM_IRQS];
b881fbe9 JK	85	qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
	86	} GSIState;
	87
	88	void gsi_handler(void *opaque, int n, int level);
845773ab	89
87ecb68b	90	/* vmport.c */
d67f679d JK	91	typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
d67f679d JK	92
48a18b3c	93	static inline void vmport_init(ISABus *bus)
6872ef61	94	{
48a18b3c	95	isa_create_simple(bus, "vmport");
6872ef61	96	}
d67f679d JK	97
d67f679d JK	98	void vmport_register(unsigned char command, VMPortReadFunc func, void opaque);
86d86414 BS	99	void vmmouse_get_data(uint32_t *data);
86d86414 BS	100	void vmmouse_set_data(const uint32_t *data);
87ecb68b	101
87ecb68b PB	102	/* pckbd.c */
	103
	104	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	105	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	106	MemoryRegion *region, ram_addr_t size,
a8170e5e	107	hwaddr mask);
956a3e6b BS	108	void i8042_isa_mouse_fake_event(void *opaque);
956a3e6b BS	109	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out);
87ecb68b	110
87ecb68b PB	111	/* pc.c */
	112	extern int fd_bootchk;
	113
8e78eb28	114	void pc_register_ferr_irq(qemu_irq irq);
845773ab IY	115	void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
845773ab IY	116
62fc403f	117	void pc_cpus_init(const char cpu_model, DeviceState icc_bridge);
c649983b	118	void pc_hot_add_cpu(const int64_t id, Error **errp);
f7e4dd6c	119	void pc_acpi_init(const char *default_dsdt);
3459a625 MT	120
	121	PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
	122	ram_addr_t above_4g_mem_size);
	123
39848901 IM	124	#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
	125	#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
	126	#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
	127	#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
	128	#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
1466cef3 MT	129	#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
	130
	131	static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
	132	{
	133	if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
	134	return 1ULL << 62;
	135	} else {
	136	return pci_hole64_size;
	137	}
	138	}
39848901 IM	139
	140	void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
	141	uint64_t pci_hole64_size);
	142
a88b362c LE	143	FWCfgState pc_memory_init(MemoryRegion system_memory,
	144	const char *kernel_filename,
	145	const char *kernel_cmdline,
	146	const char *initrd_filename,
	147	ram_addr_t below_4g_mem_size,
	148	ram_addr_t above_4g_mem_size,
	149	MemoryRegion *rom_memory,
3459a625 MT	150	MemoryRegion **ram_memory,
3459a625 MT	151	PcGuestInfo *guest_info);
845773ab	152	qemu_irq *pc_allocate_cpu_irq(void);
48a18b3c HP	153	DeviceState pc_vga_init(ISABus isa_bus, PCIBus *pci_bus);
48a18b3c HP	154	void pc_basic_device_init(ISABus isa_bus, qemu_irq gsi,
1611977c	155	ISADevice **rtc_state,
34d4260e	156	ISADevice **floppy,
1611977c	157	bool no_vmport);
48a18b3c	158	void pc_init_ne2k_isa(ISABus bus, NICInfo nd);
845773ab	159	void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
c0897e0c	160	const char *boot_device,
34d4260e	161	ISADevice floppy, BusState ide0, BusState *ide1,
63ffb564	162	ISADevice *s);
9011a1a7	163	void pc_nic_init(ISABus isa_bus, PCIBus pci_bus);
845773ab	164	void pc_pci_device_init(PCIBus *pci_bus);
8e78eb28	165
f885f1ea IY	166	typedef void (cpu_set_smm_t)(int smm, void arg);
	167	void cpu_smm_register(cpu_set_smm_t callback, void *arg);
	168
a39e3564 JB	169	void ioapic_init_gsi(GSIState gsi_state, const char parent_name);
a39e3564 JB	170
9d5e77a2	171	/* acpi_piix.c */
53b67b30	172
cf7a2fe2	173	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
da98c8eb	174	qemu_irq sci_irq, qemu_irq smi_irq,
a88b362c	175	int kvm_enabled, FWCfgState *fw_cfg);
87ecb68b	176	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
87ecb68b	177
16b29ae1 AL	178	/* hpet.c */
	179	extern int no_hpet;
	180
87ecb68b	181	/* piix_pci.c */
0a3bacf3 JQ	182	struct PCII440FXState;
	183	typedef struct PCII440FXState PCII440FXState;
	184
1e39101c	185	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix_devfn,
60573079	186	ISABus *isa_bus, qemu_irq pic,
aee97b84 AK	187	MemoryRegion *address_space_mem,
aee97b84 AK	188	MemoryRegion *address_space_io,
ae0a5466	189	ram_addr_t ram_size,
a8170e5e AK	190	hwaddr pci_hole_start,
a8170e5e AK	191	hwaddr pci_hole_size,
39848901	192	ram_addr_t above_4g_mem_size,
ae0a5466 AK	193	MemoryRegion *pci_memory,
ae0a5466 AK	194	MemoryRegion *ram_memory);
87ecb68b	195
277e9340	196	PCIBus *find_i440fx(void);
823e675a	197	/* piix4.c */
b1d8e52e	198	extern PCIDevice *piix4_dev;
142e9787	199	int piix4_init(PCIBus bus, ISABus *isa_bus, int devfn);
87ecb68b PB	200
87ecb68b PB	201	/* vga.c */
cb5a7aa8	202	enum vga_retrace_method {
	203	VGA_RETRACE_DUMB,
	204	VGA_RETRACE_PRECISE
	205	};
	206
	207	extern enum vga_retrace_method vga_retrace_method;
87ecb68b	208
a8170e5e AK	209	int isa_vga_mm_init(hwaddr vram_base,
a8170e5e AK	210	hwaddr ctrl_base, int it_shift,
be20f9e9	211	MemoryRegion *address_space);
87ecb68b	212
87ecb68b	213	/* ne2000.c */
48a18b3c	214	static inline bool isa_ne2000_init(ISABus bus, int base, int irq, NICInfo nd)
60a14ad3	215	{
4a17cc4f AF	216	DeviceState *dev;
4a17cc4f AF	217	ISADevice *isadev;
87ecb68b	218
60a14ad3 BS	219	qemu_check_nic_model(nd, "ne2k_isa");
60a14ad3 BS	220
4a17cc4f AF	221	isadev = isa_try_create(bus, "ne2k_isa");
4a17cc4f AF	222	if (!isadev) {
cd1b8a8b BS	223	return false;
cd1b8a8b BS	224	}
4a17cc4f AF	225	dev = DEVICE(isadev);
	226	qdev_prop_set_uint32(dev, "iobase", base);
	227	qdev_prop_set_uint32(dev, "irq", irq);
	228	qdev_set_nic_properties(dev, nd);
	229	qdev_init_nofail(dev);
cd1b8a8b	230	return true;
60a14ad3	231	}
87ecb68b	232
cbc5b5f3	233	/* pc_sysfw.c */
6dd2a5c9 PB	234	void pc_system_firmware_init(MemoryRegion *rom_memory,
6dd2a5c9 PB	235	bool isapc_ram_fw);
cbc5b5f3	236
3ab135f3	237	/* pvpanic.c */
309cd62d	238	uint16_t pvpanic_port(void);
3ab135f3	239
4c5b10b7 JS	240	/* e820 types */
	241	#define E820_RAM 1
	242	#define E820_RESERVED 2
	243	#define E820_ACPI 3
	244	#define E820_NVS 4
	245	#define E820_UNUSABLE 5
	246
	247	int e820_add_entry(uint64_t, uint64_t, uint32_t);
	248
e9845f09 VM	249	#define PC_COMPAT_1_6 \
	250	{\
	251	.driver = "e1000",\
	252	.property = "mitigation",\
	253	.value = "off",\
f8e6a11a EH	254	},{\
	255	.driver = "qemu64-" TYPE_X86_CPU,\
	256	.property = "model",\
	257	.value = stringify(2),\
	258	},{\
	259	.driver = "qemu32-" TYPE_X86_CPU,\
	260	.property = "model",\
	261	.value = stringify(3),\
04c7d8b8 CR	262	},{\
	263	.driver = "i440FX-pcihost",\
	264	.property = "short_root_bus",\
	265	.value = stringify(1),\
	266	},{\
	267	.driver = "q35-pcihost",\
	268	.property = "short_root_bus",\
	269	.value = stringify(1),\
e9845f09 VM	270	}
e9845f09 VM	271
ffce9ebb	272	#define PC_COMPAT_1_5 \
e9845f09	273	PC_COMPAT_1_6, \
ffce9ebb EH	274	{\
	275	.driver = "Conroe-" TYPE_X86_CPU,\
	276	.property = "model",\
	277	.value = stringify(2),\
6b11322e EH	278	},{\
	279	.driver = "Conroe-" TYPE_X86_CPU,\
	280	.property = "level",\
	281	.value = stringify(2),\
ffce9ebb EH	282	},{\
	283	.driver = "Penryn-" TYPE_X86_CPU,\
	284	.property = "model",\
	285	.value = stringify(2),\
6b11322e EH	286	},{\
	287	.driver = "Penryn-" TYPE_X86_CPU,\
	288	.property = "level",\
	289	.value = stringify(2),\
ffce9ebb EH	290	},{\
	291	.driver = "Nehalem-" TYPE_X86_CPU,\
	292	.property = "model",\
	293	.value = stringify(2),\
6b11322e EH	294	},{\
	295	.driver = "Nehalem-" TYPE_X86_CPU,\
	296	.property = "level",\
	297	.value = stringify(2),\
488f069b MT	298	},{\
	299	.driver = "virtio-net-pci",\
	300	.property = "any_layout",\
	301	.value = "off",\
9337e3b6 EH	302	},{\
	303	.driver = TYPE_X86_CPU,\
	304	.property = "pmu",\
	305	.value = "on",\
04c7d8b8 CR	306	},{\
	307	.driver = "i440FX-pcihost",\
	308	.property = "short_root_bus",\
	309	.value = stringify(0),\
	310	},{\
	311	.driver = "q35-pcihost",\
	312	.property = "short_root_bus",\
	313	.value = stringify(0),\
ffce9ebb EH	314	}
ffce9ebb EH	315
bf3caa3d	316	#define PC_COMPAT_1_4 \
ffce9ebb	317	PC_COMPAT_1_5, \
bf3caa3d PB	318	{\
	319	.driver = "scsi-hd",\
	320	.property = "discard_granularity",\
	321	.value = stringify(0),\
	322	},{\
	323	.driver = "scsi-cd",\
	324	.property = "discard_granularity",\
	325	.value = stringify(0),\
	326	},{\
	327	.driver = "scsi-disk",\
	328	.property = "discard_granularity",\
	329	.value = stringify(0),\
	330	},{\
	331	.driver = "ide-hd",\
	332	.property = "discard_granularity",\
	333	.value = stringify(0),\
	334	},{\
	335	.driver = "ide-cd",\
	336	.property = "discard_granularity",\
	337	.value = stringify(0),\
	338	},{\
	339	.driver = "ide-drive",\
	340	.property = "discard_granularity",\
	341	.value = stringify(0),\
c45e5b5b	342	},{\
bf3caa3d PB	343	.driver = "virtio-blk-pci",\
	344	.property = "discard_granularity",\
	345	.value = stringify(0),\
554f1997 GH	346	},{\
	347	.driver = "virtio-serial-pci",\
	348	.property = "vectors",\
	349	/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
	350	.value = stringify(0xFFFFFFFF),\
644c9858 DF	351	},{ \
	352	.driver = "virtio-net-pci", \
	353	.property = "ctrl_guest_offloads", \
	354	.value = "off", \
c45e5b5b GH	355	},{\
	356	.driver = "e1000",\
	357	.property = "romfile",\
	358	.value = "pxe-e1000.rom",\
	359	},{\
	360	.driver = "ne2k_pci",\
	361	.property = "romfile",\
	362	.value = "pxe-ne2k_pci.rom",\
	363	},{\
	364	.driver = "pcnet",\
	365	.property = "romfile",\
	366	.value = "pxe-pcnet.rom",\
	367	},{\
	368	.driver = "rtl8139",\
	369	.property = "romfile",\
	370	.value = "pxe-rtl8139.rom",\
	371	},{\
	372	.driver = "virtio-net-pci",\
	373	.property = "romfile",\
	374	.value = "pxe-virtio.rom",\
b2a856d9 AF	375	},{\
	376	.driver = "486-" TYPE_X86_CPU,\
	377	.property = "model",\
	378	.value = stringify(0),\
c45e5b5b	379	}
bf3caa3d	380
a0dba644 MT	381	#define PC_COMMON_MACHINE_OPTIONS \
	382	.default_boot_order = "cad"
	383
	384	#define PC_DEFAULT_MACHINE_OPTIONS \
	385	PC_COMMON_MACHINE_OPTIONS, \
	386	.hot_add_cpu = pc_hot_add_cpu, \
	387	.max_cpus = 255
	388
87ecb68b	389	#endif