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Commit | Line | Data |
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121d0712 MA |
1 | #ifndef ALLWINNER_A10_PIC_H |
2 | #define ALLWINNER_A10_PIC_H | |
c3931ee8 | 3 | |
ec150c7e | 4 | #include "hw/sysbus.h" |
db1015e9 | 5 | #include "qom/object.h" |
ec150c7e | 6 | |
c3931ee8 | 7 | #define TYPE_AW_A10_PIC "allwinner-a10-pic" |
8063396b | 8 | OBJECT_DECLARE_SIMPLE_TYPE(AwA10PICState, AW_A10_PIC) |
c3931ee8 LG |
9 | |
10 | #define AW_A10_PIC_VECTOR 0 | |
11 | #define AW_A10_PIC_BASE_ADDR 4 | |
12 | #define AW_A10_PIC_PROTECT 8 | |
13 | #define AW_A10_PIC_NMI 0xc | |
14 | #define AW_A10_PIC_IRQ_PENDING 0x10 | |
15 | #define AW_A10_PIC_FIQ_PENDING 0x20 | |
16 | #define AW_A10_PIC_SELECT 0x30 | |
17 | #define AW_A10_PIC_ENABLE 0x40 | |
18 | #define AW_A10_PIC_MASK 0x50 | |
19 | ||
20 | #define AW_A10_PIC_INT_NR 95 | |
21 | #define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32) | |
22 | ||
db1015e9 | 23 | struct AwA10PICState { |
c3931ee8 LG |
24 | /*< private >*/ |
25 | SysBusDevice parent_obj; | |
26 | /*< public >*/ | |
27 | MemoryRegion iomem; | |
28 | qemu_irq parent_fiq; | |
29 | qemu_irq parent_irq; | |
30 | ||
31 | uint32_t vector; | |
32 | uint32_t base_addr; | |
33 | uint32_t protect; | |
34 | uint32_t nmi; | |
35 | uint32_t irq_pending[AW_A10_PIC_REG_NUM]; | |
36 | uint32_t fiq_pending[AW_A10_PIC_REG_NUM]; | |
37 | uint32_t select[AW_A10_PIC_REG_NUM]; | |
38 | uint32_t enable[AW_A10_PIC_REG_NUM]; | |
39 | uint32_t mask[AW_A10_PIC_REG_NUM]; | |
40 | /*priority setting here*/ | |
db1015e9 | 41 | }; |
c3931ee8 LG |
42 | |
43 | #endif |