[qemu.git] / include / hw / ppc / spapr.h

#if !defined(__HW_SPAPR_H__)
#define __HW_SPAPR_H__

#include "sysemu/dma.h"
#include "hw/ppc/xics.h"

struct VIOsPAPRBus;
struct sPAPRPHBState;
struct sPAPRNVRAM;
struct icp_state;

typedef struct sPAPREnvironment {
    struct VIOsPAPRBus *vio_bus;
    QLIST_HEAD(, sPAPRPHBState) phbs;
    struct sPAPRNVRAM *nvram;
    struct icp_state *icp;

    hwaddr ram_limit;
    void *htab;
    long htab_shift;
    hwaddr rma_size;
    int vrma_adjust;
    hwaddr fdt_addr, rtas_addr;
    long rtas_size;
    void *fdt_skel;
    target_ulong entry_point;
    int next_irq;
    int rtc_offset;
    char *cpu_model;
    bool has_graphics;

    uint32_t epow_irq;
    Notifier epow_notifier;
} sPAPREnvironment;

#define H_SUCCESS         0
#define H_BUSY            1        /* Hardware busy -- retry later */
#define H_CLOSED          2        /* Resource closed */
#define H_NOT_AVAILABLE   3
#define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
#define H_PARTIAL         5
#define H_IN_PROGRESS     14       /* Kind of like busy */
#define H_PAGE_REGISTERED 15
#define H_PARTIAL_STORE   16
#define H_PENDING         17       /* returned from H_POLL_PENDING */
#define H_CONTINUE        18       /* Returned from H_Join on success */
#define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
#define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
                                                 is a good time to retry */
#define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
                                                 is a good time to retry */
#define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
                                                 is a good time to retry */
#define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
                                                 is a good time to retry */
#define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
                                                 is a good time to retry */
#define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
                                                 is a good time to retry */
#define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
#define H_HARDWARE        -1       /* Hardware error */
#define H_FUNCTION        -2       /* Function not supported */
#define H_PRIVILEGE       -3       /* Caller not privileged */
#define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
#define H_BAD_MODE        -5       /* Illegal msr value */
#define H_PTEG_FULL       -6       /* PTEG is full */
#define H_NOT_FOUND       -7       /* PTE was not found" */
#define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
#define H_NO_MEM          -9
#define H_AUTHORITY       -10
#define H_PERMISSION      -11
#define H_DROPPED         -12
#define H_SOURCE_PARM     -13
#define H_DEST_PARM       -14
#define H_REMOTE_PARM     -15
#define H_RESOURCE        -16
#define H_ADAPTER_PARM    -17
#define H_RH_PARM         -18
#define H_RCQ_PARM        -19
#define H_SCQ_PARM        -20
#define H_EQ_PARM         -21
#define H_RT_PARM         -22
#define H_ST_PARM         -23
#define H_SIGT_PARM       -24
#define H_TOKEN_PARM      -25
#define H_MLENGTH_PARM    -27
#define H_MEM_PARM        -28
#define H_MEM_ACCESS_PARM -29
#define H_ATTR_PARM       -30
#define H_PORT_PARM       -31
#define H_MCG_PARM        -32
#define H_VL_PARM         -33
#define H_TSIZE_PARM      -34
#define H_TRACE_PARM      -35

#define H_MASK_PARM       -37
#define H_MCG_FULL        -38
#define H_ALIAS_EXIST     -39
#define H_P_COUNTER       -40
#define H_TABLE_FULL      -41
#define H_ALT_TABLE       -42
#define H_MR_CONDITION    -43
#define H_NOT_ENOUGH_RESOURCES -44
#define H_R_STATE         -45
#define H_RESCINDEND      -46
#define H_MULTI_THREADS_ACTIVE -9005


/* Long Busy is a condition that can be returned by the firmware
 * when a call cannot be completed now, but the identical call
 * should be retried later.  This prevents calls blocking in the
 * firmware for long periods of time.  Annoyingly the firmware can return
 * a range of return codes, hinting at how long we should wait before
 * retrying.  If you don't care for the hint, the macro below is a good
 * way to check for the long_busy return codes
 */
#define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
                            && (x <= H_LONG_BUSY_END_RANGE))

/* Flags */
#define H_LARGE_PAGE      (1ULL<<(63-16))
#define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
#define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
#define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
#define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
#define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
#define H_ANDCOND         (1ULL<<(63-33))
#define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
#define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
#define H_COPY_PAGE       (1ULL<<(63-49))
#define H_N               (1ULL<<(63-61))
#define H_PP1             (1ULL<<(63-62))
#define H_PP2             (1ULL<<(63-63))

/* VASI States */
#define H_VASI_INVALID    0
#define H_VASI_ENABLED    1
#define H_VASI_ABORTED    2
#define H_VASI_SUSPENDING 3
#define H_VASI_SUSPENDED  4
#define H_VASI_RESUMED    5
#define H_VASI_COMPLETED  6

/* DABRX flags */
#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
#define H_DABRX_KERNEL     (1ULL<<(63-62))
#define H_DABRX_USER       (1ULL<<(63-63))

/* Each control block has to be on a 4K boundary */
#define H_CB_ALIGNMENT     4096

/* pSeries hypervisor opcodes */
#define H_REMOVE                0x04
#define H_ENTER                 0x08
#define H_READ                  0x0c
#define H_CLEAR_MOD             0x10
#define H_CLEAR_REF             0x14
#define H_PROTECT               0x18
#define H_GET_TCE               0x1c
#define H_PUT_TCE               0x20
#define H_SET_SPRG0             0x24
#define H_SET_DABR              0x28
#define H_PAGE_INIT             0x2c
#define H_SET_ASR               0x30
#define H_ASR_ON                0x34
#define H_ASR_OFF               0x38
#define H_LOGICAL_CI_LOAD       0x3c
#define H_LOGICAL_CI_STORE      0x40
#define H_LOGICAL_CACHE_LOAD    0x44
#define H_LOGICAL_CACHE_STORE   0x48
#define H_LOGICAL_ICBI          0x4c
#define H_LOGICAL_DCBF          0x50
#define H_GET_TERM_CHAR         0x54
#define H_PUT_TERM_CHAR         0x58
#define H_REAL_TO_LOGICAL       0x5c
#define H_HYPERVISOR_DATA       0x60
#define H_EOI                   0x64
#define H_CPPR                  0x68
#define H_IPI                   0x6c
#define H_IPOLL                 0x70
#define H_XIRR                  0x74
#define H_PERFMON               0x7c
#define H_MIGRATE_DMA           0x78
#define H_REGISTER_VPA          0xDC
#define H_CEDE                  0xE0
#define H_CONFER                0xE4
#define H_PROD                  0xE8
#define H_GET_PPP               0xEC
#define H_SET_PPP               0xF0
#define H_PURR                  0xF4
#define H_PIC                   0xF8
#define H_REG_CRQ               0xFC
#define H_FREE_CRQ              0x100
#define H_VIO_SIGNAL            0x104
#define H_SEND_CRQ              0x108
#define H_COPY_RDMA             0x110
#define H_REGISTER_LOGICAL_LAN  0x114
#define H_FREE_LOGICAL_LAN      0x118
#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
#define H_SEND_LOGICAL_LAN      0x120
#define H_BULK_REMOVE           0x124
#define H_MULTICAST_CTRL        0x130
#define H_SET_XDABR             0x134
#define H_STUFF_TCE             0x138
#define H_PUT_TCE_INDIRECT      0x13C
#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
#define H_VTERM_PARTNER_INFO    0x150
#define H_REGISTER_VTERM        0x154
#define H_FREE_VTERM            0x158
#define H_RESET_EVENTS          0x15C
#define H_ALLOC_RESOURCE        0x160
#define H_FREE_RESOURCE         0x164
#define H_MODIFY_QP             0x168
#define H_QUERY_QP              0x16C
#define H_REREGISTER_PMR        0x170
#define H_REGISTER_SMR          0x174
#define H_QUERY_MR              0x178
#define H_QUERY_MW              0x17C
#define H_QUERY_HCA             0x180
#define H_QUERY_PORT            0x184
#define H_MODIFY_PORT           0x188
#define H_DEFINE_AQP1           0x18C
#define H_GET_TRACE_BUFFER      0x190
#define H_DEFINE_AQP0           0x194
#define H_RESIZE_MR             0x198
#define H_ATTACH_MCQP           0x19C
#define H_DETACH_MCQP           0x1A0
#define H_CREATE_RPT            0x1A4
#define H_REMOVE_RPT            0x1A8
#define H_REGISTER_RPAGES       0x1AC
#define H_DISABLE_AND_GETC      0x1B0
#define H_ERROR_DATA            0x1B4
#define H_GET_HCA_INFO          0x1B8
#define H_GET_PERF_COUNT        0x1BC
#define H_MANAGE_TRACE          0x1C0
#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
#define H_QUERY_INT_STATE       0x1E4
#define H_POLL_PENDING          0x1D8
#define H_ILLAN_ATTRIBUTES      0x244
#define H_MODIFY_HEA_QP         0x250
#define H_QUERY_HEA_QP          0x254
#define H_QUERY_HEA             0x258
#define H_QUERY_HEA_PORT        0x25C
#define H_MODIFY_HEA_PORT       0x260
#define H_REG_BCMC              0x264
#define H_DEREG_BCMC            0x268
#define H_REGISTER_HEA_RPAGES   0x26C
#define H_DISABLE_AND_GET_HEA   0x270
#define H_GET_HEA_INFO          0x274
#define H_ALLOC_HEA_RESOURCE    0x278
#define H_ADD_CONN              0x284
#define H_DEL_CONN              0x288
#define H_JOIN                  0x298
#define H_VASI_STATE            0x2A4
#define H_ENABLE_CRQ            0x2B0
#define H_GET_EM_PARMS          0x2B8
#define H_SET_MPP               0x2D0
#define H_GET_MPP               0x2D4
#define MAX_HCALL_OPCODE        H_GET_MPP

/* The hcalls above are standardized in PAPR and implemented by pHyp
 * as well.
 *
 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 * So far we just need one for H_RTAS, but in future we'll need more
 * for extensions like virtio.  We put those into the 0xf000-0xfffc
 * range which is reserved by PAPR for "platform-specific" hcalls.
 */
#define KVMPPC_HCALL_BASE       0xf000
#define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
#define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
#define KVMPPC_HCALL_MAX        KVMPPC_H_LOGICAL_MEMOP

extern sPAPREnvironment *spapr;

/*#define DEBUG_SPAPR_HCALLS*/

#ifdef DEBUG_SPAPR_HCALLS
#define hcall_dprintf(fmt, ...) \
    do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0)
#else
#define hcall_dprintf(fmt, ...) \
    do { } while (0)
#endif

typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                                       target_ulong opcode,
                                       target_ulong *args);

void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
                             target_ulong *args);

int spapr_allocate_irq(int hint, bool lsi);
int spapr_allocate_irq_block(int num, bool lsi);

static inline int spapr_allocate_msi(int hint)
{
    return spapr_allocate_irq(hint, false);
}

static inline int spapr_allocate_lsi(int hint)
{
    return spapr_allocate_irq(hint, true);
}

static inline uint32_t rtas_ld(target_ulong phys, int n)
{
    return ldl_be_phys(phys + 4*n);
}

static inline void rtas_st(target_ulong phys, int n, uint32_t val)
{
    stl_be_phys(phys + 4*n, val);
}

typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                              uint32_t token,
                              uint32_t nargs, target_ulong args,
                              uint32_t nret, target_ulong rets);
int spapr_rtas_register(const char *name, spapr_rtas_fn fn);
target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                             uint32_t token, uint32_t nargs, target_ulong args,
                             uint32_t nret, target_ulong rets);
int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
                                 hwaddr rtas_size);

#define SPAPR_TCE_PAGE_SHIFT   12
#define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
#define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)

typedef struct sPAPRTCE {
    uint64_t tce;
} sPAPRTCE;

#define SPAPR_VIO_BASE_LIOBN    0x00000000
#define SPAPR_PCI_BASE_LIOBN    0x80000000

#define RTAS_ERROR_LOG_MAX      2048

typedef struct sPAPRTCETable sPAPRTCETable;

void spapr_iommu_init(void);
void spapr_events_init(sPAPREnvironment *spapr);
void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
                                   size_t window_size);
MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
void spapr_tce_free(sPAPRTCETable *tcet);
void spapr_tce_reset(sPAPRTCETable *tcet);
void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass);
int spapr_dma_dt(void *fdt, int node_off, const char *propname,
                 uint32_t liobn, uint64_t window, uint32_t size);
int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
                      sPAPRTCETable *tcet);

#endif /* !defined (__HW_SPAPR_H__) */
Commit	Line	Data
9fdf0c29 DG	1	#if !defined(__HW_SPAPR_H__)
	2	#define __HW_SPAPR_H__
	3
9c17d615	4	#include "sysemu/dma.h"
0d09e41a	5	#include "hw/ppc/xics.h"
277f9acf	6
4040ab72	7	struct VIOsPAPRBus;
3384f95c	8	struct sPAPRPHBState;
639e8102	9	struct sPAPRNVRAM;
b5cec4c5	10	struct icp_state;
4040ab72	11
9fdf0c29	12	typedef struct sPAPREnvironment {
4040ab72	13	struct VIOsPAPRBus *vio_bus;
3384f95c	14	QLIST_HEAD(, sPAPRPHBState) phbs;
639e8102	15	struct sPAPRNVRAM *nvram;
b5cec4c5	16	struct icp_state *icp;
a3467baa	17
a8170e5e	18	hwaddr ram_limit;
a3467baa	19	void *htab;
7f763a5d	20	long htab_shift;
a8170e5e	21	hwaddr rma_size;
7f763a5d	22	int vrma_adjust;
a8170e5e	23	hwaddr fdt_addr, rtas_addr;
a3467baa DG	24	long rtas_size;
	25	void *fdt_skel;
	26	target_ulong entry_point;
e6c866d4	27	int next_irq;
ac26f8c3	28	int rtc_offset;
6e806cc3	29	char *cpu_model;
3fc5acde	30	bool has_graphics;
74d042e5 DG	31
	32	uint32_t epow_irq;
	33	Notifier epow_notifier;
9fdf0c29 DG	34	} sPAPREnvironment;
	35
	36	#define H_SUCCESS 0
	37	#define H_BUSY 1 /* Hardware busy -- retry later */
	38	#define H_CLOSED 2 /* Resource closed */
	39	#define H_NOT_AVAILABLE 3
	40	#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
	41	#define H_PARTIAL 5
	42	#define H_IN_PROGRESS 14 /* Kind of like busy */
	43	#define H_PAGE_REGISTERED 15
	44	#define H_PARTIAL_STORE 16
	45	#define H_PENDING 17 /* returned from H_POLL_PENDING */
	46	#define H_CONTINUE 18 /* Returned from H_Join on success */
	47	#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
	48	#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
	49	is a good time to retry */
	50	#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
	51	is a good time to retry */
	52	#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
	53	is a good time to retry */
	54	#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
	55	is a good time to retry */
	56	#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
	57	is a good time to retry */
	58	#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
	59	is a good time to retry */
	60	#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
	61	#define H_HARDWARE -1 /* Hardware error */
	62	#define H_FUNCTION -2 /* Function not supported */
	63	#define H_PRIVILEGE -3 /* Caller not privileged */
	64	#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
	65	#define H_BAD_MODE -5 /* Illegal msr value */
	66	#define H_PTEG_FULL -6 /* PTEG is full */
	67	#define H_NOT_FOUND -7 /* PTE was not found" */
	68	#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
	69	#define H_NO_MEM -9
	70	#define H_AUTHORITY -10
	71	#define H_PERMISSION -11
	72	#define H_DROPPED -12
	73	#define H_SOURCE_PARM -13
	74	#define H_DEST_PARM -14
	75	#define H_REMOTE_PARM -15
	76	#define H_RESOURCE -16
	77	#define H_ADAPTER_PARM -17
	78	#define H_RH_PARM -18
	79	#define H_RCQ_PARM -19
	80	#define H_SCQ_PARM -20
	81	#define H_EQ_PARM -21
	82	#define H_RT_PARM -22
	83	#define H_ST_PARM -23
	84	#define H_SIGT_PARM -24
	85	#define H_TOKEN_PARM -25
	86	#define H_MLENGTH_PARM -27
	87	#define H_MEM_PARM -28
	88	#define H_MEM_ACCESS_PARM -29
	89	#define H_ATTR_PARM -30
	90	#define H_PORT_PARM -31
	91	#define H_MCG_PARM -32
	92	#define H_VL_PARM -33
	93	#define H_TSIZE_PARM -34
	94	#define H_TRACE_PARM -35
	95
	96	#define H_MASK_PARM -37
	97	#define H_MCG_FULL -38
98	#define H_ALIAS_EXIST -39
99	#define H_P_COUNTER -40
100	#define H_TABLE_FULL -41
101	#define H_ALT_TABLE -42
102	#define H_MR_CONDITION -43
103	#define H_NOT_ENOUGH_RESOURCES -44
104	#define H_R_STATE -45
105	#define H_RESCINDEND -46
106	#define H_MULTI_THREADS_ACTIVE -9005
107
108
109	/* Long Busy is a condition that can be returned by the firmware
110	* when a call cannot be completed now, but the identical call
111	* should be retried later. This prevents calls blocking in the
112	* firmware for long periods of time. Annoyingly the firmware can return
113	* a range of return codes, hinting at how long we should wait before
114	* retrying. If you don't care for the hint, the macro below is a good
115	* way to check for the long_busy return codes
116	*/
117	#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
118	&& (x <= H_LONG_BUSY_END_RANGE))
119
120	/* Flags */
121	#define H_LARGE_PAGE (1ULL<<(63-16))
122	#define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
123	#define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
124	#define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
125	#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
126	#define H_PAGE_UNUSED ((1ULL<<(63-29)) \| (1ULL<<(63-30)))
127	#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE \| H_PAGE_UNUSED)
128	#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED \| (1ULL<<(63-31)))
129	#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
130	#define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
131	#define H_ANDCOND (1ULL<<(63-33))
132	#define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
133	#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
134	#define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
135	#define H_COPY_PAGE (1ULL<<(63-49))
136	#define H_N (1ULL<<(63-61))
137	#define H_PP1 (1ULL<<(63-62))
138	#define H_PP2 (1ULL<<(63-63))
139
140	/* VASI States */
141	#define H_VASI_INVALID 0
142	#define H_VASI_ENABLED 1
143	#define H_VASI_ABORTED 2
144	#define H_VASI_SUSPENDING 3
145	#define H_VASI_SUSPENDED 4
146	#define H_VASI_RESUMED 5
147	#define H_VASI_COMPLETED 6
148
149	/* DABRX flags */
150	#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
151	#define H_DABRX_KERNEL (1ULL<<(63-62))
152	#define H_DABRX_USER (1ULL<<(63-63))
153
66a0a2cb	154	/* Each control block has to be on a 4K boundary */
9fdf0c29 DG	155	#define H_CB_ALIGNMENT 4096
	156
	157	/* pSeries hypervisor opcodes */
	158	#define H_REMOVE 0x04
	159	#define H_ENTER 0x08
	160	#define H_READ 0x0c
	161	#define H_CLEAR_MOD 0x10
	162	#define H_CLEAR_REF 0x14
	163	#define H_PROTECT 0x18
	164	#define H_GET_TCE 0x1c
	165	#define H_PUT_TCE 0x20
	166	#define H_SET_SPRG0 0x24
	167	#define H_SET_DABR 0x28
	168	#define H_PAGE_INIT 0x2c
	169	#define H_SET_ASR 0x30
	170	#define H_ASR_ON 0x34
	171	#define H_ASR_OFF 0x38
	172	#define H_LOGICAL_CI_LOAD 0x3c
	173	#define H_LOGICAL_CI_STORE 0x40
	174	#define H_LOGICAL_CACHE_LOAD 0x44
	175	#define H_LOGICAL_CACHE_STORE 0x48
	176	#define H_LOGICAL_ICBI 0x4c
	177	#define H_LOGICAL_DCBF 0x50
	178	#define H_GET_TERM_CHAR 0x54
	179	#define H_PUT_TERM_CHAR 0x58
	180	#define H_REAL_TO_LOGICAL 0x5c
	181	#define H_HYPERVISOR_DATA 0x60
	182	#define H_EOI 0x64
	183	#define H_CPPR 0x68
	184	#define H_IPI 0x6c
	185	#define H_IPOLL 0x70
	186	#define H_XIRR 0x74
	187	#define H_PERFMON 0x7c
	188	#define H_MIGRATE_DMA 0x78
	189	#define H_REGISTER_VPA 0xDC
	190	#define H_CEDE 0xE0
	191	#define H_CONFER 0xE4
	192	#define H_PROD 0xE8
	193	#define H_GET_PPP 0xEC
	194	#define H_SET_PPP 0xF0
	195	#define H_PURR 0xF4
	196	#define H_PIC 0xF8
	197	#define H_REG_CRQ 0xFC
	198	#define H_FREE_CRQ 0x100
	199	#define H_VIO_SIGNAL 0x104
	200	#define H_SEND_CRQ 0x108
	201	#define H_COPY_RDMA 0x110
	202	#define H_REGISTER_LOGICAL_LAN 0x114
	203	#define H_FREE_LOGICAL_LAN 0x118
	204	#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
	205	#define H_SEND_LOGICAL_LAN 0x120
	206	#define H_BULK_REMOVE 0x124
	207	#define H_MULTICAST_CTRL 0x130
	208	#define H_SET_XDABR 0x134
	209	#define H_STUFF_TCE 0x138
	210	#define H_PUT_TCE_INDIRECT 0x13C
	211	#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
	212	#define H_VTERM_PARTNER_INFO 0x150
	213	#define H_REGISTER_VTERM 0x154
	214	#define H_FREE_VTERM 0x158
	215	#define H_RESET_EVENTS 0x15C
	216	#define H_ALLOC_RESOURCE 0x160
	217	#define H_FREE_RESOURCE 0x164
	218	#define H_MODIFY_QP 0x168
219	#define H_QUERY_QP 0x16C
220	#define H_REREGISTER_PMR 0x170
221	#define H_REGISTER_SMR 0x174
222	#define H_QUERY_MR 0x178
223	#define H_QUERY_MW 0x17C
224	#define H_QUERY_HCA 0x180
225	#define H_QUERY_PORT 0x184
226	#define H_MODIFY_PORT 0x188
227	#define H_DEFINE_AQP1 0x18C
228	#define H_GET_TRACE_BUFFER 0x190
229	#define H_DEFINE_AQP0 0x194
230	#define H_RESIZE_MR 0x198
231	#define H_ATTACH_MCQP 0x19C
232	#define H_DETACH_MCQP 0x1A0
233	#define H_CREATE_RPT 0x1A4
234	#define H_REMOVE_RPT 0x1A8
235	#define H_REGISTER_RPAGES 0x1AC
236	#define H_DISABLE_AND_GETC 0x1B0
237	#define H_ERROR_DATA 0x1B4
238	#define H_GET_HCA_INFO 0x1B8
239	#define H_GET_PERF_COUNT 0x1BC
240	#define H_MANAGE_TRACE 0x1C0
241	#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
242	#define H_QUERY_INT_STATE 0x1E4
243	#define H_POLL_PENDING 0x1D8
244	#define H_ILLAN_ATTRIBUTES 0x244
245	#define H_MODIFY_HEA_QP 0x250
246	#define H_QUERY_HEA_QP 0x254
247	#define H_QUERY_HEA 0x258
248	#define H_QUERY_HEA_PORT 0x25C
249	#define H_MODIFY_HEA_PORT 0x260
250	#define H_REG_BCMC 0x264
251	#define H_DEREG_BCMC 0x268
252	#define H_REGISTER_HEA_RPAGES 0x26C
253	#define H_DISABLE_AND_GET_HEA 0x270
254	#define H_GET_HEA_INFO 0x274
255	#define H_ALLOC_HEA_RESOURCE 0x278
256	#define H_ADD_CONN 0x284
257	#define H_DEL_CONN 0x288
258	#define H_JOIN 0x298
259	#define H_VASI_STATE 0x2A4
260	#define H_ENABLE_CRQ 0x2B0
261	#define H_GET_EM_PARMS 0x2B8
262	#define H_SET_MPP 0x2D0
263	#define H_GET_MPP 0x2D4
264	#define MAX_HCALL_OPCODE H_GET_MPP
265
39ac8455 DG	266	/* The hcalls above are standardized in PAPR and implemented by pHyp
	267	* as well.
	268	*
	269	* We also need some hcalls which are specific to qemu / KVM-on-POWER.
	270	* So far we just need one for H_RTAS, but in future we'll need more
	271	* for extensions like virtio. We put those into the 0xf000-0xfffc
	272	* range which is reserved by PAPR for "platform-specific" hcalls.
	273	*/
	274	#define KVMPPC_HCALL_BASE 0xf000
	275	#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
c73e3771 BH	276	#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
c73e3771 BH	277	#define KVMPPC_HCALL_MAX KVMPPC_H_LOGICAL_MEMOP
39ac8455	278
9fdf0c29 DG	279	extern sPAPREnvironment *spapr;
	280
	281	/#define DEBUG_SPAPR_HCALLS/
	282
	283	#ifdef DEBUG_SPAPR_HCALLS
	284	#define hcall_dprintf(fmt, ...) \
d9599c92	285	do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0)
9fdf0c29 DG	286	#else
	287	#define hcall_dprintf(fmt, ...) \
	288	do { } while (0)
	289	#endif
	290
b13ce26d	291	typedef target_ulong (spapr_hcall_fn)(PowerPCCPU cpu, sPAPREnvironment *spapr,
9fdf0c29 DG	292	target_ulong opcode,
	293	target_ulong *args);
	294
	295	void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
aa100fa4	296	target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
9fdf0c29 DG	297	target_ulong *args);
9fdf0c29 DG	298
ff9d2afa DG	299	int spapr_allocate_irq(int hint, bool lsi);
ff9d2afa DG	300	int spapr_allocate_irq_block(int num, bool lsi);
d07fee7e	301
a307d594	302	static inline int spapr_allocate_msi(int hint)
d07fee7e	303	{
ff9d2afa	304	return spapr_allocate_irq(hint, false);
d07fee7e DG	305	}
d07fee7e DG	306
a307d594	307	static inline int spapr_allocate_lsi(int hint)
d07fee7e	308	{
ff9d2afa	309	return spapr_allocate_irq(hint, true);
d07fee7e	310	}
277f9acf	311
39ac8455 DG	312	static inline uint32_t rtas_ld(target_ulong phys, int n)
39ac8455 DG	313	{
06c46bba	314	return ldl_be_phys(phys + 4*n);
39ac8455 DG	315	}
	316
	317	static inline void rtas_st(target_ulong phys, int n, uint32_t val)
	318	{
06c46bba	319	stl_be_phys(phys + 4*n, val);
39ac8455 DG	320	}
39ac8455 DG	321
210b580b AL	322	typedef void (spapr_rtas_fn)(PowerPCCPU cpu, sPAPREnvironment *spapr,
210b580b AL	323	uint32_t token,
39ac8455 DG	324	uint32_t nargs, target_ulong args,
39ac8455 DG	325	uint32_t nret, target_ulong rets);
4aac82c3	326	int spapr_rtas_register(const char *name, spapr_rtas_fn fn);
210b580b	327	target_ulong spapr_rtas_call(PowerPCCPU cpu, sPAPREnvironment spapr,
39ac8455 DG	328	uint32_t token, uint32_t nargs, target_ulong args,
39ac8455 DG	329	uint32_t nret, target_ulong rets);
a8170e5e AK	330	int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
a8170e5e AK	331	hwaddr rtas_size);
39ac8455	332
ad0ebb91 DG	333	#define SPAPR_TCE_PAGE_SHIFT 12
	334	#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
	335	#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
	336
	337	typedef struct sPAPRTCE {
	338	uint64_t tce;
	339	} sPAPRTCE;
	340
	341	#define SPAPR_VIO_BASE_LIOBN 0x00000000
edded454	342	#define SPAPR_PCI_BASE_LIOBN 0x80000000
ad0ebb91	343
74d042e5 DG	344	#define RTAS_ERROR_LOG_MAX 2048
74d042e5 DG	345
2b7dc949	346	typedef struct sPAPRTCETable sPAPRTCETable;
74d042e5	347
ad0ebb91	348	void spapr_iommu_init(void);
74d042e5 DG	349	void spapr_events_init(sPAPREnvironment *spapr);
74d042e5 DG	350	void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
84af6d9f PB	351	sPAPRTCETable spapr_tce_new_table(DeviceState owner, uint32_t liobn,
84af6d9f PB	352	size_t window_size);
a84bb436	353	MemoryRegion spapr_tce_get_iommu(sPAPRTCETable tcet);
2b7dc949 PB	354	void spapr_tce_free(sPAPRTCETable *tcet);
	355	void spapr_tce_reset(sPAPRTCETable *tcet);
	356	void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass);
ad0ebb91	357	int spapr_dma_dt(void fdt, int node_off, const char propname,
5c4cbcf2 AK	358	uint32_t liobn, uint64_t window, uint32_t size);
5c4cbcf2 AK	359	int spapr_tcet_dma_dt(void fdt, int node_off, const char propname,
2b7dc949	360	sPAPRTCETable *tcet);
ad0ebb91	361
9fdf0c29	362	#endif /* !defined (__HW_SPAPR_H__) */