[mirror_ubuntu-bionic-kernel.git] / include / linux / regulator / ab8500.h

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License v2
 *
 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
 *          Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
 *          Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
 */

#ifndef __LINUX_MFD_AB8500_REGULATOR_H
#define __LINUX_MFD_AB8500_REGULATOR_H

#include <linux/platform_device.h>

/* AB8500 regulators */
enum ab8500_regulator_id {
	AB8500_LDO_AUX1,
	AB8500_LDO_AUX2,
	AB8500_LDO_AUX3,
	AB8500_LDO_INTCORE,
	AB8500_LDO_TVOUT,
	AB8500_LDO_AUDIO,
	AB8500_LDO_ANAMIC1,
	AB8500_LDO_ANAMIC2,
	AB8500_LDO_DMIC,
	AB8500_LDO_ANA,
	AB8500_NUM_REGULATORS,
};

/* AB8505 regulators */
enum ab8505_regulator_id {
	AB8505_LDO_AUX1,
	AB8505_LDO_AUX2,
	AB8505_LDO_AUX3,
	AB8505_LDO_AUX4,
	AB8505_LDO_AUX5,
	AB8505_LDO_AUX6,
	AB8505_LDO_INTCORE,
	AB8505_LDO_ADC,
	AB8505_LDO_AUDIO,
	AB8505_LDO_ANAMIC1,
	AB8505_LDO_ANAMIC2,
	AB8505_LDO_AUX8,
	AB8505_LDO_ANA,
	AB8505_NUM_REGULATORS,
};

/* AB9540 regulators */
enum ab9540_regulator_id {
	AB9540_LDO_AUX1,
	AB9540_LDO_AUX2,
	AB9540_LDO_AUX3,
	AB9540_LDO_AUX4,
	AB9540_LDO_INTCORE,
	AB9540_LDO_TVOUT,
	AB9540_LDO_USB,
	AB9540_LDO_AUDIO,
	AB9540_LDO_ANAMIC1,
	AB9540_LDO_ANAMIC2,
	AB9540_LDO_DMIC,
	AB9540_LDO_ANA,
	AB9540_SYSCLKREQ_2,
	AB9540_SYSCLKREQ_4,
	AB9540_NUM_REGULATORS,
};

/* AB8540 regulators */
enum ab8540_regulator_id {
	AB8540_LDO_AUX1,
	AB8540_LDO_AUX2,
	AB8540_LDO_AUX3,
	AB8540_LDO_AUX4,
	AB8540_LDO_AUX5,
	AB8540_LDO_AUX6,
	AB8540_LDO_INTCORE,
	AB8540_LDO_TVOUT,
	AB8540_LDO_AUDIO,
	AB8540_LDO_ANAMIC1,
	AB8540_LDO_ANAMIC2,
	AB8540_LDO_DMIC,
	AB8540_LDO_ANA,
	AB8540_LDO_SDIO,
	AB8540_SYSCLKREQ_2,
	AB8540_SYSCLKREQ_4,
	AB8540_NUM_REGULATORS,
};

/* AB8500, AB8505, and AB9540 register initialization */
struct ab8500_regulator_reg_init {
	int id;
	u8 mask;
	u8 value;
};

#define INIT_REGULATOR_REGISTER(_id, _mask, _value)	\
	{						\
		.id = _id,				\
		.mask = _mask,				\
		.value = _value,			\
	}

/* AB8500 registers */
enum ab8500_regulator_reg {
	AB8500_REGUREQUESTCTRL2,
	AB8500_REGUREQUESTCTRL3,
	AB8500_REGUREQUESTCTRL4,
	AB8500_REGUSYSCLKREQ1HPVALID1,
	AB8500_REGUSYSCLKREQ1HPVALID2,
	AB8500_REGUHWHPREQ1VALID1,
	AB8500_REGUHWHPREQ1VALID2,
	AB8500_REGUHWHPREQ2VALID1,
	AB8500_REGUHWHPREQ2VALID2,
	AB8500_REGUSWHPREQVALID1,
	AB8500_REGUSWHPREQVALID2,
	AB8500_REGUSYSCLKREQVALID1,
	AB8500_REGUSYSCLKREQVALID2,
	AB8500_REGUMISC1,
	AB8500_VAUDIOSUPPLY,
	AB8500_REGUCTRL1VAMIC,
	AB8500_VPLLVANAREGU,
	AB8500_VREFDDR,
	AB8500_EXTSUPPLYREGU,
	AB8500_VAUX12REGU,
	AB8500_VRF1VAUX3REGU,
	AB8500_VAUX1SEL,
	AB8500_VAUX2SEL,
	AB8500_VRF1VAUX3SEL,
	AB8500_REGUCTRL2SPARE,
	AB8500_REGUCTRLDISCH,
	AB8500_REGUCTRLDISCH2,
	AB8500_NUM_REGULATOR_REGISTERS,
};

/* AB8505 registers */
enum ab8505_regulator_reg {
	AB8505_REGUREQUESTCTRL1,
	AB8505_REGUREQUESTCTRL2,
	AB8505_REGUREQUESTCTRL3,
	AB8505_REGUREQUESTCTRL4,
	AB8505_REGUSYSCLKREQ1HPVALID1,
	AB8505_REGUSYSCLKREQ1HPVALID2,
	AB8505_REGUHWHPREQ1VALID1,
	AB8505_REGUHWHPREQ1VALID2,
	AB8505_REGUHWHPREQ2VALID1,
	AB8505_REGUHWHPREQ2VALID2,
	AB8505_REGUSWHPREQVALID1,
	AB8505_REGUSWHPREQVALID2,
	AB8505_REGUSYSCLKREQVALID1,
	AB8505_REGUSYSCLKREQVALID2,
	AB8505_REGUVAUX4REQVALID,
	AB8505_REGUMISC1,
	AB8505_VAUDIOSUPPLY,
	AB8505_REGUCTRL1VAMIC,
	AB8505_VSMPSAREGU,
	AB8505_VSMPSBREGU,
	AB8505_VSAFEREGU, /* NOTE! PRCMU register */
	AB8505_VPLLVANAREGU,
	AB8505_EXTSUPPLYREGU,
	AB8505_VAUX12REGU,
	AB8505_VRF1VAUX3REGU,
	AB8505_VSMPSASEL1,
	AB8505_VSMPSASEL2,
	AB8505_VSMPSASEL3,
	AB8505_VSMPSBSEL1,
	AB8505_VSMPSBSEL2,
	AB8505_VSMPSBSEL3,
	AB8505_VSAFESEL1, /* NOTE! PRCMU register */
	AB8505_VSAFESEL2, /* NOTE! PRCMU register */
	AB8505_VSAFESEL3, /* NOTE! PRCMU register */
	AB8505_VAUX1SEL,
	AB8505_VAUX2SEL,
	AB8505_VRF1VAUX3SEL,
	AB8505_VAUX4REQCTRL,
	AB8505_VAUX4REGU,
	AB8505_VAUX4SEL,
	AB8505_REGUCTRLDISCH,
	AB8505_REGUCTRLDISCH2,
	AB8505_REGUCTRLDISCH3,
	AB8505_CTRLVAUX5,
	AB8505_CTRLVAUX6,
	AB8505_NUM_REGULATOR_REGISTERS,
};

/* AB9540 registers */
enum ab9540_regulator_reg {
	AB9540_REGUREQUESTCTRL1,
	AB9540_REGUREQUESTCTRL2,
	AB9540_REGUREQUESTCTRL3,
	AB9540_REGUREQUESTCTRL4,
	AB9540_REGUSYSCLKREQ1HPVALID1,
	AB9540_REGUSYSCLKREQ1HPVALID2,
	AB9540_REGUHWHPREQ1VALID1,
	AB9540_REGUHWHPREQ1VALID2,
	AB9540_REGUHWHPREQ2VALID1,
	AB9540_REGUHWHPREQ2VALID2,
	AB9540_REGUSWHPREQVALID1,
	AB9540_REGUSWHPREQVALID2,
	AB9540_REGUSYSCLKREQVALID1,
	AB9540_REGUSYSCLKREQVALID2,
	AB9540_REGUVAUX4REQVALID,
	AB9540_REGUMISC1,
	AB9540_VAUDIOSUPPLY,
	AB9540_REGUCTRL1VAMIC,
	AB9540_VSMPS1REGU,
	AB9540_VSMPS2REGU,
	AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
	AB9540_VPLLVANAREGU,
	AB9540_EXTSUPPLYREGU,
	AB9540_VAUX12REGU,
	AB9540_VRF1VAUX3REGU,
	AB9540_VSMPS1SEL1,
	AB9540_VSMPS1SEL2,
	AB9540_VSMPS1SEL3,
	AB9540_VSMPS2SEL1,
	AB9540_VSMPS2SEL2,
	AB9540_VSMPS2SEL3,
	AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
	AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
	AB9540_VAUX1SEL,
	AB9540_VAUX2SEL,
	AB9540_VRF1VAUX3SEL,
	AB9540_REGUCTRL2SPARE,
	AB9540_VAUX4REQCTRL,
	AB9540_VAUX4REGU,
	AB9540_VAUX4SEL,
	AB9540_REGUCTRLDISCH,
	AB9540_REGUCTRLDISCH2,
	AB9540_REGUCTRLDISCH3,
	AB9540_NUM_REGULATOR_REGISTERS,
};

/* AB8540 registers */
enum ab8540_regulator_reg {
	AB8540_REGUREQUESTCTRL1,
	AB8540_REGUREQUESTCTRL2,
	AB8540_REGUREQUESTCTRL3,
	AB8540_REGUREQUESTCTRL4,
	AB8540_REGUSYSCLKREQ1HPVALID1,
	AB8540_REGUSYSCLKREQ1HPVALID2,
	AB8540_REGUHWHPREQ1VALID1,
	AB8540_REGUHWHPREQ1VALID2,
	AB8540_REGUHWHPREQ2VALID1,
	AB8540_REGUHWHPREQ2VALID2,
	AB8540_REGUSWHPREQVALID1,
	AB8540_REGUSWHPREQVALID2,
	AB8540_REGUSYSCLKREQVALID1,
	AB8540_REGUSYSCLKREQVALID2,
	AB8540_REGUVAUX4REQVALID,
	AB8540_REGUVAUX5REQVALID,
	AB8540_REGUVAUX6REQVALID,
	AB8540_REGUVCLKBREQVALID,
	AB8540_REGUVRF1REQVALID,
	AB8540_REGUMISC1,
	AB8540_VAUDIOSUPPLY,
	AB8540_REGUCTRL1VAMIC,
	AB8540_VHSIC,
	AB8540_VSDIO,
	AB8540_VSMPS1REGU,
	AB8540_VSMPS2REGU,
	AB8540_VSMPS3REGU,
	AB8540_VPLLVANAREGU,
	AB8540_EXTSUPPLYREGU,
	AB8540_VAUX12REGU,
	AB8540_VRF1VAUX3REGU,
	AB8540_VSMPS1SEL1,
	AB8540_VSMPS1SEL2,
	AB8540_VSMPS1SEL3,
	AB8540_VSMPS2SEL1,
	AB8540_VSMPS2SEL2,
	AB8540_VSMPS2SEL3,
	AB8540_VSMPS3SEL1,
	AB8540_VSMPS3SEL2,
	AB8540_VAUX1SEL,
	AB8540_VAUX2SEL,
	AB8540_VRF1VAUX3SEL,
	AB8540_REGUCTRL2SPARE,
	AB8540_VAUX4REQCTRL,
	AB8540_VAUX4REGU,
	AB8540_VAUX4SEL,
	AB8540_VAUX5REQCTRL,
	AB8540_VAUX5REGU,
	AB8540_VAUX5SEL,
	AB8540_VAUX6REQCTRL,
	AB8540_VAUX6REGU,
	AB8540_VAUX6SEL,
	AB8540_VCLKBREQCTRL,
	AB8540_VCLKBREGU,
	AB8540_VCLKBSEL,
	AB8540_VRF1REQCTRL,
	AB8540_REGUCTRLDISCH,
	AB8540_REGUCTRLDISCH2,
	AB8540_REGUCTRLDISCH3,
	AB8540_REGUCTRLDISCH4,
	AB8540_VSIMSYSCLKCTRL,
	AB8540_VANAVPLLSEL,
	AB8540_NUM_REGULATOR_REGISTERS,
};

/* AB8500 external regulators */
struct ab8500_ext_regulator_cfg {
	bool hwreq; /* requires hw mode or high power mode */
};

enum ab8500_ext_regulator_id {
	AB8500_EXT_SUPPLY1,
	AB8500_EXT_SUPPLY2,
	AB8500_EXT_SUPPLY3,
	AB8500_NUM_EXT_REGULATORS,
};

/* AB8500 regulator platform data */
struct ab8500_regulator_platform_data {
	int num_reg_init;
	struct ab8500_regulator_reg_init *reg_init;
	int num_regulator;
	struct regulator_init_data *regulator;
	int num_ext_regulator;
	struct regulator_init_data *ext_regulator;
};

#endif
Commit	Line	Data
549931f9 SI	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License v2
	5	*
79568b94 BJ	6	* Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
79568b94 BJ	7	* Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f	8	* Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
549931f9 SI	9	*/
	10
	11	#ifndef __LINUX_MFD_AB8500_REGULATOR_H
	12	#define __LINUX_MFD_AB8500_REGULATOR_H
	13
d1a82001 LJ	14	#include <linux/platform_device.h>
d1a82001 LJ	15
549931f9	16	/* AB8500 regulators */
cb189b07 BJ	17	enum ab8500_regulator_id {
	18	AB8500_LDO_AUX1,
	19	AB8500_LDO_AUX2,
	20	AB8500_LDO_AUX3,
	21	AB8500_LDO_INTCORE,
	22	AB8500_LDO_TVOUT,
	23	AB8500_LDO_AUDIO,
	24	AB8500_LDO_ANAMIC1,
	25	AB8500_LDO_ANAMIC2,
	26	AB8500_LDO_DMIC,
	27	AB8500_LDO_ANA,
	28	AB8500_NUM_REGULATORS,
	29	};
79568b94	30
547f384f LJ	31	/* AB8505 regulators */
	32	enum ab8505_regulator_id {
	33	AB8505_LDO_AUX1,
	34	AB8505_LDO_AUX2,
	35	AB8505_LDO_AUX3,
	36	AB8505_LDO_AUX4,
	37	AB8505_LDO_AUX5,
	38	AB8505_LDO_AUX6,
	39	AB8505_LDO_INTCORE,
	40	AB8505_LDO_ADC,
547f384f LJ	41	AB8505_LDO_AUDIO,
	42	AB8505_LDO_ANAMIC1,
	43	AB8505_LDO_ANAMIC2,
	44	AB8505_LDO_AUX8,
	45	AB8505_LDO_ANA,
547f384f LJ	46	AB8505_NUM_REGULATORS,
	47	};
	48
	49	/* AB9540 regulators */
d6255529 LW	50	enum ab9540_regulator_id {
	51	AB9540_LDO_AUX1,
	52	AB9540_LDO_AUX2,
	53	AB9540_LDO_AUX3,
	54	AB9540_LDO_AUX4,
	55	AB9540_LDO_INTCORE,
	56	AB9540_LDO_TVOUT,
	57	AB9540_LDO_USB,
	58	AB9540_LDO_AUDIO,
	59	AB9540_LDO_ANAMIC1,
	60	AB9540_LDO_ANAMIC2,
	61	AB9540_LDO_DMIC,
	62	AB9540_LDO_ANA,
	63	AB9540_SYSCLKREQ_2,
	64	AB9540_SYSCLKREQ_4,
	65	AB9540_NUM_REGULATORS,
	66	};
	67
ae0a9a3e LJ	68	/* AB8540 regulators */
	69	enum ab8540_regulator_id {
	70	AB8540_LDO_AUX1,
	71	AB8540_LDO_AUX2,
	72	AB8540_LDO_AUX3,
	73	AB8540_LDO_AUX4,
684d5ce4 ZH	74	AB8540_LDO_AUX5,
684d5ce4 ZH	75	AB8540_LDO_AUX6,
ae0a9a3e LJ	76	AB8540_LDO_INTCORE,
	77	AB8540_LDO_TVOUT,
	78	AB8540_LDO_AUDIO,
	79	AB8540_LDO_ANAMIC1,
	80	AB8540_LDO_ANAMIC2,
	81	AB8540_LDO_DMIC,
	82	AB8540_LDO_ANA,
	83	AB8540_LDO_SDIO,
	84	AB8540_SYSCLKREQ_2,
	85	AB8540_SYSCLKREQ_4,
	86	AB8540_NUM_REGULATORS,
	87	};
	88
547f384f	89	/* AB8500, AB8505, and AB9540 register initialization */
79568b94 BJ	90	struct ab8500_regulator_reg_init {
79568b94 BJ	91	int id;
3c1b8438	92	u8 mask;
79568b94 BJ	93	u8 value;
	94	};
	95
3c1b8438 LJ	96	#define INIT_REGULATOR_REGISTER(_id, _mask, _value) \
	97	{ \
	98	.id = _id, \
	99	.mask = _mask, \
	100	.value = _value, \
79568b94 BJ	101	}
	102
	103	/* AB8500 registers */
	104	enum ab8500_regulator_reg {
	105	AB8500_REGUREQUESTCTRL2,
	106	AB8500_REGUREQUESTCTRL3,
	107	AB8500_REGUREQUESTCTRL4,
	108	AB8500_REGUSYSCLKREQ1HPVALID1,
	109	AB8500_REGUSYSCLKREQ1HPVALID2,
	110	AB8500_REGUHWHPREQ1VALID1,
	111	AB8500_REGUHWHPREQ1VALID2,
	112	AB8500_REGUHWHPREQ2VALID1,
	113	AB8500_REGUHWHPREQ2VALID2,
	114	AB8500_REGUSWHPREQVALID1,
	115	AB8500_REGUSWHPREQVALID2,
	116	AB8500_REGUSYSCLKREQVALID1,
	117	AB8500_REGUSYSCLKREQVALID2,
	118	AB8500_REGUMISC1,
	119	AB8500_VAUDIOSUPPLY,
	120	AB8500_REGUCTRL1VAMIC,
	121	AB8500_VPLLVANAREGU,
	122	AB8500_VREFDDR,
	123	AB8500_EXTSUPPLYREGU,
	124	AB8500_VAUX12REGU,
	125	AB8500_VRF1VAUX3REGU,
	126	AB8500_VAUX1SEL,
	127	AB8500_VAUX2SEL,
	128	AB8500_VRF1VAUX3SEL,
	129	AB8500_REGUCTRL2SPARE,
	130	AB8500_REGUCTRLDISCH,
	131	AB8500_REGUCTRLDISCH2,
79568b94 BJ	132	AB8500_NUM_REGULATOR_REGISTERS,
	133	};
	134
547f384f LJ	135	/* AB8505 registers */
	136	enum ab8505_regulator_reg {
	137	AB8505_REGUREQUESTCTRL1,
	138	AB8505_REGUREQUESTCTRL2,
	139	AB8505_REGUREQUESTCTRL3,
	140	AB8505_REGUREQUESTCTRL4,
	141	AB8505_REGUSYSCLKREQ1HPVALID1,
	142	AB8505_REGUSYSCLKREQ1HPVALID2,
	143	AB8505_REGUHWHPREQ1VALID1,
	144	AB8505_REGUHWHPREQ1VALID2,
	145	AB8505_REGUHWHPREQ2VALID1,
	146	AB8505_REGUHWHPREQ2VALID2,
	147	AB8505_REGUSWHPREQVALID1,
	148	AB8505_REGUSWHPREQVALID2,
	149	AB8505_REGUSYSCLKREQVALID1,
	150	AB8505_REGUSYSCLKREQVALID2,
	151	AB8505_REGUVAUX4REQVALID,
	152	AB8505_REGUMISC1,
	153	AB8505_VAUDIOSUPPLY,
	154	AB8505_REGUCTRL1VAMIC,
	155	AB8505_VSMPSAREGU,
	156	AB8505_VSMPSBREGU,
	157	AB8505_VSAFEREGU, /* NOTE! PRCMU register */
	158	AB8505_VPLLVANAREGU,
	159	AB8505_EXTSUPPLYREGU,
	160	AB8505_VAUX12REGU,
	161	AB8505_VRF1VAUX3REGU,
	162	AB8505_VSMPSASEL1,
	163	AB8505_VSMPSASEL2,
	164	AB8505_VSMPSASEL3,
	165	AB8505_VSMPSBSEL1,
	166	AB8505_VSMPSBSEL2,
	167	AB8505_VSMPSBSEL3,
	168	AB8505_VSAFESEL1, /* NOTE! PRCMU register */
	169	AB8505_VSAFESEL2, /* NOTE! PRCMU register */
	170	AB8505_VSAFESEL3, /* NOTE! PRCMU register */
	171	AB8505_VAUX1SEL,
	172	AB8505_VAUX2SEL,
	173	AB8505_VRF1VAUX3SEL,
	174	AB8505_VAUX4REQCTRL,
	175	AB8505_VAUX4REGU,
	176	AB8505_VAUX4SEL,
	177	AB8505_REGUCTRLDISCH,
	178	AB8505_REGUCTRLDISCH2,
	179	AB8505_REGUCTRLDISCH3,
	180	AB8505_CTRLVAUX5,
	181	AB8505_CTRLVAUX6,
	182	AB8505_NUM_REGULATOR_REGISTERS,
	183	};
d6255529 LW	184
	185	/* AB9540 registers */
	186	enum ab9540_regulator_reg {
	187	AB9540_REGUREQUESTCTRL1,
	188	AB9540_REGUREQUESTCTRL2,
	189	AB9540_REGUREQUESTCTRL3,
	190	AB9540_REGUREQUESTCTRL4,
	191	AB9540_REGUSYSCLKREQ1HPVALID1,
	192	AB9540_REGUSYSCLKREQ1HPVALID2,
	193	AB9540_REGUHWHPREQ1VALID1,
	194	AB9540_REGUHWHPREQ1VALID2,
	195	AB9540_REGUHWHPREQ2VALID1,
	196	AB9540_REGUHWHPREQ2VALID2,
	197	AB9540_REGUSWHPREQVALID1,
	198	AB9540_REGUSWHPREQVALID2,
	199	AB9540_REGUSYSCLKREQVALID1,
	200	AB9540_REGUSYSCLKREQVALID2,
	201	AB9540_REGUVAUX4REQVALID,
	202	AB9540_REGUMISC1,
	203	AB9540_VAUDIOSUPPLY,
	204	AB9540_REGUCTRL1VAMIC,
	205	AB9540_VSMPS1REGU,
	206	AB9540_VSMPS2REGU,
	207	AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
	208	AB9540_VPLLVANAREGU,
	209	AB9540_EXTSUPPLYREGU,
	210	AB9540_VAUX12REGU,
	211	AB9540_VRF1VAUX3REGU,
	212	AB9540_VSMPS1SEL1,
	213	AB9540_VSMPS1SEL2,
	214	AB9540_VSMPS1SEL3,
	215	AB9540_VSMPS2SEL1,
	216	AB9540_VSMPS2SEL2,
	217	AB9540_VSMPS2SEL3,
	218	AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
	219	AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
	220	AB9540_VAUX1SEL,
	221	AB9540_VAUX2SEL,
	222	AB9540_VRF1VAUX3SEL,
	223	AB9540_REGUCTRL2SPARE,
	224	AB9540_VAUX4REQCTRL,
	225	AB9540_VAUX4REGU,
	226	AB9540_VAUX4SEL,
	227	AB9540_REGUCTRLDISCH,
	228	AB9540_REGUCTRLDISCH2,
	229	AB9540_REGUCTRLDISCH3,
	230	AB9540_NUM_REGULATOR_REGISTERS,
	231	};
	232
ae0a9a3e LJ	233	/* AB8540 registers */
	234	enum ab8540_regulator_reg {
	235	AB8540_REGUREQUESTCTRL1,
	236	AB8540_REGUREQUESTCTRL2,
	237	AB8540_REGUREQUESTCTRL3,
	238	AB8540_REGUREQUESTCTRL4,
	239	AB8540_REGUSYSCLKREQ1HPVALID1,
	240	AB8540_REGUSYSCLKREQ1HPVALID2,
	241	AB8540_REGUHWHPREQ1VALID1,
	242	AB8540_REGUHWHPREQ1VALID2,
	243	AB8540_REGUHWHPREQ2VALID1,
	244	AB8540_REGUHWHPREQ2VALID2,
	245	AB8540_REGUSWHPREQVALID1,
	246	AB8540_REGUSWHPREQVALID2,
	247	AB8540_REGUSYSCLKREQVALID1,
	248	AB8540_REGUSYSCLKREQVALID2,
	249	AB8540_REGUVAUX4REQVALID,
	250	AB8540_REGUVAUX5REQVALID,
	251	AB8540_REGUVAUX6REQVALID,
	252	AB8540_REGUVCLKBREQVALID,
	253	AB8540_REGUVRF1REQVALID,
	254	AB8540_REGUMISC1,
	255	AB8540_VAUDIOSUPPLY,
	256	AB8540_REGUCTRL1VAMIC,
	257	AB8540_VHSIC,
	258	AB8540_VSDIO,
	259	AB8540_VSMPS1REGU,
	260	AB8540_VSMPS2REGU,
	261	AB8540_VSMPS3REGU,
	262	AB8540_VPLLVANAREGU,
	263	AB8540_EXTSUPPLYREGU,
	264	AB8540_VAUX12REGU,
	265	AB8540_VRF1VAUX3REGU,
	266	AB8540_VSMPS1SEL1,
	267	AB8540_VSMPS1SEL2,
	268	AB8540_VSMPS1SEL3,
	269	AB8540_VSMPS2SEL1,
	270	AB8540_VSMPS2SEL2,
	271	AB8540_VSMPS2SEL3,
	272	AB8540_VSMPS3SEL1,
	273	AB8540_VSMPS3SEL2,
	274	AB8540_VAUX1SEL,
	275	AB8540_VAUX2SEL,
	276	AB8540_VRF1VAUX3SEL,
	277	AB8540_REGUCTRL2SPARE,
	278	AB8540_VAUX4REQCTRL,
	279	AB8540_VAUX4REGU,
	280	AB8540_VAUX4SEL,
	281	AB8540_VAUX5REQCTRL,
	282	AB8540_VAUX5REGU,
	283	AB8540_VAUX5SEL,
	284	AB8540_VAUX6REQCTRL,
	285	AB8540_VAUX6REGU,
	286	AB8540_VAUX6SEL,
	287	AB8540_VCLKBREQCTRL,
	288	AB8540_VCLKBREGU,
	289	AB8540_VCLKBSEL,
	290	AB8540_VRF1REQCTRL,
	291	AB8540_REGUCTRLDISCH,
	292	AB8540_REGUCTRLDISCH2,
	293	AB8540_REGUCTRLDISCH3,
	294	AB8540_REGUCTRLDISCH4,
	295	AB8540_VSIMSYSCLKCTRL,
	296	AB8540_VANAVPLLSEL,
297	AB8540_NUM_REGULATOR_REGISTERS,
298	};
299
d1a82001	300	/* AB8500 external regulators */
18bc2b39 BJ	301	struct ab8500_ext_regulator_cfg {
	302	bool hwreq; /* requires hw mode or high power mode */
	303	};
	304
d1a82001 LJ	305	enum ab8500_ext_regulator_id {
	306	AB8500_EXT_SUPPLY1,
	307	AB8500_EXT_SUPPLY2,
	308	AB8500_EXT_SUPPLY3,
	309	AB8500_NUM_EXT_REGULATORS,
	310	};
	311
	312	/* AB8500 regulator platform data */
732805a5 BJ	313	struct ab8500_regulator_platform_data {
	314	int num_reg_init;
	315	struct ab8500_regulator_reg_init *reg_init;
	316	int num_regulator;
	317	struct regulator_init_data *regulator;
d1a82001 LJ	318	int num_ext_regulator;
d1a82001 LJ	319	struct regulator_init_data *ext_regulator;
732805a5 BJ	320	};
732805a5 BJ	321
549931f9	322	#endif