]>
Commit | Line | Data |
---|---|---|
dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
961f8395 | 24 | #include "hw/qdev-core.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
1de7afc9 | 26 | #include "qemu/thread.h" |
4917cf44 | 27 | #include "qemu/tls.h" |
a23bbfda | 28 | #include "qemu/typedefs.h" |
dd83b06a | 29 | |
c72bf468 JF |
30 | typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque); |
31 | ||
577f42c0 AF |
32 | /** |
33 | * vaddr: | |
34 | * Type wide enough to contain any #target_ulong virtual address. | |
35 | */ | |
36 | typedef uint64_t vaddr; | |
37 | #define VADDR_PRId PRId64 | |
38 | #define VADDR_PRIu PRIu64 | |
39 | #define VADDR_PRIo PRIo64 | |
40 | #define VADDR_PRIx PRIx64 | |
41 | #define VADDR_PRIX PRIX64 | |
42 | #define VADDR_MAX UINT64_MAX | |
43 | ||
dd83b06a AF |
44 | /** |
45 | * SECTION:cpu | |
46 | * @section_id: QEMU-cpu | |
47 | * @title: CPU Class | |
48 | * @short_description: Base class for all CPUs | |
49 | */ | |
50 | ||
51 | #define TYPE_CPU "cpu" | |
52 | ||
53 | #define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU) | |
54 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) | |
55 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
56 | ||
57 | typedef struct CPUState CPUState; | |
58 | ||
c658b94f AF |
59 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
60 | bool is_write, bool is_exec, int opaque, | |
61 | unsigned size); | |
62 | ||
bdf7ae5b AF |
63 | struct TranslationBlock; |
64 | ||
dd83b06a AF |
65 | /** |
66 | * CPUClass: | |
2b8c2754 AF |
67 | * @class_by_name: Callback to map -cpu command line model name to an |
68 | * instantiatable CPU type. | |
f5df5baf | 69 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 70 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
97a8ea5a | 71 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 72 | * @do_unassigned_access: Callback for unassigned access handling. |
878096ee AF |
73 | * @dump_state: Callback for dumping state. |
74 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 75 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 76 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 77 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 78 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
79 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
80 | * #TranslationBlock. | |
b170fce3 | 81 | * @vmsd: State description for migration. |
dd83b06a AF |
82 | * |
83 | * Represents a CPU family or model. | |
84 | */ | |
85 | typedef struct CPUClass { | |
86 | /*< private >*/ | |
961f8395 | 87 | DeviceClass parent_class; |
dd83b06a AF |
88 | /*< public >*/ |
89 | ||
2b8c2754 AF |
90 | ObjectClass *(*class_by_name)(const char *cpu_model); |
91 | ||
dd83b06a | 92 | void (*reset)(CPUState *cpu); |
91b1df8c | 93 | int reset_dump_flags; |
97a8ea5a | 94 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 95 | CPUUnassignedAccess do_unassigned_access; |
878096ee AF |
96 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
97 | int flags); | |
98 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
99 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 100 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 101 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
102 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
103 | Error **errp); | |
f45748f1 | 104 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 105 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
b170fce3 AF |
106 | |
107 | const struct VMStateDescription *vmsd; | |
c72bf468 JF |
108 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
109 | int cpuid, void *opaque); | |
110 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
111 | void *opaque); | |
112 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
113 | int cpuid, void *opaque); | |
114 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
115 | void *opaque); | |
dd83b06a AF |
116 | } CPUClass; |
117 | ||
a60f24b5 | 118 | struct KVMState; |
f7575c96 | 119 | struct kvm_run; |
a60f24b5 | 120 | |
dd83b06a AF |
121 | /** |
122 | * CPUState: | |
55e5c285 | 123 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
124 | * @nr_cores: Number of cores within this CPU package. |
125 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 126 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 127 | * @host_tid: Host thread ID. |
0315c31c | 128 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 129 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
130 | * @interrupt_request: Indicates a pending interrupt request. |
131 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 132 | * @stop: Indicates a pending stop request. |
f324e766 | 133 | * @stopped: Indicates the CPU has been artificially stopped. |
378df4b2 PM |
134 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
135 | * CPU and return to its top level loop. | |
ed2803da | 136 | * @singlestep_enabled: Flags for single-stepping. |
c05efcb1 | 137 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 138 | * @current_tb: Currently executing TB. |
182735ef | 139 | * @next_cpu: Next CPU sharing TB cache. |
8737c51c | 140 | * @kvm_fd: vCPU file descriptor for KVM. |
dd83b06a AF |
141 | * |
142 | * State of one CPU core or thread. | |
143 | */ | |
144 | struct CPUState { | |
145 | /*< private >*/ | |
961f8395 | 146 | DeviceState parent_obj; |
dd83b06a AF |
147 | /*< public >*/ |
148 | ||
ce3960eb AF |
149 | int nr_cores; |
150 | int nr_threads; | |
1b1ed8dc | 151 | int numa_node; |
ce3960eb | 152 | |
814e612e | 153 | struct QemuThread *thread; |
bcba2a72 AF |
154 | #ifdef _WIN32 |
155 | HANDLE hThread; | |
156 | #endif | |
9f09e18a | 157 | int thread_id; |
0d34282f | 158 | uint32_t host_tid; |
0315c31c | 159 | bool running; |
f5c121b8 | 160 | struct QemuCond *halt_cond; |
c64ca814 | 161 | struct qemu_work_item *queued_work_first, *queued_work_last; |
216fc9a4 | 162 | bool thread_kicked; |
61a46217 | 163 | bool created; |
4fdeee7c | 164 | bool stop; |
f324e766 | 165 | bool stopped; |
fcd7d003 | 166 | volatile sig_atomic_t exit_request; |
378df4b2 | 167 | volatile sig_atomic_t tcg_exit_req; |
259186a7 | 168 | uint32_t interrupt_request; |
ed2803da | 169 | int singlestep_enabled; |
bcba2a72 | 170 | |
c05efcb1 | 171 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 172 | struct TranslationBlock *current_tb; |
182735ef | 173 | CPUState *next_cpu; |
d77953b9 | 174 | |
8737c51c | 175 | int kvm_fd; |
20d695a9 | 176 | bool kvm_vcpu_dirty; |
a60f24b5 | 177 | struct KVMState *kvm_state; |
f7575c96 | 178 | struct kvm_run *kvm_run; |
8737c51c | 179 | |
f5df5baf | 180 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 181 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 182 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
dd83b06a AF |
183 | }; |
184 | ||
182735ef AF |
185 | extern CPUState *first_cpu; |
186 | ||
4917cf44 AF |
187 | DECLARE_TLS(CPUState *, current_cpu); |
188 | #define current_cpu tls_var(current_cpu) | |
189 | ||
444d5590 AF |
190 | /** |
191 | * cpu_paging_enabled: | |
192 | * @cpu: The CPU whose state is to be inspected. | |
193 | * | |
194 | * Returns: %true if paging is enabled, %false otherwise. | |
195 | */ | |
196 | bool cpu_paging_enabled(const CPUState *cpu); | |
197 | ||
a23bbfda AF |
198 | /** |
199 | * cpu_get_memory_mapping: | |
200 | * @cpu: The CPU whose memory mappings are to be obtained. | |
201 | * @list: Where to write the memory mappings to. | |
202 | * @errp: Pointer for reporting an #Error. | |
203 | */ | |
204 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
205 | Error **errp); | |
206 | ||
c72bf468 JF |
207 | /** |
208 | * cpu_write_elf64_note: | |
209 | * @f: pointer to a function that writes memory to a file | |
210 | * @cpu: The CPU whose memory is to be dumped | |
211 | * @cpuid: ID number of the CPU | |
212 | * @opaque: pointer to the CPUState struct | |
213 | */ | |
214 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
215 | int cpuid, void *opaque); | |
216 | ||
217 | /** | |
218 | * cpu_write_elf64_qemunote: | |
219 | * @f: pointer to a function that writes memory to a file | |
220 | * @cpu: The CPU whose memory is to be dumped | |
221 | * @cpuid: ID number of the CPU | |
222 | * @opaque: pointer to the CPUState struct | |
223 | */ | |
224 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
225 | void *opaque); | |
226 | ||
227 | /** | |
228 | * cpu_write_elf32_note: | |
229 | * @f: pointer to a function that writes memory to a file | |
230 | * @cpu: The CPU whose memory is to be dumped | |
231 | * @cpuid: ID number of the CPU | |
232 | * @opaque: pointer to the CPUState struct | |
233 | */ | |
234 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
235 | int cpuid, void *opaque); | |
236 | ||
237 | /** | |
238 | * cpu_write_elf32_qemunote: | |
239 | * @f: pointer to a function that writes memory to a file | |
240 | * @cpu: The CPU whose memory is to be dumped | |
241 | * @cpuid: ID number of the CPU | |
242 | * @opaque: pointer to the CPUState struct | |
243 | */ | |
244 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
245 | void *opaque); | |
dd83b06a | 246 | |
878096ee AF |
247 | /** |
248 | * CPUDumpFlags: | |
249 | * @CPU_DUMP_CODE: | |
250 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
251 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
252 | */ | |
253 | enum CPUDumpFlags { | |
254 | CPU_DUMP_CODE = 0x00010000, | |
255 | CPU_DUMP_FPU = 0x00020000, | |
256 | CPU_DUMP_CCOP = 0x00040000, | |
257 | }; | |
258 | ||
259 | /** | |
260 | * cpu_dump_state: | |
261 | * @cpu: The CPU whose state is to be dumped. | |
262 | * @f: File to dump to. | |
263 | * @cpu_fprintf: Function to dump with. | |
264 | * @flags: Flags what to dump. | |
265 | * | |
266 | * Dumps CPU state. | |
267 | */ | |
268 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
269 | int flags); | |
270 | ||
271 | /** | |
272 | * cpu_dump_statistics: | |
273 | * @cpu: The CPU whose state is to be dumped. | |
274 | * @f: File to dump to. | |
275 | * @cpu_fprintf: Function to dump with. | |
276 | * @flags: Flags what to dump. | |
277 | * | |
278 | * Dumps CPU statistics. | |
279 | */ | |
280 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
281 | int flags); | |
282 | ||
dd83b06a AF |
283 | /** |
284 | * cpu_reset: | |
285 | * @cpu: The CPU whose state is to be reset. | |
286 | */ | |
287 | void cpu_reset(CPUState *cpu); | |
288 | ||
2b8c2754 AF |
289 | /** |
290 | * cpu_class_by_name: | |
291 | * @typename: The CPU base type. | |
292 | * @cpu_model: The model string without any parameters. | |
293 | * | |
294 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
295 | * | |
296 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
297 | */ | |
298 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
299 | ||
ca91b15f AF |
300 | /** |
301 | * cpu_class_set_vmsd: | |
302 | * @cc: CPU class | |
303 | * @value: Value to set. Unused for %CONFIG_USER_ONLY. | |
304 | * | |
305 | * Sets #VMStateDescription for @cc. | |
306 | * | |
307 | * The @value argument is intentionally discarded for the non-softmmu targets | |
308 | * to avoid linker errors or excessive preprocessor usage. If this behavior | |
76d5f029 | 309 | * is undesired, you should assign #CPUClass.vmsd directly instead. |
ca91b15f AF |
310 | */ |
311 | #ifndef CONFIG_USER_ONLY | |
312 | static inline void cpu_class_set_vmsd(CPUClass *cc, | |
313 | const struct VMStateDescription *value) | |
314 | { | |
315 | cc->vmsd = value; | |
316 | } | |
317 | #else | |
318 | #define cpu_class_set_vmsd(cc, value) ((cc)->vmsd = NULL) | |
319 | #endif | |
320 | ||
c658b94f AF |
321 | #ifndef CONFIG_USER_ONLY |
322 | static inline void cpu_class_set_do_unassigned_access(CPUClass *cc, | |
323 | CPUUnassignedAccess value) | |
324 | { | |
325 | cc->do_unassigned_access = value; | |
326 | } | |
327 | #else | |
328 | #define cpu_class_set_do_unassigned_access(cc, value) \ | |
329 | ((cc)->do_unassigned_access = NULL) | |
330 | #endif | |
331 | ||
19e3835c AF |
332 | /** |
333 | * device_class_set_vmsd: | |
334 | * @dc: Device class | |
335 | * @value: Value to set. Unused for %CONFIG_USER_ONLY. | |
336 | * | |
337 | * Sets #VMStateDescription for @dc. | |
338 | * | |
339 | * The @value argument is intentionally discarded for the non-softmmu targets | |
340 | * to avoid linker errors or excessive preprocessor usage. If this behavior | |
341 | * is undesired, you should assign #DeviceClass.vmsd directly instead. | |
342 | */ | |
343 | #ifndef CONFIG_USER_ONLY | |
344 | static inline void device_class_set_vmsd(DeviceClass *dc, | |
345 | const struct VMStateDescription *value) | |
346 | { | |
347 | dc->vmsd = value; | |
348 | } | |
349 | #else | |
350 | #define device_class_set_vmsd(dc, value) ((dc)->vmsd = NULL) | |
351 | #endif | |
352 | ||
3993c6bd AF |
353 | /** |
354 | * qemu_cpu_has_work: | |
355 | * @cpu: The vCPU to check. | |
356 | * | |
357 | * Checks whether the CPU has work to do. | |
358 | * | |
359 | * Returns: %true if the CPU has work, %false otherwise. | |
360 | */ | |
361 | bool qemu_cpu_has_work(CPUState *cpu); | |
362 | ||
60e82579 AF |
363 | /** |
364 | * qemu_cpu_is_self: | |
365 | * @cpu: The vCPU to check against. | |
366 | * | |
367 | * Checks whether the caller is executing on the vCPU thread. | |
368 | * | |
369 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
370 | */ | |
371 | bool qemu_cpu_is_self(CPUState *cpu); | |
372 | ||
c08d7424 AF |
373 | /** |
374 | * qemu_cpu_kick: | |
375 | * @cpu: The vCPU to kick. | |
376 | * | |
377 | * Kicks @cpu's thread. | |
378 | */ | |
379 | void qemu_cpu_kick(CPUState *cpu); | |
380 | ||
2fa45344 AF |
381 | /** |
382 | * cpu_is_stopped: | |
383 | * @cpu: The CPU to check. | |
384 | * | |
385 | * Checks whether the CPU is stopped. | |
386 | * | |
387 | * Returns: %true if run state is not running or if artificially stopped; | |
388 | * %false otherwise. | |
389 | */ | |
390 | bool cpu_is_stopped(CPUState *cpu); | |
391 | ||
f100f0b3 AF |
392 | /** |
393 | * run_on_cpu: | |
394 | * @cpu: The vCPU to run on. | |
395 | * @func: The function to be executed. | |
396 | * @data: Data to pass to the function. | |
397 | * | |
398 | * Schedules the function @func for execution on the vCPU @cpu. | |
399 | */ | |
400 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
401 | ||
3c02270d CV |
402 | /** |
403 | * async_run_on_cpu: | |
404 | * @cpu: The vCPU to run on. | |
405 | * @func: The function to be executed. | |
406 | * @data: Data to pass to the function. | |
407 | * | |
408 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
409 | */ | |
410 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
411 | ||
d6b9e0d6 MT |
412 | /** |
413 | * qemu_for_each_cpu: | |
414 | * @func: The function to be executed. | |
415 | * @data: Data to pass to the function. | |
416 | * | |
417 | * Executes @func for each CPU. | |
418 | */ | |
419 | void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data); | |
420 | ||
38d8f5c8 AF |
421 | /** |
422 | * qemu_get_cpu: | |
423 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
424 | * | |
425 | * Gets a CPU matching @index. | |
426 | * | |
427 | * Returns: The CPU or %NULL if there is no matching CPU. | |
428 | */ | |
429 | CPUState *qemu_get_cpu(int index); | |
430 | ||
69e5ff06 IM |
431 | /** |
432 | * cpu_exists: | |
433 | * @id: Guest-exposed CPU ID to lookup. | |
434 | * | |
435 | * Search for CPU with specified ID. | |
436 | * | |
437 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
438 | */ | |
439 | bool cpu_exists(int64_t id); | |
440 | ||
c3affe56 AF |
441 | #ifndef CONFIG_USER_ONLY |
442 | ||
443 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
444 | ||
445 | extern CPUInterruptHandler cpu_interrupt_handler; | |
446 | ||
447 | /** | |
448 | * cpu_interrupt: | |
449 | * @cpu: The CPU to set an interrupt on. | |
450 | * @mask: The interupts to set. | |
451 | * | |
452 | * Invokes the interrupt handler. | |
453 | */ | |
454 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
455 | { | |
456 | cpu_interrupt_handler(cpu, mask); | |
457 | } | |
458 | ||
459 | #else /* USER_ONLY */ | |
460 | ||
461 | void cpu_interrupt(CPUState *cpu, int mask); | |
462 | ||
463 | #endif /* USER_ONLY */ | |
464 | ||
c658b94f AF |
465 | #ifndef CONFIG_USER_ONLY |
466 | ||
467 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, | |
468 | bool is_write, bool is_exec, | |
469 | int opaque, unsigned size) | |
470 | { | |
471 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
472 | ||
473 | if (cc->do_unassigned_access) { | |
474 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
475 | } | |
476 | } | |
477 | ||
478 | #endif | |
479 | ||
d8ed887b AF |
480 | /** |
481 | * cpu_reset_interrupt: | |
482 | * @cpu: The CPU to clear the interrupt on. | |
483 | * @mask: The interrupt mask to clear. | |
484 | * | |
485 | * Resets interrupts on the vCPU @cpu. | |
486 | */ | |
487 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
488 | ||
60a3e17a AF |
489 | /** |
490 | * cpu_exit: | |
491 | * @cpu: The CPU to exit. | |
492 | * | |
493 | * Requests the CPU @cpu to exit execution. | |
494 | */ | |
495 | void cpu_exit(CPUState *cpu); | |
496 | ||
2993683b IM |
497 | /** |
498 | * cpu_resume: | |
499 | * @cpu: The CPU to resume. | |
500 | * | |
501 | * Resumes CPU, i.e. puts CPU into runnable state. | |
502 | */ | |
503 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 504 | |
c643bed9 AF |
505 | /** |
506 | * qemu_init_vcpu: | |
507 | * @cpu: The vCPU to initialize. | |
508 | * | |
509 | * Initializes a vCPU. | |
510 | */ | |
511 | void qemu_init_vcpu(CPUState *cpu); | |
512 | ||
3825b28f AF |
513 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
514 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
515 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
516 | ||
517 | /** | |
518 | * cpu_single_step: | |
519 | * @cpu: CPU to the flags for. | |
520 | * @enabled: Flags to enable. | |
521 | * | |
522 | * Enables or disables single-stepping for @cpu. | |
523 | */ | |
524 | void cpu_single_step(CPUState *cpu, int enabled); | |
525 | ||
1a1562f5 AF |
526 | #ifdef CONFIG_SOFTMMU |
527 | extern const struct VMStateDescription vmstate_cpu_common; | |
528 | #else | |
529 | #define vmstate_cpu_common vmstate_dummy | |
530 | #endif | |
531 | ||
532 | #define VMSTATE_CPU() { \ | |
533 | .name = "parent_obj", \ | |
534 | .size = sizeof(CPUState), \ | |
535 | .vmsd = &vmstate_cpu_common, \ | |
536 | .flags = VMS_STRUCT, \ | |
537 | .offset = 0, \ | |
538 | } | |
539 | ||
dd83b06a | 540 | #endif |