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1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
fcd7d003 23#include <signal.h>
961f8395 24#include "hw/qdev-core.h"
c658b94f 25#include "exec/hwaddr.h"
bdc44640 26#include "qemu/queue.h"
1de7afc9 27#include "qemu/thread.h"
4917cf44 28#include "qemu/tls.h"
a23bbfda 29#include "qemu/typedefs.h"
dd83b06a 30
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31typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
32
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33/**
34 * vaddr:
35 * Type wide enough to contain any #target_ulong virtual address.
36 */
37typedef uint64_t vaddr;
38#define VADDR_PRId PRId64
39#define VADDR_PRIu PRIu64
40#define VADDR_PRIo PRIo64
41#define VADDR_PRIx PRIx64
42#define VADDR_PRIX PRIX64
43#define VADDR_MAX UINT64_MAX
44
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45/**
46 * SECTION:cpu
47 * @section_id: QEMU-cpu
48 * @title: CPU Class
49 * @short_description: Base class for all CPUs
50 */
51
52#define TYPE_CPU "cpu"
53
54#define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
55#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
56#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
57
58typedef struct CPUState CPUState;
59
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60typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
61 bool is_write, bool is_exec, int opaque,
62 unsigned size);
63
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64struct TranslationBlock;
65
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66/**
67 * CPUClass:
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68 * @class_by_name: Callback to map -cpu command line model name to an
69 * instantiatable CPU type.
f5df5baf 70 * @reset: Callback to reset the #CPUState to its initial state.
91b1df8c 71 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
97a8ea5a 72 * @do_interrupt: Callback for interrupt handling.
c658b94f 73 * @do_unassigned_access: Callback for unassigned access handling.
f3659eee 74 * @memory_rw_debug: Callback for GDB memory access.
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75 * @dump_state: Callback for dumping state.
76 * @dump_statistics: Callback for dumping statistics.
997395d3 77 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
444d5590 78 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
a23bbfda 79 * @get_memory_mapping: Callback for obtaining the memory mappings.
f45748f1 80 * @set_pc: Callback for setting the Program Counter register.
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81 * @synchronize_from_tb: Callback for synchronizing state from a TCG
82 * #TranslationBlock.
00b941e5 83 * @get_phys_page_debug: Callback for obtaining a physical address.
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84 * @gdb_read_register: Callback for letting GDB read a register.
85 * @gdb_write_register: Callback for letting GDB write a register.
b170fce3 86 * @vmsd: State description for migration.
a0e372f0 87 * @gdb_num_core_regs: Number of core registers accessible to GDB.
5b24c641 88 * @gdb_core_xml_file: File name for core registers GDB XML description.
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89 *
90 * Represents a CPU family or model.
91 */
92typedef struct CPUClass {
93 /*< private >*/
961f8395 94 DeviceClass parent_class;
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95 /*< public >*/
96
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97 ObjectClass *(*class_by_name)(const char *cpu_model);
98
dd83b06a 99 void (*reset)(CPUState *cpu);
91b1df8c 100 int reset_dump_flags;
97a8ea5a 101 void (*do_interrupt)(CPUState *cpu);
c658b94f 102 CPUUnassignedAccess do_unassigned_access;
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103 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
104 uint8_t *buf, int len, bool is_write);
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105 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
106 int flags);
107 void (*dump_statistics)(CPUState *cpu, FILE *f,
108 fprintf_function cpu_fprintf, int flags);
997395d3 109 int64_t (*get_arch_id)(CPUState *cpu);
444d5590 110 bool (*get_paging_enabled)(const CPUState *cpu);
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111 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
112 Error **errp);
f45748f1 113 void (*set_pc)(CPUState *cpu, vaddr value);
bdf7ae5b 114 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
00b941e5 115 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
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116 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
117 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
b170fce3 118
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119 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
120 int cpuid, void *opaque);
121 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
122 void *opaque);
123 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
124 int cpuid, void *opaque);
125 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
126 void *opaque);
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127
128 const struct VMStateDescription *vmsd;
129 int gdb_num_core_regs;
5b24c641 130 const char *gdb_core_xml_file;
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131} CPUClass;
132
a60f24b5 133struct KVMState;
f7575c96 134struct kvm_run;
a60f24b5 135
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136/**
137 * CPUState:
55e5c285 138 * @cpu_index: CPU index (informative).
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139 * @nr_cores: Number of cores within this CPU package.
140 * @nr_threads: Number of threads within this CPU.
1b1ed8dc 141 * @numa_node: NUMA node this CPU is belonging to.
0d34282f 142 * @host_tid: Host thread ID.
0315c31c 143 * @running: #true if CPU is currently running (usermode).
61a46217 144 * @created: Indicates whether the CPU thread has been successfully created.
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145 * @interrupt_request: Indicates a pending interrupt request.
146 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 147 * @stop: Indicates a pending stop request.
f324e766 148 * @stopped: Indicates the CPU has been artificially stopped.
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149 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
150 * CPU and return to its top level loop.
ed2803da 151 * @singlestep_enabled: Flags for single-stepping.
c05efcb1 152 * @env_ptr: Pointer to subclass-specific CPUArchState field.
d77953b9 153 * @current_tb: Currently executing TB.
eac8b355 154 * @gdb_regs: Additional GDB registers.
a0e372f0 155 * @gdb_num_regs: Number of total registers accessible to GDB.
35143f01 156 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
182735ef 157 * @next_cpu: Next CPU sharing TB cache.
8737c51c 158 * @kvm_fd: vCPU file descriptor for KVM.
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159 *
160 * State of one CPU core or thread.
161 */
162struct CPUState {
163 /*< private >*/
961f8395 164 DeviceState parent_obj;
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165 /*< public >*/
166
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167 int nr_cores;
168 int nr_threads;
1b1ed8dc 169 int numa_node;
ce3960eb 170
814e612e 171 struct QemuThread *thread;
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172#ifdef _WIN32
173 HANDLE hThread;
174#endif
9f09e18a 175 int thread_id;
0d34282f 176 uint32_t host_tid;
0315c31c 177 bool running;
f5c121b8 178 struct QemuCond *halt_cond;
c64ca814 179 struct qemu_work_item *queued_work_first, *queued_work_last;
216fc9a4 180 bool thread_kicked;
61a46217 181 bool created;
4fdeee7c 182 bool stop;
f324e766 183 bool stopped;
fcd7d003 184 volatile sig_atomic_t exit_request;
378df4b2 185 volatile sig_atomic_t tcg_exit_req;
259186a7 186 uint32_t interrupt_request;
ed2803da 187 int singlestep_enabled;
bcba2a72 188
c05efcb1 189 void *env_ptr; /* CPUArchState */
d77953b9 190 struct TranslationBlock *current_tb;
eac8b355 191 struct GDBRegisterState *gdb_regs;
a0e372f0 192 int gdb_num_regs;
35143f01 193 int gdb_num_g_regs;
bdc44640 194 QTAILQ_ENTRY(CPUState) node;
d77953b9 195
8737c51c 196 int kvm_fd;
20d695a9 197 bool kvm_vcpu_dirty;
a60f24b5 198 struct KVMState *kvm_state;
f7575c96 199 struct kvm_run *kvm_run;
8737c51c 200
f5df5baf 201 /* TODO Move common fields from CPUArchState here. */
55e5c285 202 int cpu_index; /* used by alpha TCG */
259186a7 203 uint32_t halted; /* used by alpha, cris, ppc TCG */
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204};
205
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206QTAILQ_HEAD(CPUTailQ, CPUState);
207extern struct CPUTailQ cpus;
208#define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
209#define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
210#define CPU_FOREACH_SAFE(cpu, next_cpu) \
211 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
212#define first_cpu QTAILQ_FIRST(&cpus)
182735ef 213
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214DECLARE_TLS(CPUState *, current_cpu);
215#define current_cpu tls_var(current_cpu)
216
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217/**
218 * cpu_paging_enabled:
219 * @cpu: The CPU whose state is to be inspected.
220 *
221 * Returns: %true if paging is enabled, %false otherwise.
222 */
223bool cpu_paging_enabled(const CPUState *cpu);
224
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225/**
226 * cpu_get_memory_mapping:
227 * @cpu: The CPU whose memory mappings are to be obtained.
228 * @list: Where to write the memory mappings to.
229 * @errp: Pointer for reporting an #Error.
230 */
231void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
232 Error **errp);
233
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234/**
235 * cpu_write_elf64_note:
236 * @f: pointer to a function that writes memory to a file
237 * @cpu: The CPU whose memory is to be dumped
238 * @cpuid: ID number of the CPU
239 * @opaque: pointer to the CPUState struct
240 */
241int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
242 int cpuid, void *opaque);
243
244/**
245 * cpu_write_elf64_qemunote:
246 * @f: pointer to a function that writes memory to a file
247 * @cpu: The CPU whose memory is to be dumped
248 * @cpuid: ID number of the CPU
249 * @opaque: pointer to the CPUState struct
250 */
251int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
252 void *opaque);
253
254/**
255 * cpu_write_elf32_note:
256 * @f: pointer to a function that writes memory to a file
257 * @cpu: The CPU whose memory is to be dumped
258 * @cpuid: ID number of the CPU
259 * @opaque: pointer to the CPUState struct
260 */
261int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
262 int cpuid, void *opaque);
263
264/**
265 * cpu_write_elf32_qemunote:
266 * @f: pointer to a function that writes memory to a file
267 * @cpu: The CPU whose memory is to be dumped
268 * @cpuid: ID number of the CPU
269 * @opaque: pointer to the CPUState struct
270 */
271int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
272 void *opaque);
dd83b06a 273
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274/**
275 * CPUDumpFlags:
276 * @CPU_DUMP_CODE:
277 * @CPU_DUMP_FPU: dump FPU register state, not just integer
278 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
279 */
280enum CPUDumpFlags {
281 CPU_DUMP_CODE = 0x00010000,
282 CPU_DUMP_FPU = 0x00020000,
283 CPU_DUMP_CCOP = 0x00040000,
284};
285
286/**
287 * cpu_dump_state:
288 * @cpu: The CPU whose state is to be dumped.
289 * @f: File to dump to.
290 * @cpu_fprintf: Function to dump with.
291 * @flags: Flags what to dump.
292 *
293 * Dumps CPU state.
294 */
295void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
296 int flags);
297
298/**
299 * cpu_dump_statistics:
300 * @cpu: The CPU whose state is to be dumped.
301 * @f: File to dump to.
302 * @cpu_fprintf: Function to dump with.
303 * @flags: Flags what to dump.
304 *
305 * Dumps CPU statistics.
306 */
307void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
308 int flags);
309
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310#ifndef CONFIG_USER_ONLY
311/**
312 * cpu_get_phys_page_debug:
313 * @cpu: The CPU to obtain the physical page address for.
314 * @addr: The virtual address.
315 *
316 * Obtains the physical page corresponding to a virtual one.
317 * Use it only for debugging because no protection checks are done.
318 *
319 * Returns: Corresponding physical page address or -1 if no page found.
320 */
321static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
322{
323 CPUClass *cc = CPU_GET_CLASS(cpu);
324
325 return cc->get_phys_page_debug(cpu, addr);
326}
327#endif
328
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329/**
330 * cpu_reset:
331 * @cpu: The CPU whose state is to be reset.
332 */
333void cpu_reset(CPUState *cpu);
334
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335/**
336 * cpu_class_by_name:
337 * @typename: The CPU base type.
338 * @cpu_model: The model string without any parameters.
339 *
340 * Looks up a CPU #ObjectClass matching name @cpu_model.
341 *
342 * Returns: A #CPUClass or %NULL if not matching class is found.
343 */
344ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
345
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346/**
347 * qemu_cpu_has_work:
348 * @cpu: The vCPU to check.
349 *
350 * Checks whether the CPU has work to do.
351 *
352 * Returns: %true if the CPU has work, %false otherwise.
353 */
354bool qemu_cpu_has_work(CPUState *cpu);
355
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356/**
357 * qemu_cpu_is_self:
358 * @cpu: The vCPU to check against.
359 *
360 * Checks whether the caller is executing on the vCPU thread.
361 *
362 * Returns: %true if called from @cpu's thread, %false otherwise.
363 */
364bool qemu_cpu_is_self(CPUState *cpu);
365
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366/**
367 * qemu_cpu_kick:
368 * @cpu: The vCPU to kick.
369 *
370 * Kicks @cpu's thread.
371 */
372void qemu_cpu_kick(CPUState *cpu);
373
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374/**
375 * cpu_is_stopped:
376 * @cpu: The CPU to check.
377 *
378 * Checks whether the CPU is stopped.
379 *
380 * Returns: %true if run state is not running or if artificially stopped;
381 * %false otherwise.
382 */
383bool cpu_is_stopped(CPUState *cpu);
384
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385/**
386 * run_on_cpu:
387 * @cpu: The vCPU to run on.
388 * @func: The function to be executed.
389 * @data: Data to pass to the function.
390 *
391 * Schedules the function @func for execution on the vCPU @cpu.
392 */
393void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
394
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395/**
396 * async_run_on_cpu:
397 * @cpu: The vCPU to run on.
398 * @func: The function to be executed.
399 * @data: Data to pass to the function.
400 *
401 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
402 */
403void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
404
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405/**
406 * qemu_get_cpu:
407 * @index: The CPUState@cpu_index value of the CPU to obtain.
408 *
409 * Gets a CPU matching @index.
410 *
411 * Returns: The CPU or %NULL if there is no matching CPU.
412 */
413CPUState *qemu_get_cpu(int index);
414
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415/**
416 * cpu_exists:
417 * @id: Guest-exposed CPU ID to lookup.
418 *
419 * Search for CPU with specified ID.
420 *
421 * Returns: %true - CPU is found, %false - CPU isn't found.
422 */
423bool cpu_exists(int64_t id);
424
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425#ifndef CONFIG_USER_ONLY
426
427typedef void (*CPUInterruptHandler)(CPUState *, int);
428
429extern CPUInterruptHandler cpu_interrupt_handler;
430
431/**
432 * cpu_interrupt:
433 * @cpu: The CPU to set an interrupt on.
434 * @mask: The interupts to set.
435 *
436 * Invokes the interrupt handler.
437 */
438static inline void cpu_interrupt(CPUState *cpu, int mask)
439{
440 cpu_interrupt_handler(cpu, mask);
441}
442
443#else /* USER_ONLY */
444
445void cpu_interrupt(CPUState *cpu, int mask);
446
447#endif /* USER_ONLY */
448
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449#ifndef CONFIG_USER_ONLY
450
451static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
452 bool is_write, bool is_exec,
453 int opaque, unsigned size)
454{
455 CPUClass *cc = CPU_GET_CLASS(cpu);
456
457 if (cc->do_unassigned_access) {
458 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
459 }
460}
461
462#endif
463
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464/**
465 * cpu_reset_interrupt:
466 * @cpu: The CPU to clear the interrupt on.
467 * @mask: The interrupt mask to clear.
468 *
469 * Resets interrupts on the vCPU @cpu.
470 */
471void cpu_reset_interrupt(CPUState *cpu, int mask);
472
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473/**
474 * cpu_exit:
475 * @cpu: The CPU to exit.
476 *
477 * Requests the CPU @cpu to exit execution.
478 */
479void cpu_exit(CPUState *cpu);
480
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481/**
482 * cpu_resume:
483 * @cpu: The CPU to resume.
484 *
485 * Resumes CPU, i.e. puts CPU into runnable state.
486 */
487void cpu_resume(CPUState *cpu);
dd83b06a 488
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489/**
490 * qemu_init_vcpu:
491 * @cpu: The vCPU to initialize.
492 *
493 * Initializes a vCPU.
494 */
495void qemu_init_vcpu(CPUState *cpu);
496
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497#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
498#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
499#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
500
501/**
502 * cpu_single_step:
503 * @cpu: CPU to the flags for.
504 * @enabled: Flags to enable.
505 *
506 * Enables or disables single-stepping for @cpu.
507 */
508void cpu_single_step(CPUState *cpu, int enabled);
509
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510#ifdef CONFIG_SOFTMMU
511extern const struct VMStateDescription vmstate_cpu_common;
512#else
513#define vmstate_cpu_common vmstate_dummy
514#endif
515
516#define VMSTATE_CPU() { \
517 .name = "parent_obj", \
518 .size = sizeof(CPUState), \
519 .vmsd = &vmstate_cpu_common, \
520 .flags = VMS_STRUCT, \
521 .offset = 0, \
522}
523
dd83b06a 524#endif