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244ab90e AL |
1 | /* |
2 | * DMA helper functions | |
3 | * | |
4 | * Copyright (c) 2009 Red Hat | |
5 | * | |
6 | * This work is licensed under the terms of the GNU General Public License | |
7 | * (GNU GPL), version 2 or later. | |
8 | */ | |
9 | ||
10 | #ifndef DMA_H | |
11 | #define DMA_H | |
12 | ||
13 | #include <stdio.h> | |
022c62cb | 14 | #include "exec/memory.h" |
df32fd1c | 15 | #include "exec/address-spaces.h" |
1ad2134f | 16 | #include "hw/hw.h" |
737e150e | 17 | #include "block/block.h" |
9c17d615 | 18 | #include "sysemu/kvm.h" |
244ab90e | 19 | |
10dc8aef PB |
20 | typedef struct ScatterGatherEntry ScatterGatherEntry; |
21 | ||
43cf8ae6 DG |
22 | typedef enum { |
23 | DMA_DIRECTION_TO_DEVICE = 0, | |
24 | DMA_DIRECTION_FROM_DEVICE = 1, | |
25 | } DMADirection; | |
26 | ||
fead0c24 PB |
27 | struct QEMUSGList { |
28 | ScatterGatherEntry *sg; | |
29 | int nsg; | |
30 | int nalloc; | |
31 | size_t size; | |
df32fd1c | 32 | AddressSpace *as; |
fead0c24 PB |
33 | }; |
34 | ||
4be403c8 | 35 | #ifndef CONFIG_USER_ONLY |
d9d1055e | 36 | |
e5332e63 DG |
37 | /* |
38 | * When an IOMMU is present, bus addresses become distinct from | |
39 | * CPU/memory physical addresses and may be a different size. Because | |
40 | * the IOVA size depends more on the bus than on the platform, we more | |
41 | * or less have to treat these as 64-bit always to cover all (or at | |
42 | * least most) cases. | |
43 | */ | |
44 | typedef uint64_t dma_addr_t; | |
45 | ||
46 | #define DMA_ADDR_BITS 64 | |
47 | #define DMA_ADDR_FMT "%" PRIx64 | |
48 | ||
df32fd1c | 49 | static inline void dma_barrier(AddressSpace *as, DMADirection dir) |
7a0bac4d BH |
50 | { |
51 | /* | |
52 | * This is called before DMA read and write operations | |
53 | * unless the _relaxed form is used and is responsible | |
54 | * for providing some sane ordering of accesses vs | |
55 | * concurrently running VCPUs. | |
56 | * | |
57 | * Users of map(), unmap() or lower level st/ld_* | |
58 | * operations are responsible for providing their own | |
59 | * ordering via barriers. | |
60 | * | |
61 | * This primitive implementation does a simple smp_mb() | |
62 | * before each operation which provides pretty much full | |
63 | * ordering. | |
64 | * | |
65 | * A smarter implementation can be devised if needed to | |
66 | * use lighter barriers based on the direction of the | |
67 | * transfer, the DMA context, etc... | |
68 | */ | |
69 | if (kvm_enabled()) { | |
70 | smp_mb(); | |
71 | } | |
72 | } | |
73 | ||
d86a77f8 DG |
74 | /* Checks that the given range of addresses is valid for DMA. This is |
75 | * useful for certain cases, but usually you should just use | |
76 | * dma_memory_{read,write}() and check for errors */ | |
df32fd1c | 77 | static inline bool dma_memory_valid(AddressSpace *as, |
e5332e63 DG |
78 | dma_addr_t addr, dma_addr_t len, |
79 | DMADirection dir) | |
d86a77f8 | 80 | { |
df32fd1c | 81 | return address_space_access_valid(as, addr, len, |
24addbc7 | 82 | dir == DMA_DIRECTION_FROM_DEVICE); |
d86a77f8 DG |
83 | } |
84 | ||
df32fd1c | 85 | static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
86 | void *buf, dma_addr_t len, |
87 | DMADirection dir) | |
d86a77f8 | 88 | { |
df32fd1c | 89 | return address_space_rw(as, addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); |
d86a77f8 DG |
90 | } |
91 | ||
df32fd1c | 92 | static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
93 | void *buf, dma_addr_t len) |
94 | { | |
df32fd1c | 95 | return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
7a0bac4d BH |
96 | } |
97 | ||
df32fd1c | 98 | static inline int dma_memory_write_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
99 | const void *buf, dma_addr_t len) |
100 | { | |
df32fd1c | 101 | return dma_memory_rw_relaxed(as, addr, (void *)buf, len, |
7a0bac4d BH |
102 | DMA_DIRECTION_FROM_DEVICE); |
103 | } | |
104 | ||
df32fd1c | 105 | static inline int dma_memory_rw(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
106 | void *buf, dma_addr_t len, |
107 | DMADirection dir) | |
108 | { | |
df32fd1c | 109 | dma_barrier(as, dir); |
7a0bac4d | 110 | |
df32fd1c | 111 | return dma_memory_rw_relaxed(as, addr, buf, len, dir); |
7a0bac4d BH |
112 | } |
113 | ||
df32fd1c | 114 | static inline int dma_memory_read(AddressSpace *as, dma_addr_t addr, |
d86a77f8 DG |
115 | void *buf, dma_addr_t len) |
116 | { | |
df32fd1c | 117 | return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
d86a77f8 DG |
118 | } |
119 | ||
df32fd1c | 120 | static inline int dma_memory_write(AddressSpace *as, dma_addr_t addr, |
d86a77f8 DG |
121 | const void *buf, dma_addr_t len) |
122 | { | |
df32fd1c | 123 | return dma_memory_rw(as, addr, (void *)buf, len, |
d86a77f8 DG |
124 | DMA_DIRECTION_FROM_DEVICE); |
125 | } | |
126 | ||
df32fd1c | 127 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len); |
d86a77f8 | 128 | |
df32fd1c | 129 | static inline void *dma_memory_map(AddressSpace *as, |
d86a77f8 DG |
130 | dma_addr_t addr, dma_addr_t *len, |
131 | DMADirection dir) | |
132 | { | |
24addbc7 PB |
133 | hwaddr xlen = *len; |
134 | void *p; | |
135 | ||
df32fd1c | 136 | p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE); |
24addbc7 PB |
137 | *len = xlen; |
138 | return p; | |
d86a77f8 DG |
139 | } |
140 | ||
df32fd1c | 141 | static inline void dma_memory_unmap(AddressSpace *as, |
d86a77f8 DG |
142 | void *buffer, dma_addr_t len, |
143 | DMADirection dir, dma_addr_t access_len) | |
144 | { | |
df32fd1c | 145 | address_space_unmap(as, buffer, (hwaddr)len, |
24addbc7 | 146 | dir == DMA_DIRECTION_FROM_DEVICE, access_len); |
d86a77f8 DG |
147 | } |
148 | ||
149 | #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \ | |
df32fd1c | 150 | static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \ |
d86a77f8 DG |
151 | dma_addr_t addr) \ |
152 | { \ | |
153 | uint##_bits##_t val; \ | |
df32fd1c | 154 | dma_memory_read(as, addr, &val, (_bits) / 8); \ |
d86a77f8 DG |
155 | return _end##_bits##_to_cpu(val); \ |
156 | } \ | |
df32fd1c | 157 | static inline void st##_sname##_##_end##_dma(AddressSpace *as, \ |
d86a77f8 DG |
158 | dma_addr_t addr, \ |
159 | uint##_bits##_t val) \ | |
160 | { \ | |
161 | val = cpu_to_##_end##_bits(val); \ | |
df32fd1c | 162 | dma_memory_write(as, addr, &val, (_bits) / 8); \ |
d86a77f8 DG |
163 | } |
164 | ||
df32fd1c | 165 | static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr) |
d86a77f8 DG |
166 | { |
167 | uint8_t val; | |
168 | ||
df32fd1c | 169 | dma_memory_read(as, addr, &val, 1); |
d86a77f8 DG |
170 | return val; |
171 | } | |
172 | ||
df32fd1c | 173 | static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val) |
d86a77f8 | 174 | { |
df32fd1c | 175 | dma_memory_write(as, addr, &val, 1); |
d86a77f8 DG |
176 | } |
177 | ||
178 | DEFINE_LDST_DMA(uw, w, 16, le); | |
179 | DEFINE_LDST_DMA(l, l, 32, le); | |
180 | DEFINE_LDST_DMA(q, q, 64, le); | |
181 | DEFINE_LDST_DMA(uw, w, 16, be); | |
182 | DEFINE_LDST_DMA(l, l, 32, be); | |
183 | DEFINE_LDST_DMA(q, q, 64, be); | |
184 | ||
185 | #undef DEFINE_LDST_DMA | |
186 | ||
10dc8aef | 187 | struct ScatterGatherEntry { |
d3231181 DG |
188 | dma_addr_t base; |
189 | dma_addr_t len; | |
10dc8aef | 190 | }; |
244ab90e | 191 | |
df32fd1c | 192 | void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, AddressSpace *as); |
d3231181 | 193 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len); |
244ab90e | 194 | void qemu_sglist_destroy(QEMUSGList *qsg); |
10dc8aef | 195 | #endif |
244ab90e | 196 | |
cb144ccb CH |
197 | typedef BlockDriverAIOCB *DMAIOFunc(BlockDriverState *bs, int64_t sector_num, |
198 | QEMUIOVector *iov, int nb_sectors, | |
199 | BlockDriverCompletionFunc *cb, void *opaque); | |
200 | ||
201 | BlockDriverAIOCB *dma_bdrv_io(BlockDriverState *bs, | |
202 | QEMUSGList *sg, uint64_t sector_num, | |
203 | DMAIOFunc *io_func, BlockDriverCompletionFunc *cb, | |
43cf8ae6 | 204 | void *opaque, DMADirection dir); |
59a703eb AL |
205 | BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs, |
206 | QEMUSGList *sg, uint64_t sector, | |
207 | BlockDriverCompletionFunc *cb, void *opaque); | |
208 | BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs, | |
209 | QEMUSGList *sg, uint64_t sector, | |
210 | BlockDriverCompletionFunc *cb, void *opaque); | |
8171ee35 PB |
211 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg); |
212 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg); | |
213 | ||
84a69356 PB |
214 | void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie, |
215 | QEMUSGList *sg, enum BlockAcctType type); | |
216 | ||
244ab90e | 217 | #endif |