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Commit | Line | Data |
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32993977 IY |
1 | /* |
2 | * QEMU System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * splitted out ioport related stuffs from vl.c. | |
26 | */ | |
27 | ||
022c62cb | 28 | #include "exec/ioport.h" |
bd3c9aa5 | 29 | #include "trace.h" |
022c62cb | 30 | #include "exec/memory.h" |
32993977 IY |
31 | |
32 | /***********************************************************/ | |
33 | /* IO Port */ | |
34 | ||
35 | //#define DEBUG_UNUSED_IOPORT | |
36 | //#define DEBUG_IOPORT | |
37 | ||
fc7083b5 IY |
38 | #ifdef DEBUG_UNUSED_IOPORT |
39 | # define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) | |
40 | #else | |
41 | # define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0) | |
42 | #endif | |
43 | ||
32993977 IY |
44 | #ifdef DEBUG_IOPORT |
45 | # define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__) | |
46 | #else | |
47 | # define LOG_IOPORT(...) do { } while (0) | |
48 | #endif | |
49 | ||
50 | /* XXX: use a two level table to limit memory usage */ | |
51 | ||
52 | static void *ioport_opaque[MAX_IOPORTS]; | |
53 | static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS]; | |
54 | static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS]; | |
c5b703ac | 55 | static IOPortDestructor *ioport_destructor_table[MAX_IOPORTS]; |
32993977 IY |
56 | |
57 | static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl; | |
58 | static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel; | |
59 | ||
60 | static uint32_t ioport_read(int index, uint32_t address) | |
61 | { | |
1dde6fcc | 62 | static IOPortReadFunc * const default_func[3] = { |
32993977 IY |
63 | default_ioport_readb, |
64 | default_ioport_readw, | |
65 | default_ioport_readl | |
66 | }; | |
67 | IOPortReadFunc *func = ioport_read_table[index][address]; | |
68 | if (!func) | |
69 | func = default_func[index]; | |
70 | return func(ioport_opaque[address], address); | |
71 | } | |
72 | ||
73 | static void ioport_write(int index, uint32_t address, uint32_t data) | |
74 | { | |
1dde6fcc | 75 | static IOPortWriteFunc * const default_func[3] = { |
32993977 IY |
76 | default_ioport_writeb, |
77 | default_ioport_writew, | |
78 | default_ioport_writel | |
79 | }; | |
80 | IOPortWriteFunc *func = ioport_write_table[index][address]; | |
81 | if (!func) | |
82 | func = default_func[index]; | |
83 | func(ioport_opaque[address], address, data); | |
84 | } | |
85 | ||
86 | static uint32_t default_ioport_readb(void *opaque, uint32_t address) | |
87 | { | |
fc7083b5 | 88 | LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address); |
32993977 IY |
89 | return 0xff; |
90 | } | |
91 | ||
92 | static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data) | |
93 | { | |
fc7083b5 IY |
94 | LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n", |
95 | address, data); | |
32993977 IY |
96 | } |
97 | ||
98 | /* default is to make two byte accesses */ | |
99 | static uint32_t default_ioport_readw(void *opaque, uint32_t address) | |
100 | { | |
101 | uint32_t data; | |
102 | data = ioport_read(0, address); | |
d56dd6cf | 103 | address = (address + 1) & IOPORTS_MASK; |
32993977 IY |
104 | data |= ioport_read(0, address) << 8; |
105 | return data; | |
106 | } | |
107 | ||
108 | static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data) | |
109 | { | |
110 | ioport_write(0, address, data & 0xff); | |
d56dd6cf | 111 | address = (address + 1) & IOPORTS_MASK; |
32993977 IY |
112 | ioport_write(0, address, (data >> 8) & 0xff); |
113 | } | |
114 | ||
115 | static uint32_t default_ioport_readl(void *opaque, uint32_t address) | |
116 | { | |
fc7083b5 | 117 | LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address); |
32993977 IY |
118 | return 0xffffffff; |
119 | } | |
120 | ||
121 | static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data) | |
122 | { | |
fc7083b5 IY |
123 | LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n", |
124 | address, data); | |
32993977 IY |
125 | } |
126 | ||
23e0affd IY |
127 | static int ioport_bsize(int size, int *bsize) |
128 | { | |
129 | if (size == 1) { | |
130 | *bsize = 0; | |
131 | } else if (size == 2) { | |
132 | *bsize = 1; | |
133 | } else if (size == 4) { | |
134 | *bsize = 2; | |
135 | } else { | |
136 | return -1; | |
137 | } | |
138 | return 0; | |
139 | } | |
140 | ||
32993977 | 141 | /* size is the word size in byte */ |
8ab9b418 JK |
142 | static int register_ioport_read(pio_addr_t start, int length, int size, |
143 | IOPortReadFunc *func, void *opaque) | |
32993977 IY |
144 | { |
145 | int i, bsize; | |
146 | ||
23e0affd | 147 | if (ioport_bsize(size, &bsize)) { |
32993977 IY |
148 | hw_error("register_ioport_read: invalid size"); |
149 | return -1; | |
150 | } | |
bf3fb0e1 | 151 | for(i = start; i < start + length; ++i) { |
32993977 IY |
152 | ioport_read_table[bsize][i] = func; |
153 | if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) | |
f66a99d7 AF |
154 | hw_error("register_ioport_read: invalid opaque for address 0x%x", |
155 | i); | |
32993977 IY |
156 | ioport_opaque[i] = opaque; |
157 | } | |
158 | return 0; | |
159 | } | |
160 | ||
161 | /* size is the word size in byte */ | |
8ab9b418 JK |
162 | static int register_ioport_write(pio_addr_t start, int length, int size, |
163 | IOPortWriteFunc *func, void *opaque) | |
32993977 IY |
164 | { |
165 | int i, bsize; | |
166 | ||
23e0affd | 167 | if (ioport_bsize(size, &bsize)) { |
32993977 IY |
168 | hw_error("register_ioport_write: invalid size"); |
169 | return -1; | |
170 | } | |
bf3fb0e1 | 171 | for(i = start; i < start + length; ++i) { |
32993977 IY |
172 | ioport_write_table[bsize][i] = func; |
173 | if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) | |
f66a99d7 AF |
174 | hw_error("register_ioport_write: invalid opaque for address 0x%x", |
175 | i); | |
32993977 IY |
176 | ioport_opaque[i] = opaque; |
177 | } | |
178 | return 0; | |
179 | } | |
180 | ||
acd1c812 AK |
181 | static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr) |
182 | { | |
183 | IORange *ioport = opaque; | |
184 | uint64_t data; | |
185 | ||
186 | ioport->ops->read(ioport, addr - ioport->base, 1, &data); | |
187 | return data; | |
188 | } | |
189 | ||
190 | static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr) | |
191 | { | |
192 | IORange *ioport = opaque; | |
193 | uint64_t data; | |
194 | ||
195 | ioport->ops->read(ioport, addr - ioport->base, 2, &data); | |
196 | return data; | |
197 | } | |
198 | ||
199 | static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr) | |
200 | { | |
201 | IORange *ioport = opaque; | |
202 | uint64_t data; | |
203 | ||
204 | ioport->ops->read(ioport, addr - ioport->base, 4, &data); | |
205 | return data; | |
206 | } | |
207 | ||
208 | static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data) | |
209 | { | |
210 | IORange *ioport = opaque; | |
211 | ||
212 | ioport->ops->write(ioport, addr - ioport->base, 1, data); | |
213 | } | |
214 | ||
215 | static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data) | |
216 | { | |
217 | IORange *ioport = opaque; | |
218 | ||
219 | ioport->ops->write(ioport, addr - ioport->base, 2, data); | |
220 | } | |
221 | ||
222 | static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data) | |
223 | { | |
224 | IORange *ioport = opaque; | |
225 | ||
226 | ioport->ops->write(ioport, addr - ioport->base, 4, data); | |
227 | } | |
228 | ||
c5b703ac AK |
229 | static void iorange_destructor_thunk(void *opaque) |
230 | { | |
231 | IORange *iorange = opaque; | |
232 | ||
233 | if (iorange->ops->destructor) { | |
234 | iorange->ops->destructor(iorange); | |
235 | } | |
236 | } | |
237 | ||
acd1c812 AK |
238 | void ioport_register(IORange *ioport) |
239 | { | |
240 | register_ioport_read(ioport->base, ioport->len, 1, | |
241 | ioport_readb_thunk, ioport); | |
242 | register_ioport_read(ioport->base, ioport->len, 2, | |
243 | ioport_readw_thunk, ioport); | |
244 | register_ioport_read(ioport->base, ioport->len, 4, | |
245 | ioport_readl_thunk, ioport); | |
246 | register_ioport_write(ioport->base, ioport->len, 1, | |
247 | ioport_writeb_thunk, ioport); | |
248 | register_ioport_write(ioport->base, ioport->len, 2, | |
249 | ioport_writew_thunk, ioport); | |
250 | register_ioport_write(ioport->base, ioport->len, 4, | |
251 | ioport_writel_thunk, ioport); | |
c5b703ac | 252 | ioport_destructor_table[ioport->base] = iorange_destructor_thunk; |
acd1c812 AK |
253 | } |
254 | ||
c227f099 | 255 | void isa_unassign_ioport(pio_addr_t start, int length) |
32993977 IY |
256 | { |
257 | int i; | |
258 | ||
c5b703ac AK |
259 | if (ioport_destructor_table[start]) { |
260 | ioport_destructor_table[start](ioport_opaque[start]); | |
261 | ioport_destructor_table[start] = NULL; | |
262 | } | |
32993977 | 263 | for(i = start; i < start + length; i++) { |
6141dbfe PB |
264 | ioport_read_table[0][i] = NULL; |
265 | ioport_read_table[1][i] = NULL; | |
266 | ioport_read_table[2][i] = NULL; | |
32993977 | 267 | |
6141dbfe PB |
268 | ioport_write_table[0][i] = NULL; |
269 | ioport_write_table[1][i] = NULL; | |
270 | ioport_write_table[2][i] = NULL; | |
32993977 IY |
271 | |
272 | ioport_opaque[i] = NULL; | |
273 | } | |
274 | } | |
275 | ||
276 | /***********************************************************/ | |
277 | ||
c227f099 | 278 | void cpu_outb(pio_addr_t addr, uint8_t val) |
32993977 | 279 | { |
07323531 | 280 | LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); |
bd3c9aa5 | 281 | trace_cpu_out(addr, val); |
32993977 | 282 | ioport_write(0, addr, val); |
32993977 IY |
283 | } |
284 | ||
c227f099 | 285 | void cpu_outw(pio_addr_t addr, uint16_t val) |
32993977 | 286 | { |
07323531 | 287 | LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); |
bd3c9aa5 | 288 | trace_cpu_out(addr, val); |
32993977 | 289 | ioport_write(1, addr, val); |
32993977 IY |
290 | } |
291 | ||
c227f099 | 292 | void cpu_outl(pio_addr_t addr, uint32_t val) |
32993977 | 293 | { |
07323531 | 294 | LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); |
bd3c9aa5 | 295 | trace_cpu_out(addr, val); |
32993977 | 296 | ioport_write(2, addr, val); |
32993977 IY |
297 | } |
298 | ||
c227f099 | 299 | uint8_t cpu_inb(pio_addr_t addr) |
32993977 | 300 | { |
07323531 | 301 | uint8_t val; |
32993977 | 302 | val = ioport_read(0, addr); |
bd3c9aa5 | 303 | trace_cpu_in(addr, val); |
07323531 | 304 | LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); |
32993977 IY |
305 | return val; |
306 | } | |
307 | ||
c227f099 | 308 | uint16_t cpu_inw(pio_addr_t addr) |
32993977 | 309 | { |
07323531 | 310 | uint16_t val; |
32993977 | 311 | val = ioport_read(1, addr); |
bd3c9aa5 | 312 | trace_cpu_in(addr, val); |
07323531 | 313 | LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); |
32993977 IY |
314 | return val; |
315 | } | |
316 | ||
c227f099 | 317 | uint32_t cpu_inl(pio_addr_t addr) |
32993977 | 318 | { |
07323531 | 319 | uint32_t val; |
32993977 | 320 | val = ioport_read(2, addr); |
bd3c9aa5 | 321 | trace_cpu_in(addr, val); |
07323531 | 322 | LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); |
32993977 IY |
323 | return val; |
324 | } | |
6bf9fd43 AK |
325 | |
326 | void portio_list_init(PortioList *piolist, | |
327 | const MemoryRegionPortio *callbacks, | |
328 | void *opaque, const char *name) | |
329 | { | |
330 | unsigned n = 0; | |
331 | ||
332 | while (callbacks[n].size) { | |
333 | ++n; | |
334 | } | |
335 | ||
336 | piolist->ports = callbacks; | |
337 | piolist->nr = 0; | |
338 | piolist->regions = g_new0(MemoryRegion *, n); | |
de58ac72 | 339 | piolist->aliases = g_new0(MemoryRegion *, n); |
6bf9fd43 AK |
340 | piolist->address_space = NULL; |
341 | piolist->opaque = opaque; | |
342 | piolist->name = name; | |
343 | } | |
344 | ||
345 | void portio_list_destroy(PortioList *piolist) | |
346 | { | |
347 | g_free(piolist->regions); | |
de58ac72 | 348 | g_free(piolist->aliases); |
6bf9fd43 AK |
349 | } |
350 | ||
351 | static void portio_list_add_1(PortioList *piolist, | |
352 | const MemoryRegionPortio *pio_init, | |
353 | unsigned count, unsigned start, | |
354 | unsigned off_low, unsigned off_high) | |
355 | { | |
356 | MemoryRegionPortio *pio; | |
357 | MemoryRegionOps *ops; | |
de58ac72 | 358 | MemoryRegion *region, *alias; |
6bf9fd43 AK |
359 | unsigned i; |
360 | ||
361 | /* Copy the sub-list and null-terminate it. */ | |
362 | pio = g_new(MemoryRegionPortio, count + 1); | |
363 | memcpy(pio, pio_init, sizeof(MemoryRegionPortio) * count); | |
364 | memset(pio + count, 0, sizeof(MemoryRegionPortio)); | |
365 | ||
366 | /* Adjust the offsets to all be zero-based for the region. */ | |
367 | for (i = 0; i < count; ++i) { | |
368 | pio[i].offset -= off_low; | |
369 | } | |
370 | ||
371 | ops = g_new0(MemoryRegionOps, 1); | |
372 | ops->old_portio = pio; | |
373 | ||
374 | region = g_new(MemoryRegion, 1); | |
de58ac72 AK |
375 | alias = g_new(MemoryRegion, 1); |
376 | /* | |
377 | * Use an alias so that the callback is called with an absolute address, | |
378 | * rather than an offset relative to to start + off_low. | |
379 | */ | |
6bf9fd43 | 380 | memory_region_init_io(region, ops, piolist->opaque, piolist->name, |
4200872b | 381 | INT64_MAX); |
de58ac72 AK |
382 | memory_region_init_alias(alias, piolist->name, |
383 | region, start + off_low, off_high - off_low); | |
6bf9fd43 | 384 | memory_region_add_subregion(piolist->address_space, |
de58ac72 AK |
385 | start + off_low, alias); |
386 | piolist->regions[piolist->nr] = region; | |
387 | piolist->aliases[piolist->nr] = alias; | |
388 | ++piolist->nr; | |
6bf9fd43 AK |
389 | } |
390 | ||
391 | void portio_list_add(PortioList *piolist, | |
392 | MemoryRegion *address_space, | |
393 | uint32_t start) | |
394 | { | |
395 | const MemoryRegionPortio *pio, *pio_start = piolist->ports; | |
396 | unsigned int off_low, off_high, off_last, count; | |
397 | ||
398 | piolist->address_space = address_space; | |
399 | ||
400 | /* Handle the first entry specially. */ | |
401 | off_last = off_low = pio_start->offset; | |
402 | off_high = off_low + pio_start->len; | |
403 | count = 1; | |
404 | ||
405 | for (pio = pio_start + 1; pio->size != 0; pio++, count++) { | |
406 | /* All entries must be sorted by offset. */ | |
407 | assert(pio->offset >= off_last); | |
408 | off_last = pio->offset; | |
409 | ||
410 | /* If we see a hole, break the region. */ | |
411 | if (off_last > off_high) { | |
412 | portio_list_add_1(piolist, pio_start, count, start, off_low, | |
413 | off_high); | |
414 | /* ... and start collecting anew. */ | |
415 | pio_start = pio; | |
416 | off_low = off_last; | |
417 | off_high = off_low + pio->len; | |
418 | count = 0; | |
419 | } else if (off_last + pio->len > off_high) { | |
420 | off_high = off_last + pio->len; | |
421 | } | |
422 | } | |
423 | ||
424 | /* There will always be an open sub-list. */ | |
425 | portio_list_add_1(piolist, pio_start, count, start, off_low, off_high); | |
426 | } | |
427 | ||
428 | void portio_list_del(PortioList *piolist) | |
429 | { | |
de58ac72 | 430 | MemoryRegion *mr, *alias; |
6bf9fd43 AK |
431 | unsigned i; |
432 | ||
433 | for (i = 0; i < piolist->nr; ++i) { | |
434 | mr = piolist->regions[i]; | |
de58ac72 AK |
435 | alias = piolist->aliases[i]; |
436 | memory_region_del_subregion(piolist->address_space, alias); | |
437 | memory_region_destroy(alias); | |
6bf9fd43 AK |
438 | memory_region_destroy(mr); |
439 | g_free((MemoryRegionOps *)mr->ops); | |
440 | g_free(mr); | |
de58ac72 | 441 | g_free(alias); |
6bf9fd43 | 442 | piolist->regions[i] = NULL; |
de58ac72 | 443 | piolist->aliases[i] = NULL; |
6bf9fd43 AK |
444 | } |
445 | } |