[qemu.git] / linux-headers / asm-x86 / hyperv.h

#ifndef _ASM_X86_HYPERV_H
#define _ASM_X86_HYPERV_H

#include <linux/types.h>

/*
 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
 */
#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS	0x40000000
#define HYPERV_CPUID_INTERFACE			0x40000001
#define HYPERV_CPUID_VERSION			0x40000002
#define HYPERV_CPUID_FEATURES			0x40000003
#define HYPERV_CPUID_ENLIGHTMENT_INFO		0x40000004
#define HYPERV_CPUID_IMPLEMENT_LIMITS		0x40000005

#define HYPERV_HYPERVISOR_PRESENT_BIT		0x80000000
#define HYPERV_CPUID_MIN			0x40000005
#define HYPERV_CPUID_MAX			0x4000ffff

/*
 * Feature identification. EAX indicates which features are available
 * to the partition based upon the current partition privileges.
 */

/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
#define HV_X64_MSR_VP_RUNTIME_AVAILABLE		(1 << 0)
/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE	(1 << 1)
/*
 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
 */
#define HV_X64_MSR_SYNIC_AVAILABLE		(1 << 2)
/*
 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
 * HV_X64_MSR_STIMER3_COUNT) available
 */
#define HV_X64_MSR_SYNTIMER_AVAILABLE		(1 << 3)
/*
 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
 * are available
 */
#define HV_X64_MSR_APIC_ACCESS_AVAILABLE	(1 << 4)
/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
#define HV_X64_MSR_HYPERCALL_AVAILABLE		(1 << 5)
/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
#define HV_X64_MSR_VP_INDEX_AVAILABLE		(1 << 6)
/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
#define HV_X64_MSR_RESET_AVAILABLE		(1 << 7)
 /*
  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  */
#define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)

/*
 * Feature identification: EBX indicates which flags were specified at
 * partition creation. The format is the same as the partition creation
 * flag structure defined in section Partition Creation Flags.
 */
#define HV_X64_CREATE_PARTITIONS		(1 << 0)
#define HV_X64_ACCESS_PARTITION_ID		(1 << 1)
#define HV_X64_ACCESS_MEMORY_POOL		(1 << 2)
#define HV_X64_ADJUST_MESSAGE_BUFFERS		(1 << 3)
#define HV_X64_POST_MESSAGES			(1 << 4)
#define HV_X64_SIGNAL_EVENTS			(1 << 5)
#define HV_X64_CREATE_PORT			(1 << 6)
#define HV_X64_CONNECT_PORT			(1 << 7)
#define HV_X64_ACCESS_STATS			(1 << 8)
#define HV_X64_DEBUGGING			(1 << 11)
#define HV_X64_CPU_POWER_MANAGEMENT		(1 << 12)
#define HV_X64_CONFIGURE_PROFILER		(1 << 13)

/*
 * Feature identification. EDX indicates which miscellaneous features
 * are available to the partition.
 */
/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
#define HV_X64_MWAIT_AVAILABLE				(1 << 0)
/* Guest debugging support is available */
#define HV_X64_GUEST_DEBUGGING_AVAILABLE		(1 << 1)
/* Performance Monitor support is available*/
#define HV_X64_PERF_MONITOR_AVAILABLE			(1 << 2)
/* Support for physical CPU dynamic partitioning events is available*/
#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE	(1 << 3)
/*
 * Support for passing hypercall input parameter block via XMM
 * registers is available
 */
#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE		(1 << 4)
/* Support for a virtual guest idle state is available */
#define HV_X64_GUEST_IDLE_STATE_AVAILABLE		(1 << 5)

/*
 * Implementation recommendations. Indicates which behaviors the hypervisor
 * recommends the OS implement for optimal performance.
 */
 /*
  * Recommend using hypercall for address space switches rather
  * than MOV to CR3 instruction
  */
#define HV_X64_MWAIT_RECOMMENDED		(1 << 0)
/* Recommend using hypercall for local TLB flushes rather
 * than INVLPG or MOV to CR3 instructions */
#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED	(1 << 1)
/*
 * Recommend using hypercall for remote TLB flushes rather
 * than inter-processor interrupts
 */
#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED	(1 << 2)
/*
 * Recommend using MSRs for accessing APIC registers
 * EOI, ICR and TPR rather than their memory-mapped counterparts
 */
#define HV_X64_APIC_ACCESS_RECOMMENDED		(1 << 3)
/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
#define HV_X64_SYSTEM_RESET_RECOMMENDED		(1 << 4)
/*
 * Recommend using relaxed timing for this partition. If used,
 * the VM should disable any watchdog timeouts that rely on the
 * timely delivery of external interrupts
 */
#define HV_X64_RELAXED_TIMING_RECOMMENDED	(1 << 5)

/* MSR used to identify the guest OS. */
#define HV_X64_MSR_GUEST_OS_ID			0x40000000

/* MSR used to setup pages used to communicate with the hypervisor. */
#define HV_X64_MSR_HYPERCALL			0x40000001

/* MSR used to provide vcpu index */
#define HV_X64_MSR_VP_INDEX			0x40000002

/* MSR used to read the per-partition time reference counter */
#define HV_X64_MSR_TIME_REF_COUNT		0x40000020

/* Define the virtual APIC registers */
#define HV_X64_MSR_EOI				0x40000070
#define HV_X64_MSR_ICR				0x40000071
#define HV_X64_MSR_TPR				0x40000072
#define HV_X64_MSR_APIC_ASSIST_PAGE		0x40000073

/* Define synthetic interrupt controller model specific registers. */
#define HV_X64_MSR_SCONTROL			0x40000080
#define HV_X64_MSR_SVERSION			0x40000081
#define HV_X64_MSR_SIEFP			0x40000082
#define HV_X64_MSR_SIMP				0x40000083
#define HV_X64_MSR_EOM				0x40000084
#define HV_X64_MSR_SINT0			0x40000090
#define HV_X64_MSR_SINT1			0x40000091
#define HV_X64_MSR_SINT2			0x40000092
#define HV_X64_MSR_SINT3			0x40000093
#define HV_X64_MSR_SINT4			0x40000094
#define HV_X64_MSR_SINT5			0x40000095
#define HV_X64_MSR_SINT6			0x40000096
#define HV_X64_MSR_SINT7			0x40000097
#define HV_X64_MSR_SINT8			0x40000098
#define HV_X64_MSR_SINT9			0x40000099
#define HV_X64_MSR_SINT10			0x4000009A
#define HV_X64_MSR_SINT11			0x4000009B
#define HV_X64_MSR_SINT12			0x4000009C
#define HV_X64_MSR_SINT13			0x4000009D
#define HV_X64_MSR_SINT14			0x4000009E
#define HV_X64_MSR_SINT15			0x4000009F


#define HV_X64_MSR_HYPERCALL_ENABLE		0x00000001
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT	12
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK	\
		(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))

/* Declare the various hypercall operations. */
#define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT		0x0008

#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE		0x00000001
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT	12
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK	\
		(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))

#define HV_PROCESSOR_POWER_STATE_C0		0
#define HV_PROCESSOR_POWER_STATE_C1		1
#define HV_PROCESSOR_POWER_STATE_C2		2
#define HV_PROCESSOR_POWER_STATE_C3		3

/* hypercall status code */
#define HV_STATUS_SUCCESS			0
#define HV_STATUS_INVALID_HYPERCALL_CODE	2
#define HV_STATUS_INVALID_HYPERCALL_INPUT	3
#define HV_STATUS_INVALID_ALIGNMENT		4
#define HV_STATUS_INSUFFICIENT_BUFFERS		19

#endif
Commit	Line	Data
51b24e34 JK	1	#ifndef _ASM_X86_HYPERV_H
	2	#define _ASM_X86_HYPERV_H
	3
	4	#include <linux/types.h>
	5
	6	/*
	7	* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
	8	* is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
	9	*/
	10	#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
	11	#define HYPERV_CPUID_INTERFACE 0x40000001
	12	#define HYPERV_CPUID_VERSION 0x40000002
	13	#define HYPERV_CPUID_FEATURES 0x40000003
	14	#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
	15	#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
	16
	17	#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
	18	#define HYPERV_CPUID_MIN 0x40000005
	19	#define HYPERV_CPUID_MAX 0x4000ffff
	20
	21	/*
	22	* Feature identification. EAX indicates which features are available
	23	* to the partition based upon the current partition privileges.
	24	*/
	25
	26	/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
	27	#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
	28	/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
	29	#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
	30	/*
	31	* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
	32	* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
	33	*/
	34	#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
	35	/*
	36	* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
	37	* HV_X64_MSR_STIMER3_COUNT) available
	38	*/
	39	#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
	40	/*
	41	* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
	42	* are available
	43	*/
	44	#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
	45	/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
	46	#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
	47	/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
	48	#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
	49	/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
	50	#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
	51	/*
	52	* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
	53	* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
	54	* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
	55	*/
	56	#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
	57
	58	/*
	59	* Feature identification: EBX indicates which flags were specified at
	60	* partition creation. The format is the same as the partition creation
	61	* flag structure defined in section Partition Creation Flags.
	62	*/
	63	#define HV_X64_CREATE_PARTITIONS (1 << 0)
	64	#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
65	#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
66	#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
67	#define HV_X64_POST_MESSAGES (1 << 4)
68	#define HV_X64_SIGNAL_EVENTS (1 << 5)
69	#define HV_X64_CREATE_PORT (1 << 6)
70	#define HV_X64_CONNECT_PORT (1 << 7)
71	#define HV_X64_ACCESS_STATS (1 << 8)
72	#define HV_X64_DEBUGGING (1 << 11)
73	#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
74	#define HV_X64_CONFIGURE_PROFILER (1 << 13)
75
76	/*
77	* Feature identification. EDX indicates which miscellaneous features
78	* are available to the partition.
79	*/
80	/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
81	#define HV_X64_MWAIT_AVAILABLE (1 << 0)
82	/* Guest debugging support is available */
83	#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
84	/* Performance Monitor support is available*/
85	#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
86	/* Support for physical CPU dynamic partitioning events is available*/
87	#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
88	/*
89	* Support for passing hypercall input parameter block via XMM
90	* registers is available
91	*/
92	#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
93	/* Support for a virtual guest idle state is available */
94	#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
95
96	/*
97	* Implementation recommendations. Indicates which behaviors the hypervisor
98	* recommends the OS implement for optimal performance.
99	*/
100	/*
101	* Recommend using hypercall for address space switches rather
102	* than MOV to CR3 instruction
103	*/
104	#define HV_X64_MWAIT_RECOMMENDED (1 << 0)
105	/* Recommend using hypercall for local TLB flushes rather
106	* than INVLPG or MOV to CR3 instructions */
107	#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
108	/*
109	* Recommend using hypercall for remote TLB flushes rather
110	* than inter-processor interrupts
111	*/
112	#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
113	/*
114	* Recommend using MSRs for accessing APIC registers
115	* EOI, ICR and TPR rather than their memory-mapped counterparts
116	*/
117	#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
118	/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
119	#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
120	/*
121	* Recommend using relaxed timing for this partition. If used,
122	* the VM should disable any watchdog timeouts that rely on the
123	* timely delivery of external interrupts
124	*/
125	#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
126
127	/* MSR used to identify the guest OS. */
128	#define HV_X64_MSR_GUEST_OS_ID 0x40000000
129
130	/* MSR used to setup pages used to communicate with the hypervisor. */
131	#define HV_X64_MSR_HYPERCALL 0x40000001
132
133	/* MSR used to provide vcpu index */
134	#define HV_X64_MSR_VP_INDEX 0x40000002
135
136	/* MSR used to read the per-partition time reference counter */
137	#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
138
139	/* Define the virtual APIC registers */
140	#define HV_X64_MSR_EOI 0x40000070
141	#define HV_X64_MSR_ICR 0x40000071
142	#define HV_X64_MSR_TPR 0x40000072
143	#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
144
145	/* Define synthetic interrupt controller model specific registers. */
146	#define HV_X64_MSR_SCONTROL 0x40000080
147	#define HV_X64_MSR_SVERSION 0x40000081
148	#define HV_X64_MSR_SIEFP 0x40000082
149	#define HV_X64_MSR_SIMP 0x40000083
150	#define HV_X64_MSR_EOM 0x40000084
151	#define HV_X64_MSR_SINT0 0x40000090
152	#define HV_X64_MSR_SINT1 0x40000091
153	#define HV_X64_MSR_SINT2 0x40000092
154	#define HV_X64_MSR_SINT3 0x40000093
155	#define HV_X64_MSR_SINT4 0x40000094
156	#define HV_X64_MSR_SINT5 0x40000095
157	#define HV_X64_MSR_SINT6 0x40000096
158	#define HV_X64_MSR_SINT7 0x40000097
159	#define HV_X64_MSR_SINT8 0x40000098
160	#define HV_X64_MSR_SINT9 0x40000099
161	#define HV_X64_MSR_SINT10 0x4000009A
162	#define HV_X64_MSR_SINT11 0x4000009B
163	#define HV_X64_MSR_SINT12 0x4000009C
164	#define HV_X64_MSR_SINT13 0x4000009D
165	#define HV_X64_MSR_SINT14 0x4000009E
166	#define HV_X64_MSR_SINT15 0x4000009F
167
168
169	#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
170	#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
171	#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
172	(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
173
174	/* Declare the various hypercall operations. */
175	#define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT 0x0008
176
177	#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
178	#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
179	#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
180	(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
181
182	#define HV_PROCESSOR_POWER_STATE_C0 0
183	#define HV_PROCESSOR_POWER_STATE_C1 1
184	#define HV_PROCESSOR_POWER_STATE_C2 2
185	#define HV_PROCESSOR_POWER_STATE_C3 3
186
187	/* hypercall status code */
188	#define HV_STATUS_SUCCESS 0
189	#define HV_STATUS_INVALID_HYPERCALL_CODE 2
190	#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
191	#define HV_STATUS_INVALID_ALIGNMENT 4
1529ae1b	192	#define HV_STATUS_INSUFFICIENT_BUFFERS 19
51b24e34 JK	193
51b24e34 JK	194	#endif