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Merge remote-tracking branch 'qemu-kvm/uq/master' into stable-1.5
[qemu.git] / linux-user / main.c
CommitLineData
31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
45const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 72const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
d5975363
PB		 95/***********************************************************/
96/* Helper routines for implementing atomic operations. */
97
98/* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
c2764719 102static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 103static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106static int pending_cpus;
107
108/* Make sure everything is in a consistent state for calling fork(). */
109void fork_start(void)
110{
5e5f07e0 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 112 pthread_mutex_lock(&exclusive_lock);
d032d1b4 113 mmap_fork_start();
d5975363
PB		 114}
115
116void fork_end(int child)
117{
d032d1b4 118 mmap_fork_end(child);
d5975363
PB		 119 if (child) {
120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
a2247f8e 122 first_cpu = thread_cpu;
182735ef 123 first_cpu->next_cpu = NULL;
d5975363
PB		 124 pending_cpus = 0;
125 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 126 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 127 pthread_cond_init(&exclusive_cond, NULL);
128 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 129 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 130 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 131 } else {
132 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 133 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 134 }
d5975363
PB		 135}
136
137/* Wait for pending exclusive operations to complete. The exclusive lock
138 must be held. */
139static inline void exclusive_idle(void)
140{
141 while (pending_cpus) {
142 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
143 }
144}
145
146/* Start an exclusive operation.
147 Must only be called from outside cpu_arm_exec. */
148static inline void start_exclusive(void)
149{
0315c31c
AF		 150 CPUState *other_cpu;
151
d5975363
PB		 152 pthread_mutex_lock(&exclusive_lock);
153 exclusive_idle();
154
155 pending_cpus = 1;
156 /* Make all other cpus stop executing. */
182735ef 157 for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) {
0315c31c 158 if (other_cpu->running) {
d5975363 159 pending_cpus++;
60a3e17a 160 cpu_exit(other_cpu);
d5975363
PB		 161 }
162 }
163 if (pending_cpus > 1) {
164 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
165 }
166}
167
168/* Finish an exclusive operation. */
169static inline void end_exclusive(void)
170{
171 pending_cpus = 0;
172 pthread_cond_broadcast(&exclusive_resume);
173 pthread_mutex_unlock(&exclusive_lock);
174}
175
176/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 177static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 178{
179 pthread_mutex_lock(&exclusive_lock);
180 exclusive_idle();
0315c31c 181 cpu->running = true;
d5975363
PB		 182 pthread_mutex_unlock(&exclusive_lock);
183}
184
185/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 186static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 187{
188 pthread_mutex_lock(&exclusive_lock);
0315c31c 189 cpu->running = false;
d5975363
PB		 190 if (pending_cpus > 1) {
191 pending_cpus--;
192 if (pending_cpus == 1) {
193 pthread_cond_signal(&exclusive_cond);
194 }
195 }
196 exclusive_idle();
197 pthread_mutex_unlock(&exclusive_lock);
198}
c2764719
PB		 199
200void cpu_list_lock(void)
201{
202 pthread_mutex_lock(&cpu_list_mutex);
203}
204
205void cpu_list_unlock(void)
206{
207 pthread_mutex_unlock(&cpu_list_mutex);
208}
d5975363
PB		 209
210
a541f297
FB		 211#ifdef TARGET_I386
212/***********************************************************/
213/* CPUX86 core interface */
214
05390248 215void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 216{
217}
218
28ab0e2e
FB		 219uint64_t cpu_get_tsc(CPUX86State *env)
220{
221 return cpu_get_real_ticks();
222}
223
5fafdf24 224static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 225 int flags)
6dbad63e 226{
f4beb510 227 unsigned int e1, e2;
53a5960a 228 uint32_t *p;
6dbad63e
FB		 229 e1 = (addr << 16) | (limit & 0xffff);
230 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 231 e2 |= flags;
53a5960a 232 p = ptr;
d538e8f5 233 p[0] = tswap32(e1);
234 p[1] = tswap32(e2);
f4beb510
FB		 235}
236
e441570f 237static uint64_t *idt_table;
eb38c52c 238#ifdef TARGET_X86_64
d2fd1af7
FB		 239static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
240 uint64_t addr, unsigned int sel)
f4beb510 241{
4dbc422b 242 uint32_t *p, e1, e2;
f4beb510
FB		 243 e1 = (addr & 0xffff) | (sel << 16);
244 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 245 p = ptr;
4dbc422b
FB		 246 p[0] = tswap32(e1);
247 p[1] = tswap32(e2);
248 p[2] = tswap32(addr >> 32);
249 p[3] = 0;
6dbad63e 250}
d2fd1af7
FB		 251/* only dpl matters as we do only user space emulation */
252static void set_idt(int n, unsigned int dpl)
253{
254 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
255}
256#else
d2fd1af7
FB		 257static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
258 uint32_t addr, unsigned int sel)
259{
4dbc422b 260 uint32_t *p, e1, e2;
d2fd1af7
FB		 261 e1 = (addr & 0xffff) | (sel << 16);
262 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
263 p = ptr;
4dbc422b
FB		 264 p[0] = tswap32(e1);
265 p[1] = tswap32(e2);
d2fd1af7
FB		 266}
267
f4beb510
FB		 268/* only dpl matters as we do only user space emulation */
269static void set_idt(int n, unsigned int dpl)
270{
271 set_gate(idt_table + n, 0, dpl, 0, 0);
272}
d2fd1af7 273#endif
31e31b8a 274
89e957e7 275void cpu_loop(CPUX86State *env)
1b6b029e 276{
db6b81d4 277 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 278 int trapnr;
992f48a0 279 abi_ulong pc;
c227f099 280 target_siginfo_t info;
851e67a1 281
1b6b029e 282 for(;;) {
bc8a22cc 283 trapnr = cpu_x86_exec(env);
bc8a22cc 284 switch(trapnr) {
f4beb510 285 case 0x80:
d2fd1af7 286 /* linux syscall from int $0x80 */
5fafdf24
TS		 287 env->regs[R_EAX] = do_syscall(env,
288 env->regs[R_EAX],
f4beb510
FB		 289 env->regs[R_EBX],
290 env->regs[R_ECX],
291 env->regs[R_EDX],
292 env->regs[R_ESI],
293 env->regs[R_EDI],
5945cfcb
PM		 294 env->regs[R_EBP],
295 0, 0);
f4beb510 296 break;
d2fd1af7
FB		 297#ifndef TARGET_ABI32
298 case EXCP_SYSCALL:
5ba18547 299 /* linux syscall from syscall instruction */
d2fd1af7
FB		 300 env->regs[R_EAX] = do_syscall(env,
301 env->regs[R_EAX],
302 env->regs[R_EDI],
303 env->regs[R_ESI],
304 env->regs[R_EDX],
305 env->regs[10],
306 env->regs[8],
5945cfcb
PM		 307 env->regs[9],
308 0, 0);
d2fd1af7
FB		 309 env->eip = env->exception_next_eip;
310 break;
311#endif
f4beb510
FB		 312 case EXCP0B_NOSEG:
313 case EXCP0C_STACK:
314 info.si_signo = SIGBUS;
315 info.si_errno = 0;
316 info.si_code = TARGET_SI_KERNEL;
317 info._sifields._sigfault._addr = 0;
624f7979 318 queue_signal(env, info.si_signo, &info);
f4beb510 319 break;
1b6b029e 320 case EXCP0D_GPF:
d2fd1af7 321 /* XXX: potential problem if ABI32 */
84409ddb 322#ifndef TARGET_X86_64
851e67a1 323 if (env->eflags & VM_MASK) {
89e957e7 324 handle_vm86_fault(env);
84409ddb
JM		 325 } else
326#endif
327 {
f4beb510
FB		 328 info.si_signo = SIGSEGV;
329 info.si_errno = 0;
330 info.si_code = TARGET_SI_KERNEL;
331 info._sifields._sigfault._addr = 0;
624f7979 332 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 333 }
334 break;
b689bc57
FB		 335 case EXCP0E_PAGE:
336 info.si_signo = SIGSEGV;
337 info.si_errno = 0;
338 if (!(env->error_code & 1))
339 info.si_code = TARGET_SEGV_MAPERR;
340 else
341 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 342 info._sifields._sigfault._addr = env->cr[2];
624f7979 343 queue_signal(env, info.si_signo, &info);
b689bc57 344 break;
9de5e440 345 case EXCP00_DIVZ:
84409ddb 346#ifndef TARGET_X86_64
bc8a22cc 347 if (env->eflags & VM_MASK) {
447db213 348 handle_vm86_trap(env, trapnr);
84409ddb
JM		 349 } else
350#endif
351 {
bc8a22cc
FB		 352 /* division by zero */
353 info.si_signo = SIGFPE;
354 info.si_errno = 0;
355 info.si_code = TARGET_FPE_INTDIV;
356 info._sifields._sigfault._addr = env->eip;
624f7979 357 queue_signal(env, info.si_signo, &info);
bc8a22cc 358 }
9de5e440 359 break;
01df040b 360 case EXCP01_DB:
447db213 361 case EXCP03_INT3:
84409ddb 362#ifndef TARGET_X86_64
447db213
FB		 363 if (env->eflags & VM_MASK) {
364 handle_vm86_trap(env, trapnr);
84409ddb
JM		 365 } else
366#endif
367 {
447db213
FB		 368 info.si_signo = SIGTRAP;
369 info.si_errno = 0;
01df040b 370 if (trapnr == EXCP01_DB) {
447db213
FB		 371 info.si_code = TARGET_TRAP_BRKPT;
372 info._sifields._sigfault._addr = env->eip;
373 } else {
374 info.si_code = TARGET_SI_KERNEL;
375 info._sifields._sigfault._addr = 0;
376 }
624f7979 377 queue_signal(env, info.si_signo, &info);
447db213
FB		 378 }
379 break;
9de5e440
FB		 380 case EXCP04_INTO:
381 case EXCP05_BOUND:
84409ddb 382#ifndef TARGET_X86_64
bc8a22cc 383 if (env->eflags & VM_MASK) {
447db213 384 handle_vm86_trap(env, trapnr);
84409ddb
JM		 385 } else
386#endif
387 {
bc8a22cc
FB		 388 info.si_signo = SIGSEGV;
389 info.si_errno = 0;
b689bc57 390 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 391 info._sifields._sigfault._addr = 0;
624f7979 392 queue_signal(env, info.si_signo, &info);
bc8a22cc 393 }
9de5e440
FB		 394 break;
395 case EXCP06_ILLOP:
396 info.si_signo = SIGILL;
397 info.si_errno = 0;
398 info.si_code = TARGET_ILL_ILLOPN;
399 info._sifields._sigfault._addr = env->eip;
624f7979 400 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 401 break;
402 case EXCP_INTERRUPT:
403 /* just indicate that signals should be handled asap */
404 break;
1fddef4b
FB		 405 case EXCP_DEBUG:
406 {
407 int sig;
408
db6b81d4 409 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 410 if (sig)
411 {
412 info.si_signo = sig;
413 info.si_errno = 0;
414 info.si_code = TARGET_TRAP_BRKPT;
624f7979 415 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 416 }
417 }
418 break;
1b6b029e 419 default:
970a87a6 420 pc = env->segs[R_CS].base + env->eip;
5fafdf24 421 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 422 (long)pc, trapnr);
1b6b029e
FB		 423 abort();
424 }
66fb9763 425 process_pending_signals(env);
1b6b029e
FB		 426 }
427}
b346ff46
FB		 428#endif
429
430#ifdef TARGET_ARM
431
d8fd2954
PB		 432#define get_user_code_u32(x, gaddr, doswap) \
433 ({ abi_long __r = get_user_u32((x), (gaddr)); \
434 if (!__r && (doswap)) { \
435 (x) = bswap32(x); \
436 } \
437 __r; \
438 })
439
440#define get_user_code_u16(x, gaddr, doswap) \
441 ({ abi_long __r = get_user_u16((x), (gaddr)); \
442 if (!__r && (doswap)) { \
443 (x) = bswap16(x); \
444 } \
445 __r; \
446 })
447
97cc7560
DDAG		 448/*
449 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
450 * Input:
451 * r0 = pointer to oldval
452 * r1 = pointer to newval
453 * r2 = pointer to target value
454 *
455 * Output:
456 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
457 * C set if *ptr was changed, clear if no exchange happened
458 *
459 * Note segv's in kernel helpers are a bit tricky, we can set the
460 * data address sensibly but the PC address is just the entry point.
461 */
462static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
463{
464 uint64_t oldval, newval, val;
465 uint32_t addr, cpsr;
466 target_siginfo_t info;
467
468 /* Based on the 32 bit code in do_kernel_trap */
469
470 /* XXX: This only works between threads, not between processes.
471 It's probably possible to implement this with native host
472 operations. However things like ldrex/strex are much harder so
473 there's not much point trying. */
474 start_exclusive();
475 cpsr = cpsr_read(env);
476 addr = env->regs[2];
477
478 if (get_user_u64(oldval, env->regs[0])) {
479 env->cp15.c6_data = env->regs[0];
480 goto segv;
481 };
482
483 if (get_user_u64(newval, env->regs[1])) {
484 env->cp15.c6_data = env->regs[1];
485 goto segv;
486 };
487
488 if (get_user_u64(val, addr)) {
489 env->cp15.c6_data = addr;
490 goto segv;
491 }
492
493 if (val == oldval) {
494 val = newval;
495
496 if (put_user_u64(val, addr)) {
497 env->cp15.c6_data = addr;
498 goto segv;
499 };
500
501 env->regs[0] = 0;
502 cpsr |= CPSR_C;
503 } else {
504 env->regs[0] = -1;
505 cpsr &= ~CPSR_C;
506 }
507 cpsr_write(env, cpsr, CPSR_C);
508 end_exclusive();
509 return;
510
511segv:
512 end_exclusive();
513 /* We get the PC of the entry address - which is as good as anything,
514 on a real kernel what you get depends on which mode it uses. */
515 info.si_signo = SIGSEGV;
516 info.si_errno = 0;
517 /* XXX: check env->error_code */
518 info.si_code = TARGET_SEGV_MAPERR;
519 info._sifields._sigfault._addr = env->cp15.c6_data;
520 queue_signal(env, info.si_signo, &info);
521
522 end_exclusive();
523}
524
fbb4a2e3
PB		 525/* Handle a jump to the kernel code page. */
526static int
527do_kernel_trap(CPUARMState *env)
528{
529 uint32_t addr;
530 uint32_t cpsr;
531 uint32_t val;
532
533 switch (env->regs[15]) {
534 case 0xffff0fa0: /* __kernel_memory_barrier */
535 /* ??? No-op. Will need to do better for SMP. */
536 break;
537 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 538 /* XXX: This only works between threads, not between processes.
539 It's probably possible to implement this with native host
540 operations. However things like ldrex/strex are much harder so
541 there's not much point trying. */
542 start_exclusive();
fbb4a2e3
PB		 543 cpsr = cpsr_read(env);
544 addr = env->regs[2];
545 /* FIXME: This should SEGV if the access fails. */
546 if (get_user_u32(val, addr))
547 val = ~env->regs[0];
548 if (val == env->regs[0]) {
549 val = env->regs[1];
550 /* FIXME: Check for segfaults. */
551 put_user_u32(val, addr);
552 env->regs[0] = 0;
553 cpsr |= CPSR_C;
554 } else {
555 env->regs[0] = -1;
556 cpsr &= ~CPSR_C;
557 }
558 cpsr_write(env, cpsr, CPSR_C);
d5975363 559 end_exclusive();
fbb4a2e3
PB		 560 break;
561 case 0xffff0fe0: /* __kernel_get_tls */
562 env->regs[0] = env->cp15.c13_tls2;
563 break;
97cc7560
DDAG		 564 case 0xffff0f60: /* __kernel_cmpxchg64 */
565 arm_kernel_cmpxchg64_helper(env);
566 break;
567
fbb4a2e3
PB		 568 default:
569 return 1;
570 }
571 /* Jump back to the caller. */
572 addr = env->regs[14];
573 if (addr & 1) {
574 env->thumb = 1;
575 addr &= ~1;
576 }
577 env->regs[15] = addr;
578
579 return 0;
580}
581
426f5abc
PB		 582static int do_strex(CPUARMState *env)
583{
584 uint32_t val;
585 int size;
586 int rc = 1;
587 int segv = 0;
588 uint32_t addr;
589 start_exclusive();
590 addr = env->exclusive_addr;
591 if (addr != env->exclusive_test) {
592 goto fail;
593 }
594 size = env->exclusive_info & 0xf;
595 switch (size) {
596 case 0:
597 segv = get_user_u8(val, addr);
598 break;
599 case 1:
600 segv = get_user_u16(val, addr);
601 break;
602 case 2:
603 case 3:
604 segv = get_user_u32(val, addr);
605 break;
f7001a3b
AJ		 606 default:
607 abort();
426f5abc
PB		 608 }
609 if (segv) {
610 env->cp15.c6_data = addr;
611 goto done;
612 }
613 if (val != env->exclusive_val) {
614 goto fail;
615 }
616 if (size == 3) {
617 segv = get_user_u32(val, addr + 4);
618 if (segv) {
619 env->cp15.c6_data = addr + 4;
620 goto done;
621 }
622 if (val != env->exclusive_high) {
623 goto fail;
624 }
625 }
626 val = env->regs[(env->exclusive_info >> 8) & 0xf];
627 switch (size) {
628 case 0:
629 segv = put_user_u8(val, addr);
630 break;
631 case 1:
632 segv = put_user_u16(val, addr);
633 break;
634 case 2:
635 case 3:
636 segv = put_user_u32(val, addr);
637 break;
638 }
639 if (segv) {
640 env->cp15.c6_data = addr;
641 goto done;
642 }
643 if (size == 3) {
644 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 645 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 646 if (segv) {
647 env->cp15.c6_data = addr + 4;
648 goto done;
649 }
650 }
651 rc = 0;
652fail:
725b8a69 653 env->regs[15] += 4;
426f5abc
PB		 654 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
655done:
656 end_exclusive();
657 return segv;
658}
659
b346ff46
FB		 660void cpu_loop(CPUARMState *env)
661{
0315c31c 662 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 663 int trapnr;
664 unsigned int n, insn;
c227f099 665 target_siginfo_t info;
b5ff1b31 666 uint32_t addr;
3b46e624 667
b346ff46 668 for(;;) {
0315c31c 669 cpu_exec_start(cs);
b346ff46 670 trapnr = cpu_arm_exec(env);
0315c31c 671 cpu_exec_end(cs);
b346ff46
FB		 672 switch(trapnr) {
673 case EXCP_UDEF:
c6981055
FB		 674 {
675 TaskState *ts = env->opaque;
676 uint32_t opcode;
6d9a42be 677 int rc;
c6981055
FB		 678
679 /* we handle the FPU emulation here, as Linux */
680 /* we get the opcode */
2f619698 681 /* FIXME - what to do if get_user() fails? */
d8fd2954 682 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 683
6d9a42be
AJ		 684 rc = EmulateAll(opcode, &ts->fpa, env);
685 if (rc == 0) { /* illegal instruction */
c6981055
FB		 686 info.si_signo = SIGILL;
687 info.si_errno = 0;
688 info.si_code = TARGET_ILL_ILLOPN;
689 info._sifields._sigfault._addr = env->regs[15];
624f7979 690 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 691 } else if (rc < 0) { /* FP exception */
692 int arm_fpe=0;
693
694 /* translate softfloat flags to FPSR flags */
695 if (-rc & float_flag_invalid)
696 arm_fpe |= BIT_IOC;
697 if (-rc & float_flag_divbyzero)
698 arm_fpe |= BIT_DZC;
699 if (-rc & float_flag_overflow)
700 arm_fpe |= BIT_OFC;
701 if (-rc & float_flag_underflow)
702 arm_fpe |= BIT_UFC;
703 if (-rc & float_flag_inexact)
704 arm_fpe |= BIT_IXC;
705
706 FPSR fpsr = ts->fpa.fpsr;
707 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
708
709 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
710 info.si_signo = SIGFPE;
711 info.si_errno = 0;
712
713 /* ordered by priority, least first */
714 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
715 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
716 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
717 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
718 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
719
720 info._sifields._sigfault._addr = env->regs[15];
624f7979 721 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 722 } else {
723 env->regs[15] += 4;
724 }
725
726 /* accumulate unenabled exceptions */
727 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
728 fpsr |= BIT_IXC;
729 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
730 fpsr |= BIT_UFC;
731 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
732 fpsr |= BIT_OFC;
733 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
734 fpsr |= BIT_DZC;
735 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
736 fpsr |= BIT_IOC;
737 ts->fpa.fpsr=fpsr;
738 } else { /* everything OK */
c6981055
FB		 739 /* increment PC */
740 env->regs[15] += 4;
741 }
742 }
b346ff46
FB		 743 break;
744 case EXCP_SWI:
06c949e6 745 case EXCP_BKPT:
b346ff46 746 {
ce4defa0 747 env->eabi = 1;
b346ff46 748 /* system call */
06c949e6
PB		 749 if (trapnr == EXCP_BKPT) {
750 if (env->thumb) {
2f619698 751 /* FIXME - what to do if get_user() fails? */
d8fd2954 752 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 753 n = insn & 0xff;
754 env->regs[15] += 2;
755 } else {
2f619698 756 /* FIXME - what to do if get_user() fails? */
d8fd2954 757 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 758 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
759 env->regs[15] += 4;
760 }
192c7bd9 761 } else {
06c949e6 762 if (env->thumb) {
2f619698 763 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 764 get_user_code_u16(insn, env->regs[15] - 2,
765 env->bswap_code);
06c949e6
PB		 766 n = insn & 0xff;
767 } else {
2f619698 768 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 769 get_user_code_u32(insn, env->regs[15] - 4,
770 env->bswap_code);
06c949e6
PB		 771 n = insn & 0xffffff;
772 }
192c7bd9
FB		 773 }
774
6f1f31c0 775 if (n == ARM_NR_cacheflush) {
dcfd14b3 776 /* nop */
a4f81979
FB		 777 } else if (n == ARM_NR_semihosting
778 || n == ARM_NR_thumb_semihosting) {
779 env->regs[0] = do_arm_semihosting (env);
3a1363ac 780 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 781 /* linux syscall */
ce4defa0 782 if (env->thumb || n == 0) {
192c7bd9
FB		 783 n = env->regs[7];
784 } else {
785 n -= ARM_SYSCALL_BASE;
ce4defa0 786 env->eabi = 0;
192c7bd9 787 }
fbb4a2e3
PB		 788 if ( n > ARM_NR_BASE) {
789 switch (n) {
790 case ARM_NR_cacheflush:
dcfd14b3 791 /* nop */
fbb4a2e3
PB		 792 break;
793 case ARM_NR_set_tls:
794 cpu_set_tls(env, env->regs[0]);
795 env->regs[0] = 0;
796 break;
797 default:
798 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
799 n);
800 env->regs[0] = -TARGET_ENOSYS;
801 break;
802 }
803 } else {
804 env->regs[0] = do_syscall(env,
805 n,
806 env->regs[0],
807 env->regs[1],
808 env->regs[2],
809 env->regs[3],
810 env->regs[4],
5945cfcb
PM		 811 env->regs[5],
812 0, 0);
fbb4a2e3 813 }
b346ff46
FB		 814 } else {
815 goto error;
816 }
817 }
818 break;
43fff238
FB		 819 case EXCP_INTERRUPT:
820 /* just indicate that signals should be handled asap */
821 break;
68016c62 822 case EXCP_PREFETCH_ABORT:
eae473c1 823 addr = env->cp15.c6_insn;
b5ff1b31 824 goto do_segv;
68016c62 825 case EXCP_DATA_ABORT:
eae473c1 826 addr = env->cp15.c6_data;
b5ff1b31 827 do_segv:
68016c62
FB		 828 {
829 info.si_signo = SIGSEGV;
830 info.si_errno = 0;
831 /* XXX: check env->error_code */
832 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 833 info._sifields._sigfault._addr = addr;
624f7979 834 queue_signal(env, info.si_signo, &info);
68016c62
FB		 835 }
836 break;
1fddef4b
FB		 837 case EXCP_DEBUG:
838 {
839 int sig;
840
db6b81d4 841 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 842 if (sig)
843 {
844 info.si_signo = sig;
845 info.si_errno = 0;
846 info.si_code = TARGET_TRAP_BRKPT;
624f7979 847 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 848 }
849 }
850 break;
fbb4a2e3
PB		 851 case EXCP_KERNEL_TRAP:
852 if (do_kernel_trap(env))
853 goto error;
854 break;
426f5abc
PB		 855 case EXCP_STREX:
856 if (do_strex(env)) {
857 addr = env->cp15.c6_data;
858 goto do_segv;
859 }
e9273455 860 break;
b346ff46
FB		 861 default:
862 error:
5fafdf24 863 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 864 trapnr);
878096ee 865 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 866 abort();
867 }
868 process_pending_signals(env);
869 }
870}
871
872#endif
1b6b029e 873
d2fbca94
GX		 874#ifdef TARGET_UNICORE32
875
05390248 876void cpu_loop(CPUUniCore32State *env)
d2fbca94 877{
0315c31c 878 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 879 int trapnr;
880 unsigned int n, insn;
881 target_siginfo_t info;
882
883 for (;;) {
0315c31c 884 cpu_exec_start(cs);
d2fbca94 885 trapnr = uc32_cpu_exec(env);
0315c31c 886 cpu_exec_end(cs);
d2fbca94
GX		 887 switch (trapnr) {
888 case UC32_EXCP_PRIV:
889 {
890 /* system call */
891 get_user_u32(insn, env->regs[31] - 4);
892 n = insn & 0xffffff;
893
894 if (n >= UC32_SYSCALL_BASE) {
895 /* linux syscall */
896 n -= UC32_SYSCALL_BASE;
897 if (n == UC32_SYSCALL_NR_set_tls) {
898 cpu_set_tls(env, env->regs[0]);
899 env->regs[0] = 0;
900 } else {
901 env->regs[0] = do_syscall(env,
902 n,
903 env->regs[0],
904 env->regs[1],
905 env->regs[2],
906 env->regs[3],
907 env->regs[4],
5945cfcb
PM		 908 env->regs[5],
909 0, 0);
d2fbca94
GX		 910 }
911 } else {
912 goto error;
913 }
914 }
915 break;
d48813dd
GX		 916 case UC32_EXCP_DTRAP:
917 case UC32_EXCP_ITRAP:
d2fbca94
GX		 918 info.si_signo = SIGSEGV;
919 info.si_errno = 0;
920 /* XXX: check env->error_code */
921 info.si_code = TARGET_SEGV_MAPERR;
922 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
923 queue_signal(env, info.si_signo, &info);
924 break;
925 case EXCP_INTERRUPT:
926 /* just indicate that signals should be handled asap */
927 break;
928 case EXCP_DEBUG:
929 {
930 int sig;
931
db6b81d4 932 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 933 if (sig) {
934 info.si_signo = sig;
935 info.si_errno = 0;
936 info.si_code = TARGET_TRAP_BRKPT;
937 queue_signal(env, info.si_signo, &info);
938 }
939 }
940 break;
941 default:
942 goto error;
943 }
944 process_pending_signals(env);
945 }
946
947error:
948 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 949 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 950 abort();
951}
952#endif
953
93ac68bc 954#ifdef TARGET_SPARC
ed23fbd9 955#define SPARC64_STACK_BIAS 2047
93ac68bc 956
060366c5
FB		 957//#define DEBUG_WIN
958
2623cbaf
FB		 959/* WARNING: dealing with register windows _is_ complicated. More info
960 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 961static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
962{
1a14026e 963 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 964 /* wrap handling : if cwp is on the last window, then we use the
965 registers 'after' the end */
1a14026e
BS		 966 if (index < 8 && env->cwp == env->nwindows - 1)
967 index += 16 * env->nwindows;
060366c5
FB		 968 return index;
969}
970
2623cbaf
FB		 971/* save the register window 'cwp1' */
972static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 973{
2623cbaf 974 unsigned int i;
992f48a0 975 abi_ulong sp_ptr;
3b46e624 976
53a5960a 977 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 978#ifdef TARGET_SPARC64
979 if (sp_ptr & 3)
980 sp_ptr += SPARC64_STACK_BIAS;
981#endif
060366c5 982#if defined(DEBUG_WIN)
2daf0284
BS		 983 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
984 sp_ptr, cwp1);
060366c5 985#endif
2623cbaf 986 for(i = 0; i < 16; i++) {
2f619698
FB		 987 /* FIXME - what to do if put_user() fails? */
988 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 989 sp_ptr += sizeof(abi_ulong);
2623cbaf 990 }
060366c5
FB		 991}
992
993static void save_window(CPUSPARCState *env)
994{
5ef54116 995#ifndef TARGET_SPARC64
2623cbaf 996 unsigned int new_wim;
1a14026e
BS		 997 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
998 ((1LL << env->nwindows) - 1);
999 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1000 env->wim = new_wim;
5ef54116 1001#else
1a14026e 1002 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1003 env->cansave++;
1004 env->canrestore--;
1005#endif
060366c5
FB		 1006}
1007
1008static void restore_window(CPUSPARCState *env)
1009{
eda52953
BS		 1010#ifndef TARGET_SPARC64
1011 unsigned int new_wim;
1012#endif
1013 unsigned int i, cwp1;
992f48a0 1014 abi_ulong sp_ptr;
3b46e624 1015
eda52953 1016#ifndef TARGET_SPARC64
1a14026e
BS		 1017 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1018 ((1LL << env->nwindows) - 1);
eda52953 1019#endif
3b46e624 1020
060366c5 1021 /* restore the invalid window */
1a14026e 1022 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1023 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1024#ifdef TARGET_SPARC64
1025 if (sp_ptr & 3)
1026 sp_ptr += SPARC64_STACK_BIAS;
1027#endif
060366c5 1028#if defined(DEBUG_WIN)
2daf0284
BS		 1029 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1030 sp_ptr, cwp1);
060366c5 1031#endif
2623cbaf 1032 for(i = 0; i < 16; i++) {
2f619698
FB		 1033 /* FIXME - what to do if get_user() fails? */
1034 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1035 sp_ptr += sizeof(abi_ulong);
2623cbaf 1036 }
5ef54116
FB		 1037#ifdef TARGET_SPARC64
1038 env->canrestore++;
1a14026e
BS		 1039 if (env->cleanwin < env->nwindows - 1)
1040 env->cleanwin++;
5ef54116 1041 env->cansave--;
eda52953
BS		 1042#else
1043 env->wim = new_wim;
5ef54116 1044#endif
060366c5
FB		 1045}
1046
1047static void flush_windows(CPUSPARCState *env)
1048{
1049 int offset, cwp1;
2623cbaf
FB		 1050
1051 offset = 1;
060366c5
FB		 1052 for(;;) {
1053 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1054 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1055#ifndef TARGET_SPARC64
060366c5
FB		 1056 if (env->wim & (1 << cwp1))
1057 break;
eda52953
BS		 1058#else
1059 if (env->canrestore == 0)
1060 break;
1061 env->cansave++;
1062 env->canrestore--;
1063#endif
2623cbaf 1064 save_window_offset(env, cwp1);
060366c5
FB		 1065 offset++;
1066 }
1a14026e 1067 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1068#ifndef TARGET_SPARC64
1069 /* set wim so that restore will reload the registers */
2623cbaf 1070 env->wim = 1 << cwp1;
eda52953 1071#endif
2623cbaf
FB		 1072#if defined(DEBUG_WIN)
1073 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1074#endif
2623cbaf 1075}
060366c5 1076
93ac68bc
FB		 1077void cpu_loop (CPUSPARCState *env)
1078{
878096ee 1079 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1080 int trapnr;
1081 abi_long ret;
c227f099 1082 target_siginfo_t info;
3b46e624 1083
060366c5
FB		 1084 while (1) {
1085 trapnr = cpu_sparc_exec (env);
3b46e624 1086
20132b96
RH		 1087 /* Compute PSR before exposing state. */
1088 if (env->cc_op != CC_OP_FLAGS) {
1089 cpu_get_psr(env);
1090 }
1091
060366c5 1092 switch (trapnr) {
5ef54116 1093#ifndef TARGET_SPARC64
5fafdf24 1094 case 0x88:
060366c5 1095 case 0x90:
5ef54116 1096#else
cb33da57 1097 case 0x110:
5ef54116
FB		 1098 case 0x16d:
1099#endif
060366c5 1100 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1101 env->regwptr[0], env->regwptr[1],
1102 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1103 env->regwptr[4], env->regwptr[5],
1104 0, 0);
2cc20260 1105 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1106#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1107 env->xcc |= PSR_CARRY;
1108#else
060366c5 1109 env->psr |= PSR_CARRY;
27908725 1110#endif
060366c5
FB		 1111 ret = -ret;
1112 } else {
992f48a0 1113#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1114 env->xcc &= ~PSR_CARRY;
1115#else
060366c5 1116 env->psr &= ~PSR_CARRY;
27908725 1117#endif
060366c5
FB		 1118 }
1119 env->regwptr[0] = ret;
1120 /* next instruction */
1121 env->pc = env->npc;
1122 env->npc = env->npc + 4;
1123 break;
1124 case 0x83: /* flush windows */
992f48a0
BS		 1125#ifdef TARGET_ABI32
1126 case 0x103:
1127#endif
2623cbaf 1128 flush_windows(env);
060366c5
FB		 1129 /* next instruction */
1130 env->pc = env->npc;
1131 env->npc = env->npc + 4;
1132 break;
3475187d 1133#ifndef TARGET_SPARC64
060366c5
FB		 1134 case TT_WIN_OVF: /* window overflow */
1135 save_window(env);
1136 break;
1137 case TT_WIN_UNF: /* window underflow */
1138 restore_window(env);
1139 break;
61ff6f58
FB		 1140 case TT_TFAULT:
1141 case TT_DFAULT:
1142 {
59f7182f 1143 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1144 info.si_errno = 0;
1145 /* XXX: check env->error_code */
1146 info.si_code = TARGET_SEGV_MAPERR;
1147 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1148 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1149 }
1150 break;
3475187d 1151#else
5ef54116
FB		 1152 case TT_SPILL: /* window overflow */
1153 save_window(env);
1154 break;
1155 case TT_FILL: /* window underflow */
1156 restore_window(env);
1157 break;
7f84a729
BS		 1158 case TT_TFAULT:
1159 case TT_DFAULT:
1160 {
59f7182f 1161 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1162 info.si_errno = 0;
1163 /* XXX: check env->error_code */
1164 info.si_code = TARGET_SEGV_MAPERR;
1165 if (trapnr == TT_DFAULT)
1166 info._sifields._sigfault._addr = env->dmmuregs[4];
1167 else
8194f35a 1168 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1169 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1170 }
1171 break;
27524dc3 1172#ifndef TARGET_ABI32
5bfb56b2
BS		 1173 case 0x16e:
1174 flush_windows(env);
1175 sparc64_get_context(env);
1176 break;
1177 case 0x16f:
1178 flush_windows(env);
1179 sparc64_set_context(env);
1180 break;
27524dc3 1181#endif
3475187d 1182#endif
48dc41eb
FB		 1183 case EXCP_INTERRUPT:
1184 /* just indicate that signals should be handled asap */
1185 break;
75f22e4e
RH		 1186 case TT_ILL_INSN:
1187 {
1188 info.si_signo = TARGET_SIGILL;
1189 info.si_errno = 0;
1190 info.si_code = TARGET_ILL_ILLOPC;
1191 info._sifields._sigfault._addr = env->pc;
1192 queue_signal(env, info.si_signo, &info);
1193 }
1194 break;
1fddef4b
FB		 1195 case EXCP_DEBUG:
1196 {
1197 int sig;
1198
db6b81d4 1199 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1200 if (sig)
1201 {
1202 info.si_signo = sig;
1203 info.si_errno = 0;
1204 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1205 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1206 }
1207 }
1208 break;
060366c5
FB		 1209 default:
1210 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1211 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1212 exit (1);
1213 }
1214 process_pending_signals (env);
1215 }
93ac68bc
FB		 1216}
1217
1218#endif
1219
67867308 1220#ifdef TARGET_PPC
05390248 1221static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1222{
1223 /* TO FIX */
1224 return 0;
1225}
3b46e624 1226
05390248 1227uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1228{
e3ea6529 1229 return cpu_ppc_get_tb(env);
9fddaa0c 1230}
3b46e624 1231
05390248 1232uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1233{
1234 return cpu_ppc_get_tb(env) >> 32;
1235}
3b46e624 1236
05390248 1237uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1238{
b711de95 1239 return cpu_ppc_get_tb(env);
9fddaa0c 1240}
5fafdf24 1241
05390248 1242uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1243{
a062e36c 1244 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1245}
76a66253 1246
05390248 1247uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1248__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1249
05390248 1250uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1251{
76a66253 1252 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1253}
76a66253 1254
a750fc0b 1255/* XXX: to be fixed */
73b01960 1256int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1257{
1258 return -1;
1259}
1260
73b01960 1261int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1262{
1263 return -1;
1264}
1265
001faf32
BS		 1266#define EXCP_DUMP(env, fmt, ...) \
1267do { \
a0762859 1268 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1269 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1270 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1271 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1272 if (qemu_log_enabled()) { \
a0762859 1273 log_cpu_state(cs, 0); \
eeacee4d 1274 } \
e1833e1f
JM		 1275} while (0)
1276
56f066bb
NF		 1277static int do_store_exclusive(CPUPPCState *env)
1278{
1279 target_ulong addr;
1280 target_ulong page_addr;
1281 target_ulong val;
1282 int flags;
1283 int segv = 0;
1284
1285 addr = env->reserve_ea;
1286 page_addr = addr & TARGET_PAGE_MASK;
1287 start_exclusive();
1288 mmap_lock();
1289 flags = page_get_flags(page_addr);
1290 if ((flags & PAGE_READ) == 0) {
1291 segv = 1;
1292 } else {
1293 int reg = env->reserve_info & 0x1f;
1294 int size = (env->reserve_info >> 5) & 0xf;
1295 int stored = 0;
1296
1297 if (addr == env->reserve_addr) {
1298 switch (size) {
1299 case 1: segv = get_user_u8(val, addr); break;
1300 case 2: segv = get_user_u16(val, addr); break;
1301 case 4: segv = get_user_u32(val, addr); break;
1302#if defined(TARGET_PPC64)
1303 case 8: segv = get_user_u64(val, addr); break;
1304#endif
1305 default: abort();
1306 }
1307 if (!segv && val == env->reserve_val) {
1308 val = env->gpr[reg];
1309 switch (size) {
1310 case 1: segv = put_user_u8(val, addr); break;
1311 case 2: segv = put_user_u16(val, addr); break;
1312 case 4: segv = put_user_u32(val, addr); break;
1313#if defined(TARGET_PPC64)
1314 case 8: segv = put_user_u64(val, addr); break;
1315#endif
1316 default: abort();
1317 }
1318 if (!segv) {
1319 stored = 1;
1320 }
1321 }
1322 }
1323 env->crf[0] = (stored << 1) | xer_so;
1324 env->reserve_addr = (target_ulong)-1;
1325 }
1326 if (!segv) {
1327 env->nip += 4;
1328 }
1329 mmap_unlock();
1330 end_exclusive();
1331 return segv;
1332}
1333
67867308
FB		 1334void cpu_loop(CPUPPCState *env)
1335{
0315c31c 1336 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1337 target_siginfo_t info;
61190b14 1338 int trapnr;
9e0e2f96 1339 target_ulong ret;
3b46e624 1340
67867308 1341 for(;;) {
0315c31c 1342 cpu_exec_start(cs);
67867308 1343 trapnr = cpu_ppc_exec(env);
0315c31c 1344 cpu_exec_end(cs);
67867308 1345 switch(trapnr) {
e1833e1f
JM		 1346 case POWERPC_EXCP_NONE:
1347 /* Just go on */
67867308 1348 break;
e1833e1f
JM		 1349 case POWERPC_EXCP_CRITICAL: /* Critical input */
1350 cpu_abort(env, "Critical interrupt while in user mode. "
1351 "Aborting\n");
61190b14 1352 break;
e1833e1f
JM		 1353 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1354 cpu_abort(env, "Machine check exception while in user mode. "
1355 "Aborting\n");
1356 break;
1357 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1358 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1359 env->spr[SPR_DAR]);
1360 /* XXX: check this. Seems bugged */
2be0071f
FB		 1361 switch (env->error_code & 0xFF000000) {
1362 case 0x40000000:
61190b14
FB		 1363 info.si_signo = TARGET_SIGSEGV;
1364 info.si_errno = 0;
1365 info.si_code = TARGET_SEGV_MAPERR;
1366 break;
2be0071f 1367 case 0x04000000:
61190b14
FB		 1368 info.si_signo = TARGET_SIGILL;
1369 info.si_errno = 0;
1370 info.si_code = TARGET_ILL_ILLADR;
1371 break;
2be0071f 1372 case 0x08000000:
61190b14
FB		 1373 info.si_signo = TARGET_SIGSEGV;
1374 info.si_errno = 0;
1375 info.si_code = TARGET_SEGV_ACCERR;
1376 break;
61190b14
FB		 1377 default:
1378 /* Let's send a regular segfault... */
e1833e1f
JM		 1379 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1380 env->error_code);
61190b14
FB		 1381 info.si_signo = TARGET_SIGSEGV;
1382 info.si_errno = 0;
1383 info.si_code = TARGET_SEGV_MAPERR;
1384 break;
1385 }
67867308 1386 info._sifields._sigfault._addr = env->nip;
624f7979 1387 queue_signal(env, info.si_signo, &info);
67867308 1388 break;
e1833e1f 1389 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1390 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1391 "\n", env->spr[SPR_SRR0]);
e1833e1f 1392 /* XXX: check this */
2be0071f
FB		 1393 switch (env->error_code & 0xFF000000) {
1394 case 0x40000000:
61190b14 1395 info.si_signo = TARGET_SIGSEGV;
67867308 1396 info.si_errno = 0;
61190b14
FB		 1397 info.si_code = TARGET_SEGV_MAPERR;
1398 break;
2be0071f
FB		 1399 case 0x10000000:
1400 case 0x08000000:
61190b14
FB		 1401 info.si_signo = TARGET_SIGSEGV;
1402 info.si_errno = 0;
1403 info.si_code = TARGET_SEGV_ACCERR;
1404 break;
1405 default:
1406 /* Let's send a regular segfault... */
e1833e1f
JM		 1407 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1408 env->error_code);
61190b14
FB		 1409 info.si_signo = TARGET_SIGSEGV;
1410 info.si_errno = 0;
1411 info.si_code = TARGET_SEGV_MAPERR;
1412 break;
1413 }
1414 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1415 queue_signal(env, info.si_signo, &info);
67867308 1416 break;
e1833e1f
JM		 1417 case POWERPC_EXCP_EXTERNAL: /* External input */
1418 cpu_abort(env, "External interrupt while in user mode. "
1419 "Aborting\n");
1420 break;
1421 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1422 EXCP_DUMP(env, "Unaligned memory access\n");
1423 /* XXX: check this */
61190b14 1424 info.si_signo = TARGET_SIGBUS;
67867308 1425 info.si_errno = 0;
61190b14
FB		 1426 info.si_code = TARGET_BUS_ADRALN;
1427 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1428 queue_signal(env, info.si_signo, &info);
67867308 1429 break;
e1833e1f
JM		 1430 case POWERPC_EXCP_PROGRAM: /* Program exception */
1431 /* XXX: check this */
61190b14 1432 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1433 case POWERPC_EXCP_FP:
1434 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1435 info.si_signo = TARGET_SIGFPE;
1436 info.si_errno = 0;
1437 switch (env->error_code & 0xF) {
e1833e1f 1438 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1439 info.si_code = TARGET_FPE_FLTOVF;
1440 break;
e1833e1f 1441 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1442 info.si_code = TARGET_FPE_FLTUND;
1443 break;
e1833e1f
JM		 1444 case POWERPC_EXCP_FP_ZX:
1445 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1446 info.si_code = TARGET_FPE_FLTDIV;
1447 break;
e1833e1f 1448 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1449 info.si_code = TARGET_FPE_FLTRES;
1450 break;
e1833e1f 1451 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1452 info.si_code = TARGET_FPE_FLTINV;
1453 break;
7c58044c 1454 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1455 case POWERPC_EXCP_FP_VXISI:
1456 case POWERPC_EXCP_FP_VXIDI:
1457 case POWERPC_EXCP_FP_VXIMZ:
1458 case POWERPC_EXCP_FP_VXVC:
1459 case POWERPC_EXCP_FP_VXSQRT:
1460 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1461 info.si_code = TARGET_FPE_FLTSUB;
1462 break;
1463 default:
e1833e1f
JM		 1464 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1465 env->error_code);
1466 break;
61190b14 1467 }
e1833e1f
JM		 1468 break;
1469 case POWERPC_EXCP_INVAL:
1470 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1471 info.si_signo = TARGET_SIGILL;
1472 info.si_errno = 0;
1473 switch (env->error_code & 0xF) {
e1833e1f 1474 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1475 info.si_code = TARGET_ILL_ILLOPC;
1476 break;
e1833e1f 1477 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1478 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1479 break;
e1833e1f 1480 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1481 info.si_code = TARGET_ILL_PRVREG;
1482 break;
e1833e1f 1483 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1484 info.si_code = TARGET_ILL_COPROC;
1485 break;
1486 default:
e1833e1f
JM		 1487 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1488 env->error_code & 0xF);
61190b14
FB		 1489 info.si_code = TARGET_ILL_ILLADR;
1490 break;
1491 }
1492 break;
e1833e1f
JM		 1493 case POWERPC_EXCP_PRIV:
1494 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1495 info.si_signo = TARGET_SIGILL;
1496 info.si_errno = 0;
1497 switch (env->error_code & 0xF) {
e1833e1f 1498 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1499 info.si_code = TARGET_ILL_PRVOPC;
1500 break;
e1833e1f 1501 case POWERPC_EXCP_PRIV_REG:
61190b14 1502 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1503 break;
61190b14 1504 default:
e1833e1f
JM		 1505 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1506 env->error_code & 0xF);
61190b14
FB		 1507 info.si_code = TARGET_ILL_PRVOPC;
1508 break;
1509 }
1510 break;
e1833e1f
JM		 1511 case POWERPC_EXCP_TRAP:
1512 cpu_abort(env, "Tried to call a TRAP\n");
1513 break;
61190b14
FB		 1514 default:
1515 /* Should not happen ! */
e1833e1f
JM		 1516 cpu_abort(env, "Unknown program exception (%02x)\n",
1517 env->error_code);
1518 break;
61190b14
FB		 1519 }
1520 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1521 queue_signal(env, info.si_signo, &info);
67867308 1522 break;
e1833e1f
JM		 1523 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1524 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1525 info.si_signo = TARGET_SIGILL;
67867308 1526 info.si_errno = 0;
61190b14
FB		 1527 info.si_code = TARGET_ILL_COPROC;
1528 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1529 queue_signal(env, info.si_signo, &info);
67867308 1530 break;
e1833e1f
JM		 1531 case POWERPC_EXCP_SYSCALL: /* System call exception */
1532 cpu_abort(env, "Syscall exception while in user mode. "
1533 "Aborting\n");
61190b14 1534 break;
e1833e1f
JM		 1535 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1536 EXCP_DUMP(env, "No APU instruction allowed\n");
1537 info.si_signo = TARGET_SIGILL;
1538 info.si_errno = 0;
1539 info.si_code = TARGET_ILL_COPROC;
1540 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1541 queue_signal(env, info.si_signo, &info);
61190b14 1542 break;
e1833e1f
JM		 1543 case POWERPC_EXCP_DECR: /* Decrementer exception */
1544 cpu_abort(env, "Decrementer interrupt while in user mode. "
1545 "Aborting\n");
61190b14 1546 break;
e1833e1f
JM		 1547 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1548 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1549 "Aborting\n");
1550 break;
1551 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1552 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1553 "Aborting\n");
1554 break;
1555 case POWERPC_EXCP_DTLB: /* Data TLB error */
1556 cpu_abort(env, "Data TLB exception while in user mode. "
1557 "Aborting\n");
1558 break;
1559 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1560 cpu_abort(env, "Instruction TLB exception while in user mode. "
1561 "Aborting\n");
1562 break;
e1833e1f
JM		 1563 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1564 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1565 info.si_signo = TARGET_SIGILL;
1566 info.si_errno = 0;
1567 info.si_code = TARGET_ILL_COPROC;
1568 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1569 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1570 break;
1571 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1572 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1573 break;
1574 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1575 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1576 break;
1577 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1578 cpu_abort(env, "Performance monitor exception not handled\n");
1579 break;
1580 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1581 cpu_abort(env, "Doorbell interrupt while in user mode. "
1582 "Aborting\n");
1583 break;
1584 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1585 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1586 "Aborting\n");
1587 break;
1588 case POWERPC_EXCP_RESET: /* System reset exception */
1589 cpu_abort(env, "Reset interrupt while in user mode. "
1590 "Aborting\n");
1591 break;
e1833e1f
JM		 1592 case POWERPC_EXCP_DSEG: /* Data segment exception */
1593 cpu_abort(env, "Data segment exception while in user mode. "
1594 "Aborting\n");
1595 break;
1596 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1597 cpu_abort(env, "Instruction segment exception "
1598 "while in user mode. Aborting\n");
1599 break;
e85e7c6e 1600 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1601 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1602 cpu_abort(env, "Hypervisor decrementer interrupt "
1603 "while in user mode. Aborting\n");
1604 break;
e1833e1f
JM		 1605 case POWERPC_EXCP_TRACE: /* Trace exception */
1606 /* Nothing to do:
1607 * we use this exception to emulate step-by-step execution mode.
1608 */
1609 break;
e85e7c6e 1610 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1611 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1612 cpu_abort(env, "Hypervisor data storage exception "
1613 "while in user mode. Aborting\n");
1614 break;
1615 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1616 cpu_abort(env, "Hypervisor instruction storage exception "
1617 "while in user mode. Aborting\n");
1618 break;
1619 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1620 cpu_abort(env, "Hypervisor data segment exception "
1621 "while in user mode. Aborting\n");
1622 break;
1623 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1624 cpu_abort(env, "Hypervisor instruction segment exception "
1625 "while in user mode. Aborting\n");
1626 break;
e1833e1f
JM		 1627 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1628 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1629 info.si_signo = TARGET_SIGILL;
1630 info.si_errno = 0;
1631 info.si_code = TARGET_ILL_COPROC;
1632 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1633 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1634 break;
1635 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1636 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1637 "while in user mode. Aborting\n");
1638 break;
1639 case POWERPC_EXCP_IO: /* IO error exception */
1640 cpu_abort(env, "IO error exception while in user mode. "
1641 "Aborting\n");
1642 break;
1643 case POWERPC_EXCP_RUNM: /* Run mode exception */
1644 cpu_abort(env, "Run mode exception while in user mode. "
1645 "Aborting\n");
1646 break;
1647 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1648 cpu_abort(env, "Emulation trap exception not handled\n");
1649 break;
1650 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1651 cpu_abort(env, "Instruction fetch TLB exception "
1652 "while in user-mode. Aborting");
1653 break;
1654 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1655 cpu_abort(env, "Data load TLB exception while in user-mode. "
1656 "Aborting");
1657 break;
1658 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1659 cpu_abort(env, "Data store TLB exception while in user-mode. "
1660 "Aborting");
1661 break;
1662 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1663 cpu_abort(env, "Floating-point assist exception not handled\n");
1664 break;
1665 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1666 cpu_abort(env, "Instruction address breakpoint exception "
1667 "not handled\n");
1668 break;
1669 case POWERPC_EXCP_SMI: /* System management interrupt */
1670 cpu_abort(env, "System management interrupt while in user mode. "
1671 "Aborting\n");
1672 break;
1673 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1674 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1675 "Aborting\n");
1676 break;
1677 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1678 cpu_abort(env, "Performance monitor exception not handled\n");
1679 break;
1680 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1681 cpu_abort(env, "Vector assist exception not handled\n");
1682 break;
1683 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1684 cpu_abort(env, "Soft patch exception not handled\n");
1685 break;
1686 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1687 cpu_abort(env, "Maintenance exception while in user mode. "
1688 "Aborting\n");
1689 break;
1690 case POWERPC_EXCP_STOP: /* stop translation */
1691 /* We did invalidate the instruction cache. Go on */
1692 break;
1693 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1694 /* We just stopped because of a branch. Go on */
1695 break;
1696 case POWERPC_EXCP_SYSCALL_USER:
1697 /* system call in user-mode emulation */
1698 /* WARNING:
1699 * PPC ABI uses overflow flag in cr0 to signal an error
1700 * in syscalls.
1701 */
e1833e1f
JM		 1702 env->crf[0] &= ~0x1;
1703 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1704 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1705 env->gpr[8], 0, 0);
9e0e2f96 1706 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1707 /* Returning from a successful sigreturn syscall.
1708 Avoid corrupting register state. */
1709 break;
1710 }
9e0e2f96 1711 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1712 env->crf[0] |= 0x1;
1713 ret = -ret;
61190b14 1714 }
e1833e1f 1715 env->gpr[3] = ret;
e1833e1f 1716 break;
56f066bb
NF		 1717 case POWERPC_EXCP_STCX:
1718 if (do_store_exclusive(env)) {
1719 info.si_signo = TARGET_SIGSEGV;
1720 info.si_errno = 0;
1721 info.si_code = TARGET_SEGV_MAPERR;
1722 info._sifields._sigfault._addr = env->nip;
1723 queue_signal(env, info.si_signo, &info);
1724 }
1725 break;
71f75756
AJ		 1726 case EXCP_DEBUG:
1727 {
1728 int sig;
1729
db6b81d4 1730 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1731 if (sig) {
1732 info.si_signo = sig;
1733 info.si_errno = 0;
1734 info.si_code = TARGET_TRAP_BRKPT;
1735 queue_signal(env, info.si_signo, &info);
1736 }
1737 }
1738 break;
56ba31ff
JM		 1739 case EXCP_INTERRUPT:
1740 /* just indicate that signals should be handled asap */
1741 break;
e1833e1f
JM		 1742 default:
1743 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1744 break;
67867308
FB		 1745 }
1746 process_pending_signals(env);
1747 }
1748}
1749#endif
1750
048f6b4d
FB		 1751#ifdef TARGET_MIPS
1752
ff4f7382
RH		 1753# ifdef TARGET_ABI_MIPSO32
1754# define MIPS_SYS(name, args) args,
048f6b4d 1755static const uint8_t mips_syscall_args[] = {
29fb0f25 1756 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1757 MIPS_SYS(sys_exit , 1)
1758 MIPS_SYS(sys_fork , 0)
1759 MIPS_SYS(sys_read , 3)
1760 MIPS_SYS(sys_write , 3)
1761 MIPS_SYS(sys_open , 3) /* 4005 */
1762 MIPS_SYS(sys_close , 1)
1763 MIPS_SYS(sys_waitpid , 3)
1764 MIPS_SYS(sys_creat , 2)
1765 MIPS_SYS(sys_link , 2)
1766 MIPS_SYS(sys_unlink , 1) /* 4010 */
1767 MIPS_SYS(sys_execve , 0)
1768 MIPS_SYS(sys_chdir , 1)
1769 MIPS_SYS(sys_time , 1)
1770 MIPS_SYS(sys_mknod , 3)
1771 MIPS_SYS(sys_chmod , 2) /* 4015 */
1772 MIPS_SYS(sys_lchown , 3)
1773 MIPS_SYS(sys_ni_syscall , 0)
1774 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1775 MIPS_SYS(sys_lseek , 3)
1776 MIPS_SYS(sys_getpid , 0) /* 4020 */
1777 MIPS_SYS(sys_mount , 5)
1778 MIPS_SYS(sys_oldumount , 1)
1779 MIPS_SYS(sys_setuid , 1)
1780 MIPS_SYS(sys_getuid , 0)
1781 MIPS_SYS(sys_stime , 1) /* 4025 */
1782 MIPS_SYS(sys_ptrace , 4)
1783 MIPS_SYS(sys_alarm , 1)
1784 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1785 MIPS_SYS(sys_pause , 0)
1786 MIPS_SYS(sys_utime , 2) /* 4030 */
1787 MIPS_SYS(sys_ni_syscall , 0)
1788 MIPS_SYS(sys_ni_syscall , 0)
1789 MIPS_SYS(sys_access , 2)
1790 MIPS_SYS(sys_nice , 1)
1791 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1792 MIPS_SYS(sys_sync , 0)
1793 MIPS_SYS(sys_kill , 2)
1794 MIPS_SYS(sys_rename , 2)
1795 MIPS_SYS(sys_mkdir , 2)
1796 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1797 MIPS_SYS(sys_dup , 1)
1798 MIPS_SYS(sys_pipe , 0)
1799 MIPS_SYS(sys_times , 1)
1800 MIPS_SYS(sys_ni_syscall , 0)
1801 MIPS_SYS(sys_brk , 1) /* 4045 */
1802 MIPS_SYS(sys_setgid , 1)
1803 MIPS_SYS(sys_getgid , 0)
1804 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1805 MIPS_SYS(sys_geteuid , 0)
1806 MIPS_SYS(sys_getegid , 0) /* 4050 */
1807 MIPS_SYS(sys_acct , 0)
1808 MIPS_SYS(sys_umount , 2)
1809 MIPS_SYS(sys_ni_syscall , 0)
1810 MIPS_SYS(sys_ioctl , 3)
1811 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1812 MIPS_SYS(sys_ni_syscall , 2)
1813 MIPS_SYS(sys_setpgid , 2)
1814 MIPS_SYS(sys_ni_syscall , 0)
1815 MIPS_SYS(sys_olduname , 1)
1816 MIPS_SYS(sys_umask , 1) /* 4060 */
1817 MIPS_SYS(sys_chroot , 1)
1818 MIPS_SYS(sys_ustat , 2)
1819 MIPS_SYS(sys_dup2 , 2)
1820 MIPS_SYS(sys_getppid , 0)
1821 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1822 MIPS_SYS(sys_setsid , 0)
1823 MIPS_SYS(sys_sigaction , 3)
1824 MIPS_SYS(sys_sgetmask , 0)
1825 MIPS_SYS(sys_ssetmask , 1)
1826 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1827 MIPS_SYS(sys_setregid , 2)
1828 MIPS_SYS(sys_sigsuspend , 0)
1829 MIPS_SYS(sys_sigpending , 1)
1830 MIPS_SYS(sys_sethostname , 2)
1831 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1832 MIPS_SYS(sys_getrlimit , 2)
1833 MIPS_SYS(sys_getrusage , 2)
1834 MIPS_SYS(sys_gettimeofday, 2)
1835 MIPS_SYS(sys_settimeofday, 2)
1836 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1837 MIPS_SYS(sys_setgroups , 2)
1838 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1839 MIPS_SYS(sys_symlink , 2)
1840 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1841 MIPS_SYS(sys_readlink , 3) /* 4085 */
1842 MIPS_SYS(sys_uselib , 1)
1843 MIPS_SYS(sys_swapon , 2)
1844 MIPS_SYS(sys_reboot , 3)
1845 MIPS_SYS(old_readdir , 3)
1846 MIPS_SYS(old_mmap , 6) /* 4090 */
1847 MIPS_SYS(sys_munmap , 2)
1848 MIPS_SYS(sys_truncate , 2)
1849 MIPS_SYS(sys_ftruncate , 2)
1850 MIPS_SYS(sys_fchmod , 2)
1851 MIPS_SYS(sys_fchown , 3) /* 4095 */
1852 MIPS_SYS(sys_getpriority , 2)
1853 MIPS_SYS(sys_setpriority , 3)
1854 MIPS_SYS(sys_ni_syscall , 0)
1855 MIPS_SYS(sys_statfs , 2)
1856 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1857 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1858 MIPS_SYS(sys_socketcall , 2)
1859 MIPS_SYS(sys_syslog , 3)
1860 MIPS_SYS(sys_setitimer , 3)
1861 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1862 MIPS_SYS(sys_newstat , 2)
1863 MIPS_SYS(sys_newlstat , 2)
1864 MIPS_SYS(sys_newfstat , 2)
1865 MIPS_SYS(sys_uname , 1)
1866 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1867 MIPS_SYS(sys_vhangup , 0)
1868 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1869 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1870 MIPS_SYS(sys_wait4 , 4)
1871 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1872 MIPS_SYS(sys_sysinfo , 1)
1873 MIPS_SYS(sys_ipc , 6)
1874 MIPS_SYS(sys_fsync , 1)
1875 MIPS_SYS(sys_sigreturn , 0)
18113962 1876 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1877 MIPS_SYS(sys_setdomainname, 2)
1878 MIPS_SYS(sys_newuname , 1)
1879 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1880 MIPS_SYS(sys_adjtimex , 1)
1881 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1882 MIPS_SYS(sys_sigprocmask , 3)
1883 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1884 MIPS_SYS(sys_init_module , 5)
1885 MIPS_SYS(sys_delete_module, 1)
1886 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1887 MIPS_SYS(sys_quotactl , 0)
1888 MIPS_SYS(sys_getpgid , 1)
1889 MIPS_SYS(sys_fchdir , 1)
1890 MIPS_SYS(sys_bdflush , 2)
1891 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1892 MIPS_SYS(sys_personality , 1)
1893 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1894 MIPS_SYS(sys_setfsuid , 1)
1895 MIPS_SYS(sys_setfsgid , 1)
1896 MIPS_SYS(sys_llseek , 5) /* 4140 */
1897 MIPS_SYS(sys_getdents , 3)
1898 MIPS_SYS(sys_select , 5)
1899 MIPS_SYS(sys_flock , 2)
1900 MIPS_SYS(sys_msync , 3)
1901 MIPS_SYS(sys_readv , 3) /* 4145 */
1902 MIPS_SYS(sys_writev , 3)
1903 MIPS_SYS(sys_cacheflush , 3)
1904 MIPS_SYS(sys_cachectl , 3)
1905 MIPS_SYS(sys_sysmips , 4)
1906 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1907 MIPS_SYS(sys_getsid , 1)
1908 MIPS_SYS(sys_fdatasync , 0)
1909 MIPS_SYS(sys_sysctl , 1)
1910 MIPS_SYS(sys_mlock , 2)
1911 MIPS_SYS(sys_munlock , 2) /* 4155 */
1912 MIPS_SYS(sys_mlockall , 1)
1913 MIPS_SYS(sys_munlockall , 0)
1914 MIPS_SYS(sys_sched_setparam, 2)
1915 MIPS_SYS(sys_sched_getparam, 2)
1916 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1917 MIPS_SYS(sys_sched_getscheduler, 1)
1918 MIPS_SYS(sys_sched_yield , 0)
1919 MIPS_SYS(sys_sched_get_priority_max, 1)
1920 MIPS_SYS(sys_sched_get_priority_min, 1)
1921 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1922 MIPS_SYS(sys_nanosleep, 2)
b0932e06 1923 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 1924 MIPS_SYS(sys_accept , 3)
1925 MIPS_SYS(sys_bind , 3)
1926 MIPS_SYS(sys_connect , 3) /* 4170 */
1927 MIPS_SYS(sys_getpeername , 3)
1928 MIPS_SYS(sys_getsockname , 3)
1929 MIPS_SYS(sys_getsockopt , 5)
1930 MIPS_SYS(sys_listen , 2)
1931 MIPS_SYS(sys_recv , 4) /* 4175 */
1932 MIPS_SYS(sys_recvfrom , 6)
1933 MIPS_SYS(sys_recvmsg , 3)
1934 MIPS_SYS(sys_send , 4)
1935 MIPS_SYS(sys_sendmsg , 3)
1936 MIPS_SYS(sys_sendto , 6) /* 4180 */
1937 MIPS_SYS(sys_setsockopt , 5)
1938 MIPS_SYS(sys_shutdown , 2)
1939 MIPS_SYS(sys_socket , 3)
1940 MIPS_SYS(sys_socketpair , 4)
1941 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1942 MIPS_SYS(sys_getresuid , 3)
1943 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1944 MIPS_SYS(sys_poll , 3)
1945 MIPS_SYS(sys_nfsservctl , 3)
1946 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1947 MIPS_SYS(sys_getresgid , 3)
1948 MIPS_SYS(sys_prctl , 5)
1949 MIPS_SYS(sys_rt_sigreturn, 0)
1950 MIPS_SYS(sys_rt_sigaction, 4)
1951 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1952 MIPS_SYS(sys_rt_sigpending, 2)
1953 MIPS_SYS(sys_rt_sigtimedwait, 4)
1954 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1955 MIPS_SYS(sys_rt_sigsuspend, 0)
1956 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1957 MIPS_SYS(sys_pwrite64 , 6)
1958 MIPS_SYS(sys_chown , 3)
1959 MIPS_SYS(sys_getcwd , 2)
1960 MIPS_SYS(sys_capget , 2)
1961 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 1962 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 1963 MIPS_SYS(sys_sendfile , 4)
1964 MIPS_SYS(sys_ni_syscall , 0)
1965 MIPS_SYS(sys_ni_syscall , 0)
1966 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1967 MIPS_SYS(sys_truncate64 , 4)
1968 MIPS_SYS(sys_ftruncate64 , 4)
1969 MIPS_SYS(sys_stat64 , 2)
1970 MIPS_SYS(sys_lstat64 , 2)
1971 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1972 MIPS_SYS(sys_pivot_root , 2)
1973 MIPS_SYS(sys_mincore , 3)
1974 MIPS_SYS(sys_madvise , 3)
1975 MIPS_SYS(sys_getdents64 , 3)
1976 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1977 MIPS_SYS(sys_ni_syscall , 0)
1978 MIPS_SYS(sys_gettid , 0)
1979 MIPS_SYS(sys_readahead , 5)
1980 MIPS_SYS(sys_setxattr , 5)
1981 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1982 MIPS_SYS(sys_fsetxattr , 5)
1983 MIPS_SYS(sys_getxattr , 4)
1984 MIPS_SYS(sys_lgetxattr , 4)
1985 MIPS_SYS(sys_fgetxattr , 4)
1986 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1987 MIPS_SYS(sys_llistxattr , 3)
1988 MIPS_SYS(sys_flistxattr , 3)
1989 MIPS_SYS(sys_removexattr , 2)
1990 MIPS_SYS(sys_lremovexattr, 2)
1991 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1992 MIPS_SYS(sys_tkill , 2)
1993 MIPS_SYS(sys_sendfile64 , 5)
43be1343 1994 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 1995 MIPS_SYS(sys_sched_setaffinity, 3)
1996 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1997 MIPS_SYS(sys_io_setup , 2)
1998 MIPS_SYS(sys_io_destroy , 1)
1999 MIPS_SYS(sys_io_getevents, 5)
2000 MIPS_SYS(sys_io_submit , 3)
2001 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2002 MIPS_SYS(sys_exit_group , 1)
2003 MIPS_SYS(sys_lookup_dcookie, 3)
2004 MIPS_SYS(sys_epoll_create, 1)
2005 MIPS_SYS(sys_epoll_ctl , 4)
2006 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2007 MIPS_SYS(sys_remap_file_pages, 5)
2008 MIPS_SYS(sys_set_tid_address, 1)
2009 MIPS_SYS(sys_restart_syscall, 0)
2010 MIPS_SYS(sys_fadvise64_64, 7)
2011 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2012 MIPS_SYS(sys_fstatfs64 , 2)
2013 MIPS_SYS(sys_timer_create, 3)
2014 MIPS_SYS(sys_timer_settime, 4)
2015 MIPS_SYS(sys_timer_gettime, 2)
2016 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2017 MIPS_SYS(sys_timer_delete, 1)
2018 MIPS_SYS(sys_clock_settime, 2)
2019 MIPS_SYS(sys_clock_gettime, 2)
2020 MIPS_SYS(sys_clock_getres, 2)
2021 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2022 MIPS_SYS(sys_tgkill , 3)
2023 MIPS_SYS(sys_utimes , 2)
2024 MIPS_SYS(sys_mbind , 4)
2025 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2026 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2027 MIPS_SYS(sys_mq_open , 4)
2028 MIPS_SYS(sys_mq_unlink , 1)
2029 MIPS_SYS(sys_mq_timedsend, 5)
2030 MIPS_SYS(sys_mq_timedreceive, 5)
2031 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2032 MIPS_SYS(sys_mq_getsetattr, 3)
2033 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2034 MIPS_SYS(sys_waitid , 4)
2035 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2036 MIPS_SYS(sys_add_key , 5)
388bb21a 2037 MIPS_SYS(sys_request_key, 4)
048f6b4d 2038 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2039 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2040 MIPS_SYS(sys_inotify_init, 0)
2041 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2042 MIPS_SYS(sys_inotify_rm_watch, 2)
2043 MIPS_SYS(sys_migrate_pages, 4)
2044 MIPS_SYS(sys_openat, 4)
2045 MIPS_SYS(sys_mkdirat, 3)
2046 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2047 MIPS_SYS(sys_fchownat, 5)
2048 MIPS_SYS(sys_futimesat, 3)
2049 MIPS_SYS(sys_fstatat64, 4)
2050 MIPS_SYS(sys_unlinkat, 3)
2051 MIPS_SYS(sys_renameat, 4) /* 4295 */
2052 MIPS_SYS(sys_linkat, 5)
2053 MIPS_SYS(sys_symlinkat, 3)
2054 MIPS_SYS(sys_readlinkat, 4)
2055 MIPS_SYS(sys_fchmodat, 3)
2056 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2057 MIPS_SYS(sys_pselect6, 6)
2058 MIPS_SYS(sys_ppoll, 5)
2059 MIPS_SYS(sys_unshare, 1)
b0932e06 2060 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2061 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2062 MIPS_SYS(sys_tee, 4)
2063 MIPS_SYS(sys_vmsplice, 4)
2064 MIPS_SYS(sys_move_pages, 6)
2065 MIPS_SYS(sys_set_robust_list, 2)
2066 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2067 MIPS_SYS(sys_kexec_load, 4)
2068 MIPS_SYS(sys_getcpu, 3)
2069 MIPS_SYS(sys_epoll_pwait, 6)
2070 MIPS_SYS(sys_ioprio_set, 3)
2071 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2072 MIPS_SYS(sys_utimensat, 4)
2073 MIPS_SYS(sys_signalfd, 3)
2074 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2075 MIPS_SYS(sys_eventfd, 1)
2076 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2077 MIPS_SYS(sys_timerfd_create, 2)
2078 MIPS_SYS(sys_timerfd_gettime, 2)
2079 MIPS_SYS(sys_timerfd_settime, 4)
2080 MIPS_SYS(sys_signalfd4, 4)
2081 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2082 MIPS_SYS(sys_epoll_create1, 1)
2083 MIPS_SYS(sys_dup3, 3)
2084 MIPS_SYS(sys_pipe2, 2)
2085 MIPS_SYS(sys_inotify_init1, 1)
2086 MIPS_SYS(sys_preadv, 6) /* 4330 */
2087 MIPS_SYS(sys_pwritev, 6)
2088 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2089 MIPS_SYS(sys_perf_event_open, 5)
2090 MIPS_SYS(sys_accept4, 4)
2091 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2092 MIPS_SYS(sys_fanotify_init, 2)
2093 MIPS_SYS(sys_fanotify_mark, 6)
2094 MIPS_SYS(sys_prlimit64, 4)
2095 MIPS_SYS(sys_name_to_handle_at, 5)
2096 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2097 MIPS_SYS(sys_clock_adjtime, 2)
2098 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2099};
ff4f7382
RH		 2100# undef MIPS_SYS
2101# endif /* O32 */
048f6b4d 2102
590bc601
PB		 2103static int do_store_exclusive(CPUMIPSState *env)
2104{
2105 target_ulong addr;
2106 target_ulong page_addr;
2107 target_ulong val;
2108 int flags;
2109 int segv = 0;
2110 int reg;
2111 int d;
2112
5499b6ff 2113 addr = env->lladdr;
590bc601
PB		 2114 page_addr = addr & TARGET_PAGE_MASK;
2115 start_exclusive();
2116 mmap_lock();
2117 flags = page_get_flags(page_addr);
2118 if ((flags & PAGE_READ) == 0) {
2119 segv = 1;
2120 } else {
2121 reg = env->llreg & 0x1f;
2122 d = (env->llreg & 0x20) != 0;
2123 if (d) {
2124 segv = get_user_s64(val, addr);
2125 } else {
2126 segv = get_user_s32(val, addr);
2127 }
2128 if (!segv) {
2129 if (val != env->llval) {
2130 env->active_tc.gpr[reg] = 0;
2131 } else {
2132 if (d) {
2133 segv = put_user_u64(env->llnewval, addr);
2134 } else {
2135 segv = put_user_u32(env->llnewval, addr);
2136 }
2137 if (!segv) {
2138 env->active_tc.gpr[reg] = 1;
2139 }
2140 }
2141 }
2142 }
5499b6ff 2143 env->lladdr = -1;
590bc601
PB		 2144 if (!segv) {
2145 env->active_tc.PC += 4;
2146 }
2147 mmap_unlock();
2148 end_exclusive();
2149 return segv;
2150}
2151
54b2f42c
MI		 2152/* Break codes */
2153enum {
2154 BRK_OVERFLOW = 6,
2155 BRK_DIVZERO = 7
2156};
2157
2158static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2159 unsigned int code)
2160{
2161 int ret = -1;
2162
2163 switch (code) {
2164 case BRK_OVERFLOW:
2165 case BRK_DIVZERO:
2166 info->si_signo = TARGET_SIGFPE;
2167 info->si_errno = 0;
2168 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2169 queue_signal(env, info->si_signo, &*info);
2170 ret = 0;
2171 break;
2172 default:
2173 break;
2174 }
2175
2176 return ret;
2177}
2178
048f6b4d
FB		 2179void cpu_loop(CPUMIPSState *env)
2180{
0315c31c 2181 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2182 target_siginfo_t info;
ff4f7382
RH		 2183 int trapnr;
2184 abi_long ret;
2185# ifdef TARGET_ABI_MIPSO32
048f6b4d 2186 unsigned int syscall_num;
ff4f7382 2187# endif
048f6b4d
FB		 2188
2189 for(;;) {
0315c31c 2190 cpu_exec_start(cs);
048f6b4d 2191 trapnr = cpu_mips_exec(env);
0315c31c 2192 cpu_exec_end(cs);
048f6b4d
FB		 2193 switch(trapnr) {
2194 case EXCP_SYSCALL:
b5dc7732 2195 env->active_tc.PC += 4;
ff4f7382
RH		 2196# ifdef TARGET_ABI_MIPSO32
2197 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2198 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2199 ret = -TARGET_ENOSYS;
388bb21a
TS		 2200 } else {
2201 int nb_args;
992f48a0
BS		 2202 abi_ulong sp_reg;
2203 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2204
2205 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2206 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2207 switch (nb_args) {
2208 /* these arguments are taken from the stack */
94c19610
ACH		 2209 case 8:
2210 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2211 goto done_syscall;
2212 }
2213 case 7:
2214 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2215 goto done_syscall;
2216 }
2217 case 6:
2218 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2219 goto done_syscall;
2220 }
2221 case 5:
2222 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2223 goto done_syscall;
2224 }
388bb21a
TS		 2225 default:
2226 break;
048f6b4d 2227 }
b5dc7732
TS		 2228 ret = do_syscall(env, env->active_tc.gpr[2],
2229 env->active_tc.gpr[4],
2230 env->active_tc.gpr[5],
2231 env->active_tc.gpr[6],
2232 env->active_tc.gpr[7],
5945cfcb 2233 arg5, arg6, arg7, arg8);
388bb21a 2234 }
94c19610 2235done_syscall:
ff4f7382
RH		 2236# else
2237 ret = do_syscall(env, env->active_tc.gpr[2],
2238 env->active_tc.gpr[4], env->active_tc.gpr[5],
2239 env->active_tc.gpr[6], env->active_tc.gpr[7],
2240 env->active_tc.gpr[8], env->active_tc.gpr[9],
2241 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2242# endif /* O32 */
0b1bcb00
PB		 2243 if (ret == -TARGET_QEMU_ESIGRETURN) {
2244 /* Returning from a successful sigreturn syscall.
2245 Avoid clobbering register state. */
2246 break;
2247 }
ff4f7382 2248 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2249 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2250 ret = -ret;
2251 } else {
b5dc7732 2252 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2253 }
b5dc7732 2254 env->active_tc.gpr[2] = ret;
048f6b4d 2255 break;
ca7c2b1b
TS		 2256 case EXCP_TLBL:
2257 case EXCP_TLBS:
e6e5bd2d
WT		 2258 case EXCP_AdEL:
2259 case EXCP_AdES:
e4474235
PB		 2260 info.si_signo = TARGET_SIGSEGV;
2261 info.si_errno = 0;
2262 /* XXX: check env->error_code */
2263 info.si_code = TARGET_SEGV_MAPERR;
2264 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2265 queue_signal(env, info.si_signo, &info);
2266 break;
6900e84b 2267 case EXCP_CpU:
048f6b4d 2268 case EXCP_RI:
bc1ad2de
FB		 2269 info.si_signo = TARGET_SIGILL;
2270 info.si_errno = 0;
2271 info.si_code = 0;
624f7979 2272 queue_signal(env, info.si_signo, &info);
048f6b4d 2273 break;
106ec879
FB		 2274 case EXCP_INTERRUPT:
2275 /* just indicate that signals should be handled asap */
2276 break;
d08b2a28
PB		 2277 case EXCP_DEBUG:
2278 {
2279 int sig;
2280
db6b81d4 2281 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2282 if (sig)
2283 {
2284 info.si_signo = sig;
2285 info.si_errno = 0;
2286 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2287 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2288 }
2289 }
2290 break;
590bc601
PB		 2291 case EXCP_SC:
2292 if (do_store_exclusive(env)) {
2293 info.si_signo = TARGET_SIGSEGV;
2294 info.si_errno = 0;
2295 info.si_code = TARGET_SEGV_MAPERR;
2296 info._sifields._sigfault._addr = env->active_tc.PC;
2297 queue_signal(env, info.si_signo, &info);
2298 }
2299 break;
853c3240
JL		 2300 case EXCP_DSPDIS:
2301 info.si_signo = TARGET_SIGILL;
2302 info.si_errno = 0;
2303 info.si_code = TARGET_ILL_ILLOPC;
2304 queue_signal(env, info.si_signo, &info);
2305 break;
54b2f42c
MI		 2306 /* The code below was inspired by the MIPS Linux kernel trap
2307 * handling code in arch/mips/kernel/traps.c.
2308 */
2309 case EXCP_BREAK:
2310 {
2311 abi_ulong trap_instr;
2312 unsigned int code;
2313
a0333817
KCY		 2314 if (env->hflags & MIPS_HFLAG_M16) {
2315 if (env->insn_flags & ASE_MICROMIPS) {
2316 /* microMIPS mode */
2317 abi_ulong instr[2];
2318
2319 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2320 get_user_u16(instr[1], env->active_tc.PC + 2);
2321
2322 trap_instr = (instr[0] << 16) | instr[1];
2323 } else {
2324 /* MIPS16e mode */
2325 ret = get_user_u16(trap_instr, env->active_tc.PC);
2326 if (ret != 0) {
2327 goto error;
2328 }
2329 code = (trap_instr >> 6) & 0x3f;
2330 if (do_break(env, &info, code) != 0) {
2331 goto error;
2332 }
2333 break;
2334 }
2335 } else {
2336 ret = get_user_ual(trap_instr, env->active_tc.PC);
2337 }
2338
54b2f42c
MI		 2339 if (ret != 0) {
2340 goto error;
2341 }
2342
2343 /* As described in the original Linux kernel code, the
2344 * below checks on 'code' are to work around an old
2345 * assembly bug.
2346 */
2347 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2348 if (code >= (1 << 10)) {
2349 code >>= 10;
2350 }
2351
2352 if (do_break(env, &info, code) != 0) {
2353 goto error;
2354 }
2355 }
2356 break;
2357 case EXCP_TRAP:
2358 {
2359 abi_ulong trap_instr;
2360 unsigned int code = 0;
2361
a0333817
KCY		 2362 if (env->hflags & MIPS_HFLAG_M16) {
2363 /* microMIPS mode */
2364 abi_ulong instr[2];
2365
2366 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2367 get_user_u16(instr[1], env->active_tc.PC + 2);
2368
2369 trap_instr = (instr[0] << 16) | instr[1];
2370 } else {
2371 ret = get_user_ual(trap_instr, env->active_tc.PC);
2372 }
2373
54b2f42c
MI		 2374 if (ret != 0) {
2375 goto error;
2376 }
2377
2378 /* The immediate versions don't provide a code. */
2379 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2380 if (env->hflags & MIPS_HFLAG_M16) {
2381 /* microMIPS mode */
2382 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2383 } else {
2384 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2385 }
54b2f42c
MI		 2386 }
2387
2388 if (do_break(env, &info, code) != 0) {
2389 goto error;
2390 }
2391 }
2392 break;
048f6b4d 2393 default:
54b2f42c 2394error:
5fafdf24 2395 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2396 trapnr);
878096ee 2397 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2398 abort();
2399 }
2400 process_pending_signals(env);
2401 }
2402}
2403#endif
2404
d962783e
JL		 2405#ifdef TARGET_OPENRISC
2406
2407void cpu_loop(CPUOpenRISCState *env)
2408{
878096ee 2409 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2410 int trapnr, gdbsig;
2411
2412 for (;;) {
2413 trapnr = cpu_exec(env);
2414 gdbsig = 0;
2415
2416 switch (trapnr) {
2417 case EXCP_RESET:
2418 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2419 exit(1);
2420 break;
2421 case EXCP_BUSERR:
2422 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2423 gdbsig = SIGBUS;
2424 break;
2425 case EXCP_DPF:
2426 case EXCP_IPF:
878096ee 2427 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2428 gdbsig = TARGET_SIGSEGV;
2429 break;
2430 case EXCP_TICK:
2431 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2432 break;
2433 case EXCP_ALIGN:
2434 qemu_log("\nAlignment pc is %#x\n", env->pc);
2435 gdbsig = SIGBUS;
2436 break;
2437 case EXCP_ILLEGAL:
2438 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2439 gdbsig = SIGILL;
2440 break;
2441 case EXCP_INT:
2442 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2443 break;
2444 case EXCP_DTLBMISS:
2445 case EXCP_ITLBMISS:
2446 qemu_log("\nTLB miss\n");
2447 break;
2448 case EXCP_RANGE:
2449 qemu_log("\nRange\n");
2450 gdbsig = SIGSEGV;
2451 break;
2452 case EXCP_SYSCALL:
2453 env->pc += 4; /* 0xc00; */
2454 env->gpr[11] = do_syscall(env,
2455 env->gpr[11], /* return value */
2456 env->gpr[3], /* r3 - r7 are params */
2457 env->gpr[4],
2458 env->gpr[5],
2459 env->gpr[6],
2460 env->gpr[7],
2461 env->gpr[8], 0, 0);
2462 break;
2463 case EXCP_FPE:
2464 qemu_log("\nFloating point error\n");
2465 break;
2466 case EXCP_TRAP:
2467 qemu_log("\nTrap\n");
2468 gdbsig = SIGTRAP;
2469 break;
2470 case EXCP_NR:
2471 qemu_log("\nNR\n");
2472 break;
2473 default:
2474 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2475 trapnr);
878096ee 2476 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2477 gdbsig = TARGET_SIGILL;
2478 break;
2479 }
2480 if (gdbsig) {
db6b81d4 2481 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2482 if (gdbsig != TARGET_SIGTRAP) {
2483 exit(1);
2484 }
2485 }
2486
2487 process_pending_signals(env);
2488 }
2489}
2490
2491#endif /* TARGET_OPENRISC */
2492
fdf9b3e8 2493#ifdef TARGET_SH4
05390248 2494void cpu_loop(CPUSH4State *env)
fdf9b3e8 2495{
878096ee 2496 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2497 int trapnr, ret;
c227f099 2498 target_siginfo_t info;
3b46e624 2499
fdf9b3e8
FB		 2500 while (1) {
2501 trapnr = cpu_sh4_exec (env);
3b46e624 2502
fdf9b3e8
FB		 2503 switch (trapnr) {
2504 case 0x160:
0b6d3ae0 2505 env->pc += 2;
5fafdf24
TS		 2506 ret = do_syscall(env,
2507 env->gregs[3],
2508 env->gregs[4],
2509 env->gregs[5],
2510 env->gregs[6],
2511 env->gregs[7],
2512 env->gregs[0],
5945cfcb
PM		 2513 env->gregs[1],
2514 0, 0);
9c2a9ea1 2515 env->gregs[0] = ret;
fdf9b3e8 2516 break;
c3b5bc8a
TS		 2517 case EXCP_INTERRUPT:
2518 /* just indicate that signals should be handled asap */
2519 break;
355fb23d
PB		 2520 case EXCP_DEBUG:
2521 {
2522 int sig;
2523
db6b81d4 2524 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2525 if (sig)
2526 {
2527 info.si_signo = sig;
2528 info.si_errno = 0;
2529 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2530 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2531 }
2532 }
2533 break;
c3b5bc8a
TS		 2534 case 0xa0:
2535 case 0xc0:
2536 info.si_signo = SIGSEGV;
2537 info.si_errno = 0;
2538 info.si_code = TARGET_SEGV_MAPERR;
2539 info._sifields._sigfault._addr = env->tea;
624f7979 2540 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2541 break;
2542
fdf9b3e8
FB		 2543 default:
2544 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2545 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2546 exit (1);
2547 }
2548 process_pending_signals (env);
2549 }
2550}
2551#endif
2552
48733d19 2553#ifdef TARGET_CRIS
05390248 2554void cpu_loop(CPUCRISState *env)
48733d19 2555{
878096ee 2556 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2557 int trapnr, ret;
c227f099 2558 target_siginfo_t info;
48733d19
TS		 2559
2560 while (1) {
2561 trapnr = cpu_cris_exec (env);
2562 switch (trapnr) {
2563 case 0xaa:
2564 {
2565 info.si_signo = SIGSEGV;
2566 info.si_errno = 0;
2567 /* XXX: check env->error_code */
2568 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2569 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2570 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2571 }
2572 break;
b6d3abda
EI		 2573 case EXCP_INTERRUPT:
2574 /* just indicate that signals should be handled asap */
2575 break;
48733d19
TS		 2576 case EXCP_BREAK:
2577 ret = do_syscall(env,
2578 env->regs[9],
2579 env->regs[10],
2580 env->regs[11],
2581 env->regs[12],
2582 env->regs[13],
2583 env->pregs[7],
5945cfcb
PM		 2584 env->pregs[11],
2585 0, 0);
48733d19 2586 env->regs[10] = ret;
48733d19
TS		 2587 break;
2588 case EXCP_DEBUG:
2589 {
2590 int sig;
2591
db6b81d4 2592 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2593 if (sig)
2594 {
2595 info.si_signo = sig;
2596 info.si_errno = 0;
2597 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2598 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2599 }
2600 }
2601 break;
2602 default:
2603 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2604 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2605 exit (1);
2606 }
2607 process_pending_signals (env);
2608 }
2609}
2610#endif
2611
b779e29e 2612#ifdef TARGET_MICROBLAZE
05390248 2613void cpu_loop(CPUMBState *env)
b779e29e 2614{
878096ee 2615 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2616 int trapnr, ret;
c227f099 2617 target_siginfo_t info;
b779e29e
EI		 2618
2619 while (1) {
2620 trapnr = cpu_mb_exec (env);
2621 switch (trapnr) {
2622 case 0xaa:
2623 {
2624 info.si_signo = SIGSEGV;
2625 info.si_errno = 0;
2626 /* XXX: check env->error_code */
2627 info.si_code = TARGET_SEGV_MAPERR;
2628 info._sifields._sigfault._addr = 0;
2629 queue_signal(env, info.si_signo, &info);
2630 }
2631 break;
2632 case EXCP_INTERRUPT:
2633 /* just indicate that signals should be handled asap */
2634 break;
2635 case EXCP_BREAK:
2636 /* Return address is 4 bytes after the call. */
2637 env->regs[14] += 4;
d7dce494 2638 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2639 ret = do_syscall(env,
2640 env->regs[12],
2641 env->regs[5],
2642 env->regs[6],
2643 env->regs[7],
2644 env->regs[8],
2645 env->regs[9],
5945cfcb
PM		 2646 env->regs[10],
2647 0, 0);
b779e29e 2648 env->regs[3] = ret;
b779e29e 2649 break;
b76da7e3
EI		 2650 case EXCP_HW_EXCP:
2651 env->regs[17] = env->sregs[SR_PC] + 4;
2652 if (env->iflags & D_FLAG) {
2653 env->sregs[SR_ESR] |= 1 << 12;
2654 env->sregs[SR_PC] -= 4;
b4916d7b 2655 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2656 }
2657
2658 env->iflags &= ~(IMM_FLAG | D_FLAG);
2659
2660 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2661 case ESR_EC_DIVZERO:
2662 info.si_signo = SIGFPE;
2663 info.si_errno = 0;
2664 info.si_code = TARGET_FPE_FLTDIV;
2665 info._sifields._sigfault._addr = 0;
2666 queue_signal(env, info.si_signo, &info);
2667 break;
b76da7e3
EI		 2668 case ESR_EC_FPU:
2669 info.si_signo = SIGFPE;
2670 info.si_errno = 0;
2671 if (env->sregs[SR_FSR] & FSR_IO) {
2672 info.si_code = TARGET_FPE_FLTINV;
2673 }
2674 if (env->sregs[SR_FSR] & FSR_DZ) {
2675 info.si_code = TARGET_FPE_FLTDIV;
2676 }
2677 info._sifields._sigfault._addr = 0;
2678 queue_signal(env, info.si_signo, &info);
2679 break;
2680 default:
2681 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2682 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2683 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2684 exit (1);
2685 break;
2686 }
2687 break;
b779e29e
EI		 2688 case EXCP_DEBUG:
2689 {
2690 int sig;
2691
db6b81d4 2692 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2693 if (sig)
2694 {
2695 info.si_signo = sig;
2696 info.si_errno = 0;
2697 info.si_code = TARGET_TRAP_BRKPT;
2698 queue_signal(env, info.si_signo, &info);
2699 }
2700 }
2701 break;
2702 default:
2703 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2704 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2705 exit (1);
2706 }
2707 process_pending_signals (env);
2708 }
2709}
2710#endif
2711
e6e5906b
PB		 2712#ifdef TARGET_M68K
2713
2714void cpu_loop(CPUM68KState *env)
2715{
878096ee 2716 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2717 int trapnr;
2718 unsigned int n;
c227f099 2719 target_siginfo_t info;
e6e5906b 2720 TaskState *ts = env->opaque;
3b46e624 2721
e6e5906b
PB		 2722 for(;;) {
2723 trapnr = cpu_m68k_exec(env);
2724 switch(trapnr) {
2725 case EXCP_ILLEGAL:
2726 {
2727 if (ts->sim_syscalls) {
2728 uint16_t nr;
2729 nr = lduw(env->pc + 2);
2730 env->pc += 4;
2731 do_m68k_simcall(env, nr);
2732 } else {
2733 goto do_sigill;
2734 }
2735 }
2736 break;
a87295e8 2737 case EXCP_HALT_INSN:
e6e5906b 2738 /* Semihosing syscall. */
a87295e8 2739 env->pc += 4;
e6e5906b
PB		 2740 do_m68k_semihosting(env, env->dregs[0]);
2741 break;
2742 case EXCP_LINEA:
2743 case EXCP_LINEF:
2744 case EXCP_UNSUPPORTED:
2745 do_sigill:
2746 info.si_signo = SIGILL;
2747 info.si_errno = 0;
2748 info.si_code = TARGET_ILL_ILLOPN;
2749 info._sifields._sigfault._addr = env->pc;
624f7979 2750 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2751 break;
2752 case EXCP_TRAP0:
2753 {
2754 ts->sim_syscalls = 0;
2755 n = env->dregs[0];
2756 env->pc += 2;
5fafdf24
TS		 2757 env->dregs[0] = do_syscall(env,
2758 n,
e6e5906b
PB		 2759 env->dregs[1],
2760 env->dregs[2],
2761 env->dregs[3],
2762 env->dregs[4],
2763 env->dregs[5],
5945cfcb
PM		 2764 env->aregs[0],
2765 0, 0);
e6e5906b
PB		 2766 }
2767 break;
2768 case EXCP_INTERRUPT:
2769 /* just indicate that signals should be handled asap */
2770 break;
2771 case EXCP_ACCESS:
2772 {
2773 info.si_signo = SIGSEGV;
2774 info.si_errno = 0;
2775 /* XXX: check env->error_code */
2776 info.si_code = TARGET_SEGV_MAPERR;
2777 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2778 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2779 }
2780 break;
2781 case EXCP_DEBUG:
2782 {
2783 int sig;
2784
db6b81d4 2785 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 2786 if (sig)
2787 {
2788 info.si_signo = sig;
2789 info.si_errno = 0;
2790 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2791 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2792 }
2793 }
2794 break;
2795 default:
5fafdf24 2796 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 2797 trapnr);
878096ee 2798 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 2799 abort();
2800 }
2801 process_pending_signals(env);
2802 }
2803}
2804#endif /* TARGET_M68K */
2805
7a3148a9 2806#ifdef TARGET_ALPHA
6910b8f6
RH		 2807static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2808{
2809 target_ulong addr, val, tmp;
2810 target_siginfo_t info;
2811 int ret = 0;
2812
2813 addr = env->lock_addr;
2814 tmp = env->lock_st_addr;
2815 env->lock_addr = -1;
2816 env->lock_st_addr = 0;
2817
2818 start_exclusive();
2819 mmap_lock();
2820
2821 if (addr == tmp) {
2822 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2823 goto do_sigsegv;
2824 }
2825
2826 if (val == env->lock_value) {
2827 tmp = env->ir[reg];
2828 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2829 goto do_sigsegv;
2830 }
2831 ret = 1;
2832 }
2833 }
2834 env->ir[reg] = ret;
2835 env->pc += 4;
2836
2837 mmap_unlock();
2838 end_exclusive();
2839 return;
2840
2841 do_sigsegv:
2842 mmap_unlock();
2843 end_exclusive();
2844
2845 info.si_signo = TARGET_SIGSEGV;
2846 info.si_errno = 0;
2847 info.si_code = TARGET_SEGV_MAPERR;
2848 info._sifields._sigfault._addr = addr;
2849 queue_signal(env, TARGET_SIGSEGV, &info);
2850}
2851
05390248 2852void cpu_loop(CPUAlphaState *env)
7a3148a9 2853{
878096ee 2854 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 2855 int trapnr;
c227f099 2856 target_siginfo_t info;
6049f4f8 2857 abi_long sysret;
3b46e624 2858
7a3148a9
JM		 2859 while (1) {
2860 trapnr = cpu_alpha_exec (env);
3b46e624 2861
ac316ca4
RH		 2862 /* All of the traps imply a transition through PALcode, which
2863 implies an REI instruction has been executed. Which means
2864 that the intr_flag should be cleared. */
2865 env->intr_flag = 0;
2866
7a3148a9
JM		 2867 switch (trapnr) {
2868 case EXCP_RESET:
2869 fprintf(stderr, "Reset requested. Exit\n");
2870 exit(1);
2871 break;
2872 case EXCP_MCHK:
2873 fprintf(stderr, "Machine check exception. Exit\n");
2874 exit(1);
2875 break;
07b6c13b
RH		 2876 case EXCP_SMP_INTERRUPT:
2877 case EXCP_CLK_INTERRUPT:
2878 case EXCP_DEV_INTERRUPT:
5fafdf24 2879 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2880 exit(1);
2881 break;
07b6c13b 2882 case EXCP_MMFAULT:
6910b8f6 2883 env->lock_addr = -1;
6049f4f8
RH		 2884 info.si_signo = TARGET_SIGSEGV;
2885 info.si_errno = 0;
129d8aa5 2886 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2887 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2888 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2889 queue_signal(env, info.si_signo, &info);
7a3148a9 2890 break;
7a3148a9 2891 case EXCP_UNALIGN:
6910b8f6 2892 env->lock_addr = -1;
6049f4f8
RH		 2893 info.si_signo = TARGET_SIGBUS;
2894 info.si_errno = 0;
2895 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2896 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2897 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2898 break;
2899 case EXCP_OPCDEC:
6049f4f8 2900 do_sigill:
6910b8f6 2901 env->lock_addr = -1;
6049f4f8
RH		 2902 info.si_signo = TARGET_SIGILL;
2903 info.si_errno = 0;
2904 info.si_code = TARGET_ILL_ILLOPC;
2905 info._sifields._sigfault._addr = env->pc;
2906 queue_signal(env, info.si_signo, &info);
7a3148a9 2907 break;
07b6c13b
RH		 2908 case EXCP_ARITH:
2909 env->lock_addr = -1;
2910 info.si_signo = TARGET_SIGFPE;
2911 info.si_errno = 0;
2912 info.si_code = TARGET_FPE_FLTINV;
2913 info._sifields._sigfault._addr = env->pc;
2914 queue_signal(env, info.si_signo, &info);
2915 break;
7a3148a9 2916 case EXCP_FEN:
6049f4f8 2917 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2918 break;
07b6c13b 2919 case EXCP_CALL_PAL:
6910b8f6 2920 env->lock_addr = -1;
07b6c13b 2921 switch (env->error_code) {
6049f4f8
RH		 2922 case 0x80:
2923 /* BPT */
2924 info.si_signo = TARGET_SIGTRAP;
2925 info.si_errno = 0;
2926 info.si_code = TARGET_TRAP_BRKPT;
2927 info._sifields._sigfault._addr = env->pc;
2928 queue_signal(env, info.si_signo, &info);
2929 break;
2930 case 0x81:
2931 /* BUGCHK */
2932 info.si_signo = TARGET_SIGTRAP;
2933 info.si_errno = 0;
2934 info.si_code = 0;
2935 info._sifields._sigfault._addr = env->pc;
2936 queue_signal(env, info.si_signo, &info);
2937 break;
2938 case 0x83:
2939 /* CALLSYS */
2940 trapnr = env->ir[IR_V0];
2941 sysret = do_syscall(env, trapnr,
2942 env->ir[IR_A0], env->ir[IR_A1],
2943 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 2944 env->ir[IR_A4], env->ir[IR_A5],
2945 0, 0);
a5b3b13b
RH		 2946 if (trapnr == TARGET_NR_sigreturn
2947 || trapnr == TARGET_NR_rt_sigreturn) {
2948 break;
2949 }
2950 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 2951 to how this is handled internal to Linux kernel.
2952 (Ab)use trapnr temporarily as boolean indicating error. */
2953 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2954 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2955 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 2956 break;
2957 case 0x86:
2958 /* IMB */
2959 /* ??? We can probably elide the code using page_unprotect
2960 that is checking for self-modifying code. Instead we
2961 could simply call tb_flush here. Until we work out the
2962 changes required to turn off the extra write protection,
2963 this can be a no-op. */
2964 break;
2965 case 0x9E:
2966 /* RDUNIQUE */
2967 /* Handled in the translator for usermode. */
2968 abort();
2969 case 0x9F:
2970 /* WRUNIQUE */
2971 /* Handled in the translator for usermode. */
2972 abort();
2973 case 0xAA:
2974 /* GENTRAP */
2975 info.si_signo = TARGET_SIGFPE;
2976 switch (env->ir[IR_A0]) {
2977 case TARGET_GEN_INTOVF:
2978 info.si_code = TARGET_FPE_INTOVF;
2979 break;
2980 case TARGET_GEN_INTDIV:
2981 info.si_code = TARGET_FPE_INTDIV;
2982 break;
2983 case TARGET_GEN_FLTOVF:
2984 info.si_code = TARGET_FPE_FLTOVF;
2985 break;
2986 case TARGET_GEN_FLTUND:
2987 info.si_code = TARGET_FPE_FLTUND;
2988 break;
2989 case TARGET_GEN_FLTINV:
2990 info.si_code = TARGET_FPE_FLTINV;
2991 break;
2992 case TARGET_GEN_FLTINE:
2993 info.si_code = TARGET_FPE_FLTRES;
2994 break;
2995 case TARGET_GEN_ROPRAND:
2996 info.si_code = 0;
2997 break;
2998 default:
2999 info.si_signo = TARGET_SIGTRAP;
3000 info.si_code = 0;
3001 break;
3002 }
3003 info.si_errno = 0;
3004 info._sifields._sigfault._addr = env->pc;
3005 queue_signal(env, info.si_signo, &info);
3006 break;
3007 default:
3008 goto do_sigill;
3009 }
7a3148a9 3010 break;
7a3148a9 3011 case EXCP_DEBUG:
db6b81d4 3012 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3013 if (info.si_signo) {
6910b8f6 3014 env->lock_addr = -1;
6049f4f8
RH		 3015 info.si_errno = 0;
3016 info.si_code = TARGET_TRAP_BRKPT;
3017 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3018 }
3019 break;
6910b8f6
RH		 3020 case EXCP_STL_C:
3021 case EXCP_STQ_C:
3022 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3023 break;
d0f20495
RH		 3024 case EXCP_INTERRUPT:
3025 /* Just indicate that signals should be handled asap. */
3026 break;
7a3148a9
JM		 3027 default:
3028 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3029 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3030 exit (1);
3031 }
3032 process_pending_signals (env);
3033 }
3034}
3035#endif /* TARGET_ALPHA */
3036
a4c075f1
UH		 3037#ifdef TARGET_S390X
3038void cpu_loop(CPUS390XState *env)
3039{
878096ee 3040 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3041 int trapnr, n, sig;
a4c075f1 3042 target_siginfo_t info;
d5a103cd 3043 target_ulong addr;
a4c075f1
UH		 3044
3045 while (1) {
d5a103cd 3046 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3047 switch (trapnr) {
3048 case EXCP_INTERRUPT:
d5a103cd 3049 /* Just indicate that signals should be handled asap. */
a4c075f1 3050 break;
a4c075f1 3051
d5a103cd
RH		 3052 case EXCP_SVC:
3053 n = env->int_svc_code;
3054 if (!n) {
3055 /* syscalls > 255 */
3056 n = env->regs[1];
a4c075f1 3057 }
d5a103cd
RH		 3058 env->psw.addr += env->int_svc_ilen;
3059 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3060 env->regs[4], env->regs[5],
3061 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3062 break;
d5a103cd
RH		 3063
3064 case EXCP_DEBUG:
db6b81d4 3065 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3066 if (sig) {
3067 n = TARGET_TRAP_BRKPT;
3068 goto do_signal_pc;
a4c075f1
UH		 3069 }
3070 break;
d5a103cd
RH		 3071 case EXCP_PGM:
3072 n = env->int_pgm_code;
3073 switch (n) {
3074 case PGM_OPERATION:
3075 case PGM_PRIVILEGED:
3076 sig = SIGILL;
3077 n = TARGET_ILL_ILLOPC;
3078 goto do_signal_pc;
3079 case PGM_PROTECTION:
3080 case PGM_ADDRESSING:
3081 sig = SIGSEGV;
a4c075f1 3082 /* XXX: check env->error_code */
d5a103cd
RH		 3083 n = TARGET_SEGV_MAPERR;
3084 addr = env->__excp_addr;
3085 goto do_signal;
3086 case PGM_EXECUTE:
3087 case PGM_SPECIFICATION:
3088 case PGM_SPECIAL_OP:
3089 case PGM_OPERAND:
3090 do_sigill_opn:
3091 sig = SIGILL;
3092 n = TARGET_ILL_ILLOPN;
3093 goto do_signal_pc;
3094
3095 case PGM_FIXPT_OVERFLOW:
3096 sig = SIGFPE;
3097 n = TARGET_FPE_INTOVF;
3098 goto do_signal_pc;
3099 case PGM_FIXPT_DIVIDE:
3100 sig = SIGFPE;
3101 n = TARGET_FPE_INTDIV;
3102 goto do_signal_pc;
3103
3104 case PGM_DATA:
3105 n = (env->fpc >> 8) & 0xff;
3106 if (n == 0xff) {
3107 /* compare-and-trap */
3108 goto do_sigill_opn;
3109 } else {
3110 /* An IEEE exception, simulated or otherwise. */
3111 if (n & 0x80) {
3112 n = TARGET_FPE_FLTINV;
3113 } else if (n & 0x40) {
3114 n = TARGET_FPE_FLTDIV;
3115 } else if (n & 0x20) {
3116 n = TARGET_FPE_FLTOVF;
3117 } else if (n & 0x10) {
3118 n = TARGET_FPE_FLTUND;
3119 } else if (n & 0x08) {
3120 n = TARGET_FPE_FLTRES;
3121 } else {
3122 /* ??? Quantum exception; BFP, DFP error. */
3123 goto do_sigill_opn;
3124 }
3125 sig = SIGFPE;
3126 goto do_signal_pc;
3127 }
3128
3129 default:
3130 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3131 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3132 exit(1);
a4c075f1
UH		 3133 }
3134 break;
d5a103cd
RH		 3135
3136 do_signal_pc:
3137 addr = env->psw.addr;
3138 do_signal:
3139 info.si_signo = sig;
3140 info.si_errno = 0;
3141 info.si_code = n;
3142 info._sifields._sigfault._addr = addr;
3143 queue_signal(env, info.si_signo, &info);
a4c075f1 3144 break;
d5a103cd 3145
a4c075f1 3146 default:
d5a103cd 3147 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3148 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3149 exit(1);
a4c075f1
UH		 3150 }
3151 process_pending_signals (env);
3152 }
3153}
3154
3155#endif /* TARGET_S390X */
3156
a2247f8e 3157THREAD CPUState *thread_cpu;
59faf6d6 3158
edf8e2af
MW		 3159void task_settid(TaskState *ts)
3160{
3161 if (ts->ts_tid == 0) {
edf8e2af 3162 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3163 }
3164}
3165
3166void stop_all_tasks(void)
3167{
3168 /*
3169 * We trust that when using NPTL, start_exclusive()
3170 * handles thread stopping correctly.
3171 */
3172 start_exclusive();
3173}
3174
c3a92833 3175/* Assumes contents are already zeroed. */
624f7979
PB		 3176void init_task_state(TaskState *ts)
3177{
3178 int i;
3179
624f7979
PB		 3180 ts->used = 1;
3181 ts->first_free = ts->sigqueue_table;
3182 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3183 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3184 }
3185 ts->sigqueue_table[i].next = NULL;
3186}
fc9c5412
JS		 3187
3188static void handle_arg_help(const char *arg)
3189{
3190 usage();
3191}
3192
3193static void handle_arg_log(const char *arg)
3194{
3195 int mask;
fc9c5412 3196
4fde1eba 3197 mask = qemu_str_to_log_mask(arg);
fc9c5412 3198 if (!mask) {
59a6fa6e 3199 qemu_print_log_usage(stdout);
fc9c5412
JS		 3200 exit(1);
3201 }
24537a01 3202 qemu_set_log(mask);
fc9c5412
JS		 3203}
3204
50171d42 3205static void handle_arg_log_filename(const char *arg)
3206{
9a7e5424 3207 qemu_set_log_filename(arg);
50171d42 3208}
3209
fc9c5412
JS		 3210static void handle_arg_set_env(const char *arg)
3211{
3212 char *r, *p, *token;
3213 r = p = strdup(arg);
3214 while ((token = strsep(&p, ",")) != NULL) {
3215 if (envlist_setenv(envlist, token) != 0) {
3216 usage();
3217 }
3218 }
3219 free(r);
3220}
3221
3222static void handle_arg_unset_env(const char *arg)
3223{
3224 char *r, *p, *token;
3225 r = p = strdup(arg);
3226 while ((token = strsep(&p, ",")) != NULL) {
3227 if (envlist_unsetenv(envlist, token) != 0) {
3228 usage();
3229 }
3230 }
3231 free(r);
3232}
3233
3234static void handle_arg_argv0(const char *arg)
3235{
3236 argv0 = strdup(arg);
3237}
3238
3239static void handle_arg_stack_size(const char *arg)
3240{
3241 char *p;
3242 guest_stack_size = strtoul(arg, &p, 0);
3243 if (guest_stack_size == 0) {
3244 usage();
3245 }
3246
3247 if (*p == 'M') {
3248 guest_stack_size *= 1024 * 1024;
3249 } else if (*p == 'k' || *p == 'K') {
3250 guest_stack_size *= 1024;
3251 }
3252}
3253
3254static void handle_arg_ld_prefix(const char *arg)
3255{
3256 interp_prefix = strdup(arg);
3257}
3258
3259static void handle_arg_pagesize(const char *arg)
3260{
3261 qemu_host_page_size = atoi(arg);
3262 if (qemu_host_page_size == 0 ||
3263 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3264 fprintf(stderr, "page size must be a power of two\n");
3265 exit(1);
3266 }
3267}
3268
3269static void handle_arg_gdb(const char *arg)
3270{
3271 gdbstub_port = atoi(arg);
3272}
3273
3274static void handle_arg_uname(const char *arg)
3275{
3276 qemu_uname_release = strdup(arg);
3277}
3278
3279static void handle_arg_cpu(const char *arg)
3280{
3281 cpu_model = strdup(arg);
c8057f95 3282 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3283 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3284#if defined(cpu_list)
3285 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3286#endif
3287 exit(1);
3288 }
3289}
3290
3291#if defined(CONFIG_USE_GUEST_BASE)
3292static void handle_arg_guest_base(const char *arg)
3293{
3294 guest_base = strtol(arg, NULL, 0);
3295 have_guest_base = 1;
3296}
3297
3298static void handle_arg_reserved_va(const char *arg)
3299{
3300 char *p;
3301 int shift = 0;
3302 reserved_va = strtoul(arg, &p, 0);
3303 switch (*p) {
3304 case 'k':
3305 case 'K':
3306 shift = 10;
3307 break;
3308 case 'M':
3309 shift = 20;
3310 break;
3311 case 'G':
3312 shift = 30;
3313 break;
3314 }
3315 if (shift) {
3316 unsigned long unshifted = reserved_va;
3317 p++;
3318 reserved_va <<= shift;
3319 if (((reserved_va >> shift) != unshifted)
3320#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3321 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3322#endif
3323 ) {
3324 fprintf(stderr, "Reserved virtual address too big\n");
3325 exit(1);
3326 }
3327 }
3328 if (*p) {
3329 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3330 exit(1);
3331 }
3332}
3333#endif
3334
3335static void handle_arg_singlestep(const char *arg)
3336{
3337 singlestep = 1;
3338}
3339
3340static void handle_arg_strace(const char *arg)
3341{
3342 do_strace = 1;
3343}
3344
3345static void handle_arg_version(const char *arg)
3346{
2e59915d 3347 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3348 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3349 exit(0);
fc9c5412
JS		 3350}
3351
3352struct qemu_argument {
3353 const char *argv;
3354 const char *env;
3355 bool has_arg;
3356 void (*handle_opt)(const char *arg);
3357 const char *example;
3358 const char *help;
3359};
3360
42644cee 3361static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3362 {"h", "", false, handle_arg_help,
3363 "", "print this help"},
3364 {"g", "QEMU_GDB", true, handle_arg_gdb,
3365 "port", "wait gdb connection to 'port'"},
3366 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3367 "path", "set the elf interpreter prefix to 'path'"},
3368 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3369 "size", "set the stack size to 'size' bytes"},
3370 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3371 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3372 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3373 "var=value", "sets targets environment variable (see below)"},
3374 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3375 "var", "unsets targets environment variable (see below)"},
3376 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3377 "argv0", "forces target process argv[0] to be 'argv0'"},
3378 {"r", "QEMU_UNAME", true, handle_arg_uname,
3379 "uname", "set qemu uname release string to 'uname'"},
3380#if defined(CONFIG_USE_GUEST_BASE)
3381 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3382 "address", "set guest_base address to 'address'"},
3383 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3384 "size", "reserve 'size' bytes for guest virtual address space"},
3385#endif
3386 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3387 "item[,...]", "enable logging of specified items "
3388 "(use '-d help' for a list of items)"},
50171d42 3389 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3390 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3391 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3392 "pagesize", "set the host page size to 'pagesize'"},
3393 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3394 "", "run in singlestep mode"},
3395 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3396 "", "log system calls"},
3397 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3398 "", "display version information and exit"},
fc9c5412
JS		 3399 {NULL, NULL, false, NULL, NULL, NULL}
3400};
3401
3402static void usage(void)
3403{
42644cee 3404 const struct qemu_argument *arginfo;
fc9c5412
JS		 3405 int maxarglen;
3406 int maxenvlen;
3407
2e59915d
PB		 3408 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3409 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3410 "\n"
3411 "Options and associated environment variables:\n"
3412 "\n");
3413
63ec54d7
PM		 3414 /* Calculate column widths. We must always have at least enough space
3415 * for the column header.
3416 */
3417 maxarglen = strlen("Argument");
3418 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3419
3420 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3421 int arglen = strlen(arginfo->argv);
3422 if (arginfo->has_arg) {
3423 arglen += strlen(arginfo->example) + 1;
3424 }
fc9c5412
JS		 3425 if (strlen(arginfo->env) > maxenvlen) {
3426 maxenvlen = strlen(arginfo->env);
3427 }
63ec54d7
PM		 3428 if (arglen > maxarglen) {
3429 maxarglen = arglen;
fc9c5412
JS		 3430 }
3431 }
3432
63ec54d7
PM		 3433 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3434 maxenvlen, "Env-variable");
fc9c5412
JS		 3435
3436 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3437 if (arginfo->has_arg) {
3438 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3439 (int)(maxarglen - strlen(arginfo->argv) - 1),
3440 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3441 } else {
63ec54d7 3442 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3443 maxenvlen, arginfo->env,
3444 arginfo->help);
3445 }
3446 }
3447
3448 printf("\n"
3449 "Defaults:\n"
3450 "QEMU_LD_PREFIX = %s\n"
989b697d 3451 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3452 interp_prefix,
989b697d 3453 guest_stack_size);
fc9c5412
JS		 3454
3455 printf("\n"
3456 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3457 "QEMU_UNSET_ENV environment variables to set and unset\n"
3458 "environment variables for the target process.\n"
3459 "It is possible to provide several variables by separating them\n"
3460 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3461 "provide the -E and -U options multiple times.\n"
3462 "The following lines are equivalent:\n"
3463 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3464 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3465 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3466 "Note that if you provide several changes to a single variable\n"
3467 "the last change will stay in effect.\n");
3468
3469 exit(1);
3470}
3471
3472static int parse_args(int argc, char **argv)
3473{
3474 const char *r;
3475 int optind;
42644cee 3476 const struct qemu_argument *arginfo;
fc9c5412
JS		 3477
3478 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3479 if (arginfo->env == NULL) {
3480 continue;
3481 }
3482
3483 r = getenv(arginfo->env);
3484 if (r != NULL) {
3485 arginfo->handle_opt(r);
3486 }
3487 }
3488
3489 optind = 1;
3490 for (;;) {
3491 if (optind >= argc) {
3492 break;
3493 }
3494 r = argv[optind];
3495 if (r[0] != '-') {
3496 break;
3497 }
3498 optind++;
3499 r++;
3500 if (!strcmp(r, "-")) {
3501 break;
3502 }
3503
3504 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3505 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3506 if (arginfo->has_arg) {
1386d4c0
PM		 3507 if (optind >= argc) {
3508 usage();
3509 }
3510 arginfo->handle_opt(argv[optind]);
fc9c5412 3511 optind++;
1386d4c0
PM		 3512 } else {
3513 arginfo->handle_opt(NULL);
fc9c5412 3514 }
fc9c5412
JS		 3515 break;
3516 }
3517 }
3518
3519 /* no option matched the current argv */
3520 if (arginfo->handle_opt == NULL) {
3521 usage();
3522 }
3523 }
3524
3525 if (optind >= argc) {
3526 usage();
3527 }
3528
3529 filename = argv[optind];
3530 exec_path = argv[optind];
3531
3532 return optind;
3533}
3534
902b3d5c 3535int main(int argc, char **argv, char **envp)
31e31b8a 3536{
01ffc75b 3537 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3538 struct image_info info1, *info = &info1;
edf8e2af 3539 struct linux_binprm bprm;
48e15fc2 3540 TaskState *ts;
9349b4f9 3541 CPUArchState *env;
db6b81d4 3542 CPUState *cpu;
586314f2 3543 int optind;
04a6dfeb 3544 char **target_environ, **wrk;
7d8cec95
AJ		 3545 char **target_argv;
3546 int target_argc;
7d8cec95 3547 int i;
fd4d81dd 3548 int ret;
b12b6a18 3549
ce008c1f
AF		 3550 module_call_init(MODULE_INIT_QOM);
3551
902b3d5c 3552 qemu_cache_utils_init(envp);
3553
04a6dfeb
AJ		 3554 if ((envlist = envlist_create()) == NULL) {
3555 (void) fprintf(stderr, "Unable to allocate envlist\n");
3556 exit(1);
3557 }
3558
3559 /* add current environment into the list */
3560 for (wrk = environ; *wrk != NULL; wrk++) {
3561 (void) envlist_setenv(envlist, *wrk);
3562 }
3563
703e0e89
RH		 3564 /* Read the stack limit from the kernel. If it's "unlimited",
3565 then we can do little else besides use the default. */
3566 {
3567 struct rlimit lim;
3568 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906 3569 && lim.rlim_cur != RLIM_INFINITY
3570 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3571 guest_stack_size = lim.rlim_cur;
3572 }
3573 }
3574
b1f9be31 3575 cpu_model = NULL;
b5ec5ce0 3576#if defined(cpudef_setup)
3577 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3578#endif
3579
fc9c5412 3580 optind = parse_args(argc, argv);
586314f2 3581
31e31b8a 3582 /* Zero out regs */
01ffc75b 3583 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3584
3585 /* Zero out image_info */
3586 memset(info, 0, sizeof(struct image_info));
3587
edf8e2af
MW		 3588 memset(&bprm, 0, sizeof (bprm));
3589
74cd30b8
FB		 3590 /* Scan interp_prefix dir for replacement files. */
3591 init_paths(interp_prefix);
3592
46027c07 3593 if (cpu_model == NULL) {
aaed909a 3594#if defined(TARGET_I386)
46027c07
FB		 3595#ifdef TARGET_X86_64
3596 cpu_model = "qemu64";
3597#else
3598 cpu_model = "qemu32";
3599#endif
aaed909a 3600#elif defined(TARGET_ARM)
088ab16c 3601 cpu_model = "any";
d2fbca94
GX		 3602#elif defined(TARGET_UNICORE32)
3603 cpu_model = "any";
aaed909a
FB		 3604#elif defined(TARGET_M68K)
3605 cpu_model = "any";
3606#elif defined(TARGET_SPARC)
3607#ifdef TARGET_SPARC64
3608 cpu_model = "TI UltraSparc II";
3609#else
3610 cpu_model = "Fujitsu MB86904";
46027c07 3611#endif
aaed909a
FB		 3612#elif defined(TARGET_MIPS)
3613#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3614 cpu_model = "20Kc";
3615#else
3616 cpu_model = "24Kf";
3617#endif
d962783e
JL		 3618#elif defined TARGET_OPENRISC
3619 cpu_model = "or1200";
aaed909a 3620#elif defined(TARGET_PPC)
7ded4f52 3621#ifdef TARGET_PPC64
f7177937 3622 cpu_model = "970fx";
7ded4f52 3623#else
aaed909a 3624 cpu_model = "750";
7ded4f52 3625#endif
aaed909a
FB		 3626#else
3627 cpu_model = "any";
3628#endif
3629 }
d5ab9713
JK		 3630 tcg_exec_init(0);
3631 cpu_exec_init_all();
83fb7adf
FB		 3632 /* NOTE: we need to init the CPU at this stage to get
3633 qemu_host_page_size */
aaed909a
FB		 3634 env = cpu_init(cpu_model);
3635 if (!env) {
3636 fprintf(stderr, "Unable to find CPU definition\n");
3637 exit(1);
3638 }
db6b81d4 3639 cpu = ENV_GET_CPU(env);
0ac46af3 3640 cpu_reset(cpu);
b55a37c9 3641
db6b81d4 3642 thread_cpu = cpu;
3b46e624 3643
b6741956
FB		 3644 if (getenv("QEMU_STRACE")) {
3645 do_strace = 1;
b92c47c1
TS		 3646 }
3647
04a6dfeb
AJ		 3648 target_environ = envlist_to_environ(envlist, NULL);
3649 envlist_free(envlist);
b12b6a18 3650
379f6698
PB		 3651#if defined(CONFIG_USE_GUEST_BASE)
3652 /*
3653 * Now that page sizes are configured in cpu_init() we can do
3654 * proper page alignment for guest_base.
3655 */
3656 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3657
806d1021
MI		 3658 if (reserved_va || have_guest_base) {
3659 guest_base = init_guest_space(guest_base, reserved_va, 0,
3660 have_guest_base);
3661 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3662 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3663 "space for use as guest address space (check your virtual "
3664 "memory ulimit setting or reserve less using -R option)\n",
3665 reserved_va);
68a1c816
PB		 3666 exit(1);
3667 }
97cc7560 3668
806d1021
MI		 3669 if (reserved_va) {
3670 mmap_next_start = reserved_va;
97cc7560
DDAG		 3671 }
3672 }
14f24e14 3673#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3674
3675 /*
3676 * Read in mmap_min_addr kernel parameter. This value is used
3677 * When loading the ELF image to determine whether guest_base
14f24e14 3678 * is needed. It is also used in mmap_find_vma.
379f6698 3679 */
14f24e14 3680 {
379f6698
PB		 3681 FILE *fp;
3682
3683 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3684 unsigned long tmp;
3685 if (fscanf(fp, "%lu", &tmp) == 1) {
3686 mmap_min_addr = tmp;
3687 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3688 }
3689 fclose(fp);
3690 }
3691 }
379f6698 3692
7d8cec95
AJ		 3693 /*
3694 * Prepare copy of argv vector for target.
3695 */
3696 target_argc = argc - optind;
3697 target_argv = calloc(target_argc + 1, sizeof (char *));
3698 if (target_argv == NULL) {
3699 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3700 exit(1);
3701 }
3702
3703 /*
3704 * If argv0 is specified (using '-0' switch) we replace
3705 * argv[0] pointer with the given one.
3706 */
3707 i = 0;
3708 if (argv0 != NULL) {
3709 target_argv[i++] = strdup(argv0);
3710 }
3711 for (; i < target_argc; i++) {
3712 target_argv[i] = strdup(argv[optind + i]);
3713 }
3714 target_argv[target_argc] = NULL;
3715
7267c094 3716 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3717 init_task_state(ts);
3718 /* build Task State */
3719 ts->info = info;
3720 ts->bprm = &bprm;
3721 env->opaque = ts;
3722 task_settid(ts);
3723
fd4d81dd
AP		 3724 ret = loader_exec(filename, target_argv, target_environ, regs,
3725 info, &bprm);
3726 if (ret != 0) {
885c1d10 3727 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3728 _exit(1);
3729 }
3730
3731 for (wrk = target_environ; *wrk; wrk++) {
3732 free(*wrk);
31e31b8a 3733 }
3b46e624 3734
b12b6a18
TS		 3735 free(target_environ);
3736
2e77eac6 3737 if (qemu_log_enabled()) {
379f6698
PB		 3738#if defined(CONFIG_USE_GUEST_BASE)
3739 qemu_log("guest_base 0x%lx\n", guest_base);
3740#endif
2e77eac6
BS		 3741 log_page_dump();
3742
3743 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3744 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3745 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3746 info->start_code);
3747 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3748 info->start_data);
3749 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3750 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3751 info->start_stack);
3752 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3753 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3754 }
31e31b8a 3755
53a5960a 3756 target_set_brk(info->brk);
31e31b8a 3757 syscall_init();
66fb9763 3758 signal_init();
31e31b8a 3759
9002ec79
RH		 3760#if defined(CONFIG_USE_GUEST_BASE)
3761 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3762 generating the prologue until now so that the prologue can take
3763 the real value of GUEST_BASE into account. */
3764 tcg_prologue_init(&tcg_ctx);
3765#endif
3766
b346ff46 3767#if defined(TARGET_I386)
2e255c6b
FB		 3768 cpu_x86_set_cpl(env, 3);
3769
3802ce26 3770 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e 3771 env->hflags |= HF_PE_MASK;
0514ef2f 3772 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 3773 env->cr[4] |= CR4_OSFXSR_MASK;
3774 env->hflags |= HF_OSFXSR_MASK;
3775 }
d2fd1af7 3776#ifndef TARGET_ABI32
4dbc422b 3777 /* enable 64 bit mode if possible */
0514ef2f 3778 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 3779 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3780 exit(1);
3781 }
d2fd1af7 3782 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3783 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3784 env->hflags |= HF_LMA_MASK;
3785#endif
1bde465e 3786
415e561f
FB		 3787 /* flags setup : we activate the IRQs by default as in user mode */
3788 env->eflags |= IF_MASK;
3b46e624 3789
6dbad63e 3790 /* linux register setup */
d2fd1af7 3791#ifndef TARGET_ABI32
84409ddb
JM		 3792 env->regs[R_EAX] = regs->rax;
3793 env->regs[R_EBX] = regs->rbx;
3794 env->regs[R_ECX] = regs->rcx;
3795 env->regs[R_EDX] = regs->rdx;
3796 env->regs[R_ESI] = regs->rsi;
3797 env->regs[R_EDI] = regs->rdi;
3798 env->regs[R_EBP] = regs->rbp;
3799 env->regs[R_ESP] = regs->rsp;
3800 env->eip = regs->rip;
3801#else
0ecfa993
FB		 3802 env->regs[R_EAX] = regs->eax;
3803 env->regs[R_EBX] = regs->ebx;
3804 env->regs[R_ECX] = regs->ecx;
3805 env->regs[R_EDX] = regs->edx;
3806 env->regs[R_ESI] = regs->esi;
3807 env->regs[R_EDI] = regs->edi;
3808 env->regs[R_EBP] = regs->ebp;
3809 env->regs[R_ESP] = regs->esp;
dab2ed99 3810 env->eip = regs->eip;
84409ddb 3811#endif
31e31b8a 3812
f4beb510 3813 /* linux interrupt setup */
e441570f
AZ		 3814#ifndef TARGET_ABI32
3815 env->idt.limit = 511;
3816#else
3817 env->idt.limit = 255;
3818#endif
3819 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3820 PROT_READ|PROT_WRITE,
3821 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3822 idt_table = g2h(env->idt.base);
f4beb510
FB		 3823 set_idt(0, 0);
3824 set_idt(1, 0);
3825 set_idt(2, 0);
3826 set_idt(3, 3);
3827 set_idt(4, 3);
ec95da6c 3828 set_idt(5, 0);
f4beb510
FB		 3829 set_idt(6, 0);
3830 set_idt(7, 0);
3831 set_idt(8, 0);
3832 set_idt(9, 0);
3833 set_idt(10, 0);
3834 set_idt(11, 0);
3835 set_idt(12, 0);
3836 set_idt(13, 0);
3837 set_idt(14, 0);
3838 set_idt(15, 0);
3839 set_idt(16, 0);
3840 set_idt(17, 0);
3841 set_idt(18, 0);
3842 set_idt(19, 0);
3843 set_idt(0x80, 3);
3844
6dbad63e 3845 /* linux segment setup */
8d18e893
FB		 3846 {
3847 uint64_t *gdt_table;
e441570f
AZ		 3848 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3849 PROT_READ|PROT_WRITE,
3850 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3851 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3852 gdt_table = g2h(env->gdt.base);
d2fd1af7 3853#ifdef TARGET_ABI32
8d18e893
FB		 3854 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3855 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3856 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3857#else
3858 /* 64 bit code segment */
3859 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3860 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3861 DESC_L_MASK |
3862 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3863#endif
8d18e893
FB		 3864 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3865 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3866 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3867 }
6dbad63e 3868 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3869 cpu_x86_load_seg(env, R_SS, __USER_DS);
3870#ifdef TARGET_ABI32
6dbad63e
FB		 3871 cpu_x86_load_seg(env, R_DS, __USER_DS);
3872 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3873 cpu_x86_load_seg(env, R_FS, __USER_DS);
3874 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3875 /* This hack makes Wine work... */
3876 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3877#else
3878 cpu_x86_load_seg(env, R_DS, 0);
3879 cpu_x86_load_seg(env, R_ES, 0);
3880 cpu_x86_load_seg(env, R_FS, 0);
3881 cpu_x86_load_seg(env, R_GS, 0);
3882#endif
b346ff46
FB		 3883#elif defined(TARGET_ARM)
3884 {
3885 int i;
b5ff1b31 3886 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3887 for(i = 0; i < 16; i++) {
3888 env->regs[i] = regs->uregs[i];
3889 }
d8fd2954
PB		 3890 /* Enable BE8. */
3891 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3892 && (info->elf_flags & EF_ARM_BE8)) {
3893 env->bswap_code = 1;
3894 }
b346ff46 3895 }
d2fbca94
GX		 3896#elif defined(TARGET_UNICORE32)
3897 {
3898 int i;
3899 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3900 for (i = 0; i < 32; i++) {
3901 env->regs[i] = regs->uregs[i];
3902 }
3903 }
93ac68bc 3904#elif defined(TARGET_SPARC)
060366c5
FB		 3905 {
3906 int i;
3907 env->pc = regs->pc;
3908 env->npc = regs->npc;
3909 env->y = regs->y;
3910 for(i = 0; i < 8; i++)
3911 env->gregs[i] = regs->u_regs[i];
3912 for(i = 0; i < 8; i++)
3913 env->regwptr[i] = regs->u_regs[i + 8];
3914 }
67867308
FB		 3915#elif defined(TARGET_PPC)
3916 {
3917 int i;
3fc6c082 3918
0411a972
JM		 3919#if defined(TARGET_PPC64)
3920#if defined(TARGET_ABI32)
3921 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3922#else
0411a972
JM		 3923 env->msr |= (target_ulong)1 << MSR_SF;
3924#endif
84409ddb 3925#endif
67867308
FB		 3926 env->nip = regs->nip;
3927 for(i = 0; i < 32; i++) {
3928 env->gpr[i] = regs->gpr[i];
3929 }
3930 }
e6e5906b
PB		 3931#elif defined(TARGET_M68K)
3932 {
e6e5906b
PB		 3933 env->pc = regs->pc;
3934 env->dregs[0] = regs->d0;
3935 env->dregs[1] = regs->d1;
3936 env->dregs[2] = regs->d2;
3937 env->dregs[3] = regs->d3;
3938 env->dregs[4] = regs->d4;
3939 env->dregs[5] = regs->d5;
3940 env->dregs[6] = regs->d6;
3941 env->dregs[7] = regs->d7;
3942 env->aregs[0] = regs->a0;
3943 env->aregs[1] = regs->a1;
3944 env->aregs[2] = regs->a2;
3945 env->aregs[3] = regs->a3;
3946 env->aregs[4] = regs->a4;
3947 env->aregs[5] = regs->a5;
3948 env->aregs[6] = regs->a6;
3949 env->aregs[7] = regs->usp;
3950 env->sr = regs->sr;
3951 ts->sim_syscalls = 1;
3952 }
b779e29e
EI		 3953#elif defined(TARGET_MICROBLAZE)
3954 {
3955 env->regs[0] = regs->r0;
3956 env->regs[1] = regs->r1;
3957 env->regs[2] = regs->r2;
3958 env->regs[3] = regs->r3;
3959 env->regs[4] = regs->r4;
3960 env->regs[5] = regs->r5;
3961 env->regs[6] = regs->r6;
3962 env->regs[7] = regs->r7;
3963 env->regs[8] = regs->r8;
3964 env->regs[9] = regs->r9;
3965 env->regs[10] = regs->r10;
3966 env->regs[11] = regs->r11;
3967 env->regs[12] = regs->r12;
3968 env->regs[13] = regs->r13;
3969 env->regs[14] = regs->r14;
3970 env->regs[15] = regs->r15;
3971 env->regs[16] = regs->r16;
3972 env->regs[17] = regs->r17;
3973 env->regs[18] = regs->r18;
3974 env->regs[19] = regs->r19;
3975 env->regs[20] = regs->r20;
3976 env->regs[21] = regs->r21;
3977 env->regs[22] = regs->r22;
3978 env->regs[23] = regs->r23;
3979 env->regs[24] = regs->r24;
3980 env->regs[25] = regs->r25;
3981 env->regs[26] = regs->r26;
3982 env->regs[27] = regs->r27;
3983 env->regs[28] = regs->r28;
3984 env->regs[29] = regs->r29;
3985 env->regs[30] = regs->r30;
3986 env->regs[31] = regs->r31;
3987 env->sregs[SR_PC] = regs->pc;
3988 }
048f6b4d
FB		 3989#elif defined(TARGET_MIPS)
3990 {
3991 int i;
3992
3993 for(i = 0; i < 32; i++) {
b5dc7732 3994 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3995 }
0fddbbf2
NF		 3996 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3997 if (regs->cp0_epc & 1) {
3998 env->hflags |= MIPS_HFLAG_M16;
3999 }
048f6b4d 4000 }
d962783e
JL		 4001#elif defined(TARGET_OPENRISC)
4002 {
4003 int i;
4004
4005 for (i = 0; i < 32; i++) {
4006 env->gpr[i] = regs->gpr[i];
4007 }
4008
4009 env->sr = regs->sr;
4010 env->pc = regs->pc;
4011 }
fdf9b3e8
FB		 4012#elif defined(TARGET_SH4)
4013 {
4014 int i;
4015
4016 for(i = 0; i < 16; i++) {
4017 env->gregs[i] = regs->regs[i];
4018 }
4019 env->pc = regs->pc;
4020 }
7a3148a9
JM		 4021#elif defined(TARGET_ALPHA)
4022 {
4023 int i;
4024
4025 for(i = 0; i < 28; i++) {
992f48a0 4026 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4027 }
dad081ee 4028 env->ir[IR_SP] = regs->usp;
7a3148a9 4029 env->pc = regs->pc;
7a3148a9 4030 }
48733d19
TS		 4031#elif defined(TARGET_CRIS)
4032 {
4033 env->regs[0] = regs->r0;
4034 env->regs[1] = regs->r1;
4035 env->regs[2] = regs->r2;
4036 env->regs[3] = regs->r3;
4037 env->regs[4] = regs->r4;
4038 env->regs[5] = regs->r5;
4039 env->regs[6] = regs->r6;
4040 env->regs[7] = regs->r7;
4041 env->regs[8] = regs->r8;
4042 env->regs[9] = regs->r9;
4043 env->regs[10] = regs->r10;
4044 env->regs[11] = regs->r11;
4045 env->regs[12] = regs->r12;
4046 env->regs[13] = regs->r13;
4047 env->regs[14] = info->start_stack;
4048 env->regs[15] = regs->acr;
4049 env->pc = regs->erp;
4050 }
a4c075f1
UH		 4051#elif defined(TARGET_S390X)
4052 {
4053 int i;
4054 for (i = 0; i < 16; i++) {
4055 env->regs[i] = regs->gprs[i];
4056 }
4057 env->psw.mask = regs->psw.mask;
4058 env->psw.addr = regs->psw.addr;
4059 }
b346ff46
FB		 4060#else
4061#error unsupported target CPU
4062#endif
31e31b8a 4063
d2fbca94 4064#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4065 ts->stack_base = info->start_stack;
4066 ts->heap_base = info->brk;
4067 /* This will be filled in on the first SYS_HEAPINFO call. */
4068 ts->heap_limit = 0;
4069#endif
4070
74c33bed 4071 if (gdbstub_port) {
ff7a981a
PM		 4072 if (gdbserver_start(gdbstub_port) < 0) {
4073 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4074 gdbstub_port);
4075 exit(1);
4076 }
db6b81d4 4077 gdb_handlesig(cpu, 0);
1fddef4b 4078 }
1b6b029e
FB		 4079 cpu_loop(env);
4080 /* never exits */
31e31b8a
FB		 4081 return 0;
4082}
Qemu copy for testing