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linux-user: Fix pipe syscall return for SPARC
[qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
45const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 72const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
d5975363
PB		 95/***********************************************************/
96/* Helper routines for implementing atomic operations. */
97
98/* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
c2764719 102static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 103static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106static int pending_cpus;
107
108/* Make sure everything is in a consistent state for calling fork(). */
109void fork_start(void)
110{
5e5f07e0 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 112 pthread_mutex_lock(&exclusive_lock);
d032d1b4 113 mmap_fork_start();
d5975363
PB		 114}
115
116void fork_end(int child)
117{
d032d1b4 118 mmap_fork_end(child);
d5975363
PB		 119 if (child) {
120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
a2247f8e 122 first_cpu = thread_cpu;
182735ef 123 first_cpu->next_cpu = NULL;
d5975363
PB		 124 pending_cpus = 0;
125 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 126 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 127 pthread_cond_init(&exclusive_cond, NULL);
128 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 129 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 130 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 131 } else {
132 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 133 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 134 }
d5975363
PB		 135}
136
137/* Wait for pending exclusive operations to complete. The exclusive lock
138 must be held. */
139static inline void exclusive_idle(void)
140{
141 while (pending_cpus) {
142 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
143 }
144}
145
146/* Start an exclusive operation.
147 Must only be called from outside cpu_arm_exec. */
148static inline void start_exclusive(void)
149{
0315c31c
AF		 150 CPUState *other_cpu;
151
d5975363
PB		 152 pthread_mutex_lock(&exclusive_lock);
153 exclusive_idle();
154
155 pending_cpus = 1;
156 /* Make all other cpus stop executing. */
182735ef 157 for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) {
0315c31c 158 if (other_cpu->running) {
d5975363 159 pending_cpus++;
60a3e17a 160 cpu_exit(other_cpu);
d5975363
PB		 161 }
162 }
163 if (pending_cpus > 1) {
164 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
165 }
166}
167
168/* Finish an exclusive operation. */
169static inline void end_exclusive(void)
170{
171 pending_cpus = 0;
172 pthread_cond_broadcast(&exclusive_resume);
173 pthread_mutex_unlock(&exclusive_lock);
174}
175
176/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 177static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 178{
179 pthread_mutex_lock(&exclusive_lock);
180 exclusive_idle();
0315c31c 181 cpu->running = true;
d5975363
PB		 182 pthread_mutex_unlock(&exclusive_lock);
183}
184
185/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 186static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 187{
188 pthread_mutex_lock(&exclusive_lock);
0315c31c 189 cpu->running = false;
d5975363
PB		 190 if (pending_cpus > 1) {
191 pending_cpus--;
192 if (pending_cpus == 1) {
193 pthread_cond_signal(&exclusive_cond);
194 }
195 }
196 exclusive_idle();
197 pthread_mutex_unlock(&exclusive_lock);
198}
c2764719
PB		 199
200void cpu_list_lock(void)
201{
202 pthread_mutex_lock(&cpu_list_mutex);
203}
204
205void cpu_list_unlock(void)
206{
207 pthread_mutex_unlock(&cpu_list_mutex);
208}
d5975363
PB		 209
210
a541f297
FB		 211#ifdef TARGET_I386
212/***********************************************************/
213/* CPUX86 core interface */
214
05390248 215void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 216{
217}
218
28ab0e2e
FB		 219uint64_t cpu_get_tsc(CPUX86State *env)
220{
221 return cpu_get_real_ticks();
222}
223
5fafdf24 224static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 225 int flags)
6dbad63e 226{
f4beb510 227 unsigned int e1, e2;
53a5960a 228 uint32_t *p;
6dbad63e
FB		 229 e1 = (addr << 16) | (limit & 0xffff);
230 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 231 e2 |= flags;
53a5960a 232 p = ptr;
d538e8f5 233 p[0] = tswap32(e1);
234 p[1] = tswap32(e2);
f4beb510
FB		 235}
236
e441570f 237static uint64_t *idt_table;
eb38c52c 238#ifdef TARGET_X86_64
d2fd1af7
FB		 239static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
240 uint64_t addr, unsigned int sel)
f4beb510 241{
4dbc422b 242 uint32_t *p, e1, e2;
f4beb510
FB		 243 e1 = (addr & 0xffff) | (sel << 16);
244 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 245 p = ptr;
4dbc422b
FB		 246 p[0] = tswap32(e1);
247 p[1] = tswap32(e2);
248 p[2] = tswap32(addr >> 32);
249 p[3] = 0;
6dbad63e 250}
d2fd1af7
FB		 251/* only dpl matters as we do only user space emulation */
252static void set_idt(int n, unsigned int dpl)
253{
254 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
255}
256#else
d2fd1af7
FB		 257static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
258 uint32_t addr, unsigned int sel)
259{
4dbc422b 260 uint32_t *p, e1, e2;
d2fd1af7
FB		 261 e1 = (addr & 0xffff) | (sel << 16);
262 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
263 p = ptr;
4dbc422b
FB		 264 p[0] = tswap32(e1);
265 p[1] = tswap32(e2);
d2fd1af7
FB		 266}
267
f4beb510
FB		 268/* only dpl matters as we do only user space emulation */
269static void set_idt(int n, unsigned int dpl)
270{
271 set_gate(idt_table + n, 0, dpl, 0, 0);
272}
d2fd1af7 273#endif
31e31b8a 274
89e957e7 275void cpu_loop(CPUX86State *env)
1b6b029e 276{
bc8a22cc 277 int trapnr;
992f48a0 278 abi_ulong pc;
c227f099 279 target_siginfo_t info;
851e67a1 280
1b6b029e 281 for(;;) {
bc8a22cc 282 trapnr = cpu_x86_exec(env);
bc8a22cc 283 switch(trapnr) {
f4beb510 284 case 0x80:
d2fd1af7 285 /* linux syscall from int $0x80 */
5fafdf24
TS		 286 env->regs[R_EAX] = do_syscall(env,
287 env->regs[R_EAX],
f4beb510
FB		 288 env->regs[R_EBX],
289 env->regs[R_ECX],
290 env->regs[R_EDX],
291 env->regs[R_ESI],
292 env->regs[R_EDI],
5945cfcb
PM		 293 env->regs[R_EBP],
294 0, 0);
f4beb510 295 break;
d2fd1af7
FB		 296#ifndef TARGET_ABI32
297 case EXCP_SYSCALL:
5ba18547 298 /* linux syscall from syscall instruction */
d2fd1af7
FB		 299 env->regs[R_EAX] = do_syscall(env,
300 env->regs[R_EAX],
301 env->regs[R_EDI],
302 env->regs[R_ESI],
303 env->regs[R_EDX],
304 env->regs[10],
305 env->regs[8],
5945cfcb
PM		 306 env->regs[9],
307 0, 0);
d2fd1af7
FB		 308 env->eip = env->exception_next_eip;
309 break;
310#endif
f4beb510
FB		 311 case EXCP0B_NOSEG:
312 case EXCP0C_STACK:
313 info.si_signo = SIGBUS;
314 info.si_errno = 0;
315 info.si_code = TARGET_SI_KERNEL;
316 info._sifields._sigfault._addr = 0;
624f7979 317 queue_signal(env, info.si_signo, &info);
f4beb510 318 break;
1b6b029e 319 case EXCP0D_GPF:
d2fd1af7 320 /* XXX: potential problem if ABI32 */
84409ddb 321#ifndef TARGET_X86_64
851e67a1 322 if (env->eflags & VM_MASK) {
89e957e7 323 handle_vm86_fault(env);
84409ddb
JM		 324 } else
325#endif
326 {
f4beb510
FB		 327 info.si_signo = SIGSEGV;
328 info.si_errno = 0;
329 info.si_code = TARGET_SI_KERNEL;
330 info._sifields._sigfault._addr = 0;
624f7979 331 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 332 }
333 break;
b689bc57
FB		 334 case EXCP0E_PAGE:
335 info.si_signo = SIGSEGV;
336 info.si_errno = 0;
337 if (!(env->error_code & 1))
338 info.si_code = TARGET_SEGV_MAPERR;
339 else
340 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 341 info._sifields._sigfault._addr = env->cr[2];
624f7979 342 queue_signal(env, info.si_signo, &info);
b689bc57 343 break;
9de5e440 344 case EXCP00_DIVZ:
84409ddb 345#ifndef TARGET_X86_64
bc8a22cc 346 if (env->eflags & VM_MASK) {
447db213 347 handle_vm86_trap(env, trapnr);
84409ddb
JM		 348 } else
349#endif
350 {
bc8a22cc
FB		 351 /* division by zero */
352 info.si_signo = SIGFPE;
353 info.si_errno = 0;
354 info.si_code = TARGET_FPE_INTDIV;
355 info._sifields._sigfault._addr = env->eip;
624f7979 356 queue_signal(env, info.si_signo, &info);
bc8a22cc 357 }
9de5e440 358 break;
01df040b 359 case EXCP01_DB:
447db213 360 case EXCP03_INT3:
84409ddb 361#ifndef TARGET_X86_64
447db213
FB		 362 if (env->eflags & VM_MASK) {
363 handle_vm86_trap(env, trapnr);
84409ddb
JM		 364 } else
365#endif
366 {
447db213
FB		 367 info.si_signo = SIGTRAP;
368 info.si_errno = 0;
01df040b 369 if (trapnr == EXCP01_DB) {
447db213
FB		 370 info.si_code = TARGET_TRAP_BRKPT;
371 info._sifields._sigfault._addr = env->eip;
372 } else {
373 info.si_code = TARGET_SI_KERNEL;
374 info._sifields._sigfault._addr = 0;
375 }
624f7979 376 queue_signal(env, info.si_signo, &info);
447db213
FB		 377 }
378 break;
9de5e440
FB		 379 case EXCP04_INTO:
380 case EXCP05_BOUND:
84409ddb 381#ifndef TARGET_X86_64
bc8a22cc 382 if (env->eflags & VM_MASK) {
447db213 383 handle_vm86_trap(env, trapnr);
84409ddb
JM		 384 } else
385#endif
386 {
bc8a22cc
FB		 387 info.si_signo = SIGSEGV;
388 info.si_errno = 0;
b689bc57 389 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 390 info._sifields._sigfault._addr = 0;
624f7979 391 queue_signal(env, info.si_signo, &info);
bc8a22cc 392 }
9de5e440
FB		 393 break;
394 case EXCP06_ILLOP:
395 info.si_signo = SIGILL;
396 info.si_errno = 0;
397 info.si_code = TARGET_ILL_ILLOPN;
398 info._sifields._sigfault._addr = env->eip;
624f7979 399 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 400 break;
401 case EXCP_INTERRUPT:
402 /* just indicate that signals should be handled asap */
403 break;
1fddef4b
FB		 404 case EXCP_DEBUG:
405 {
406 int sig;
407
408 sig = gdb_handlesig (env, TARGET_SIGTRAP);
409 if (sig)
410 {
411 info.si_signo = sig;
412 info.si_errno = 0;
413 info.si_code = TARGET_TRAP_BRKPT;
624f7979 414 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 415 }
416 }
417 break;
1b6b029e 418 default:
970a87a6 419 pc = env->segs[R_CS].base + env->eip;
5fafdf24 420 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 421 (long)pc, trapnr);
1b6b029e
FB		 422 abort();
423 }
66fb9763 424 process_pending_signals(env);
1b6b029e
FB		 425 }
426}
b346ff46
FB		 427#endif
428
429#ifdef TARGET_ARM
430
d8fd2954
PB		 431#define get_user_code_u32(x, gaddr, doswap) \
432 ({ abi_long __r = get_user_u32((x), (gaddr)); \
433 if (!__r && (doswap)) { \
434 (x) = bswap32(x); \
435 } \
436 __r; \
437 })
438
439#define get_user_code_u16(x, gaddr, doswap) \
440 ({ abi_long __r = get_user_u16((x), (gaddr)); \
441 if (!__r && (doswap)) { \
442 (x) = bswap16(x); \
443 } \
444 __r; \
445 })
446
97cc7560
DDAG		 447/*
448 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
449 * Input:
450 * r0 = pointer to oldval
451 * r1 = pointer to newval
452 * r2 = pointer to target value
453 *
454 * Output:
455 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
456 * C set if *ptr was changed, clear if no exchange happened
457 *
458 * Note segv's in kernel helpers are a bit tricky, we can set the
459 * data address sensibly but the PC address is just the entry point.
460 */
461static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
462{
463 uint64_t oldval, newval, val;
464 uint32_t addr, cpsr;
465 target_siginfo_t info;
466
467 /* Based on the 32 bit code in do_kernel_trap */
468
469 /* XXX: This only works between threads, not between processes.
470 It's probably possible to implement this with native host
471 operations. However things like ldrex/strex are much harder so
472 there's not much point trying. */
473 start_exclusive();
474 cpsr = cpsr_read(env);
475 addr = env->regs[2];
476
477 if (get_user_u64(oldval, env->regs[0])) {
478 env->cp15.c6_data = env->regs[0];
479 goto segv;
480 };
481
482 if (get_user_u64(newval, env->regs[1])) {
483 env->cp15.c6_data = env->regs[1];
484 goto segv;
485 };
486
487 if (get_user_u64(val, addr)) {
488 env->cp15.c6_data = addr;
489 goto segv;
490 }
491
492 if (val == oldval) {
493 val = newval;
494
495 if (put_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 };
499
500 env->regs[0] = 0;
501 cpsr |= CPSR_C;
502 } else {
503 env->regs[0] = -1;
504 cpsr &= ~CPSR_C;
505 }
506 cpsr_write(env, cpsr, CPSR_C);
507 end_exclusive();
508 return;
509
510segv:
511 end_exclusive();
512 /* We get the PC of the entry address - which is as good as anything,
513 on a real kernel what you get depends on which mode it uses. */
514 info.si_signo = SIGSEGV;
515 info.si_errno = 0;
516 /* XXX: check env->error_code */
517 info.si_code = TARGET_SEGV_MAPERR;
518 info._sifields._sigfault._addr = env->cp15.c6_data;
519 queue_signal(env, info.si_signo, &info);
520
521 end_exclusive();
522}
523
fbb4a2e3
PB		 524/* Handle a jump to the kernel code page. */
525static int
526do_kernel_trap(CPUARMState *env)
527{
528 uint32_t addr;
529 uint32_t cpsr;
530 uint32_t val;
531
532 switch (env->regs[15]) {
533 case 0xffff0fa0: /* __kernel_memory_barrier */
534 /* ??? No-op. Will need to do better for SMP. */
535 break;
536 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 537 /* XXX: This only works between threads, not between processes.
538 It's probably possible to implement this with native host
539 operations. However things like ldrex/strex are much harder so
540 there's not much point trying. */
541 start_exclusive();
fbb4a2e3
PB		 542 cpsr = cpsr_read(env);
543 addr = env->regs[2];
544 /* FIXME: This should SEGV if the access fails. */
545 if (get_user_u32(val, addr))
546 val = ~env->regs[0];
547 if (val == env->regs[0]) {
548 val = env->regs[1];
549 /* FIXME: Check for segfaults. */
550 put_user_u32(val, addr);
551 env->regs[0] = 0;
552 cpsr |= CPSR_C;
553 } else {
554 env->regs[0] = -1;
555 cpsr &= ~CPSR_C;
556 }
557 cpsr_write(env, cpsr, CPSR_C);
d5975363 558 end_exclusive();
fbb4a2e3
PB		 559 break;
560 case 0xffff0fe0: /* __kernel_get_tls */
561 env->regs[0] = env->cp15.c13_tls2;
562 break;
97cc7560
DDAG		 563 case 0xffff0f60: /* __kernel_cmpxchg64 */
564 arm_kernel_cmpxchg64_helper(env);
565 break;
566
fbb4a2e3
PB		 567 default:
568 return 1;
569 }
570 /* Jump back to the caller. */
571 addr = env->regs[14];
572 if (addr & 1) {
573 env->thumb = 1;
574 addr &= ~1;
575 }
576 env->regs[15] = addr;
577
578 return 0;
579}
580
426f5abc
PB		 581static int do_strex(CPUARMState *env)
582{
583 uint32_t val;
584 int size;
585 int rc = 1;
586 int segv = 0;
587 uint32_t addr;
588 start_exclusive();
589 addr = env->exclusive_addr;
590 if (addr != env->exclusive_test) {
591 goto fail;
592 }
593 size = env->exclusive_info & 0xf;
594 switch (size) {
595 case 0:
596 segv = get_user_u8(val, addr);
597 break;
598 case 1:
599 segv = get_user_u16(val, addr);
600 break;
601 case 2:
602 case 3:
603 segv = get_user_u32(val, addr);
604 break;
f7001a3b
AJ		 605 default:
606 abort();
426f5abc
PB		 607 }
608 if (segv) {
609 env->cp15.c6_data = addr;
610 goto done;
611 }
612 if (val != env->exclusive_val) {
613 goto fail;
614 }
615 if (size == 3) {
616 segv = get_user_u32(val, addr + 4);
617 if (segv) {
618 env->cp15.c6_data = addr + 4;
619 goto done;
620 }
621 if (val != env->exclusive_high) {
622 goto fail;
623 }
624 }
625 val = env->regs[(env->exclusive_info >> 8) & 0xf];
626 switch (size) {
627 case 0:
628 segv = put_user_u8(val, addr);
629 break;
630 case 1:
631 segv = put_user_u16(val, addr);
632 break;
633 case 2:
634 case 3:
635 segv = put_user_u32(val, addr);
636 break;
637 }
638 if (segv) {
639 env->cp15.c6_data = addr;
640 goto done;
641 }
642 if (size == 3) {
643 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 644 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 645 if (segv) {
646 env->cp15.c6_data = addr + 4;
647 goto done;
648 }
649 }
650 rc = 0;
651fail:
725b8a69 652 env->regs[15] += 4;
426f5abc
PB		 653 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
654done:
655 end_exclusive();
656 return segv;
657}
658
b346ff46
FB		 659void cpu_loop(CPUARMState *env)
660{
0315c31c 661 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 662 int trapnr;
663 unsigned int n, insn;
c227f099 664 target_siginfo_t info;
b5ff1b31 665 uint32_t addr;
3b46e624 666
b346ff46 667 for(;;) {
0315c31c 668 cpu_exec_start(cs);
b346ff46 669 trapnr = cpu_arm_exec(env);
0315c31c 670 cpu_exec_end(cs);
b346ff46
FB		 671 switch(trapnr) {
672 case EXCP_UDEF:
c6981055
FB		 673 {
674 TaskState *ts = env->opaque;
675 uint32_t opcode;
6d9a42be 676 int rc;
c6981055
FB		 677
678 /* we handle the FPU emulation here, as Linux */
679 /* we get the opcode */
2f619698 680 /* FIXME - what to do if get_user() fails? */
d8fd2954 681 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 682
6d9a42be
AJ		 683 rc = EmulateAll(opcode, &ts->fpa, env);
684 if (rc == 0) { /* illegal instruction */
c6981055
FB		 685 info.si_signo = SIGILL;
686 info.si_errno = 0;
687 info.si_code = TARGET_ILL_ILLOPN;
688 info._sifields._sigfault._addr = env->regs[15];
624f7979 689 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 690 } else if (rc < 0) { /* FP exception */
691 int arm_fpe=0;
692
693 /* translate softfloat flags to FPSR flags */
694 if (-rc & float_flag_invalid)
695 arm_fpe |= BIT_IOC;
696 if (-rc & float_flag_divbyzero)
697 arm_fpe |= BIT_DZC;
698 if (-rc & float_flag_overflow)
699 arm_fpe |= BIT_OFC;
700 if (-rc & float_flag_underflow)
701 arm_fpe |= BIT_UFC;
702 if (-rc & float_flag_inexact)
703 arm_fpe |= BIT_IXC;
704
705 FPSR fpsr = ts->fpa.fpsr;
706 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
707
708 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
709 info.si_signo = SIGFPE;
710 info.si_errno = 0;
711
712 /* ordered by priority, least first */
713 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
714 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
715 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
716 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
717 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
718
719 info._sifields._sigfault._addr = env->regs[15];
624f7979 720 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 721 } else {
722 env->regs[15] += 4;
723 }
724
725 /* accumulate unenabled exceptions */
726 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
727 fpsr |= BIT_IXC;
728 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
729 fpsr |= BIT_UFC;
730 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
731 fpsr |= BIT_OFC;
732 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
733 fpsr |= BIT_DZC;
734 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
735 fpsr |= BIT_IOC;
736 ts->fpa.fpsr=fpsr;
737 } else { /* everything OK */
c6981055
FB		 738 /* increment PC */
739 env->regs[15] += 4;
740 }
741 }
b346ff46
FB		 742 break;
743 case EXCP_SWI:
06c949e6 744 case EXCP_BKPT:
b346ff46 745 {
ce4defa0 746 env->eabi = 1;
b346ff46 747 /* system call */
06c949e6
PB		 748 if (trapnr == EXCP_BKPT) {
749 if (env->thumb) {
2f619698 750 /* FIXME - what to do if get_user() fails? */
d8fd2954 751 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 752 n = insn & 0xff;
753 env->regs[15] += 2;
754 } else {
2f619698 755 /* FIXME - what to do if get_user() fails? */
d8fd2954 756 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 757 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
758 env->regs[15] += 4;
759 }
192c7bd9 760 } else {
06c949e6 761 if (env->thumb) {
2f619698 762 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 763 get_user_code_u16(insn, env->regs[15] - 2,
764 env->bswap_code);
06c949e6
PB		 765 n = insn & 0xff;
766 } else {
2f619698 767 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 768 get_user_code_u32(insn, env->regs[15] - 4,
769 env->bswap_code);
06c949e6
PB		 770 n = insn & 0xffffff;
771 }
192c7bd9
FB		 772 }
773
6f1f31c0 774 if (n == ARM_NR_cacheflush) {
dcfd14b3 775 /* nop */
a4f81979
FB		 776 } else if (n == ARM_NR_semihosting
777 || n == ARM_NR_thumb_semihosting) {
778 env->regs[0] = do_arm_semihosting (env);
3a1363ac 779 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 780 /* linux syscall */
ce4defa0 781 if (env->thumb || n == 0) {
192c7bd9
FB		 782 n = env->regs[7];
783 } else {
784 n -= ARM_SYSCALL_BASE;
ce4defa0 785 env->eabi = 0;
192c7bd9 786 }
fbb4a2e3
PB		 787 if ( n > ARM_NR_BASE) {
788 switch (n) {
789 case ARM_NR_cacheflush:
dcfd14b3 790 /* nop */
fbb4a2e3
PB		 791 break;
792 case ARM_NR_set_tls:
793 cpu_set_tls(env, env->regs[0]);
794 env->regs[0] = 0;
795 break;
796 default:
797 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
798 n);
799 env->regs[0] = -TARGET_ENOSYS;
800 break;
801 }
802 } else {
803 env->regs[0] = do_syscall(env,
804 n,
805 env->regs[0],
806 env->regs[1],
807 env->regs[2],
808 env->regs[3],
809 env->regs[4],
5945cfcb
PM		 810 env->regs[5],
811 0, 0);
fbb4a2e3 812 }
b346ff46
FB		 813 } else {
814 goto error;
815 }
816 }
817 break;
43fff238
FB		 818 case EXCP_INTERRUPT:
819 /* just indicate that signals should be handled asap */
820 break;
68016c62 821 case EXCP_PREFETCH_ABORT:
eae473c1 822 addr = env->cp15.c6_insn;
b5ff1b31 823 goto do_segv;
68016c62 824 case EXCP_DATA_ABORT:
eae473c1 825 addr = env->cp15.c6_data;
b5ff1b31 826 do_segv:
68016c62
FB		 827 {
828 info.si_signo = SIGSEGV;
829 info.si_errno = 0;
830 /* XXX: check env->error_code */
831 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 832 info._sifields._sigfault._addr = addr;
624f7979 833 queue_signal(env, info.si_signo, &info);
68016c62
FB		 834 }
835 break;
1fddef4b
FB		 836 case EXCP_DEBUG:
837 {
838 int sig;
839
840 sig = gdb_handlesig (env, TARGET_SIGTRAP);
841 if (sig)
842 {
843 info.si_signo = sig;
844 info.si_errno = 0;
845 info.si_code = TARGET_TRAP_BRKPT;
624f7979 846 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 847 }
848 }
849 break;
fbb4a2e3
PB		 850 case EXCP_KERNEL_TRAP:
851 if (do_kernel_trap(env))
852 goto error;
853 break;
426f5abc
PB		 854 case EXCP_STREX:
855 if (do_strex(env)) {
856 addr = env->cp15.c6_data;
857 goto do_segv;
858 }
e9273455 859 break;
b346ff46
FB		 860 default:
861 error:
5fafdf24 862 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 863 trapnr);
878096ee 864 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 865 abort();
866 }
867 process_pending_signals(env);
868 }
869}
870
871#endif
1b6b029e 872
d2fbca94
GX		 873#ifdef TARGET_UNICORE32
874
05390248 875void cpu_loop(CPUUniCore32State *env)
d2fbca94 876{
0315c31c 877 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 878 int trapnr;
879 unsigned int n, insn;
880 target_siginfo_t info;
881
882 for (;;) {
0315c31c 883 cpu_exec_start(cs);
d2fbca94 884 trapnr = uc32_cpu_exec(env);
0315c31c 885 cpu_exec_end(cs);
d2fbca94
GX		 886 switch (trapnr) {
887 case UC32_EXCP_PRIV:
888 {
889 /* system call */
890 get_user_u32(insn, env->regs[31] - 4);
891 n = insn & 0xffffff;
892
893 if (n >= UC32_SYSCALL_BASE) {
894 /* linux syscall */
895 n -= UC32_SYSCALL_BASE;
896 if (n == UC32_SYSCALL_NR_set_tls) {
897 cpu_set_tls(env, env->regs[0]);
898 env->regs[0] = 0;
899 } else {
900 env->regs[0] = do_syscall(env,
901 n,
902 env->regs[0],
903 env->regs[1],
904 env->regs[2],
905 env->regs[3],
906 env->regs[4],
5945cfcb
PM		 907 env->regs[5],
908 0, 0);
d2fbca94
GX		 909 }
910 } else {
911 goto error;
912 }
913 }
914 break;
d48813dd
GX		 915 case UC32_EXCP_DTRAP:
916 case UC32_EXCP_ITRAP:
d2fbca94
GX		 917 info.si_signo = SIGSEGV;
918 info.si_errno = 0;
919 /* XXX: check env->error_code */
920 info.si_code = TARGET_SEGV_MAPERR;
921 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
922 queue_signal(env, info.si_signo, &info);
923 break;
924 case EXCP_INTERRUPT:
925 /* just indicate that signals should be handled asap */
926 break;
927 case EXCP_DEBUG:
928 {
929 int sig;
930
931 sig = gdb_handlesig(env, TARGET_SIGTRAP);
932 if (sig) {
933 info.si_signo = sig;
934 info.si_errno = 0;
935 info.si_code = TARGET_TRAP_BRKPT;
936 queue_signal(env, info.si_signo, &info);
937 }
938 }
939 break;
940 default:
941 goto error;
942 }
943 process_pending_signals(env);
944 }
945
946error:
947 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 948 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 949 abort();
950}
951#endif
952
93ac68bc 953#ifdef TARGET_SPARC
ed23fbd9 954#define SPARC64_STACK_BIAS 2047
93ac68bc 955
060366c5
FB		 956//#define DEBUG_WIN
957
2623cbaf
FB		 958/* WARNING: dealing with register windows _is_ complicated. More info
959 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 960static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
961{
1a14026e 962 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 963 /* wrap handling : if cwp is on the last window, then we use the
964 registers 'after' the end */
1a14026e
BS		 965 if (index < 8 && env->cwp == env->nwindows - 1)
966 index += 16 * env->nwindows;
060366c5
FB		 967 return index;
968}
969
2623cbaf
FB		 970/* save the register window 'cwp1' */
971static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 972{
2623cbaf 973 unsigned int i;
992f48a0 974 abi_ulong sp_ptr;
3b46e624 975
53a5960a 976 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 977#ifdef TARGET_SPARC64
978 if (sp_ptr & 3)
979 sp_ptr += SPARC64_STACK_BIAS;
980#endif
060366c5 981#if defined(DEBUG_WIN)
2daf0284
BS		 982 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
983 sp_ptr, cwp1);
060366c5 984#endif
2623cbaf 985 for(i = 0; i < 16; i++) {
2f619698
FB		 986 /* FIXME - what to do if put_user() fails? */
987 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 988 sp_ptr += sizeof(abi_ulong);
2623cbaf 989 }
060366c5
FB		 990}
991
992static void save_window(CPUSPARCState *env)
993{
5ef54116 994#ifndef TARGET_SPARC64
2623cbaf 995 unsigned int new_wim;
1a14026e
BS		 996 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
997 ((1LL << env->nwindows) - 1);
998 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 999 env->wim = new_wim;
5ef54116 1000#else
1a14026e 1001 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1002 env->cansave++;
1003 env->canrestore--;
1004#endif
060366c5
FB		 1005}
1006
1007static void restore_window(CPUSPARCState *env)
1008{
eda52953
BS		 1009#ifndef TARGET_SPARC64
1010 unsigned int new_wim;
1011#endif
1012 unsigned int i, cwp1;
992f48a0 1013 abi_ulong sp_ptr;
3b46e624 1014
eda52953 1015#ifndef TARGET_SPARC64
1a14026e
BS		 1016 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1017 ((1LL << env->nwindows) - 1);
eda52953 1018#endif
3b46e624 1019
060366c5 1020 /* restore the invalid window */
1a14026e 1021 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1022 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1023#ifdef TARGET_SPARC64
1024 if (sp_ptr & 3)
1025 sp_ptr += SPARC64_STACK_BIAS;
1026#endif
060366c5 1027#if defined(DEBUG_WIN)
2daf0284
BS		 1028 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1029 sp_ptr, cwp1);
060366c5 1030#endif
2623cbaf 1031 for(i = 0; i < 16; i++) {
2f619698
FB		 1032 /* FIXME - what to do if get_user() fails? */
1033 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1034 sp_ptr += sizeof(abi_ulong);
2623cbaf 1035 }
5ef54116
FB		 1036#ifdef TARGET_SPARC64
1037 env->canrestore++;
1a14026e
BS		 1038 if (env->cleanwin < env->nwindows - 1)
1039 env->cleanwin++;
5ef54116 1040 env->cansave--;
eda52953
BS		 1041#else
1042 env->wim = new_wim;
5ef54116 1043#endif
060366c5
FB		 1044}
1045
1046static void flush_windows(CPUSPARCState *env)
1047{
1048 int offset, cwp1;
2623cbaf
FB		 1049
1050 offset = 1;
060366c5
FB		 1051 for(;;) {
1052 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1053 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1054#ifndef TARGET_SPARC64
060366c5
FB		 1055 if (env->wim & (1 << cwp1))
1056 break;
eda52953
BS		 1057#else
1058 if (env->canrestore == 0)
1059 break;
1060 env->cansave++;
1061 env->canrestore--;
1062#endif
2623cbaf 1063 save_window_offset(env, cwp1);
060366c5
FB		 1064 offset++;
1065 }
1a14026e 1066 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1067#ifndef TARGET_SPARC64
1068 /* set wim so that restore will reload the registers */
2623cbaf 1069 env->wim = 1 << cwp1;
eda52953 1070#endif
2623cbaf
FB		 1071#if defined(DEBUG_WIN)
1072 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1073#endif
2623cbaf 1074}
060366c5 1075
93ac68bc
FB		 1076void cpu_loop (CPUSPARCState *env)
1077{
878096ee 1078 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1079 int trapnr;
1080 abi_long ret;
c227f099 1081 target_siginfo_t info;
3b46e624 1082
060366c5
FB		 1083 while (1) {
1084 trapnr = cpu_sparc_exec (env);
3b46e624 1085
20132b96
RH		 1086 /* Compute PSR before exposing state. */
1087 if (env->cc_op != CC_OP_FLAGS) {
1088 cpu_get_psr(env);
1089 }
1090
060366c5 1091 switch (trapnr) {
5ef54116 1092#ifndef TARGET_SPARC64
5fafdf24 1093 case 0x88:
060366c5 1094 case 0x90:
5ef54116 1095#else
cb33da57 1096 case 0x110:
5ef54116
FB		 1097 case 0x16d:
1098#endif
060366c5 1099 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1100 env->regwptr[0], env->regwptr[1],
1101 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1102 env->regwptr[4], env->regwptr[5],
1103 0, 0);
2cc20260 1104 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1105#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1106 env->xcc |= PSR_CARRY;
1107#else
060366c5 1108 env->psr |= PSR_CARRY;
27908725 1109#endif
060366c5
FB		 1110 ret = -ret;
1111 } else {
992f48a0 1112#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1113 env->xcc &= ~PSR_CARRY;
1114#else
060366c5 1115 env->psr &= ~PSR_CARRY;
27908725 1116#endif
060366c5
FB		 1117 }
1118 env->regwptr[0] = ret;
1119 /* next instruction */
1120 env->pc = env->npc;
1121 env->npc = env->npc + 4;
1122 break;
1123 case 0x83: /* flush windows */
992f48a0
BS		 1124#ifdef TARGET_ABI32
1125 case 0x103:
1126#endif
2623cbaf 1127 flush_windows(env);
060366c5
FB		 1128 /* next instruction */
1129 env->pc = env->npc;
1130 env->npc = env->npc + 4;
1131 break;
3475187d 1132#ifndef TARGET_SPARC64
060366c5
FB		 1133 case TT_WIN_OVF: /* window overflow */
1134 save_window(env);
1135 break;
1136 case TT_WIN_UNF: /* window underflow */
1137 restore_window(env);
1138 break;
61ff6f58
FB		 1139 case TT_TFAULT:
1140 case TT_DFAULT:
1141 {
59f7182f 1142 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1143 info.si_errno = 0;
1144 /* XXX: check env->error_code */
1145 info.si_code = TARGET_SEGV_MAPERR;
1146 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1147 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1148 }
1149 break;
3475187d 1150#else
5ef54116
FB		 1151 case TT_SPILL: /* window overflow */
1152 save_window(env);
1153 break;
1154 case TT_FILL: /* window underflow */
1155 restore_window(env);
1156 break;
7f84a729
BS		 1157 case TT_TFAULT:
1158 case TT_DFAULT:
1159 {
59f7182f 1160 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1161 info.si_errno = 0;
1162 /* XXX: check env->error_code */
1163 info.si_code = TARGET_SEGV_MAPERR;
1164 if (trapnr == TT_DFAULT)
1165 info._sifields._sigfault._addr = env->dmmuregs[4];
1166 else
8194f35a 1167 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1168 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1169 }
1170 break;
27524dc3 1171#ifndef TARGET_ABI32
5bfb56b2
BS		 1172 case 0x16e:
1173 flush_windows(env);
1174 sparc64_get_context(env);
1175 break;
1176 case 0x16f:
1177 flush_windows(env);
1178 sparc64_set_context(env);
1179 break;
27524dc3 1180#endif
3475187d 1181#endif
48dc41eb
FB		 1182 case EXCP_INTERRUPT:
1183 /* just indicate that signals should be handled asap */
1184 break;
75f22e4e
RH		 1185 case TT_ILL_INSN:
1186 {
1187 info.si_signo = TARGET_SIGILL;
1188 info.si_errno = 0;
1189 info.si_code = TARGET_ILL_ILLOPC;
1190 info._sifields._sigfault._addr = env->pc;
1191 queue_signal(env, info.si_signo, &info);
1192 }
1193 break;
1fddef4b
FB		 1194 case EXCP_DEBUG:
1195 {
1196 int sig;
1197
1198 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1199 if (sig)
1200 {
1201 info.si_signo = sig;
1202 info.si_errno = 0;
1203 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1204 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1205 }
1206 }
1207 break;
060366c5
FB		 1208 default:
1209 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1210 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1211 exit (1);
1212 }
1213 process_pending_signals (env);
1214 }
93ac68bc
FB		 1215}
1216
1217#endif
1218
67867308 1219#ifdef TARGET_PPC
05390248 1220static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1221{
1222 /* TO FIX */
1223 return 0;
1224}
3b46e624 1225
05390248 1226uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1227{
e3ea6529 1228 return cpu_ppc_get_tb(env);
9fddaa0c 1229}
3b46e624 1230
05390248 1231uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1232{
1233 return cpu_ppc_get_tb(env) >> 32;
1234}
3b46e624 1235
05390248 1236uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1237{
b711de95 1238 return cpu_ppc_get_tb(env);
9fddaa0c 1239}
5fafdf24 1240
05390248 1241uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1242{
a062e36c 1243 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1244}
76a66253 1245
05390248 1246uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1247__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1248
05390248 1249uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1250{
76a66253 1251 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1252}
76a66253 1253
a750fc0b 1254/* XXX: to be fixed */
73b01960 1255int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1256{
1257 return -1;
1258}
1259
73b01960 1260int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1261{
1262 return -1;
1263}
1264
001faf32
BS		 1265#define EXCP_DUMP(env, fmt, ...) \
1266do { \
a0762859 1267 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1268 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1269 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1270 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1271 if (qemu_log_enabled()) { \
a0762859 1272 log_cpu_state(cs, 0); \
eeacee4d 1273 } \
e1833e1f
JM		 1274} while (0)
1275
56f066bb
NF		 1276static int do_store_exclusive(CPUPPCState *env)
1277{
1278 target_ulong addr;
1279 target_ulong page_addr;
1280 target_ulong val;
1281 int flags;
1282 int segv = 0;
1283
1284 addr = env->reserve_ea;
1285 page_addr = addr & TARGET_PAGE_MASK;
1286 start_exclusive();
1287 mmap_lock();
1288 flags = page_get_flags(page_addr);
1289 if ((flags & PAGE_READ) == 0) {
1290 segv = 1;
1291 } else {
1292 int reg = env->reserve_info & 0x1f;
1293 int size = (env->reserve_info >> 5) & 0xf;
1294 int stored = 0;
1295
1296 if (addr == env->reserve_addr) {
1297 switch (size) {
1298 case 1: segv = get_user_u8(val, addr); break;
1299 case 2: segv = get_user_u16(val, addr); break;
1300 case 4: segv = get_user_u32(val, addr); break;
1301#if defined(TARGET_PPC64)
1302 case 8: segv = get_user_u64(val, addr); break;
1303#endif
1304 default: abort();
1305 }
1306 if (!segv && val == env->reserve_val) {
1307 val = env->gpr[reg];
1308 switch (size) {
1309 case 1: segv = put_user_u8(val, addr); break;
1310 case 2: segv = put_user_u16(val, addr); break;
1311 case 4: segv = put_user_u32(val, addr); break;
1312#if defined(TARGET_PPC64)
1313 case 8: segv = put_user_u64(val, addr); break;
1314#endif
1315 default: abort();
1316 }
1317 if (!segv) {
1318 stored = 1;
1319 }
1320 }
1321 }
1322 env->crf[0] = (stored << 1) | xer_so;
1323 env->reserve_addr = (target_ulong)-1;
1324 }
1325 if (!segv) {
1326 env->nip += 4;
1327 }
1328 mmap_unlock();
1329 end_exclusive();
1330 return segv;
1331}
1332
67867308
FB		 1333void cpu_loop(CPUPPCState *env)
1334{
0315c31c 1335 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1336 target_siginfo_t info;
61190b14 1337 int trapnr;
9e0e2f96 1338 target_ulong ret;
3b46e624 1339
67867308 1340 for(;;) {
0315c31c 1341 cpu_exec_start(cs);
67867308 1342 trapnr = cpu_ppc_exec(env);
0315c31c 1343 cpu_exec_end(cs);
67867308 1344 switch(trapnr) {
e1833e1f
JM		 1345 case POWERPC_EXCP_NONE:
1346 /* Just go on */
67867308 1347 break;
e1833e1f
JM		 1348 case POWERPC_EXCP_CRITICAL: /* Critical input */
1349 cpu_abort(env, "Critical interrupt while in user mode. "
1350 "Aborting\n");
61190b14 1351 break;
e1833e1f
JM		 1352 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1353 cpu_abort(env, "Machine check exception while in user mode. "
1354 "Aborting\n");
1355 break;
1356 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1357 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1358 env->spr[SPR_DAR]);
1359 /* XXX: check this. Seems bugged */
2be0071f
FB		 1360 switch (env->error_code & 0xFF000000) {
1361 case 0x40000000:
61190b14
FB		 1362 info.si_signo = TARGET_SIGSEGV;
1363 info.si_errno = 0;
1364 info.si_code = TARGET_SEGV_MAPERR;
1365 break;
2be0071f 1366 case 0x04000000:
61190b14
FB		 1367 info.si_signo = TARGET_SIGILL;
1368 info.si_errno = 0;
1369 info.si_code = TARGET_ILL_ILLADR;
1370 break;
2be0071f 1371 case 0x08000000:
61190b14
FB		 1372 info.si_signo = TARGET_SIGSEGV;
1373 info.si_errno = 0;
1374 info.si_code = TARGET_SEGV_ACCERR;
1375 break;
61190b14
FB		 1376 default:
1377 /* Let's send a regular segfault... */
e1833e1f
JM		 1378 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1379 env->error_code);
61190b14
FB		 1380 info.si_signo = TARGET_SIGSEGV;
1381 info.si_errno = 0;
1382 info.si_code = TARGET_SEGV_MAPERR;
1383 break;
1384 }
67867308 1385 info._sifields._sigfault._addr = env->nip;
624f7979 1386 queue_signal(env, info.si_signo, &info);
67867308 1387 break;
e1833e1f 1388 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1389 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1390 "\n", env->spr[SPR_SRR0]);
e1833e1f 1391 /* XXX: check this */
2be0071f
FB		 1392 switch (env->error_code & 0xFF000000) {
1393 case 0x40000000:
61190b14 1394 info.si_signo = TARGET_SIGSEGV;
67867308 1395 info.si_errno = 0;
61190b14
FB		 1396 info.si_code = TARGET_SEGV_MAPERR;
1397 break;
2be0071f
FB		 1398 case 0x10000000:
1399 case 0x08000000:
61190b14
FB		 1400 info.si_signo = TARGET_SIGSEGV;
1401 info.si_errno = 0;
1402 info.si_code = TARGET_SEGV_ACCERR;
1403 break;
1404 default:
1405 /* Let's send a regular segfault... */
e1833e1f
JM		 1406 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1407 env->error_code);
61190b14
FB		 1408 info.si_signo = TARGET_SIGSEGV;
1409 info.si_errno = 0;
1410 info.si_code = TARGET_SEGV_MAPERR;
1411 break;
1412 }
1413 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1414 queue_signal(env, info.si_signo, &info);
67867308 1415 break;
e1833e1f
JM		 1416 case POWERPC_EXCP_EXTERNAL: /* External input */
1417 cpu_abort(env, "External interrupt while in user mode. "
1418 "Aborting\n");
1419 break;
1420 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1421 EXCP_DUMP(env, "Unaligned memory access\n");
1422 /* XXX: check this */
61190b14 1423 info.si_signo = TARGET_SIGBUS;
67867308 1424 info.si_errno = 0;
61190b14
FB		 1425 info.si_code = TARGET_BUS_ADRALN;
1426 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1427 queue_signal(env, info.si_signo, &info);
67867308 1428 break;
e1833e1f
JM		 1429 case POWERPC_EXCP_PROGRAM: /* Program exception */
1430 /* XXX: check this */
61190b14 1431 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1432 case POWERPC_EXCP_FP:
1433 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1434 info.si_signo = TARGET_SIGFPE;
1435 info.si_errno = 0;
1436 switch (env->error_code & 0xF) {
e1833e1f 1437 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1438 info.si_code = TARGET_FPE_FLTOVF;
1439 break;
e1833e1f 1440 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1441 info.si_code = TARGET_FPE_FLTUND;
1442 break;
e1833e1f
JM		 1443 case POWERPC_EXCP_FP_ZX:
1444 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1445 info.si_code = TARGET_FPE_FLTDIV;
1446 break;
e1833e1f 1447 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1448 info.si_code = TARGET_FPE_FLTRES;
1449 break;
e1833e1f 1450 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1451 info.si_code = TARGET_FPE_FLTINV;
1452 break;
7c58044c 1453 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1454 case POWERPC_EXCP_FP_VXISI:
1455 case POWERPC_EXCP_FP_VXIDI:
1456 case POWERPC_EXCP_FP_VXIMZ:
1457 case POWERPC_EXCP_FP_VXVC:
1458 case POWERPC_EXCP_FP_VXSQRT:
1459 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1460 info.si_code = TARGET_FPE_FLTSUB;
1461 break;
1462 default:
e1833e1f
JM		 1463 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1464 env->error_code);
1465 break;
61190b14 1466 }
e1833e1f
JM		 1467 break;
1468 case POWERPC_EXCP_INVAL:
1469 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1470 info.si_signo = TARGET_SIGILL;
1471 info.si_errno = 0;
1472 switch (env->error_code & 0xF) {
e1833e1f 1473 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1474 info.si_code = TARGET_ILL_ILLOPC;
1475 break;
e1833e1f 1476 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1477 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1478 break;
e1833e1f 1479 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1480 info.si_code = TARGET_ILL_PRVREG;
1481 break;
e1833e1f 1482 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1483 info.si_code = TARGET_ILL_COPROC;
1484 break;
1485 default:
e1833e1f
JM		 1486 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1487 env->error_code & 0xF);
61190b14
FB		 1488 info.si_code = TARGET_ILL_ILLADR;
1489 break;
1490 }
1491 break;
e1833e1f
JM		 1492 case POWERPC_EXCP_PRIV:
1493 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1494 info.si_signo = TARGET_SIGILL;
1495 info.si_errno = 0;
1496 switch (env->error_code & 0xF) {
e1833e1f 1497 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1498 info.si_code = TARGET_ILL_PRVOPC;
1499 break;
e1833e1f 1500 case POWERPC_EXCP_PRIV_REG:
61190b14 1501 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1502 break;
61190b14 1503 default:
e1833e1f
JM		 1504 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1505 env->error_code & 0xF);
61190b14
FB		 1506 info.si_code = TARGET_ILL_PRVOPC;
1507 break;
1508 }
1509 break;
e1833e1f
JM		 1510 case POWERPC_EXCP_TRAP:
1511 cpu_abort(env, "Tried to call a TRAP\n");
1512 break;
61190b14
FB		 1513 default:
1514 /* Should not happen ! */
e1833e1f
JM		 1515 cpu_abort(env, "Unknown program exception (%02x)\n",
1516 env->error_code);
1517 break;
61190b14
FB		 1518 }
1519 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1520 queue_signal(env, info.si_signo, &info);
67867308 1521 break;
e1833e1f
JM		 1522 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1523 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1524 info.si_signo = TARGET_SIGILL;
67867308 1525 info.si_errno = 0;
61190b14
FB		 1526 info.si_code = TARGET_ILL_COPROC;
1527 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1528 queue_signal(env, info.si_signo, &info);
67867308 1529 break;
e1833e1f
JM		 1530 case POWERPC_EXCP_SYSCALL: /* System call exception */
1531 cpu_abort(env, "Syscall exception while in user mode. "
1532 "Aborting\n");
61190b14 1533 break;
e1833e1f
JM		 1534 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1535 EXCP_DUMP(env, "No APU instruction allowed\n");
1536 info.si_signo = TARGET_SIGILL;
1537 info.si_errno = 0;
1538 info.si_code = TARGET_ILL_COPROC;
1539 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1540 queue_signal(env, info.si_signo, &info);
61190b14 1541 break;
e1833e1f
JM		 1542 case POWERPC_EXCP_DECR: /* Decrementer exception */
1543 cpu_abort(env, "Decrementer interrupt while in user mode. "
1544 "Aborting\n");
61190b14 1545 break;
e1833e1f
JM		 1546 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1547 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1548 "Aborting\n");
1549 break;
1550 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1551 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1552 "Aborting\n");
1553 break;
1554 case POWERPC_EXCP_DTLB: /* Data TLB error */
1555 cpu_abort(env, "Data TLB exception while in user mode. "
1556 "Aborting\n");
1557 break;
1558 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1559 cpu_abort(env, "Instruction TLB exception while in user mode. "
1560 "Aborting\n");
1561 break;
e1833e1f
JM		 1562 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1563 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1564 info.si_signo = TARGET_SIGILL;
1565 info.si_errno = 0;
1566 info.si_code = TARGET_ILL_COPROC;
1567 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1568 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1569 break;
1570 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1571 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1572 break;
1573 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1574 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1575 break;
1576 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1577 cpu_abort(env, "Performance monitor exception not handled\n");
1578 break;
1579 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1580 cpu_abort(env, "Doorbell interrupt while in user mode. "
1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1584 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_RESET: /* System reset exception */
1588 cpu_abort(env, "Reset interrupt while in user mode. "
1589 "Aborting\n");
1590 break;
e1833e1f
JM		 1591 case POWERPC_EXCP_DSEG: /* Data segment exception */
1592 cpu_abort(env, "Data segment exception while in user mode. "
1593 "Aborting\n");
1594 break;
1595 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1596 cpu_abort(env, "Instruction segment exception "
1597 "while in user mode. Aborting\n");
1598 break;
e85e7c6e 1599 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1600 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1601 cpu_abort(env, "Hypervisor decrementer interrupt "
1602 "while in user mode. Aborting\n");
1603 break;
e1833e1f
JM		 1604 case POWERPC_EXCP_TRACE: /* Trace exception */
1605 /* Nothing to do:
1606 * we use this exception to emulate step-by-step execution mode.
1607 */
1608 break;
e85e7c6e 1609 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1610 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1611 cpu_abort(env, "Hypervisor data storage exception "
1612 "while in user mode. Aborting\n");
1613 break;
1614 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1615 cpu_abort(env, "Hypervisor instruction storage exception "
1616 "while in user mode. Aborting\n");
1617 break;
1618 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1619 cpu_abort(env, "Hypervisor data segment exception "
1620 "while in user mode. Aborting\n");
1621 break;
1622 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1623 cpu_abort(env, "Hypervisor instruction segment exception "
1624 "while in user mode. Aborting\n");
1625 break;
e1833e1f
JM		 1626 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1627 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1628 info.si_signo = TARGET_SIGILL;
1629 info.si_errno = 0;
1630 info.si_code = TARGET_ILL_COPROC;
1631 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1632 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1633 break;
1634 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1635 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1636 "while in user mode. Aborting\n");
1637 break;
1638 case POWERPC_EXCP_IO: /* IO error exception */
1639 cpu_abort(env, "IO error exception while in user mode. "
1640 "Aborting\n");
1641 break;
1642 case POWERPC_EXCP_RUNM: /* Run mode exception */
1643 cpu_abort(env, "Run mode exception while in user mode. "
1644 "Aborting\n");
1645 break;
1646 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1647 cpu_abort(env, "Emulation trap exception not handled\n");
1648 break;
1649 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1650 cpu_abort(env, "Instruction fetch TLB exception "
1651 "while in user-mode. Aborting");
1652 break;
1653 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1654 cpu_abort(env, "Data load TLB exception while in user-mode. "
1655 "Aborting");
1656 break;
1657 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1658 cpu_abort(env, "Data store TLB exception while in user-mode. "
1659 "Aborting");
1660 break;
1661 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1662 cpu_abort(env, "Floating-point assist exception not handled\n");
1663 break;
1664 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1665 cpu_abort(env, "Instruction address breakpoint exception "
1666 "not handled\n");
1667 break;
1668 case POWERPC_EXCP_SMI: /* System management interrupt */
1669 cpu_abort(env, "System management interrupt while in user mode. "
1670 "Aborting\n");
1671 break;
1672 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1673 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1674 "Aborting\n");
1675 break;
1676 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1677 cpu_abort(env, "Performance monitor exception not handled\n");
1678 break;
1679 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1680 cpu_abort(env, "Vector assist exception not handled\n");
1681 break;
1682 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1683 cpu_abort(env, "Soft patch exception not handled\n");
1684 break;
1685 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1686 cpu_abort(env, "Maintenance exception while in user mode. "
1687 "Aborting\n");
1688 break;
1689 case POWERPC_EXCP_STOP: /* stop translation */
1690 /* We did invalidate the instruction cache. Go on */
1691 break;
1692 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1693 /* We just stopped because of a branch. Go on */
1694 break;
1695 case POWERPC_EXCP_SYSCALL_USER:
1696 /* system call in user-mode emulation */
1697 /* WARNING:
1698 * PPC ABI uses overflow flag in cr0 to signal an error
1699 * in syscalls.
1700 */
e1833e1f
JM		 1701 env->crf[0] &= ~0x1;
1702 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1703 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1704 env->gpr[8], 0, 0);
9e0e2f96 1705 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1706 /* Returning from a successful sigreturn syscall.
1707 Avoid corrupting register state. */
1708 break;
1709 }
9e0e2f96 1710 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1711 env->crf[0] |= 0x1;
1712 ret = -ret;
61190b14 1713 }
e1833e1f 1714 env->gpr[3] = ret;
e1833e1f 1715 break;
56f066bb
NF		 1716 case POWERPC_EXCP_STCX:
1717 if (do_store_exclusive(env)) {
1718 info.si_signo = TARGET_SIGSEGV;
1719 info.si_errno = 0;
1720 info.si_code = TARGET_SEGV_MAPERR;
1721 info._sifields._sigfault._addr = env->nip;
1722 queue_signal(env, info.si_signo, &info);
1723 }
1724 break;
71f75756
AJ		 1725 case EXCP_DEBUG:
1726 {
1727 int sig;
1728
1729 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1730 if (sig) {
1731 info.si_signo = sig;
1732 info.si_errno = 0;
1733 info.si_code = TARGET_TRAP_BRKPT;
1734 queue_signal(env, info.si_signo, &info);
1735 }
1736 }
1737 break;
56ba31ff
JM		 1738 case EXCP_INTERRUPT:
1739 /* just indicate that signals should be handled asap */
1740 break;
e1833e1f
JM		 1741 default:
1742 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1743 break;
67867308
FB		 1744 }
1745 process_pending_signals(env);
1746 }
1747}
1748#endif
1749
048f6b4d
FB		 1750#ifdef TARGET_MIPS
1751
ff4f7382
RH		 1752# ifdef TARGET_ABI_MIPSO32
1753# define MIPS_SYS(name, args) args,
048f6b4d 1754static const uint8_t mips_syscall_args[] = {
29fb0f25 1755 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1756 MIPS_SYS(sys_exit , 1)
1757 MIPS_SYS(sys_fork , 0)
1758 MIPS_SYS(sys_read , 3)
1759 MIPS_SYS(sys_write , 3)
1760 MIPS_SYS(sys_open , 3) /* 4005 */
1761 MIPS_SYS(sys_close , 1)
1762 MIPS_SYS(sys_waitpid , 3)
1763 MIPS_SYS(sys_creat , 2)
1764 MIPS_SYS(sys_link , 2)
1765 MIPS_SYS(sys_unlink , 1) /* 4010 */
1766 MIPS_SYS(sys_execve , 0)
1767 MIPS_SYS(sys_chdir , 1)
1768 MIPS_SYS(sys_time , 1)
1769 MIPS_SYS(sys_mknod , 3)
1770 MIPS_SYS(sys_chmod , 2) /* 4015 */
1771 MIPS_SYS(sys_lchown , 3)
1772 MIPS_SYS(sys_ni_syscall , 0)
1773 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1774 MIPS_SYS(sys_lseek , 3)
1775 MIPS_SYS(sys_getpid , 0) /* 4020 */
1776 MIPS_SYS(sys_mount , 5)
1777 MIPS_SYS(sys_oldumount , 1)
1778 MIPS_SYS(sys_setuid , 1)
1779 MIPS_SYS(sys_getuid , 0)
1780 MIPS_SYS(sys_stime , 1) /* 4025 */
1781 MIPS_SYS(sys_ptrace , 4)
1782 MIPS_SYS(sys_alarm , 1)
1783 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1784 MIPS_SYS(sys_pause , 0)
1785 MIPS_SYS(sys_utime , 2) /* 4030 */
1786 MIPS_SYS(sys_ni_syscall , 0)
1787 MIPS_SYS(sys_ni_syscall , 0)
1788 MIPS_SYS(sys_access , 2)
1789 MIPS_SYS(sys_nice , 1)
1790 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1791 MIPS_SYS(sys_sync , 0)
1792 MIPS_SYS(sys_kill , 2)
1793 MIPS_SYS(sys_rename , 2)
1794 MIPS_SYS(sys_mkdir , 2)
1795 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1796 MIPS_SYS(sys_dup , 1)
1797 MIPS_SYS(sys_pipe , 0)
1798 MIPS_SYS(sys_times , 1)
1799 MIPS_SYS(sys_ni_syscall , 0)
1800 MIPS_SYS(sys_brk , 1) /* 4045 */
1801 MIPS_SYS(sys_setgid , 1)
1802 MIPS_SYS(sys_getgid , 0)
1803 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1804 MIPS_SYS(sys_geteuid , 0)
1805 MIPS_SYS(sys_getegid , 0) /* 4050 */
1806 MIPS_SYS(sys_acct , 0)
1807 MIPS_SYS(sys_umount , 2)
1808 MIPS_SYS(sys_ni_syscall , 0)
1809 MIPS_SYS(sys_ioctl , 3)
1810 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1811 MIPS_SYS(sys_ni_syscall , 2)
1812 MIPS_SYS(sys_setpgid , 2)
1813 MIPS_SYS(sys_ni_syscall , 0)
1814 MIPS_SYS(sys_olduname , 1)
1815 MIPS_SYS(sys_umask , 1) /* 4060 */
1816 MIPS_SYS(sys_chroot , 1)
1817 MIPS_SYS(sys_ustat , 2)
1818 MIPS_SYS(sys_dup2 , 2)
1819 MIPS_SYS(sys_getppid , 0)
1820 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1821 MIPS_SYS(sys_setsid , 0)
1822 MIPS_SYS(sys_sigaction , 3)
1823 MIPS_SYS(sys_sgetmask , 0)
1824 MIPS_SYS(sys_ssetmask , 1)
1825 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1826 MIPS_SYS(sys_setregid , 2)
1827 MIPS_SYS(sys_sigsuspend , 0)
1828 MIPS_SYS(sys_sigpending , 1)
1829 MIPS_SYS(sys_sethostname , 2)
1830 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1831 MIPS_SYS(sys_getrlimit , 2)
1832 MIPS_SYS(sys_getrusage , 2)
1833 MIPS_SYS(sys_gettimeofday, 2)
1834 MIPS_SYS(sys_settimeofday, 2)
1835 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1836 MIPS_SYS(sys_setgroups , 2)
1837 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1838 MIPS_SYS(sys_symlink , 2)
1839 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1840 MIPS_SYS(sys_readlink , 3) /* 4085 */
1841 MIPS_SYS(sys_uselib , 1)
1842 MIPS_SYS(sys_swapon , 2)
1843 MIPS_SYS(sys_reboot , 3)
1844 MIPS_SYS(old_readdir , 3)
1845 MIPS_SYS(old_mmap , 6) /* 4090 */
1846 MIPS_SYS(sys_munmap , 2)
1847 MIPS_SYS(sys_truncate , 2)
1848 MIPS_SYS(sys_ftruncate , 2)
1849 MIPS_SYS(sys_fchmod , 2)
1850 MIPS_SYS(sys_fchown , 3) /* 4095 */
1851 MIPS_SYS(sys_getpriority , 2)
1852 MIPS_SYS(sys_setpriority , 3)
1853 MIPS_SYS(sys_ni_syscall , 0)
1854 MIPS_SYS(sys_statfs , 2)
1855 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1856 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1857 MIPS_SYS(sys_socketcall , 2)
1858 MIPS_SYS(sys_syslog , 3)
1859 MIPS_SYS(sys_setitimer , 3)
1860 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1861 MIPS_SYS(sys_newstat , 2)
1862 MIPS_SYS(sys_newlstat , 2)
1863 MIPS_SYS(sys_newfstat , 2)
1864 MIPS_SYS(sys_uname , 1)
1865 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1866 MIPS_SYS(sys_vhangup , 0)
1867 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1868 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1869 MIPS_SYS(sys_wait4 , 4)
1870 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1871 MIPS_SYS(sys_sysinfo , 1)
1872 MIPS_SYS(sys_ipc , 6)
1873 MIPS_SYS(sys_fsync , 1)
1874 MIPS_SYS(sys_sigreturn , 0)
18113962 1875 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1876 MIPS_SYS(sys_setdomainname, 2)
1877 MIPS_SYS(sys_newuname , 1)
1878 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1879 MIPS_SYS(sys_adjtimex , 1)
1880 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1881 MIPS_SYS(sys_sigprocmask , 3)
1882 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1883 MIPS_SYS(sys_init_module , 5)
1884 MIPS_SYS(sys_delete_module, 1)
1885 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1886 MIPS_SYS(sys_quotactl , 0)
1887 MIPS_SYS(sys_getpgid , 1)
1888 MIPS_SYS(sys_fchdir , 1)
1889 MIPS_SYS(sys_bdflush , 2)
1890 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1891 MIPS_SYS(sys_personality , 1)
1892 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1893 MIPS_SYS(sys_setfsuid , 1)
1894 MIPS_SYS(sys_setfsgid , 1)
1895 MIPS_SYS(sys_llseek , 5) /* 4140 */
1896 MIPS_SYS(sys_getdents , 3)
1897 MIPS_SYS(sys_select , 5)
1898 MIPS_SYS(sys_flock , 2)
1899 MIPS_SYS(sys_msync , 3)
1900 MIPS_SYS(sys_readv , 3) /* 4145 */
1901 MIPS_SYS(sys_writev , 3)
1902 MIPS_SYS(sys_cacheflush , 3)
1903 MIPS_SYS(sys_cachectl , 3)
1904 MIPS_SYS(sys_sysmips , 4)
1905 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1906 MIPS_SYS(sys_getsid , 1)
1907 MIPS_SYS(sys_fdatasync , 0)
1908 MIPS_SYS(sys_sysctl , 1)
1909 MIPS_SYS(sys_mlock , 2)
1910 MIPS_SYS(sys_munlock , 2) /* 4155 */
1911 MIPS_SYS(sys_mlockall , 1)
1912 MIPS_SYS(sys_munlockall , 0)
1913 MIPS_SYS(sys_sched_setparam, 2)
1914 MIPS_SYS(sys_sched_getparam, 2)
1915 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1916 MIPS_SYS(sys_sched_getscheduler, 1)
1917 MIPS_SYS(sys_sched_yield , 0)
1918 MIPS_SYS(sys_sched_get_priority_max, 1)
1919 MIPS_SYS(sys_sched_get_priority_min, 1)
1920 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1921 MIPS_SYS(sys_nanosleep, 2)
1922 MIPS_SYS(sys_mremap , 4)
1923 MIPS_SYS(sys_accept , 3)
1924 MIPS_SYS(sys_bind , 3)
1925 MIPS_SYS(sys_connect , 3) /* 4170 */
1926 MIPS_SYS(sys_getpeername , 3)
1927 MIPS_SYS(sys_getsockname , 3)
1928 MIPS_SYS(sys_getsockopt , 5)
1929 MIPS_SYS(sys_listen , 2)
1930 MIPS_SYS(sys_recv , 4) /* 4175 */
1931 MIPS_SYS(sys_recvfrom , 6)
1932 MIPS_SYS(sys_recvmsg , 3)
1933 MIPS_SYS(sys_send , 4)
1934 MIPS_SYS(sys_sendmsg , 3)
1935 MIPS_SYS(sys_sendto , 6) /* 4180 */
1936 MIPS_SYS(sys_setsockopt , 5)
1937 MIPS_SYS(sys_shutdown , 2)
1938 MIPS_SYS(sys_socket , 3)
1939 MIPS_SYS(sys_socketpair , 4)
1940 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1941 MIPS_SYS(sys_getresuid , 3)
1942 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1943 MIPS_SYS(sys_poll , 3)
1944 MIPS_SYS(sys_nfsservctl , 3)
1945 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1946 MIPS_SYS(sys_getresgid , 3)
1947 MIPS_SYS(sys_prctl , 5)
1948 MIPS_SYS(sys_rt_sigreturn, 0)
1949 MIPS_SYS(sys_rt_sigaction, 4)
1950 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1951 MIPS_SYS(sys_rt_sigpending, 2)
1952 MIPS_SYS(sys_rt_sigtimedwait, 4)
1953 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1954 MIPS_SYS(sys_rt_sigsuspend, 0)
1955 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1956 MIPS_SYS(sys_pwrite64 , 6)
1957 MIPS_SYS(sys_chown , 3)
1958 MIPS_SYS(sys_getcwd , 2)
1959 MIPS_SYS(sys_capget , 2)
1960 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 1961 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 1962 MIPS_SYS(sys_sendfile , 4)
1963 MIPS_SYS(sys_ni_syscall , 0)
1964 MIPS_SYS(sys_ni_syscall , 0)
1965 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1966 MIPS_SYS(sys_truncate64 , 4)
1967 MIPS_SYS(sys_ftruncate64 , 4)
1968 MIPS_SYS(sys_stat64 , 2)
1969 MIPS_SYS(sys_lstat64 , 2)
1970 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1971 MIPS_SYS(sys_pivot_root , 2)
1972 MIPS_SYS(sys_mincore , 3)
1973 MIPS_SYS(sys_madvise , 3)
1974 MIPS_SYS(sys_getdents64 , 3)
1975 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1976 MIPS_SYS(sys_ni_syscall , 0)
1977 MIPS_SYS(sys_gettid , 0)
1978 MIPS_SYS(sys_readahead , 5)
1979 MIPS_SYS(sys_setxattr , 5)
1980 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1981 MIPS_SYS(sys_fsetxattr , 5)
1982 MIPS_SYS(sys_getxattr , 4)
1983 MIPS_SYS(sys_lgetxattr , 4)
1984 MIPS_SYS(sys_fgetxattr , 4)
1985 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1986 MIPS_SYS(sys_llistxattr , 3)
1987 MIPS_SYS(sys_flistxattr , 3)
1988 MIPS_SYS(sys_removexattr , 2)
1989 MIPS_SYS(sys_lremovexattr, 2)
1990 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1991 MIPS_SYS(sys_tkill , 2)
1992 MIPS_SYS(sys_sendfile64 , 5)
43be1343 1993 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 1994 MIPS_SYS(sys_sched_setaffinity, 3)
1995 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1996 MIPS_SYS(sys_io_setup , 2)
1997 MIPS_SYS(sys_io_destroy , 1)
1998 MIPS_SYS(sys_io_getevents, 5)
1999 MIPS_SYS(sys_io_submit , 3)
2000 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2001 MIPS_SYS(sys_exit_group , 1)
2002 MIPS_SYS(sys_lookup_dcookie, 3)
2003 MIPS_SYS(sys_epoll_create, 1)
2004 MIPS_SYS(sys_epoll_ctl , 4)
2005 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2006 MIPS_SYS(sys_remap_file_pages, 5)
2007 MIPS_SYS(sys_set_tid_address, 1)
2008 MIPS_SYS(sys_restart_syscall, 0)
2009 MIPS_SYS(sys_fadvise64_64, 7)
2010 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2011 MIPS_SYS(sys_fstatfs64 , 2)
2012 MIPS_SYS(sys_timer_create, 3)
2013 MIPS_SYS(sys_timer_settime, 4)
2014 MIPS_SYS(sys_timer_gettime, 2)
2015 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2016 MIPS_SYS(sys_timer_delete, 1)
2017 MIPS_SYS(sys_clock_settime, 2)
2018 MIPS_SYS(sys_clock_gettime, 2)
2019 MIPS_SYS(sys_clock_getres, 2)
2020 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2021 MIPS_SYS(sys_tgkill , 3)
2022 MIPS_SYS(sys_utimes , 2)
2023 MIPS_SYS(sys_mbind , 4)
2024 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2025 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2026 MIPS_SYS(sys_mq_open , 4)
2027 MIPS_SYS(sys_mq_unlink , 1)
2028 MIPS_SYS(sys_mq_timedsend, 5)
2029 MIPS_SYS(sys_mq_timedreceive, 5)
2030 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2031 MIPS_SYS(sys_mq_getsetattr, 3)
2032 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2033 MIPS_SYS(sys_waitid , 4)
2034 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2035 MIPS_SYS(sys_add_key , 5)
388bb21a 2036 MIPS_SYS(sys_request_key, 4)
048f6b4d 2037 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2038 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2039 MIPS_SYS(sys_inotify_init, 0)
2040 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2041 MIPS_SYS(sys_inotify_rm_watch, 2)
2042 MIPS_SYS(sys_migrate_pages, 4)
2043 MIPS_SYS(sys_openat, 4)
2044 MIPS_SYS(sys_mkdirat, 3)
2045 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2046 MIPS_SYS(sys_fchownat, 5)
2047 MIPS_SYS(sys_futimesat, 3)
2048 MIPS_SYS(sys_fstatat64, 4)
2049 MIPS_SYS(sys_unlinkat, 3)
2050 MIPS_SYS(sys_renameat, 4) /* 4295 */
2051 MIPS_SYS(sys_linkat, 5)
2052 MIPS_SYS(sys_symlinkat, 3)
2053 MIPS_SYS(sys_readlinkat, 4)
2054 MIPS_SYS(sys_fchmodat, 3)
2055 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2056 MIPS_SYS(sys_pselect6, 6)
2057 MIPS_SYS(sys_ppoll, 5)
2058 MIPS_SYS(sys_unshare, 1)
2059 MIPS_SYS(sys_splice, 4)
2060 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2061 MIPS_SYS(sys_tee, 4)
2062 MIPS_SYS(sys_vmsplice, 4)
2063 MIPS_SYS(sys_move_pages, 6)
2064 MIPS_SYS(sys_set_robust_list, 2)
2065 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2066 MIPS_SYS(sys_kexec_load, 4)
2067 MIPS_SYS(sys_getcpu, 3)
2068 MIPS_SYS(sys_epoll_pwait, 6)
2069 MIPS_SYS(sys_ioprio_set, 3)
2070 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2071 MIPS_SYS(sys_utimensat, 4)
2072 MIPS_SYS(sys_signalfd, 3)
2073 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2074 MIPS_SYS(sys_eventfd, 1)
2075 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2076 MIPS_SYS(sys_timerfd_create, 2)
2077 MIPS_SYS(sys_timerfd_gettime, 2)
2078 MIPS_SYS(sys_timerfd_settime, 4)
2079 MIPS_SYS(sys_signalfd4, 4)
2080 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2081 MIPS_SYS(sys_epoll_create1, 1)
2082 MIPS_SYS(sys_dup3, 3)
2083 MIPS_SYS(sys_pipe2, 2)
2084 MIPS_SYS(sys_inotify_init1, 1)
2085 MIPS_SYS(sys_preadv, 6) /* 4330 */
2086 MIPS_SYS(sys_pwritev, 6)
2087 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2088 MIPS_SYS(sys_perf_event_open, 5)
2089 MIPS_SYS(sys_accept4, 4)
2090 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2091 MIPS_SYS(sys_fanotify_init, 2)
2092 MIPS_SYS(sys_fanotify_mark, 6)
2093 MIPS_SYS(sys_prlimit64, 4)
2094 MIPS_SYS(sys_name_to_handle_at, 5)
2095 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2096 MIPS_SYS(sys_clock_adjtime, 2)
2097 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2098};
ff4f7382
RH		 2099# undef MIPS_SYS
2100# endif /* O32 */
048f6b4d 2101
590bc601
PB		 2102static int do_store_exclusive(CPUMIPSState *env)
2103{
2104 target_ulong addr;
2105 target_ulong page_addr;
2106 target_ulong val;
2107 int flags;
2108 int segv = 0;
2109 int reg;
2110 int d;
2111
5499b6ff 2112 addr = env->lladdr;
590bc601
PB		 2113 page_addr = addr & TARGET_PAGE_MASK;
2114 start_exclusive();
2115 mmap_lock();
2116 flags = page_get_flags(page_addr);
2117 if ((flags & PAGE_READ) == 0) {
2118 segv = 1;
2119 } else {
2120 reg = env->llreg & 0x1f;
2121 d = (env->llreg & 0x20) != 0;
2122 if (d) {
2123 segv = get_user_s64(val, addr);
2124 } else {
2125 segv = get_user_s32(val, addr);
2126 }
2127 if (!segv) {
2128 if (val != env->llval) {
2129 env->active_tc.gpr[reg] = 0;
2130 } else {
2131 if (d) {
2132 segv = put_user_u64(env->llnewval, addr);
2133 } else {
2134 segv = put_user_u32(env->llnewval, addr);
2135 }
2136 if (!segv) {
2137 env->active_tc.gpr[reg] = 1;
2138 }
2139 }
2140 }
2141 }
5499b6ff 2142 env->lladdr = -1;
590bc601
PB		 2143 if (!segv) {
2144 env->active_tc.PC += 4;
2145 }
2146 mmap_unlock();
2147 end_exclusive();
2148 return segv;
2149}
2150
54b2f42c
MI		 2151/* Break codes */
2152enum {
2153 BRK_OVERFLOW = 6,
2154 BRK_DIVZERO = 7
2155};
2156
2157static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2158 unsigned int code)
2159{
2160 int ret = -1;
2161
2162 switch (code) {
2163 case BRK_OVERFLOW:
2164 case BRK_DIVZERO:
2165 info->si_signo = TARGET_SIGFPE;
2166 info->si_errno = 0;
2167 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2168 queue_signal(env, info->si_signo, &*info);
2169 ret = 0;
2170 break;
2171 default:
2172 break;
2173 }
2174
2175 return ret;
2176}
2177
048f6b4d
FB		 2178void cpu_loop(CPUMIPSState *env)
2179{
0315c31c 2180 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2181 target_siginfo_t info;
ff4f7382
RH		 2182 int trapnr;
2183 abi_long ret;
2184# ifdef TARGET_ABI_MIPSO32
048f6b4d 2185 unsigned int syscall_num;
ff4f7382 2186# endif
048f6b4d
FB		 2187
2188 for(;;) {
0315c31c 2189 cpu_exec_start(cs);
048f6b4d 2190 trapnr = cpu_mips_exec(env);
0315c31c 2191 cpu_exec_end(cs);
048f6b4d
FB		 2192 switch(trapnr) {
2193 case EXCP_SYSCALL:
b5dc7732 2194 env->active_tc.PC += 4;
ff4f7382
RH		 2195# ifdef TARGET_ABI_MIPSO32
2196 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2197 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2198 ret = -TARGET_ENOSYS;
388bb21a
TS		 2199 } else {
2200 int nb_args;
992f48a0
BS		 2201 abi_ulong sp_reg;
2202 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2203
2204 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2205 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2206 switch (nb_args) {
2207 /* these arguments are taken from the stack */
94c19610
ACH		 2208 case 8:
2209 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2210 goto done_syscall;
2211 }
2212 case 7:
2213 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2214 goto done_syscall;
2215 }
2216 case 6:
2217 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2218 goto done_syscall;
2219 }
2220 case 5:
2221 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2222 goto done_syscall;
2223 }
388bb21a
TS		 2224 default:
2225 break;
048f6b4d 2226 }
b5dc7732
TS		 2227 ret = do_syscall(env, env->active_tc.gpr[2],
2228 env->active_tc.gpr[4],
2229 env->active_tc.gpr[5],
2230 env->active_tc.gpr[6],
2231 env->active_tc.gpr[7],
5945cfcb 2232 arg5, arg6, arg7, arg8);
388bb21a 2233 }
94c19610 2234done_syscall:
ff4f7382
RH		 2235# else
2236 ret = do_syscall(env, env->active_tc.gpr[2],
2237 env->active_tc.gpr[4], env->active_tc.gpr[5],
2238 env->active_tc.gpr[6], env->active_tc.gpr[7],
2239 env->active_tc.gpr[8], env->active_tc.gpr[9],
2240 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2241# endif /* O32 */
0b1bcb00
PB		 2242 if (ret == -TARGET_QEMU_ESIGRETURN) {
2243 /* Returning from a successful sigreturn syscall.
2244 Avoid clobbering register state. */
2245 break;
2246 }
ff4f7382 2247 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2248 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2249 ret = -ret;
2250 } else {
b5dc7732 2251 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2252 }
b5dc7732 2253 env->active_tc.gpr[2] = ret;
048f6b4d 2254 break;
ca7c2b1b
TS		 2255 case EXCP_TLBL:
2256 case EXCP_TLBS:
e6e5bd2d
WT		 2257 case EXCP_AdEL:
2258 case EXCP_AdES:
e4474235
PB		 2259 info.si_signo = TARGET_SIGSEGV;
2260 info.si_errno = 0;
2261 /* XXX: check env->error_code */
2262 info.si_code = TARGET_SEGV_MAPERR;
2263 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2264 queue_signal(env, info.si_signo, &info);
2265 break;
6900e84b 2266 case EXCP_CpU:
048f6b4d 2267 case EXCP_RI:
bc1ad2de
FB		 2268 info.si_signo = TARGET_SIGILL;
2269 info.si_errno = 0;
2270 info.si_code = 0;
624f7979 2271 queue_signal(env, info.si_signo, &info);
048f6b4d 2272 break;
106ec879
FB		 2273 case EXCP_INTERRUPT:
2274 /* just indicate that signals should be handled asap */
2275 break;
d08b2a28
PB		 2276 case EXCP_DEBUG:
2277 {
2278 int sig;
2279
2280 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2281 if (sig)
2282 {
2283 info.si_signo = sig;
2284 info.si_errno = 0;
2285 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2286 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2287 }
2288 }
2289 break;
590bc601
PB		 2290 case EXCP_SC:
2291 if (do_store_exclusive(env)) {
2292 info.si_signo = TARGET_SIGSEGV;
2293 info.si_errno = 0;
2294 info.si_code = TARGET_SEGV_MAPERR;
2295 info._sifields._sigfault._addr = env->active_tc.PC;
2296 queue_signal(env, info.si_signo, &info);
2297 }
2298 break;
853c3240
JL		 2299 case EXCP_DSPDIS:
2300 info.si_signo = TARGET_SIGILL;
2301 info.si_errno = 0;
2302 info.si_code = TARGET_ILL_ILLOPC;
2303 queue_signal(env, info.si_signo, &info);
2304 break;
54b2f42c
MI		 2305 /* The code below was inspired by the MIPS Linux kernel trap
2306 * handling code in arch/mips/kernel/traps.c.
2307 */
2308 case EXCP_BREAK:
2309 {
2310 abi_ulong trap_instr;
2311 unsigned int code;
2312
2313 ret = get_user_ual(trap_instr, env->active_tc.PC);
2314 if (ret != 0) {
2315 goto error;
2316 }
2317
2318 /* As described in the original Linux kernel code, the
2319 * below checks on 'code' are to work around an old
2320 * assembly bug.
2321 */
2322 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2323 if (code >= (1 << 10)) {
2324 code >>= 10;
2325 }
2326
2327 if (do_break(env, &info, code) != 0) {
2328 goto error;
2329 }
2330 }
2331 break;
2332 case EXCP_TRAP:
2333 {
2334 abi_ulong trap_instr;
2335 unsigned int code = 0;
2336
2337 ret = get_user_ual(trap_instr, env->active_tc.PC);
2338 if (ret != 0) {
2339 goto error;
2340 }
2341
2342 /* The immediate versions don't provide a code. */
2343 if (!(trap_instr & 0xFC000000)) {
2344 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2345 }
2346
2347 if (do_break(env, &info, code) != 0) {
2348 goto error;
2349 }
2350 }
2351 break;
048f6b4d 2352 default:
54b2f42c 2353error:
5fafdf24 2354 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2355 trapnr);
878096ee 2356 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2357 abort();
2358 }
2359 process_pending_signals(env);
2360 }
2361}
2362#endif
2363
d962783e
JL		 2364#ifdef TARGET_OPENRISC
2365
2366void cpu_loop(CPUOpenRISCState *env)
2367{
878096ee 2368 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2369 int trapnr, gdbsig;
2370
2371 for (;;) {
2372 trapnr = cpu_exec(env);
2373 gdbsig = 0;
2374
2375 switch (trapnr) {
2376 case EXCP_RESET:
2377 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2378 exit(1);
2379 break;
2380 case EXCP_BUSERR:
2381 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2382 gdbsig = SIGBUS;
2383 break;
2384 case EXCP_DPF:
2385 case EXCP_IPF:
878096ee 2386 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2387 gdbsig = TARGET_SIGSEGV;
2388 break;
2389 case EXCP_TICK:
2390 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2391 break;
2392 case EXCP_ALIGN:
2393 qemu_log("\nAlignment pc is %#x\n", env->pc);
2394 gdbsig = SIGBUS;
2395 break;
2396 case EXCP_ILLEGAL:
2397 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2398 gdbsig = SIGILL;
2399 break;
2400 case EXCP_INT:
2401 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2402 break;
2403 case EXCP_DTLBMISS:
2404 case EXCP_ITLBMISS:
2405 qemu_log("\nTLB miss\n");
2406 break;
2407 case EXCP_RANGE:
2408 qemu_log("\nRange\n");
2409 gdbsig = SIGSEGV;
2410 break;
2411 case EXCP_SYSCALL:
2412 env->pc += 4; /* 0xc00; */
2413 env->gpr[11] = do_syscall(env,
2414 env->gpr[11], /* return value */
2415 env->gpr[3], /* r3 - r7 are params */
2416 env->gpr[4],
2417 env->gpr[5],
2418 env->gpr[6],
2419 env->gpr[7],
2420 env->gpr[8], 0, 0);
2421 break;
2422 case EXCP_FPE:
2423 qemu_log("\nFloating point error\n");
2424 break;
2425 case EXCP_TRAP:
2426 qemu_log("\nTrap\n");
2427 gdbsig = SIGTRAP;
2428 break;
2429 case EXCP_NR:
2430 qemu_log("\nNR\n");
2431 break;
2432 default:
2433 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2434 trapnr);
878096ee 2435 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2436 gdbsig = TARGET_SIGILL;
2437 break;
2438 }
2439 if (gdbsig) {
2440 gdb_handlesig(env, gdbsig);
2441 if (gdbsig != TARGET_SIGTRAP) {
2442 exit(1);
2443 }
2444 }
2445
2446 process_pending_signals(env);
2447 }
2448}
2449
2450#endif /* TARGET_OPENRISC */
2451
fdf9b3e8 2452#ifdef TARGET_SH4
05390248 2453void cpu_loop(CPUSH4State *env)
fdf9b3e8 2454{
878096ee 2455 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2456 int trapnr, ret;
c227f099 2457 target_siginfo_t info;
3b46e624 2458
fdf9b3e8
FB		 2459 while (1) {
2460 trapnr = cpu_sh4_exec (env);
3b46e624 2461
fdf9b3e8
FB		 2462 switch (trapnr) {
2463 case 0x160:
0b6d3ae0 2464 env->pc += 2;
5fafdf24
TS		 2465 ret = do_syscall(env,
2466 env->gregs[3],
2467 env->gregs[4],
2468 env->gregs[5],
2469 env->gregs[6],
2470 env->gregs[7],
2471 env->gregs[0],
5945cfcb
PM		 2472 env->gregs[1],
2473 0, 0);
9c2a9ea1 2474 env->gregs[0] = ret;
fdf9b3e8 2475 break;
c3b5bc8a
TS		 2476 case EXCP_INTERRUPT:
2477 /* just indicate that signals should be handled asap */
2478 break;
355fb23d
PB		 2479 case EXCP_DEBUG:
2480 {
2481 int sig;
2482
2483 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2484 if (sig)
2485 {
2486 info.si_signo = sig;
2487 info.si_errno = 0;
2488 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2489 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2490 }
2491 }
2492 break;
c3b5bc8a
TS		 2493 case 0xa0:
2494 case 0xc0:
2495 info.si_signo = SIGSEGV;
2496 info.si_errno = 0;
2497 info.si_code = TARGET_SEGV_MAPERR;
2498 info._sifields._sigfault._addr = env->tea;
624f7979 2499 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2500 break;
2501
fdf9b3e8
FB		 2502 default:
2503 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2504 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2505 exit (1);
2506 }
2507 process_pending_signals (env);
2508 }
2509}
2510#endif
2511
48733d19 2512#ifdef TARGET_CRIS
05390248 2513void cpu_loop(CPUCRISState *env)
48733d19 2514{
878096ee 2515 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2516 int trapnr, ret;
c227f099 2517 target_siginfo_t info;
48733d19
TS		 2518
2519 while (1) {
2520 trapnr = cpu_cris_exec (env);
2521 switch (trapnr) {
2522 case 0xaa:
2523 {
2524 info.si_signo = SIGSEGV;
2525 info.si_errno = 0;
2526 /* XXX: check env->error_code */
2527 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2528 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2529 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2530 }
2531 break;
b6d3abda
EI		 2532 case EXCP_INTERRUPT:
2533 /* just indicate that signals should be handled asap */
2534 break;
48733d19
TS		 2535 case EXCP_BREAK:
2536 ret = do_syscall(env,
2537 env->regs[9],
2538 env->regs[10],
2539 env->regs[11],
2540 env->regs[12],
2541 env->regs[13],
2542 env->pregs[7],
5945cfcb
PM		 2543 env->pregs[11],
2544 0, 0);
48733d19 2545 env->regs[10] = ret;
48733d19
TS		 2546 break;
2547 case EXCP_DEBUG:
2548 {
2549 int sig;
2550
2551 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2552 if (sig)
2553 {
2554 info.si_signo = sig;
2555 info.si_errno = 0;
2556 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2557 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2558 }
2559 }
2560 break;
2561 default:
2562 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2563 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2564 exit (1);
2565 }
2566 process_pending_signals (env);
2567 }
2568}
2569#endif
2570
b779e29e 2571#ifdef TARGET_MICROBLAZE
05390248 2572void cpu_loop(CPUMBState *env)
b779e29e 2573{
878096ee 2574 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2575 int trapnr, ret;
c227f099 2576 target_siginfo_t info;
b779e29e
EI		 2577
2578 while (1) {
2579 trapnr = cpu_mb_exec (env);
2580 switch (trapnr) {
2581 case 0xaa:
2582 {
2583 info.si_signo = SIGSEGV;
2584 info.si_errno = 0;
2585 /* XXX: check env->error_code */
2586 info.si_code = TARGET_SEGV_MAPERR;
2587 info._sifields._sigfault._addr = 0;
2588 queue_signal(env, info.si_signo, &info);
2589 }
2590 break;
2591 case EXCP_INTERRUPT:
2592 /* just indicate that signals should be handled asap */
2593 break;
2594 case EXCP_BREAK:
2595 /* Return address is 4 bytes after the call. */
2596 env->regs[14] += 4;
d7dce494 2597 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2598 ret = do_syscall(env,
2599 env->regs[12],
2600 env->regs[5],
2601 env->regs[6],
2602 env->regs[7],
2603 env->regs[8],
2604 env->regs[9],
5945cfcb
PM		 2605 env->regs[10],
2606 0, 0);
b779e29e 2607 env->regs[3] = ret;
b779e29e 2608 break;
b76da7e3
EI		 2609 case EXCP_HW_EXCP:
2610 env->regs[17] = env->sregs[SR_PC] + 4;
2611 if (env->iflags & D_FLAG) {
2612 env->sregs[SR_ESR] |= 1 << 12;
2613 env->sregs[SR_PC] -= 4;
b4916d7b 2614 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2615 }
2616
2617 env->iflags &= ~(IMM_FLAG | D_FLAG);
2618
2619 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2620 case ESR_EC_DIVZERO:
2621 info.si_signo = SIGFPE;
2622 info.si_errno = 0;
2623 info.si_code = TARGET_FPE_FLTDIV;
2624 info._sifields._sigfault._addr = 0;
2625 queue_signal(env, info.si_signo, &info);
2626 break;
b76da7e3
EI		 2627 case ESR_EC_FPU:
2628 info.si_signo = SIGFPE;
2629 info.si_errno = 0;
2630 if (env->sregs[SR_FSR] & FSR_IO) {
2631 info.si_code = TARGET_FPE_FLTINV;
2632 }
2633 if (env->sregs[SR_FSR] & FSR_DZ) {
2634 info.si_code = TARGET_FPE_FLTDIV;
2635 }
2636 info._sifields._sigfault._addr = 0;
2637 queue_signal(env, info.si_signo, &info);
2638 break;
2639 default:
2640 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2641 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2642 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2643 exit (1);
2644 break;
2645 }
2646 break;
b779e29e
EI		 2647 case EXCP_DEBUG:
2648 {
2649 int sig;
2650
2651 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2652 if (sig)
2653 {
2654 info.si_signo = sig;
2655 info.si_errno = 0;
2656 info.si_code = TARGET_TRAP_BRKPT;
2657 queue_signal(env, info.si_signo, &info);
2658 }
2659 }
2660 break;
2661 default:
2662 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2663 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2664 exit (1);
2665 }
2666 process_pending_signals (env);
2667 }
2668}
2669#endif
2670
e6e5906b
PB		 2671#ifdef TARGET_M68K
2672
2673void cpu_loop(CPUM68KState *env)
2674{
878096ee 2675 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2676 int trapnr;
2677 unsigned int n;
c227f099 2678 target_siginfo_t info;
e6e5906b 2679 TaskState *ts = env->opaque;
3b46e624 2680
e6e5906b
PB		 2681 for(;;) {
2682 trapnr = cpu_m68k_exec(env);
2683 switch(trapnr) {
2684 case EXCP_ILLEGAL:
2685 {
2686 if (ts->sim_syscalls) {
2687 uint16_t nr;
2688 nr = lduw(env->pc + 2);
2689 env->pc += 4;
2690 do_m68k_simcall(env, nr);
2691 } else {
2692 goto do_sigill;
2693 }
2694 }
2695 break;
a87295e8 2696 case EXCP_HALT_INSN:
e6e5906b 2697 /* Semihosing syscall. */
a87295e8 2698 env->pc += 4;
e6e5906b
PB		 2699 do_m68k_semihosting(env, env->dregs[0]);
2700 break;
2701 case EXCP_LINEA:
2702 case EXCP_LINEF:
2703 case EXCP_UNSUPPORTED:
2704 do_sigill:
2705 info.si_signo = SIGILL;
2706 info.si_errno = 0;
2707 info.si_code = TARGET_ILL_ILLOPN;
2708 info._sifields._sigfault._addr = env->pc;
624f7979 2709 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2710 break;
2711 case EXCP_TRAP0:
2712 {
2713 ts->sim_syscalls = 0;
2714 n = env->dregs[0];
2715 env->pc += 2;
5fafdf24
TS		 2716 env->dregs[0] = do_syscall(env,
2717 n,
e6e5906b
PB		 2718 env->dregs[1],
2719 env->dregs[2],
2720 env->dregs[3],
2721 env->dregs[4],
2722 env->dregs[5],
5945cfcb
PM		 2723 env->aregs[0],
2724 0, 0);
e6e5906b
PB		 2725 }
2726 break;
2727 case EXCP_INTERRUPT:
2728 /* just indicate that signals should be handled asap */
2729 break;
2730 case EXCP_ACCESS:
2731 {
2732 info.si_signo = SIGSEGV;
2733 info.si_errno = 0;
2734 /* XXX: check env->error_code */
2735 info.si_code = TARGET_SEGV_MAPERR;
2736 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2737 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2738 }
2739 break;
2740 case EXCP_DEBUG:
2741 {
2742 int sig;
2743
2744 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2745 if (sig)
2746 {
2747 info.si_signo = sig;
2748 info.si_errno = 0;
2749 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2750 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2751 }
2752 }
2753 break;
2754 default:
5fafdf24 2755 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 2756 trapnr);
878096ee 2757 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 2758 abort();
2759 }
2760 process_pending_signals(env);
2761 }
2762}
2763#endif /* TARGET_M68K */
2764
7a3148a9 2765#ifdef TARGET_ALPHA
6910b8f6
RH		 2766static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2767{
2768 target_ulong addr, val, tmp;
2769 target_siginfo_t info;
2770 int ret = 0;
2771
2772 addr = env->lock_addr;
2773 tmp = env->lock_st_addr;
2774 env->lock_addr = -1;
2775 env->lock_st_addr = 0;
2776
2777 start_exclusive();
2778 mmap_lock();
2779
2780 if (addr == tmp) {
2781 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2782 goto do_sigsegv;
2783 }
2784
2785 if (val == env->lock_value) {
2786 tmp = env->ir[reg];
2787 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2788 goto do_sigsegv;
2789 }
2790 ret = 1;
2791 }
2792 }
2793 env->ir[reg] = ret;
2794 env->pc += 4;
2795
2796 mmap_unlock();
2797 end_exclusive();
2798 return;
2799
2800 do_sigsegv:
2801 mmap_unlock();
2802 end_exclusive();
2803
2804 info.si_signo = TARGET_SIGSEGV;
2805 info.si_errno = 0;
2806 info.si_code = TARGET_SEGV_MAPERR;
2807 info._sifields._sigfault._addr = addr;
2808 queue_signal(env, TARGET_SIGSEGV, &info);
2809}
2810
05390248 2811void cpu_loop(CPUAlphaState *env)
7a3148a9 2812{
878096ee 2813 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 2814 int trapnr;
c227f099 2815 target_siginfo_t info;
6049f4f8 2816 abi_long sysret;
3b46e624 2817
7a3148a9
JM		 2818 while (1) {
2819 trapnr = cpu_alpha_exec (env);
3b46e624 2820
ac316ca4
RH		 2821 /* All of the traps imply a transition through PALcode, which
2822 implies an REI instruction has been executed. Which means
2823 that the intr_flag should be cleared. */
2824 env->intr_flag = 0;
2825
7a3148a9
JM		 2826 switch (trapnr) {
2827 case EXCP_RESET:
2828 fprintf(stderr, "Reset requested. Exit\n");
2829 exit(1);
2830 break;
2831 case EXCP_MCHK:
2832 fprintf(stderr, "Machine check exception. Exit\n");
2833 exit(1);
2834 break;
07b6c13b
RH		 2835 case EXCP_SMP_INTERRUPT:
2836 case EXCP_CLK_INTERRUPT:
2837 case EXCP_DEV_INTERRUPT:
5fafdf24 2838 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2839 exit(1);
2840 break;
07b6c13b 2841 case EXCP_MMFAULT:
6910b8f6 2842 env->lock_addr = -1;
6049f4f8
RH		 2843 info.si_signo = TARGET_SIGSEGV;
2844 info.si_errno = 0;
129d8aa5 2845 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2846 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2847 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2848 queue_signal(env, info.si_signo, &info);
7a3148a9 2849 break;
7a3148a9 2850 case EXCP_UNALIGN:
6910b8f6 2851 env->lock_addr = -1;
6049f4f8
RH		 2852 info.si_signo = TARGET_SIGBUS;
2853 info.si_errno = 0;
2854 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2855 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2856 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2857 break;
2858 case EXCP_OPCDEC:
6049f4f8 2859 do_sigill:
6910b8f6 2860 env->lock_addr = -1;
6049f4f8
RH		 2861 info.si_signo = TARGET_SIGILL;
2862 info.si_errno = 0;
2863 info.si_code = TARGET_ILL_ILLOPC;
2864 info._sifields._sigfault._addr = env->pc;
2865 queue_signal(env, info.si_signo, &info);
7a3148a9 2866 break;
07b6c13b
RH		 2867 case EXCP_ARITH:
2868 env->lock_addr = -1;
2869 info.si_signo = TARGET_SIGFPE;
2870 info.si_errno = 0;
2871 info.si_code = TARGET_FPE_FLTINV;
2872 info._sifields._sigfault._addr = env->pc;
2873 queue_signal(env, info.si_signo, &info);
2874 break;
7a3148a9 2875 case EXCP_FEN:
6049f4f8 2876 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2877 break;
07b6c13b 2878 case EXCP_CALL_PAL:
6910b8f6 2879 env->lock_addr = -1;
07b6c13b 2880 switch (env->error_code) {
6049f4f8
RH		 2881 case 0x80:
2882 /* BPT */
2883 info.si_signo = TARGET_SIGTRAP;
2884 info.si_errno = 0;
2885 info.si_code = TARGET_TRAP_BRKPT;
2886 info._sifields._sigfault._addr = env->pc;
2887 queue_signal(env, info.si_signo, &info);
2888 break;
2889 case 0x81:
2890 /* BUGCHK */
2891 info.si_signo = TARGET_SIGTRAP;
2892 info.si_errno = 0;
2893 info.si_code = 0;
2894 info._sifields._sigfault._addr = env->pc;
2895 queue_signal(env, info.si_signo, &info);
2896 break;
2897 case 0x83:
2898 /* CALLSYS */
2899 trapnr = env->ir[IR_V0];
2900 sysret = do_syscall(env, trapnr,
2901 env->ir[IR_A0], env->ir[IR_A1],
2902 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 2903 env->ir[IR_A4], env->ir[IR_A5],
2904 0, 0);
a5b3b13b
RH		 2905 if (trapnr == TARGET_NR_sigreturn
2906 || trapnr == TARGET_NR_rt_sigreturn) {
2907 break;
2908 }
2909 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 2910 to how this is handled internal to Linux kernel.
2911 (Ab)use trapnr temporarily as boolean indicating error. */
2912 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2913 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2914 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 2915 break;
2916 case 0x86:
2917 /* IMB */
2918 /* ??? We can probably elide the code using page_unprotect
2919 that is checking for self-modifying code. Instead we
2920 could simply call tb_flush here. Until we work out the
2921 changes required to turn off the extra write protection,
2922 this can be a no-op. */
2923 break;
2924 case 0x9E:
2925 /* RDUNIQUE */
2926 /* Handled in the translator for usermode. */
2927 abort();
2928 case 0x9F:
2929 /* WRUNIQUE */
2930 /* Handled in the translator for usermode. */
2931 abort();
2932 case 0xAA:
2933 /* GENTRAP */
2934 info.si_signo = TARGET_SIGFPE;
2935 switch (env->ir[IR_A0]) {
2936 case TARGET_GEN_INTOVF:
2937 info.si_code = TARGET_FPE_INTOVF;
2938 break;
2939 case TARGET_GEN_INTDIV:
2940 info.si_code = TARGET_FPE_INTDIV;
2941 break;
2942 case TARGET_GEN_FLTOVF:
2943 info.si_code = TARGET_FPE_FLTOVF;
2944 break;
2945 case TARGET_GEN_FLTUND:
2946 info.si_code = TARGET_FPE_FLTUND;
2947 break;
2948 case TARGET_GEN_FLTINV:
2949 info.si_code = TARGET_FPE_FLTINV;
2950 break;
2951 case TARGET_GEN_FLTINE:
2952 info.si_code = TARGET_FPE_FLTRES;
2953 break;
2954 case TARGET_GEN_ROPRAND:
2955 info.si_code = 0;
2956 break;
2957 default:
2958 info.si_signo = TARGET_SIGTRAP;
2959 info.si_code = 0;
2960 break;
2961 }
2962 info.si_errno = 0;
2963 info._sifields._sigfault._addr = env->pc;
2964 queue_signal(env, info.si_signo, &info);
2965 break;
2966 default:
2967 goto do_sigill;
2968 }
7a3148a9 2969 break;
7a3148a9 2970 case EXCP_DEBUG:
6049f4f8
RH		 2971 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2972 if (info.si_signo) {
6910b8f6 2973 env->lock_addr = -1;
6049f4f8
RH		 2974 info.si_errno = 0;
2975 info.si_code = TARGET_TRAP_BRKPT;
2976 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2977 }
2978 break;
6910b8f6
RH		 2979 case EXCP_STL_C:
2980 case EXCP_STQ_C:
2981 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2982 break;
d0f20495
RH		 2983 case EXCP_INTERRUPT:
2984 /* Just indicate that signals should be handled asap. */
2985 break;
7a3148a9
JM		 2986 default:
2987 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2988 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 2989 exit (1);
2990 }
2991 process_pending_signals (env);
2992 }
2993}
2994#endif /* TARGET_ALPHA */
2995
a4c075f1
UH		 2996#ifdef TARGET_S390X
2997void cpu_loop(CPUS390XState *env)
2998{
878096ee 2999 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3000 int trapnr, n, sig;
a4c075f1 3001 target_siginfo_t info;
d5a103cd 3002 target_ulong addr;
a4c075f1
UH		 3003
3004 while (1) {
d5a103cd 3005 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3006 switch (trapnr) {
3007 case EXCP_INTERRUPT:
d5a103cd 3008 /* Just indicate that signals should be handled asap. */
a4c075f1 3009 break;
a4c075f1 3010
d5a103cd
RH		 3011 case EXCP_SVC:
3012 n = env->int_svc_code;
3013 if (!n) {
3014 /* syscalls > 255 */
3015 n = env->regs[1];
a4c075f1 3016 }
d5a103cd
RH		 3017 env->psw.addr += env->int_svc_ilen;
3018 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3019 env->regs[4], env->regs[5],
3020 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3021 break;
d5a103cd
RH		 3022
3023 case EXCP_DEBUG:
3024 sig = gdb_handlesig(env, TARGET_SIGTRAP);
3025 if (sig) {
3026 n = TARGET_TRAP_BRKPT;
3027 goto do_signal_pc;
a4c075f1
UH		 3028 }
3029 break;
d5a103cd
RH		 3030 case EXCP_PGM:
3031 n = env->int_pgm_code;
3032 switch (n) {
3033 case PGM_OPERATION:
3034 case PGM_PRIVILEGED:
3035 sig = SIGILL;
3036 n = TARGET_ILL_ILLOPC;
3037 goto do_signal_pc;
3038 case PGM_PROTECTION:
3039 case PGM_ADDRESSING:
3040 sig = SIGSEGV;
a4c075f1 3041 /* XXX: check env->error_code */
d5a103cd
RH		 3042 n = TARGET_SEGV_MAPERR;
3043 addr = env->__excp_addr;
3044 goto do_signal;
3045 case PGM_EXECUTE:
3046 case PGM_SPECIFICATION:
3047 case PGM_SPECIAL_OP:
3048 case PGM_OPERAND:
3049 do_sigill_opn:
3050 sig = SIGILL;
3051 n = TARGET_ILL_ILLOPN;
3052 goto do_signal_pc;
3053
3054 case PGM_FIXPT_OVERFLOW:
3055 sig = SIGFPE;
3056 n = TARGET_FPE_INTOVF;
3057 goto do_signal_pc;
3058 case PGM_FIXPT_DIVIDE:
3059 sig = SIGFPE;
3060 n = TARGET_FPE_INTDIV;
3061 goto do_signal_pc;
3062
3063 case PGM_DATA:
3064 n = (env->fpc >> 8) & 0xff;
3065 if (n == 0xff) {
3066 /* compare-and-trap */
3067 goto do_sigill_opn;
3068 } else {
3069 /* An IEEE exception, simulated or otherwise. */
3070 if (n & 0x80) {
3071 n = TARGET_FPE_FLTINV;
3072 } else if (n & 0x40) {
3073 n = TARGET_FPE_FLTDIV;
3074 } else if (n & 0x20) {
3075 n = TARGET_FPE_FLTOVF;
3076 } else if (n & 0x10) {
3077 n = TARGET_FPE_FLTUND;
3078 } else if (n & 0x08) {
3079 n = TARGET_FPE_FLTRES;
3080 } else {
3081 /* ??? Quantum exception; BFP, DFP error. */
3082 goto do_sigill_opn;
3083 }
3084 sig = SIGFPE;
3085 goto do_signal_pc;
3086 }
3087
3088 default:
3089 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3090 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3091 exit(1);
a4c075f1
UH		 3092 }
3093 break;
d5a103cd
RH		 3094
3095 do_signal_pc:
3096 addr = env->psw.addr;
3097 do_signal:
3098 info.si_signo = sig;
3099 info.si_errno = 0;
3100 info.si_code = n;
3101 info._sifields._sigfault._addr = addr;
3102 queue_signal(env, info.si_signo, &info);
a4c075f1 3103 break;
d5a103cd 3104
a4c075f1 3105 default:
d5a103cd 3106 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3107 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3108 exit(1);
a4c075f1
UH		 3109 }
3110 process_pending_signals (env);
3111 }
3112}
3113
3114#endif /* TARGET_S390X */
3115
a2247f8e 3116THREAD CPUState *thread_cpu;
59faf6d6 3117
edf8e2af
MW		 3118void task_settid(TaskState *ts)
3119{
3120 if (ts->ts_tid == 0) {
edf8e2af 3121 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3122 }
3123}
3124
3125void stop_all_tasks(void)
3126{
3127 /*
3128 * We trust that when using NPTL, start_exclusive()
3129 * handles thread stopping correctly.
3130 */
3131 start_exclusive();
3132}
3133
c3a92833 3134/* Assumes contents are already zeroed. */
624f7979
PB		 3135void init_task_state(TaskState *ts)
3136{
3137 int i;
3138
624f7979
PB		 3139 ts->used = 1;
3140 ts->first_free = ts->sigqueue_table;
3141 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3142 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3143 }
3144 ts->sigqueue_table[i].next = NULL;
3145}
fc9c5412
JS		 3146
3147static void handle_arg_help(const char *arg)
3148{
3149 usage();
3150}
3151
3152static void handle_arg_log(const char *arg)
3153{
3154 int mask;
fc9c5412 3155
4fde1eba 3156 mask = qemu_str_to_log_mask(arg);
fc9c5412 3157 if (!mask) {
59a6fa6e 3158 qemu_print_log_usage(stdout);
fc9c5412
JS		 3159 exit(1);
3160 }
24537a01 3161 qemu_set_log(mask);
fc9c5412
JS		 3162}
3163
50171d42 3164static void handle_arg_log_filename(const char *arg)
3165{
9a7e5424 3166 qemu_set_log_filename(arg);
50171d42 3167}
3168
fc9c5412
JS		 3169static void handle_arg_set_env(const char *arg)
3170{
3171 char *r, *p, *token;
3172 r = p = strdup(arg);
3173 while ((token = strsep(&p, ",")) != NULL) {
3174 if (envlist_setenv(envlist, token) != 0) {
3175 usage();
3176 }
3177 }
3178 free(r);
3179}
3180
3181static void handle_arg_unset_env(const char *arg)
3182{
3183 char *r, *p, *token;
3184 r = p = strdup(arg);
3185 while ((token = strsep(&p, ",")) != NULL) {
3186 if (envlist_unsetenv(envlist, token) != 0) {
3187 usage();
3188 }
3189 }
3190 free(r);
3191}
3192
3193static void handle_arg_argv0(const char *arg)
3194{
3195 argv0 = strdup(arg);
3196}
3197
3198static void handle_arg_stack_size(const char *arg)
3199{
3200 char *p;
3201 guest_stack_size = strtoul(arg, &p, 0);
3202 if (guest_stack_size == 0) {
3203 usage();
3204 }
3205
3206 if (*p == 'M') {
3207 guest_stack_size *= 1024 * 1024;
3208 } else if (*p == 'k' || *p == 'K') {
3209 guest_stack_size *= 1024;
3210 }
3211}
3212
3213static void handle_arg_ld_prefix(const char *arg)
3214{
3215 interp_prefix = strdup(arg);
3216}
3217
3218static void handle_arg_pagesize(const char *arg)
3219{
3220 qemu_host_page_size = atoi(arg);
3221 if (qemu_host_page_size == 0 ||
3222 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3223 fprintf(stderr, "page size must be a power of two\n");
3224 exit(1);
3225 }
3226}
3227
3228static void handle_arg_gdb(const char *arg)
3229{
3230 gdbstub_port = atoi(arg);
3231}
3232
3233static void handle_arg_uname(const char *arg)
3234{
3235 qemu_uname_release = strdup(arg);
3236}
3237
3238static void handle_arg_cpu(const char *arg)
3239{
3240 cpu_model = strdup(arg);
c8057f95 3241 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3242 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3243#if defined(cpu_list)
3244 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3245#endif
3246 exit(1);
3247 }
3248}
3249
3250#if defined(CONFIG_USE_GUEST_BASE)
3251static void handle_arg_guest_base(const char *arg)
3252{
3253 guest_base = strtol(arg, NULL, 0);
3254 have_guest_base = 1;
3255}
3256
3257static void handle_arg_reserved_va(const char *arg)
3258{
3259 char *p;
3260 int shift = 0;
3261 reserved_va = strtoul(arg, &p, 0);
3262 switch (*p) {
3263 case 'k':
3264 case 'K':
3265 shift = 10;
3266 break;
3267 case 'M':
3268 shift = 20;
3269 break;
3270 case 'G':
3271 shift = 30;
3272 break;
3273 }
3274 if (shift) {
3275 unsigned long unshifted = reserved_va;
3276 p++;
3277 reserved_va <<= shift;
3278 if (((reserved_va >> shift) != unshifted)
3279#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3280 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3281#endif
3282 ) {
3283 fprintf(stderr, "Reserved virtual address too big\n");
3284 exit(1);
3285 }
3286 }
3287 if (*p) {
3288 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3289 exit(1);
3290 }
3291}
3292#endif
3293
3294static void handle_arg_singlestep(const char *arg)
3295{
3296 singlestep = 1;
3297}
3298
3299static void handle_arg_strace(const char *arg)
3300{
3301 do_strace = 1;
3302}
3303
3304static void handle_arg_version(const char *arg)
3305{
2e59915d 3306 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3307 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3308 exit(0);
fc9c5412
JS		 3309}
3310
3311struct qemu_argument {
3312 const char *argv;
3313 const char *env;
3314 bool has_arg;
3315 void (*handle_opt)(const char *arg);
3316 const char *example;
3317 const char *help;
3318};
3319
42644cee 3320static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3321 {"h", "", false, handle_arg_help,
3322 "", "print this help"},
3323 {"g", "QEMU_GDB", true, handle_arg_gdb,
3324 "port", "wait gdb connection to 'port'"},
3325 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3326 "path", "set the elf interpreter prefix to 'path'"},
3327 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3328 "size", "set the stack size to 'size' bytes"},
3329 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3330 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3331 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3332 "var=value", "sets targets environment variable (see below)"},
3333 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3334 "var", "unsets targets environment variable (see below)"},
3335 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3336 "argv0", "forces target process argv[0] to be 'argv0'"},
3337 {"r", "QEMU_UNAME", true, handle_arg_uname,
3338 "uname", "set qemu uname release string to 'uname'"},
3339#if defined(CONFIG_USE_GUEST_BASE)
3340 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3341 "address", "set guest_base address to 'address'"},
3342 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3343 "size", "reserve 'size' bytes for guest virtual address space"},
3344#endif
3345 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3346 "item[,...]", "enable logging of specified items "
3347 "(use '-d help' for a list of items)"},
50171d42 3348 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3349 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3350 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3351 "pagesize", "set the host page size to 'pagesize'"},
3352 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3353 "", "run in singlestep mode"},
3354 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3355 "", "log system calls"},
3356 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3357 "", "display version information and exit"},
fc9c5412
JS		 3358 {NULL, NULL, false, NULL, NULL, NULL}
3359};
3360
3361static void usage(void)
3362{
42644cee 3363 const struct qemu_argument *arginfo;
fc9c5412
JS		 3364 int maxarglen;
3365 int maxenvlen;
3366
2e59915d
PB		 3367 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3368 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3369 "\n"
3370 "Options and associated environment variables:\n"
3371 "\n");
3372
63ec54d7
PM		 3373 /* Calculate column widths. We must always have at least enough space
3374 * for the column header.
3375 */
3376 maxarglen = strlen("Argument");
3377 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3378
3379 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3380 int arglen = strlen(arginfo->argv);
3381 if (arginfo->has_arg) {
3382 arglen += strlen(arginfo->example) + 1;
3383 }
fc9c5412
JS		 3384 if (strlen(arginfo->env) > maxenvlen) {
3385 maxenvlen = strlen(arginfo->env);
3386 }
63ec54d7
PM		 3387 if (arglen > maxarglen) {
3388 maxarglen = arglen;
fc9c5412
JS		 3389 }
3390 }
3391
63ec54d7
PM		 3392 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3393 maxenvlen, "Env-variable");
fc9c5412
JS		 3394
3395 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3396 if (arginfo->has_arg) {
3397 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3398 (int)(maxarglen - strlen(arginfo->argv) - 1),
3399 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3400 } else {
63ec54d7 3401 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3402 maxenvlen, arginfo->env,
3403 arginfo->help);
3404 }
3405 }
3406
3407 printf("\n"
3408 "Defaults:\n"
3409 "QEMU_LD_PREFIX = %s\n"
989b697d 3410 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3411 interp_prefix,
989b697d 3412 guest_stack_size);
fc9c5412
JS		 3413
3414 printf("\n"
3415 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3416 "QEMU_UNSET_ENV environment variables to set and unset\n"
3417 "environment variables for the target process.\n"
3418 "It is possible to provide several variables by separating them\n"
3419 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3420 "provide the -E and -U options multiple times.\n"
3421 "The following lines are equivalent:\n"
3422 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3423 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3424 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3425 "Note that if you provide several changes to a single variable\n"
3426 "the last change will stay in effect.\n");
3427
3428 exit(1);
3429}
3430
3431static int parse_args(int argc, char **argv)
3432{
3433 const char *r;
3434 int optind;
42644cee 3435 const struct qemu_argument *arginfo;
fc9c5412
JS		 3436
3437 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3438 if (arginfo->env == NULL) {
3439 continue;
3440 }
3441
3442 r = getenv(arginfo->env);
3443 if (r != NULL) {
3444 arginfo->handle_opt(r);
3445 }
3446 }
3447
3448 optind = 1;
3449 for (;;) {
3450 if (optind >= argc) {
3451 break;
3452 }
3453 r = argv[optind];
3454 if (r[0] != '-') {
3455 break;
3456 }
3457 optind++;
3458 r++;
3459 if (!strcmp(r, "-")) {
3460 break;
3461 }
3462
3463 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3464 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3465 if (arginfo->has_arg) {
1386d4c0
PM		 3466 if (optind >= argc) {
3467 usage();
3468 }
3469 arginfo->handle_opt(argv[optind]);
fc9c5412 3470 optind++;
1386d4c0
PM		 3471 } else {
3472 arginfo->handle_opt(NULL);
fc9c5412 3473 }
fc9c5412
JS		 3474 break;
3475 }
3476 }
3477
3478 /* no option matched the current argv */
3479 if (arginfo->handle_opt == NULL) {
3480 usage();
3481 }
3482 }
3483
3484 if (optind >= argc) {
3485 usage();
3486 }
3487
3488 filename = argv[optind];
3489 exec_path = argv[optind];
3490
3491 return optind;
3492}
3493
902b3d5c 3494int main(int argc, char **argv, char **envp)
31e31b8a 3495{
01ffc75b 3496 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3497 struct image_info info1, *info = &info1;
edf8e2af 3498 struct linux_binprm bprm;
48e15fc2 3499 TaskState *ts;
9349b4f9 3500 CPUArchState *env;
586314f2 3501 int optind;
04a6dfeb 3502 char **target_environ, **wrk;
7d8cec95
AJ		 3503 char **target_argv;
3504 int target_argc;
7d8cec95 3505 int i;
fd4d81dd 3506 int ret;
b12b6a18 3507
ce008c1f
AF		 3508 module_call_init(MODULE_INIT_QOM);
3509
902b3d5c 3510 qemu_cache_utils_init(envp);
3511
04a6dfeb
AJ		 3512 if ((envlist = envlist_create()) == NULL) {
3513 (void) fprintf(stderr, "Unable to allocate envlist\n");
3514 exit(1);
3515 }
3516
3517 /* add current environment into the list */
3518 for (wrk = environ; *wrk != NULL; wrk++) {
3519 (void) envlist_setenv(envlist, *wrk);
3520 }
3521
703e0e89
RH		 3522 /* Read the stack limit from the kernel. If it's "unlimited",
3523 then we can do little else besides use the default. */
3524 {
3525 struct rlimit lim;
3526 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906 3527 && lim.rlim_cur != RLIM_INFINITY
3528 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3529 guest_stack_size = lim.rlim_cur;
3530 }
3531 }
3532
b1f9be31 3533 cpu_model = NULL;
b5ec5ce0 3534#if defined(cpudef_setup)
3535 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3536#endif
3537
fc9c5412 3538 optind = parse_args(argc, argv);
586314f2 3539
31e31b8a 3540 /* Zero out regs */
01ffc75b 3541 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3542
3543 /* Zero out image_info */
3544 memset(info, 0, sizeof(struct image_info));
3545
edf8e2af
MW		 3546 memset(&bprm, 0, sizeof (bprm));
3547
74cd30b8
FB		 3548 /* Scan interp_prefix dir for replacement files. */
3549 init_paths(interp_prefix);
3550
46027c07 3551 if (cpu_model == NULL) {
aaed909a 3552#if defined(TARGET_I386)
46027c07
FB		 3553#ifdef TARGET_X86_64
3554 cpu_model = "qemu64";
3555#else
3556 cpu_model = "qemu32";
3557#endif
aaed909a 3558#elif defined(TARGET_ARM)
088ab16c 3559 cpu_model = "any";
d2fbca94
GX		 3560#elif defined(TARGET_UNICORE32)
3561 cpu_model = "any";
aaed909a
FB		 3562#elif defined(TARGET_M68K)
3563 cpu_model = "any";
3564#elif defined(TARGET_SPARC)
3565#ifdef TARGET_SPARC64
3566 cpu_model = "TI UltraSparc II";
3567#else
3568 cpu_model = "Fujitsu MB86904";
46027c07 3569#endif
aaed909a
FB		 3570#elif defined(TARGET_MIPS)
3571#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3572 cpu_model = "20Kc";
3573#else
3574 cpu_model = "24Kf";
3575#endif
d962783e
JL		 3576#elif defined TARGET_OPENRISC
3577 cpu_model = "or1200";
aaed909a 3578#elif defined(TARGET_PPC)
7ded4f52 3579#ifdef TARGET_PPC64
f7177937 3580 cpu_model = "970fx";
7ded4f52 3581#else
aaed909a 3582 cpu_model = "750";
7ded4f52 3583#endif
aaed909a
FB		 3584#else
3585 cpu_model = "any";
3586#endif
3587 }
d5ab9713
JK		 3588 tcg_exec_init(0);
3589 cpu_exec_init_all();
83fb7adf
FB		 3590 /* NOTE: we need to init the CPU at this stage to get
3591 qemu_host_page_size */
aaed909a
FB		 3592 env = cpu_init(cpu_model);
3593 if (!env) {
3594 fprintf(stderr, "Unable to find CPU definition\n");
3595 exit(1);
3596 }
ff18b762 3597 cpu_reset(ENV_GET_CPU(env));
b55a37c9 3598
a2247f8e 3599 thread_cpu = ENV_GET_CPU(env);
3b46e624 3600
b6741956
FB		 3601 if (getenv("QEMU_STRACE")) {
3602 do_strace = 1;
b92c47c1
TS		 3603 }
3604
04a6dfeb
AJ		 3605 target_environ = envlist_to_environ(envlist, NULL);
3606 envlist_free(envlist);
b12b6a18 3607
379f6698
PB		 3608#if defined(CONFIG_USE_GUEST_BASE)
3609 /*
3610 * Now that page sizes are configured in cpu_init() we can do
3611 * proper page alignment for guest_base.
3612 */
3613 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3614
806d1021
MI		 3615 if (reserved_va || have_guest_base) {
3616 guest_base = init_guest_space(guest_base, reserved_va, 0,
3617 have_guest_base);
3618 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3619 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3620 "space for use as guest address space (check your virtual "
3621 "memory ulimit setting or reserve less using -R option)\n",
3622 reserved_va);
68a1c816
PB		 3623 exit(1);
3624 }
97cc7560 3625
806d1021
MI		 3626 if (reserved_va) {
3627 mmap_next_start = reserved_va;
97cc7560
DDAG		 3628 }
3629 }
14f24e14 3630#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3631
3632 /*
3633 * Read in mmap_min_addr kernel parameter. This value is used
3634 * When loading the ELF image to determine whether guest_base
14f24e14 3635 * is needed. It is also used in mmap_find_vma.
379f6698 3636 */
14f24e14 3637 {
379f6698
PB		 3638 FILE *fp;
3639
3640 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3641 unsigned long tmp;
3642 if (fscanf(fp, "%lu", &tmp) == 1) {
3643 mmap_min_addr = tmp;
3644 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3645 }
3646 fclose(fp);
3647 }
3648 }
379f6698 3649
7d8cec95
AJ		 3650 /*
3651 * Prepare copy of argv vector for target.
3652 */
3653 target_argc = argc - optind;
3654 target_argv = calloc(target_argc + 1, sizeof (char *));
3655 if (target_argv == NULL) {
3656 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3657 exit(1);
3658 }
3659
3660 /*
3661 * If argv0 is specified (using '-0' switch) we replace
3662 * argv[0] pointer with the given one.
3663 */
3664 i = 0;
3665 if (argv0 != NULL) {
3666 target_argv[i++] = strdup(argv0);
3667 }
3668 for (; i < target_argc; i++) {
3669 target_argv[i] = strdup(argv[optind + i]);
3670 }
3671 target_argv[target_argc] = NULL;
3672
7267c094 3673 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3674 init_task_state(ts);
3675 /* build Task State */
3676 ts->info = info;
3677 ts->bprm = &bprm;
3678 env->opaque = ts;
3679 task_settid(ts);
3680
fd4d81dd
AP		 3681 ret = loader_exec(filename, target_argv, target_environ, regs,
3682 info, &bprm);
3683 if (ret != 0) {
885c1d10 3684 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3685 _exit(1);
3686 }
3687
3688 for (wrk = target_environ; *wrk; wrk++) {
3689 free(*wrk);
31e31b8a 3690 }
3b46e624 3691
b12b6a18
TS		 3692 free(target_environ);
3693
2e77eac6 3694 if (qemu_log_enabled()) {
379f6698
PB		 3695#if defined(CONFIG_USE_GUEST_BASE)
3696 qemu_log("guest_base 0x%lx\n", guest_base);
3697#endif
2e77eac6
BS		 3698 log_page_dump();
3699
3700 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3701 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3702 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3703 info->start_code);
3704 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3705 info->start_data);
3706 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3707 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3708 info->start_stack);
3709 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3710 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3711 }
31e31b8a 3712
53a5960a 3713 target_set_brk(info->brk);
31e31b8a 3714 syscall_init();
66fb9763 3715 signal_init();
31e31b8a 3716
9002ec79
RH		 3717#if defined(CONFIG_USE_GUEST_BASE)
3718 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3719 generating the prologue until now so that the prologue can take
3720 the real value of GUEST_BASE into account. */
3721 tcg_prologue_init(&tcg_ctx);
3722#endif
3723
b346ff46 3724#if defined(TARGET_I386)
2e255c6b
FB		 3725 cpu_x86_set_cpl(env, 3);
3726
3802ce26 3727 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e 3728 env->hflags |= HF_PE_MASK;
0514ef2f 3729 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 3730 env->cr[4] |= CR4_OSFXSR_MASK;
3731 env->hflags |= HF_OSFXSR_MASK;
3732 }
d2fd1af7 3733#ifndef TARGET_ABI32
4dbc422b 3734 /* enable 64 bit mode if possible */
0514ef2f 3735 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 3736 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3737 exit(1);
3738 }
d2fd1af7 3739 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3740 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3741 env->hflags |= HF_LMA_MASK;
3742#endif
1bde465e 3743
415e561f
FB		 3744 /* flags setup : we activate the IRQs by default as in user mode */
3745 env->eflags |= IF_MASK;
3b46e624 3746
6dbad63e 3747 /* linux register setup */
d2fd1af7 3748#ifndef TARGET_ABI32
84409ddb
JM		 3749 env->regs[R_EAX] = regs->rax;
3750 env->regs[R_EBX] = regs->rbx;
3751 env->regs[R_ECX] = regs->rcx;
3752 env->regs[R_EDX] = regs->rdx;
3753 env->regs[R_ESI] = regs->rsi;
3754 env->regs[R_EDI] = regs->rdi;
3755 env->regs[R_EBP] = regs->rbp;
3756 env->regs[R_ESP] = regs->rsp;
3757 env->eip = regs->rip;
3758#else
0ecfa993
FB		 3759 env->regs[R_EAX] = regs->eax;
3760 env->regs[R_EBX] = regs->ebx;
3761 env->regs[R_ECX] = regs->ecx;
3762 env->regs[R_EDX] = regs->edx;
3763 env->regs[R_ESI] = regs->esi;
3764 env->regs[R_EDI] = regs->edi;
3765 env->regs[R_EBP] = regs->ebp;
3766 env->regs[R_ESP] = regs->esp;
dab2ed99 3767 env->eip = regs->eip;
84409ddb 3768#endif
31e31b8a 3769
f4beb510 3770 /* linux interrupt setup */
e441570f
AZ		 3771#ifndef TARGET_ABI32
3772 env->idt.limit = 511;
3773#else
3774 env->idt.limit = 255;
3775#endif
3776 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3777 PROT_READ|PROT_WRITE,
3778 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3779 idt_table = g2h(env->idt.base);
f4beb510
FB		 3780 set_idt(0, 0);
3781 set_idt(1, 0);
3782 set_idt(2, 0);
3783 set_idt(3, 3);
3784 set_idt(4, 3);
ec95da6c 3785 set_idt(5, 0);
f4beb510
FB		 3786 set_idt(6, 0);
3787 set_idt(7, 0);
3788 set_idt(8, 0);
3789 set_idt(9, 0);
3790 set_idt(10, 0);
3791 set_idt(11, 0);
3792 set_idt(12, 0);
3793 set_idt(13, 0);
3794 set_idt(14, 0);
3795 set_idt(15, 0);
3796 set_idt(16, 0);
3797 set_idt(17, 0);
3798 set_idt(18, 0);
3799 set_idt(19, 0);
3800 set_idt(0x80, 3);
3801
6dbad63e 3802 /* linux segment setup */
8d18e893
FB		 3803 {
3804 uint64_t *gdt_table;
e441570f
AZ		 3805 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3806 PROT_READ|PROT_WRITE,
3807 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3808 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3809 gdt_table = g2h(env->gdt.base);
d2fd1af7 3810#ifdef TARGET_ABI32
8d18e893
FB		 3811 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3812 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3813 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3814#else
3815 /* 64 bit code segment */
3816 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3817 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3818 DESC_L_MASK |
3819 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3820#endif
8d18e893
FB		 3821 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3822 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3823 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3824 }
6dbad63e 3825 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3826 cpu_x86_load_seg(env, R_SS, __USER_DS);
3827#ifdef TARGET_ABI32
6dbad63e
FB		 3828 cpu_x86_load_seg(env, R_DS, __USER_DS);
3829 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3830 cpu_x86_load_seg(env, R_FS, __USER_DS);
3831 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3832 /* This hack makes Wine work... */
3833 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3834#else
3835 cpu_x86_load_seg(env, R_DS, 0);
3836 cpu_x86_load_seg(env, R_ES, 0);
3837 cpu_x86_load_seg(env, R_FS, 0);
3838 cpu_x86_load_seg(env, R_GS, 0);
3839#endif
b346ff46
FB		 3840#elif defined(TARGET_ARM)
3841 {
3842 int i;
b5ff1b31 3843 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3844 for(i = 0; i < 16; i++) {
3845 env->regs[i] = regs->uregs[i];
3846 }
d8fd2954
PB		 3847 /* Enable BE8. */
3848 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3849 && (info->elf_flags & EF_ARM_BE8)) {
3850 env->bswap_code = 1;
3851 }
b346ff46 3852 }
d2fbca94
GX		 3853#elif defined(TARGET_UNICORE32)
3854 {
3855 int i;
3856 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3857 for (i = 0; i < 32; i++) {
3858 env->regs[i] = regs->uregs[i];
3859 }
3860 }
93ac68bc 3861#elif defined(TARGET_SPARC)
060366c5
FB		 3862 {
3863 int i;
3864 env->pc = regs->pc;
3865 env->npc = regs->npc;
3866 env->y = regs->y;
3867 for(i = 0; i < 8; i++)
3868 env->gregs[i] = regs->u_regs[i];
3869 for(i = 0; i < 8; i++)
3870 env->regwptr[i] = regs->u_regs[i + 8];
3871 }
67867308
FB		 3872#elif defined(TARGET_PPC)
3873 {
3874 int i;
3fc6c082 3875
0411a972
JM		 3876#if defined(TARGET_PPC64)
3877#if defined(TARGET_ABI32)
3878 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3879#else
0411a972
JM		 3880 env->msr |= (target_ulong)1 << MSR_SF;
3881#endif
84409ddb 3882#endif
67867308
FB		 3883 env->nip = regs->nip;
3884 for(i = 0; i < 32; i++) {
3885 env->gpr[i] = regs->gpr[i];
3886 }
3887 }
e6e5906b
PB		 3888#elif defined(TARGET_M68K)
3889 {
e6e5906b
PB		 3890 env->pc = regs->pc;
3891 env->dregs[0] = regs->d0;
3892 env->dregs[1] = regs->d1;
3893 env->dregs[2] = regs->d2;
3894 env->dregs[3] = regs->d3;
3895 env->dregs[4] = regs->d4;
3896 env->dregs[5] = regs->d5;
3897 env->dregs[6] = regs->d6;
3898 env->dregs[7] = regs->d7;
3899 env->aregs[0] = regs->a0;
3900 env->aregs[1] = regs->a1;
3901 env->aregs[2] = regs->a2;
3902 env->aregs[3] = regs->a3;
3903 env->aregs[4] = regs->a4;
3904 env->aregs[5] = regs->a5;
3905 env->aregs[6] = regs->a6;
3906 env->aregs[7] = regs->usp;
3907 env->sr = regs->sr;
3908 ts->sim_syscalls = 1;
3909 }
b779e29e
EI		 3910#elif defined(TARGET_MICROBLAZE)
3911 {
3912 env->regs[0] = regs->r0;
3913 env->regs[1] = regs->r1;
3914 env->regs[2] = regs->r2;
3915 env->regs[3] = regs->r3;
3916 env->regs[4] = regs->r4;
3917 env->regs[5] = regs->r5;
3918 env->regs[6] = regs->r6;
3919 env->regs[7] = regs->r7;
3920 env->regs[8] = regs->r8;
3921 env->regs[9] = regs->r9;
3922 env->regs[10] = regs->r10;
3923 env->regs[11] = regs->r11;
3924 env->regs[12] = regs->r12;
3925 env->regs[13] = regs->r13;
3926 env->regs[14] = regs->r14;
3927 env->regs[15] = regs->r15;
3928 env->regs[16] = regs->r16;
3929 env->regs[17] = regs->r17;
3930 env->regs[18] = regs->r18;
3931 env->regs[19] = regs->r19;
3932 env->regs[20] = regs->r20;
3933 env->regs[21] = regs->r21;
3934 env->regs[22] = regs->r22;
3935 env->regs[23] = regs->r23;
3936 env->regs[24] = regs->r24;
3937 env->regs[25] = regs->r25;
3938 env->regs[26] = regs->r26;
3939 env->regs[27] = regs->r27;
3940 env->regs[28] = regs->r28;
3941 env->regs[29] = regs->r29;
3942 env->regs[30] = regs->r30;
3943 env->regs[31] = regs->r31;
3944 env->sregs[SR_PC] = regs->pc;
3945 }
048f6b4d
FB		 3946#elif defined(TARGET_MIPS)
3947 {
3948 int i;
3949
3950 for(i = 0; i < 32; i++) {
b5dc7732 3951 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3952 }
0fddbbf2
NF		 3953 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3954 if (regs->cp0_epc & 1) {
3955 env->hflags |= MIPS_HFLAG_M16;
3956 }
048f6b4d 3957 }
d962783e
JL		 3958#elif defined(TARGET_OPENRISC)
3959 {
3960 int i;
3961
3962 for (i = 0; i < 32; i++) {
3963 env->gpr[i] = regs->gpr[i];
3964 }
3965
3966 env->sr = regs->sr;
3967 env->pc = regs->pc;
3968 }
fdf9b3e8
FB		 3969#elif defined(TARGET_SH4)
3970 {
3971 int i;
3972
3973 for(i = 0; i < 16; i++) {
3974 env->gregs[i] = regs->regs[i];
3975 }
3976 env->pc = regs->pc;
3977 }
7a3148a9
JM		 3978#elif defined(TARGET_ALPHA)
3979 {
3980 int i;
3981
3982 for(i = 0; i < 28; i++) {
992f48a0 3983 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 3984 }
dad081ee 3985 env->ir[IR_SP] = regs->usp;
7a3148a9 3986 env->pc = regs->pc;
7a3148a9 3987 }
48733d19
TS		 3988#elif defined(TARGET_CRIS)
3989 {
3990 env->regs[0] = regs->r0;
3991 env->regs[1] = regs->r1;
3992 env->regs[2] = regs->r2;
3993 env->regs[3] = regs->r3;
3994 env->regs[4] = regs->r4;
3995 env->regs[5] = regs->r5;
3996 env->regs[6] = regs->r6;
3997 env->regs[7] = regs->r7;
3998 env->regs[8] = regs->r8;
3999 env->regs[9] = regs->r9;
4000 env->regs[10] = regs->r10;
4001 env->regs[11] = regs->r11;
4002 env->regs[12] = regs->r12;
4003 env->regs[13] = regs->r13;
4004 env->regs[14] = info->start_stack;
4005 env->regs[15] = regs->acr;
4006 env->pc = regs->erp;
4007 }
a4c075f1
UH		 4008#elif defined(TARGET_S390X)
4009 {
4010 int i;
4011 for (i = 0; i < 16; i++) {
4012 env->regs[i] = regs->gprs[i];
4013 }
4014 env->psw.mask = regs->psw.mask;
4015 env->psw.addr = regs->psw.addr;
4016 }
b346ff46
FB		 4017#else
4018#error unsupported target CPU
4019#endif
31e31b8a 4020
d2fbca94 4021#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4022 ts->stack_base = info->start_stack;
4023 ts->heap_base = info->brk;
4024 /* This will be filled in on the first SYS_HEAPINFO call. */
4025 ts->heap_limit = 0;
4026#endif
4027
74c33bed 4028 if (gdbstub_port) {
ff7a981a
PM		 4029 if (gdbserver_start(gdbstub_port) < 0) {
4030 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4031 gdbstub_port);
4032 exit(1);
4033 }
1fddef4b
FB		 4034 gdb_handlesig(env, 0);
4035 }
1b6b029e
FB		 4036 cpu_loop(env);
4037 /* never exits */
31e31b8a
FB		 4038 return 0;
4039}
Qemu copy for testing