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Merge remote-tracking branch 'afaerber/qom-cpu' into staging
[qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
3ef693a0 38#define DEBUG_LOGFILE "/tmp/qemu.log"
586314f2 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
fc9c5412
JS		 43const char *filename;
44const char *argv0;
45int gdbstub_port;
46envlist_t *envlist;
47const char *cpu_model;
379f6698 48unsigned long mmap_min_addr;
14f24e14 49#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 50unsigned long guest_base;
51int have_guest_base;
288e65b9
AG		 52#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
53/*
54 * When running 32-on-64 we should make sure we can fit all of the possible
55 * guest address space into a contiguous chunk of virtual host memory.
56 *
57 * This way we will never overlap with our own libraries or binaries or stack
58 * or anything else that QEMU maps.
59 */
314992b1
AG		 60# ifdef TARGET_MIPS
61/* MIPS only supports 31 bits of virtual address space for user space */
62unsigned long reserved_va = 0x77000000;
63# else
288e65b9 64unsigned long reserved_va = 0xf7000000;
314992b1 65# endif
288e65b9 66#else
68a1c816 67unsigned long reserved_va;
379f6698 68#endif
288e65b9 69#endif
1b530a6d 70
fc9c5412
JS		 71static void usage(void);
72
7ee2822c 73static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 74const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 75
9de5e440
FB		 76/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
77 we allocate a bigger stack. Need a better solution, for example
78 by remapping the process stack directly at the right place */
703e0e89 79unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 80
81void gemu_log(const char *fmt, ...)
82{
83 va_list ap;
84
85 va_start(ap, fmt);
86 vfprintf(stderr, fmt, ap);
87 va_end(ap);
88}
89
8fcd3692 90#if defined(TARGET_I386)
05390248 91int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 92{
93 return -1;
94}
8fcd3692 95#endif
92ccca6a 96
2f7bb878 97#if defined(CONFIG_USE_NPTL)
d5975363
PB		 98/***********************************************************/
99/* Helper routines for implementing atomic operations. */
100
101/* To implement exclusive operations we force all cpus to syncronise.
102 We don't require a full sync, only that no cpus are executing guest code.
103 The alternative is to map target atomic ops onto host equivalents,
104 which requires quite a lot of per host/target work. */
c2764719 105static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 106static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
107static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
108static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
109static int pending_cpus;
110
111/* Make sure everything is in a consistent state for calling fork(). */
112void fork_start(void)
113{
5e5f07e0 114 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 115 pthread_mutex_lock(&exclusive_lock);
d032d1b4 116 mmap_fork_start();
d5975363
PB		 117}
118
119void fork_end(int child)
120{
d032d1b4 121 mmap_fork_end(child);
d5975363
PB		 122 if (child) {
123 /* Child processes created by fork() only have a single thread.
124 Discard information about the parent threads. */
125 first_cpu = thread_env;
126 thread_env->next_cpu = NULL;
127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 129 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
2b1319c8 133 gdbserver_fork(thread_env);
d5975363
PB		 134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 137 }
d5975363
PB		 138}
139
140/* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142static inline void exclusive_idle(void)
143{
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147}
148
149/* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151static inline void start_exclusive(void)
152{
9349b4f9 153 CPUArchState *other;
0315c31c
AF		 154 CPUState *other_cpu;
155
d5975363
PB		 156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
161 for (other = first_cpu; other; other = other->next_cpu) {
0315c31c
AF		 162 other_cpu = ENV_GET_CPU(other);
163 if (other_cpu->running) {
d5975363 164 pending_cpus++;
3098dba0 165 cpu_exit(other);
d5975363
PB		 166 }
167 }
168 if (pending_cpus > 1) {
169 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
170 }
171}
172
173/* Finish an exclusive operation. */
174static inline void end_exclusive(void)
175{
176 pending_cpus = 0;
177 pthread_cond_broadcast(&exclusive_resume);
178 pthread_mutex_unlock(&exclusive_lock);
179}
180
181/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 182static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 183{
184 pthread_mutex_lock(&exclusive_lock);
185 exclusive_idle();
0315c31c 186 cpu->running = true;
d5975363
PB		 187 pthread_mutex_unlock(&exclusive_lock);
188}
189
190/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 191static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 192{
193 pthread_mutex_lock(&exclusive_lock);
0315c31c 194 cpu->running = false;
d5975363
PB		 195 if (pending_cpus > 1) {
196 pending_cpus--;
197 if (pending_cpus == 1) {
198 pthread_cond_signal(&exclusive_cond);
199 }
200 }
201 exclusive_idle();
202 pthread_mutex_unlock(&exclusive_lock);
203}
c2764719
PB		 204
205void cpu_list_lock(void)
206{
207 pthread_mutex_lock(&cpu_list_mutex);
208}
209
210void cpu_list_unlock(void)
211{
212 pthread_mutex_unlock(&cpu_list_mutex);
213}
2f7bb878 214#else /* if !CONFIG_USE_NPTL */
d5975363 215/* These are no-ops because we are not threadsafe. */
0315c31c 216static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 217{
218}
219
0315c31c 220static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 221{
222}
223
224static inline void start_exclusive(void)
225{
226}
227
228static inline void end_exclusive(void)
229{
230}
231
232void fork_start(void)
233{
234}
235
236void fork_end(int child)
237{
2b1319c8
AJ		 238 if (child) {
239 gdbserver_fork(thread_env);
240 }
d5975363 241}
c2764719
PB		 242
243void cpu_list_lock(void)
244{
245}
246
247void cpu_list_unlock(void)
248{
249}
d5975363
PB		 250#endif
251
252
a541f297
FB		 253#ifdef TARGET_I386
254/***********************************************************/
255/* CPUX86 core interface */
256
05390248 257void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 258{
259}
260
28ab0e2e
FB		 261uint64_t cpu_get_tsc(CPUX86State *env)
262{
263 return cpu_get_real_ticks();
264}
265
5fafdf24 266static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 267 int flags)
6dbad63e 268{
f4beb510 269 unsigned int e1, e2;
53a5960a 270 uint32_t *p;
6dbad63e
FB		 271 e1 = (addr << 16) | (limit & 0xffff);
272 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 273 e2 |= flags;
53a5960a 274 p = ptr;
d538e8f5 275 p[0] = tswap32(e1);
276 p[1] = tswap32(e2);
f4beb510
FB		 277}
278
e441570f 279static uint64_t *idt_table;
eb38c52c 280#ifdef TARGET_X86_64
d2fd1af7
FB		 281static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
282 uint64_t addr, unsigned int sel)
f4beb510 283{
4dbc422b 284 uint32_t *p, e1, e2;
f4beb510
FB		 285 e1 = (addr & 0xffff) | (sel << 16);
286 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 287 p = ptr;
4dbc422b
FB		 288 p[0] = tswap32(e1);
289 p[1] = tswap32(e2);
290 p[2] = tswap32(addr >> 32);
291 p[3] = 0;
6dbad63e 292}
d2fd1af7
FB		 293/* only dpl matters as we do only user space emulation */
294static void set_idt(int n, unsigned int dpl)
295{
296 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
297}
298#else
d2fd1af7
FB		 299static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
300 uint32_t addr, unsigned int sel)
301{
4dbc422b 302 uint32_t *p, e1, e2;
d2fd1af7
FB		 303 e1 = (addr & 0xffff) | (sel << 16);
304 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
305 p = ptr;
4dbc422b
FB		 306 p[0] = tswap32(e1);
307 p[1] = tswap32(e2);
d2fd1af7
FB		 308}
309
f4beb510
FB		 310/* only dpl matters as we do only user space emulation */
311static void set_idt(int n, unsigned int dpl)
312{
313 set_gate(idt_table + n, 0, dpl, 0, 0);
314}
d2fd1af7 315#endif
31e31b8a 316
89e957e7 317void cpu_loop(CPUX86State *env)
1b6b029e 318{
bc8a22cc 319 int trapnr;
992f48a0 320 abi_ulong pc;
c227f099 321 target_siginfo_t info;
851e67a1 322
1b6b029e 323 for(;;) {
bc8a22cc 324 trapnr = cpu_x86_exec(env);
bc8a22cc 325 switch(trapnr) {
f4beb510 326 case 0x80:
d2fd1af7 327 /* linux syscall from int $0x80 */
5fafdf24
TS		 328 env->regs[R_EAX] = do_syscall(env,
329 env->regs[R_EAX],
f4beb510
FB		 330 env->regs[R_EBX],
331 env->regs[R_ECX],
332 env->regs[R_EDX],
333 env->regs[R_ESI],
334 env->regs[R_EDI],
5945cfcb
PM		 335 env->regs[R_EBP],
336 0, 0);
f4beb510 337 break;
d2fd1af7
FB		 338#ifndef TARGET_ABI32
339 case EXCP_SYSCALL:
5ba18547 340 /* linux syscall from syscall instruction */
d2fd1af7
FB		 341 env->regs[R_EAX] = do_syscall(env,
342 env->regs[R_EAX],
343 env->regs[R_EDI],
344 env->regs[R_ESI],
345 env->regs[R_EDX],
346 env->regs[10],
347 env->regs[8],
5945cfcb
PM		 348 env->regs[9],
349 0, 0);
d2fd1af7
FB		 350 env->eip = env->exception_next_eip;
351 break;
352#endif
f4beb510
FB		 353 case EXCP0B_NOSEG:
354 case EXCP0C_STACK:
355 info.si_signo = SIGBUS;
356 info.si_errno = 0;
357 info.si_code = TARGET_SI_KERNEL;
358 info._sifields._sigfault._addr = 0;
624f7979 359 queue_signal(env, info.si_signo, &info);
f4beb510 360 break;
1b6b029e 361 case EXCP0D_GPF:
d2fd1af7 362 /* XXX: potential problem if ABI32 */
84409ddb 363#ifndef TARGET_X86_64
851e67a1 364 if (env->eflags & VM_MASK) {
89e957e7 365 handle_vm86_fault(env);
84409ddb
JM		 366 } else
367#endif
368 {
f4beb510
FB		 369 info.si_signo = SIGSEGV;
370 info.si_errno = 0;
371 info.si_code = TARGET_SI_KERNEL;
372 info._sifields._sigfault._addr = 0;
624f7979 373 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 374 }
375 break;
b689bc57
FB		 376 case EXCP0E_PAGE:
377 info.si_signo = SIGSEGV;
378 info.si_errno = 0;
379 if (!(env->error_code & 1))
380 info.si_code = TARGET_SEGV_MAPERR;
381 else
382 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 383 info._sifields._sigfault._addr = env->cr[2];
624f7979 384 queue_signal(env, info.si_signo, &info);
b689bc57 385 break;
9de5e440 386 case EXCP00_DIVZ:
84409ddb 387#ifndef TARGET_X86_64
bc8a22cc 388 if (env->eflags & VM_MASK) {
447db213 389 handle_vm86_trap(env, trapnr);
84409ddb
JM		 390 } else
391#endif
392 {
bc8a22cc
FB		 393 /* division by zero */
394 info.si_signo = SIGFPE;
395 info.si_errno = 0;
396 info.si_code = TARGET_FPE_INTDIV;
397 info._sifields._sigfault._addr = env->eip;
624f7979 398 queue_signal(env, info.si_signo, &info);
bc8a22cc 399 }
9de5e440 400 break;
01df040b 401 case EXCP01_DB:
447db213 402 case EXCP03_INT3:
84409ddb 403#ifndef TARGET_X86_64
447db213
FB		 404 if (env->eflags & VM_MASK) {
405 handle_vm86_trap(env, trapnr);
84409ddb
JM		 406 } else
407#endif
408 {
447db213
FB		 409 info.si_signo = SIGTRAP;
410 info.si_errno = 0;
01df040b 411 if (trapnr == EXCP01_DB) {
447db213
FB		 412 info.si_code = TARGET_TRAP_BRKPT;
413 info._sifields._sigfault._addr = env->eip;
414 } else {
415 info.si_code = TARGET_SI_KERNEL;
416 info._sifields._sigfault._addr = 0;
417 }
624f7979 418 queue_signal(env, info.si_signo, &info);
447db213
FB		 419 }
420 break;
9de5e440
FB		 421 case EXCP04_INTO:
422 case EXCP05_BOUND:
84409ddb 423#ifndef TARGET_X86_64
bc8a22cc 424 if (env->eflags & VM_MASK) {
447db213 425 handle_vm86_trap(env, trapnr);
84409ddb
JM		 426 } else
427#endif
428 {
bc8a22cc
FB		 429 info.si_signo = SIGSEGV;
430 info.si_errno = 0;
b689bc57 431 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 432 info._sifields._sigfault._addr = 0;
624f7979 433 queue_signal(env, info.si_signo, &info);
bc8a22cc 434 }
9de5e440
FB		 435 break;
436 case EXCP06_ILLOP:
437 info.si_signo = SIGILL;
438 info.si_errno = 0;
439 info.si_code = TARGET_ILL_ILLOPN;
440 info._sifields._sigfault._addr = env->eip;
624f7979 441 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 442 break;
443 case EXCP_INTERRUPT:
444 /* just indicate that signals should be handled asap */
445 break;
1fddef4b
FB		 446 case EXCP_DEBUG:
447 {
448 int sig;
449
450 sig = gdb_handlesig (env, TARGET_SIGTRAP);
451 if (sig)
452 {
453 info.si_signo = sig;
454 info.si_errno = 0;
455 info.si_code = TARGET_TRAP_BRKPT;
624f7979 456 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 457 }
458 }
459 break;
1b6b029e 460 default:
970a87a6 461 pc = env->segs[R_CS].base + env->eip;
5fafdf24 462 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 463 (long)pc, trapnr);
1b6b029e
FB		 464 abort();
465 }
66fb9763 466 process_pending_signals(env);
1b6b029e
FB		 467 }
468}
b346ff46
FB		 469#endif
470
471#ifdef TARGET_ARM
472
d8fd2954
PB		 473#define get_user_code_u32(x, gaddr, doswap) \
474 ({ abi_long __r = get_user_u32((x), (gaddr)); \
475 if (!__r && (doswap)) { \
476 (x) = bswap32(x); \
477 } \
478 __r; \
479 })
480
481#define get_user_code_u16(x, gaddr, doswap) \
482 ({ abi_long __r = get_user_u16((x), (gaddr)); \
483 if (!__r && (doswap)) { \
484 (x) = bswap16(x); \
485 } \
486 __r; \
487 })
488
97cc7560
DDAG		 489/*
490 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
491 * Input:
492 * r0 = pointer to oldval
493 * r1 = pointer to newval
494 * r2 = pointer to target value
495 *
496 * Output:
497 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
498 * C set if *ptr was changed, clear if no exchange happened
499 *
500 * Note segv's in kernel helpers are a bit tricky, we can set the
501 * data address sensibly but the PC address is just the entry point.
502 */
503static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
504{
505 uint64_t oldval, newval, val;
506 uint32_t addr, cpsr;
507 target_siginfo_t info;
508
509 /* Based on the 32 bit code in do_kernel_trap */
510
511 /* XXX: This only works between threads, not between processes.
512 It's probably possible to implement this with native host
513 operations. However things like ldrex/strex are much harder so
514 there's not much point trying. */
515 start_exclusive();
516 cpsr = cpsr_read(env);
517 addr = env->regs[2];
518
519 if (get_user_u64(oldval, env->regs[0])) {
520 env->cp15.c6_data = env->regs[0];
521 goto segv;
522 };
523
524 if (get_user_u64(newval, env->regs[1])) {
525 env->cp15.c6_data = env->regs[1];
526 goto segv;
527 };
528
529 if (get_user_u64(val, addr)) {
530 env->cp15.c6_data = addr;
531 goto segv;
532 }
533
534 if (val == oldval) {
535 val = newval;
536
537 if (put_user_u64(val, addr)) {
538 env->cp15.c6_data = addr;
539 goto segv;
540 };
541
542 env->regs[0] = 0;
543 cpsr |= CPSR_C;
544 } else {
545 env->regs[0] = -1;
546 cpsr &= ~CPSR_C;
547 }
548 cpsr_write(env, cpsr, CPSR_C);
549 end_exclusive();
550 return;
551
552segv:
553 end_exclusive();
554 /* We get the PC of the entry address - which is as good as anything,
555 on a real kernel what you get depends on which mode it uses. */
556 info.si_signo = SIGSEGV;
557 info.si_errno = 0;
558 /* XXX: check env->error_code */
559 info.si_code = TARGET_SEGV_MAPERR;
560 info._sifields._sigfault._addr = env->cp15.c6_data;
561 queue_signal(env, info.si_signo, &info);
562
563 end_exclusive();
564}
565
fbb4a2e3
PB		 566/* Handle a jump to the kernel code page. */
567static int
568do_kernel_trap(CPUARMState *env)
569{
570 uint32_t addr;
571 uint32_t cpsr;
572 uint32_t val;
573
574 switch (env->regs[15]) {
575 case 0xffff0fa0: /* __kernel_memory_barrier */
576 /* ??? No-op. Will need to do better for SMP. */
577 break;
578 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 579 /* XXX: This only works between threads, not between processes.
580 It's probably possible to implement this with native host
581 operations. However things like ldrex/strex are much harder so
582 there's not much point trying. */
583 start_exclusive();
fbb4a2e3
PB		 584 cpsr = cpsr_read(env);
585 addr = env->regs[2];
586 /* FIXME: This should SEGV if the access fails. */
587 if (get_user_u32(val, addr))
588 val = ~env->regs[0];
589 if (val == env->regs[0]) {
590 val = env->regs[1];
591 /* FIXME: Check for segfaults. */
592 put_user_u32(val, addr);
593 env->regs[0] = 0;
594 cpsr |= CPSR_C;
595 } else {
596 env->regs[0] = -1;
597 cpsr &= ~CPSR_C;
598 }
599 cpsr_write(env, cpsr, CPSR_C);
d5975363 600 end_exclusive();
fbb4a2e3
PB		 601 break;
602 case 0xffff0fe0: /* __kernel_get_tls */
603 env->regs[0] = env->cp15.c13_tls2;
604 break;
97cc7560
DDAG		 605 case 0xffff0f60: /* __kernel_cmpxchg64 */
606 arm_kernel_cmpxchg64_helper(env);
607 break;
608
fbb4a2e3
PB		 609 default:
610 return 1;
611 }
612 /* Jump back to the caller. */
613 addr = env->regs[14];
614 if (addr & 1) {
615 env->thumb = 1;
616 addr &= ~1;
617 }
618 env->regs[15] = addr;
619
620 return 0;
621}
622
426f5abc
PB		 623static int do_strex(CPUARMState *env)
624{
625 uint32_t val;
626 int size;
627 int rc = 1;
628 int segv = 0;
629 uint32_t addr;
630 start_exclusive();
631 addr = env->exclusive_addr;
632 if (addr != env->exclusive_test) {
633 goto fail;
634 }
635 size = env->exclusive_info & 0xf;
636 switch (size) {
637 case 0:
638 segv = get_user_u8(val, addr);
639 break;
640 case 1:
641 segv = get_user_u16(val, addr);
642 break;
643 case 2:
644 case 3:
645 segv = get_user_u32(val, addr);
646 break;
f7001a3b
AJ		 647 default:
648 abort();
426f5abc
PB		 649 }
650 if (segv) {
651 env->cp15.c6_data = addr;
652 goto done;
653 }
654 if (val != env->exclusive_val) {
655 goto fail;
656 }
657 if (size == 3) {
658 segv = get_user_u32(val, addr + 4);
659 if (segv) {
660 env->cp15.c6_data = addr + 4;
661 goto done;
662 }
663 if (val != env->exclusive_high) {
664 goto fail;
665 }
666 }
667 val = env->regs[(env->exclusive_info >> 8) & 0xf];
668 switch (size) {
669 case 0:
670 segv = put_user_u8(val, addr);
671 break;
672 case 1:
673 segv = put_user_u16(val, addr);
674 break;
675 case 2:
676 case 3:
677 segv = put_user_u32(val, addr);
678 break;
679 }
680 if (segv) {
681 env->cp15.c6_data = addr;
682 goto done;
683 }
684 if (size == 3) {
685 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 686 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 687 if (segv) {
688 env->cp15.c6_data = addr + 4;
689 goto done;
690 }
691 }
692 rc = 0;
693fail:
725b8a69 694 env->regs[15] += 4;
426f5abc
PB		 695 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
696done:
697 end_exclusive();
698 return segv;
699}
700
b346ff46
FB		 701void cpu_loop(CPUARMState *env)
702{
0315c31c 703 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 704 int trapnr;
705 unsigned int n, insn;
c227f099 706 target_siginfo_t info;
b5ff1b31 707 uint32_t addr;
3b46e624 708
b346ff46 709 for(;;) {
0315c31c 710 cpu_exec_start(cs);
b346ff46 711 trapnr = cpu_arm_exec(env);
0315c31c 712 cpu_exec_end(cs);
b346ff46
FB		 713 switch(trapnr) {
714 case EXCP_UDEF:
c6981055
FB		 715 {
716 TaskState *ts = env->opaque;
717 uint32_t opcode;
6d9a42be 718 int rc;
c6981055
FB		 719
720 /* we handle the FPU emulation here, as Linux */
721 /* we get the opcode */
2f619698 722 /* FIXME - what to do if get_user() fails? */
d8fd2954 723 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 724
6d9a42be
AJ		 725 rc = EmulateAll(opcode, &ts->fpa, env);
726 if (rc == 0) { /* illegal instruction */
c6981055
FB		 727 info.si_signo = SIGILL;
728 info.si_errno = 0;
729 info.si_code = TARGET_ILL_ILLOPN;
730 info._sifields._sigfault._addr = env->regs[15];
624f7979 731 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 732 } else if (rc < 0) { /* FP exception */
733 int arm_fpe=0;
734
735 /* translate softfloat flags to FPSR flags */
736 if (-rc & float_flag_invalid)
737 arm_fpe |= BIT_IOC;
738 if (-rc & float_flag_divbyzero)
739 arm_fpe |= BIT_DZC;
740 if (-rc & float_flag_overflow)
741 arm_fpe |= BIT_OFC;
742 if (-rc & float_flag_underflow)
743 arm_fpe |= BIT_UFC;
744 if (-rc & float_flag_inexact)
745 arm_fpe |= BIT_IXC;
746
747 FPSR fpsr = ts->fpa.fpsr;
748 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
749
750 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
751 info.si_signo = SIGFPE;
752 info.si_errno = 0;
753
754 /* ordered by priority, least first */
755 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
756 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
757 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
758 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
759 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
760
761 info._sifields._sigfault._addr = env->regs[15];
624f7979 762 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 763 } else {
764 env->regs[15] += 4;
765 }
766
767 /* accumulate unenabled exceptions */
768 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
769 fpsr |= BIT_IXC;
770 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
771 fpsr |= BIT_UFC;
772 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
773 fpsr |= BIT_OFC;
774 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
775 fpsr |= BIT_DZC;
776 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
777 fpsr |= BIT_IOC;
778 ts->fpa.fpsr=fpsr;
779 } else { /* everything OK */
c6981055
FB		 780 /* increment PC */
781 env->regs[15] += 4;
782 }
783 }
b346ff46
FB		 784 break;
785 case EXCP_SWI:
06c949e6 786 case EXCP_BKPT:
b346ff46 787 {
ce4defa0 788 env->eabi = 1;
b346ff46 789 /* system call */
06c949e6
PB		 790 if (trapnr == EXCP_BKPT) {
791 if (env->thumb) {
2f619698 792 /* FIXME - what to do if get_user() fails? */
d8fd2954 793 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 794 n = insn & 0xff;
795 env->regs[15] += 2;
796 } else {
2f619698 797 /* FIXME - what to do if get_user() fails? */
d8fd2954 798 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 799 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
800 env->regs[15] += 4;
801 }
192c7bd9 802 } else {
06c949e6 803 if (env->thumb) {
2f619698 804 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 805 get_user_code_u16(insn, env->regs[15] - 2,
806 env->bswap_code);
06c949e6
PB		 807 n = insn & 0xff;
808 } else {
2f619698 809 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 810 get_user_code_u32(insn, env->regs[15] - 4,
811 env->bswap_code);
06c949e6
PB		 812 n = insn & 0xffffff;
813 }
192c7bd9
FB		 814 }
815
6f1f31c0 816 if (n == ARM_NR_cacheflush) {
dcfd14b3 817 /* nop */
a4f81979
FB		 818 } else if (n == ARM_NR_semihosting
819 || n == ARM_NR_thumb_semihosting) {
820 env->regs[0] = do_arm_semihosting (env);
3a1363ac 821 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 822 /* linux syscall */
ce4defa0 823 if (env->thumb || n == 0) {
192c7bd9
FB		 824 n = env->regs[7];
825 } else {
826 n -= ARM_SYSCALL_BASE;
ce4defa0 827 env->eabi = 0;
192c7bd9 828 }
fbb4a2e3
PB		 829 if ( n > ARM_NR_BASE) {
830 switch (n) {
831 case ARM_NR_cacheflush:
dcfd14b3 832 /* nop */
fbb4a2e3
PB		 833 break;
834 case ARM_NR_set_tls:
835 cpu_set_tls(env, env->regs[0]);
836 env->regs[0] = 0;
837 break;
838 default:
839 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
840 n);
841 env->regs[0] = -TARGET_ENOSYS;
842 break;
843 }
844 } else {
845 env->regs[0] = do_syscall(env,
846 n,
847 env->regs[0],
848 env->regs[1],
849 env->regs[2],
850 env->regs[3],
851 env->regs[4],
5945cfcb
PM		 852 env->regs[5],
853 0, 0);
fbb4a2e3 854 }
b346ff46
FB		 855 } else {
856 goto error;
857 }
858 }
859 break;
43fff238
FB		 860 case EXCP_INTERRUPT:
861 /* just indicate that signals should be handled asap */
862 break;
68016c62 863 case EXCP_PREFETCH_ABORT:
eae473c1 864 addr = env->cp15.c6_insn;
b5ff1b31 865 goto do_segv;
68016c62 866 case EXCP_DATA_ABORT:
eae473c1 867 addr = env->cp15.c6_data;
b5ff1b31 868 do_segv:
68016c62
FB		 869 {
870 info.si_signo = SIGSEGV;
871 info.si_errno = 0;
872 /* XXX: check env->error_code */
873 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 874 info._sifields._sigfault._addr = addr;
624f7979 875 queue_signal(env, info.si_signo, &info);
68016c62
FB		 876 }
877 break;
1fddef4b
FB		 878 case EXCP_DEBUG:
879 {
880 int sig;
881
882 sig = gdb_handlesig (env, TARGET_SIGTRAP);
883 if (sig)
884 {
885 info.si_signo = sig;
886 info.si_errno = 0;
887 info.si_code = TARGET_TRAP_BRKPT;
624f7979 888 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 889 }
890 }
891 break;
fbb4a2e3
PB		 892 case EXCP_KERNEL_TRAP:
893 if (do_kernel_trap(env))
894 goto error;
895 break;
426f5abc
PB		 896 case EXCP_STREX:
897 if (do_strex(env)) {
898 addr = env->cp15.c6_data;
899 goto do_segv;
900 }
e9273455 901 break;
b346ff46
FB		 902 default:
903 error:
5fafdf24 904 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 905 trapnr);
7fe48483 906 cpu_dump_state(env, stderr, fprintf, 0);
b346ff46
FB		 907 abort();
908 }
909 process_pending_signals(env);
910 }
911}
912
913#endif
1b6b029e 914
d2fbca94
GX		 915#ifdef TARGET_UNICORE32
916
05390248 917void cpu_loop(CPUUniCore32State *env)
d2fbca94 918{
0315c31c 919 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 920 int trapnr;
921 unsigned int n, insn;
922 target_siginfo_t info;
923
924 for (;;) {
0315c31c 925 cpu_exec_start(cs);
d2fbca94 926 trapnr = uc32_cpu_exec(env);
0315c31c 927 cpu_exec_end(cs);
d2fbca94
GX		 928 switch (trapnr) {
929 case UC32_EXCP_PRIV:
930 {
931 /* system call */
932 get_user_u32(insn, env->regs[31] - 4);
933 n = insn & 0xffffff;
934
935 if (n >= UC32_SYSCALL_BASE) {
936 /* linux syscall */
937 n -= UC32_SYSCALL_BASE;
938 if (n == UC32_SYSCALL_NR_set_tls) {
939 cpu_set_tls(env, env->regs[0]);
940 env->regs[0] = 0;
941 } else {
942 env->regs[0] = do_syscall(env,
943 n,
944 env->regs[0],
945 env->regs[1],
946 env->regs[2],
947 env->regs[3],
948 env->regs[4],
5945cfcb
PM		 949 env->regs[5],
950 0, 0);
d2fbca94
GX		 951 }
952 } else {
953 goto error;
954 }
955 }
956 break;
d48813dd
GX		 957 case UC32_EXCP_DTRAP:
958 case UC32_EXCP_ITRAP:
d2fbca94
GX		 959 info.si_signo = SIGSEGV;
960 info.si_errno = 0;
961 /* XXX: check env->error_code */
962 info.si_code = TARGET_SEGV_MAPERR;
963 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
964 queue_signal(env, info.si_signo, &info);
965 break;
966 case EXCP_INTERRUPT:
967 /* just indicate that signals should be handled asap */
968 break;
969 case EXCP_DEBUG:
970 {
971 int sig;
972
973 sig = gdb_handlesig(env, TARGET_SIGTRAP);
974 if (sig) {
975 info.si_signo = sig;
976 info.si_errno = 0;
977 info.si_code = TARGET_TRAP_BRKPT;
978 queue_signal(env, info.si_signo, &info);
979 }
980 }
981 break;
982 default:
983 goto error;
984 }
985 process_pending_signals(env);
986 }
987
988error:
989 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
990 cpu_dump_state(env, stderr, fprintf, 0);
991 abort();
992}
993#endif
994
93ac68bc 995#ifdef TARGET_SPARC
ed23fbd9 996#define SPARC64_STACK_BIAS 2047
93ac68bc 997
060366c5
FB		 998//#define DEBUG_WIN
999
2623cbaf
FB		 1000/* WARNING: dealing with register windows _is_ complicated. More info
1001 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1002static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1003{
1a14026e 1004 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1005 /* wrap handling : if cwp is on the last window, then we use the
1006 registers 'after' the end */
1a14026e
BS		 1007 if (index < 8 && env->cwp == env->nwindows - 1)
1008 index += 16 * env->nwindows;
060366c5
FB		 1009 return index;
1010}
1011
2623cbaf
FB		 1012/* save the register window 'cwp1' */
1013static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1014{
2623cbaf 1015 unsigned int i;
992f48a0 1016 abi_ulong sp_ptr;
3b46e624 1017
53a5960a 1018 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1019#ifdef TARGET_SPARC64
1020 if (sp_ptr & 3)
1021 sp_ptr += SPARC64_STACK_BIAS;
1022#endif
060366c5 1023#if defined(DEBUG_WIN)
2daf0284
BS		 1024 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1025 sp_ptr, cwp1);
060366c5 1026#endif
2623cbaf 1027 for(i = 0; i < 16; i++) {
2f619698
FB		 1028 /* FIXME - what to do if put_user() fails? */
1029 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1030 sp_ptr += sizeof(abi_ulong);
2623cbaf 1031 }
060366c5
FB		 1032}
1033
1034static void save_window(CPUSPARCState *env)
1035{
5ef54116 1036#ifndef TARGET_SPARC64
2623cbaf 1037 unsigned int new_wim;
1a14026e
BS		 1038 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1039 ((1LL << env->nwindows) - 1);
1040 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1041 env->wim = new_wim;
5ef54116 1042#else
1a14026e 1043 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1044 env->cansave++;
1045 env->canrestore--;
1046#endif
060366c5
FB		 1047}
1048
1049static void restore_window(CPUSPARCState *env)
1050{
eda52953
BS		 1051#ifndef TARGET_SPARC64
1052 unsigned int new_wim;
1053#endif
1054 unsigned int i, cwp1;
992f48a0 1055 abi_ulong sp_ptr;
3b46e624 1056
eda52953 1057#ifndef TARGET_SPARC64
1a14026e
BS		 1058 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1059 ((1LL << env->nwindows) - 1);
eda52953 1060#endif
3b46e624 1061
060366c5 1062 /* restore the invalid window */
1a14026e 1063 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1064 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1065#ifdef TARGET_SPARC64
1066 if (sp_ptr & 3)
1067 sp_ptr += SPARC64_STACK_BIAS;
1068#endif
060366c5 1069#if defined(DEBUG_WIN)
2daf0284
BS		 1070 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1071 sp_ptr, cwp1);
060366c5 1072#endif
2623cbaf 1073 for(i = 0; i < 16; i++) {
2f619698
FB		 1074 /* FIXME - what to do if get_user() fails? */
1075 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1076 sp_ptr += sizeof(abi_ulong);
2623cbaf 1077 }
5ef54116
FB		 1078#ifdef TARGET_SPARC64
1079 env->canrestore++;
1a14026e
BS		 1080 if (env->cleanwin < env->nwindows - 1)
1081 env->cleanwin++;
5ef54116 1082 env->cansave--;
eda52953
BS		 1083#else
1084 env->wim = new_wim;
5ef54116 1085#endif
060366c5
FB		 1086}
1087
1088static void flush_windows(CPUSPARCState *env)
1089{
1090 int offset, cwp1;
2623cbaf
FB		 1091
1092 offset = 1;
060366c5
FB		 1093 for(;;) {
1094 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1095 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1096#ifndef TARGET_SPARC64
060366c5
FB		 1097 if (env->wim & (1 << cwp1))
1098 break;
eda52953
BS		 1099#else
1100 if (env->canrestore == 0)
1101 break;
1102 env->cansave++;
1103 env->canrestore--;
1104#endif
2623cbaf 1105 save_window_offset(env, cwp1);
060366c5
FB		 1106 offset++;
1107 }
1a14026e 1108 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1109#ifndef TARGET_SPARC64
1110 /* set wim so that restore will reload the registers */
2623cbaf 1111 env->wim = 1 << cwp1;
eda52953 1112#endif
2623cbaf
FB		 1113#if defined(DEBUG_WIN)
1114 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1115#endif
2623cbaf 1116}
060366c5 1117
93ac68bc
FB		 1118void cpu_loop (CPUSPARCState *env)
1119{
2cc20260
RH		 1120 int trapnr;
1121 abi_long ret;
c227f099 1122 target_siginfo_t info;
3b46e624 1123
060366c5
FB		 1124 while (1) {
1125 trapnr = cpu_sparc_exec (env);
3b46e624 1126
20132b96
RH		 1127 /* Compute PSR before exposing state. */
1128 if (env->cc_op != CC_OP_FLAGS) {
1129 cpu_get_psr(env);
1130 }
1131
060366c5 1132 switch (trapnr) {
5ef54116 1133#ifndef TARGET_SPARC64
5fafdf24 1134 case 0x88:
060366c5 1135 case 0x90:
5ef54116 1136#else
cb33da57 1137 case 0x110:
5ef54116
FB		 1138 case 0x16d:
1139#endif
060366c5 1140 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1141 env->regwptr[0], env->regwptr[1],
1142 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1143 env->regwptr[4], env->regwptr[5],
1144 0, 0);
2cc20260 1145 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1146#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1147 env->xcc |= PSR_CARRY;
1148#else
060366c5 1149 env->psr |= PSR_CARRY;
27908725 1150#endif
060366c5
FB		 1151 ret = -ret;
1152 } else {
992f48a0 1153#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1154 env->xcc &= ~PSR_CARRY;
1155#else
060366c5 1156 env->psr &= ~PSR_CARRY;
27908725 1157#endif
060366c5
FB		 1158 }
1159 env->regwptr[0] = ret;
1160 /* next instruction */
1161 env->pc = env->npc;
1162 env->npc = env->npc + 4;
1163 break;
1164 case 0x83: /* flush windows */
992f48a0
BS		 1165#ifdef TARGET_ABI32
1166 case 0x103:
1167#endif
2623cbaf 1168 flush_windows(env);
060366c5
FB		 1169 /* next instruction */
1170 env->pc = env->npc;
1171 env->npc = env->npc + 4;
1172 break;
3475187d 1173#ifndef TARGET_SPARC64
060366c5
FB		 1174 case TT_WIN_OVF: /* window overflow */
1175 save_window(env);
1176 break;
1177 case TT_WIN_UNF: /* window underflow */
1178 restore_window(env);
1179 break;
61ff6f58
FB		 1180 case TT_TFAULT:
1181 case TT_DFAULT:
1182 {
59f7182f 1183 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1184 info.si_errno = 0;
1185 /* XXX: check env->error_code */
1186 info.si_code = TARGET_SEGV_MAPERR;
1187 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1188 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1189 }
1190 break;
3475187d 1191#else
5ef54116
FB		 1192 case TT_SPILL: /* window overflow */
1193 save_window(env);
1194 break;
1195 case TT_FILL: /* window underflow */
1196 restore_window(env);
1197 break;
7f84a729
BS		 1198 case TT_TFAULT:
1199 case TT_DFAULT:
1200 {
59f7182f 1201 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1202 info.si_errno = 0;
1203 /* XXX: check env->error_code */
1204 info.si_code = TARGET_SEGV_MAPERR;
1205 if (trapnr == TT_DFAULT)
1206 info._sifields._sigfault._addr = env->dmmuregs[4];
1207 else
8194f35a 1208 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1209 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1210 }
1211 break;
27524dc3 1212#ifndef TARGET_ABI32
5bfb56b2
BS		 1213 case 0x16e:
1214 flush_windows(env);
1215 sparc64_get_context(env);
1216 break;
1217 case 0x16f:
1218 flush_windows(env);
1219 sparc64_set_context(env);
1220 break;
27524dc3 1221#endif
3475187d 1222#endif
48dc41eb
FB		 1223 case EXCP_INTERRUPT:
1224 /* just indicate that signals should be handled asap */
1225 break;
75f22e4e
RH		 1226 case TT_ILL_INSN:
1227 {
1228 info.si_signo = TARGET_SIGILL;
1229 info.si_errno = 0;
1230 info.si_code = TARGET_ILL_ILLOPC;
1231 info._sifields._sigfault._addr = env->pc;
1232 queue_signal(env, info.si_signo, &info);
1233 }
1234 break;
1fddef4b
FB		 1235 case EXCP_DEBUG:
1236 {
1237 int sig;
1238
1239 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1240 if (sig)
1241 {
1242 info.si_signo = sig;
1243 info.si_errno = 0;
1244 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1245 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1246 }
1247 }
1248 break;
060366c5
FB		 1249 default:
1250 printf ("Unhandled trap: 0x%x\n", trapnr);
7fe48483 1251 cpu_dump_state(env, stderr, fprintf, 0);
060366c5
FB		 1252 exit (1);
1253 }
1254 process_pending_signals (env);
1255 }
93ac68bc
FB		 1256}
1257
1258#endif
1259
67867308 1260#ifdef TARGET_PPC
05390248 1261static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1262{
1263 /* TO FIX */
1264 return 0;
1265}
3b46e624 1266
05390248 1267uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1268{
e3ea6529 1269 return cpu_ppc_get_tb(env);
9fddaa0c 1270}
3b46e624 1271
05390248 1272uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1273{
1274 return cpu_ppc_get_tb(env) >> 32;
1275}
3b46e624 1276
05390248 1277uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1278{
b711de95 1279 return cpu_ppc_get_tb(env);
9fddaa0c 1280}
5fafdf24 1281
05390248 1282uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1283{
a062e36c 1284 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1285}
76a66253 1286
05390248 1287uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1288__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1289
05390248 1290uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1291{
76a66253 1292 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1293}
76a66253 1294
a750fc0b 1295/* XXX: to be fixed */
73b01960 1296int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1297{
1298 return -1;
1299}
1300
73b01960 1301int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1302{
1303 return -1;
1304}
1305
001faf32
BS		 1306#define EXCP_DUMP(env, fmt, ...) \
1307do { \
1308 fprintf(stderr, fmt , ## __VA_ARGS__); \
1309 cpu_dump_state(env, stderr, fprintf, 0); \
1310 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1311 if (qemu_log_enabled()) { \
430c7ec7 1312 log_cpu_state(env, 0); \
eeacee4d 1313 } \
e1833e1f
JM		 1314} while (0)
1315
56f066bb
NF		 1316static int do_store_exclusive(CPUPPCState *env)
1317{
1318 target_ulong addr;
1319 target_ulong page_addr;
1320 target_ulong val;
1321 int flags;
1322 int segv = 0;
1323
1324 addr = env->reserve_ea;
1325 page_addr = addr & TARGET_PAGE_MASK;
1326 start_exclusive();
1327 mmap_lock();
1328 flags = page_get_flags(page_addr);
1329 if ((flags & PAGE_READ) == 0) {
1330 segv = 1;
1331 } else {
1332 int reg = env->reserve_info & 0x1f;
1333 int size = (env->reserve_info >> 5) & 0xf;
1334 int stored = 0;
1335
1336 if (addr == env->reserve_addr) {
1337 switch (size) {
1338 case 1: segv = get_user_u8(val, addr); break;
1339 case 2: segv = get_user_u16(val, addr); break;
1340 case 4: segv = get_user_u32(val, addr); break;
1341#if defined(TARGET_PPC64)
1342 case 8: segv = get_user_u64(val, addr); break;
1343#endif
1344 default: abort();
1345 }
1346 if (!segv && val == env->reserve_val) {
1347 val = env->gpr[reg];
1348 switch (size) {
1349 case 1: segv = put_user_u8(val, addr); break;
1350 case 2: segv = put_user_u16(val, addr); break;
1351 case 4: segv = put_user_u32(val, addr); break;
1352#if defined(TARGET_PPC64)
1353 case 8: segv = put_user_u64(val, addr); break;
1354#endif
1355 default: abort();
1356 }
1357 if (!segv) {
1358 stored = 1;
1359 }
1360 }
1361 }
1362 env->crf[0] = (stored << 1) | xer_so;
1363 env->reserve_addr = (target_ulong)-1;
1364 }
1365 if (!segv) {
1366 env->nip += 4;
1367 }
1368 mmap_unlock();
1369 end_exclusive();
1370 return segv;
1371}
1372
67867308
FB		 1373void cpu_loop(CPUPPCState *env)
1374{
0315c31c 1375 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1376 target_siginfo_t info;
61190b14 1377 int trapnr;
9e0e2f96 1378 target_ulong ret;
3b46e624 1379
67867308 1380 for(;;) {
0315c31c 1381 cpu_exec_start(cs);
67867308 1382 trapnr = cpu_ppc_exec(env);
0315c31c 1383 cpu_exec_end(cs);
67867308 1384 switch(trapnr) {
e1833e1f
JM		 1385 case POWERPC_EXCP_NONE:
1386 /* Just go on */
67867308 1387 break;
e1833e1f
JM		 1388 case POWERPC_EXCP_CRITICAL: /* Critical input */
1389 cpu_abort(env, "Critical interrupt while in user mode. "
1390 "Aborting\n");
61190b14 1391 break;
e1833e1f
JM		 1392 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1393 cpu_abort(env, "Machine check exception while in user mode. "
1394 "Aborting\n");
1395 break;
1396 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1397 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1398 env->spr[SPR_DAR]);
1399 /* XXX: check this. Seems bugged */
2be0071f
FB		 1400 switch (env->error_code & 0xFF000000) {
1401 case 0x40000000:
61190b14
FB		 1402 info.si_signo = TARGET_SIGSEGV;
1403 info.si_errno = 0;
1404 info.si_code = TARGET_SEGV_MAPERR;
1405 break;
2be0071f 1406 case 0x04000000:
61190b14
FB		 1407 info.si_signo = TARGET_SIGILL;
1408 info.si_errno = 0;
1409 info.si_code = TARGET_ILL_ILLADR;
1410 break;
2be0071f 1411 case 0x08000000:
61190b14
FB		 1412 info.si_signo = TARGET_SIGSEGV;
1413 info.si_errno = 0;
1414 info.si_code = TARGET_SEGV_ACCERR;
1415 break;
61190b14
FB		 1416 default:
1417 /* Let's send a regular segfault... */
e1833e1f
JM		 1418 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1419 env->error_code);
61190b14
FB		 1420 info.si_signo = TARGET_SIGSEGV;
1421 info.si_errno = 0;
1422 info.si_code = TARGET_SEGV_MAPERR;
1423 break;
1424 }
67867308 1425 info._sifields._sigfault._addr = env->nip;
624f7979 1426 queue_signal(env, info.si_signo, &info);
67867308 1427 break;
e1833e1f 1428 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1429 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1430 "\n", env->spr[SPR_SRR0]);
e1833e1f 1431 /* XXX: check this */
2be0071f
FB		 1432 switch (env->error_code & 0xFF000000) {
1433 case 0x40000000:
61190b14 1434 info.si_signo = TARGET_SIGSEGV;
67867308 1435 info.si_errno = 0;
61190b14
FB		 1436 info.si_code = TARGET_SEGV_MAPERR;
1437 break;
2be0071f
FB		 1438 case 0x10000000:
1439 case 0x08000000:
61190b14
FB		 1440 info.si_signo = TARGET_SIGSEGV;
1441 info.si_errno = 0;
1442 info.si_code = TARGET_SEGV_ACCERR;
1443 break;
1444 default:
1445 /* Let's send a regular segfault... */
e1833e1f
JM		 1446 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1447 env->error_code);
61190b14
FB		 1448 info.si_signo = TARGET_SIGSEGV;
1449 info.si_errno = 0;
1450 info.si_code = TARGET_SEGV_MAPERR;
1451 break;
1452 }
1453 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1454 queue_signal(env, info.si_signo, &info);
67867308 1455 break;
e1833e1f
JM		 1456 case POWERPC_EXCP_EXTERNAL: /* External input */
1457 cpu_abort(env, "External interrupt while in user mode. "
1458 "Aborting\n");
1459 break;
1460 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1461 EXCP_DUMP(env, "Unaligned memory access\n");
1462 /* XXX: check this */
61190b14 1463 info.si_signo = TARGET_SIGBUS;
67867308 1464 info.si_errno = 0;
61190b14
FB		 1465 info.si_code = TARGET_BUS_ADRALN;
1466 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1467 queue_signal(env, info.si_signo, &info);
67867308 1468 break;
e1833e1f
JM		 1469 case POWERPC_EXCP_PROGRAM: /* Program exception */
1470 /* XXX: check this */
61190b14 1471 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1472 case POWERPC_EXCP_FP:
1473 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1474 info.si_signo = TARGET_SIGFPE;
1475 info.si_errno = 0;
1476 switch (env->error_code & 0xF) {
e1833e1f 1477 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1478 info.si_code = TARGET_FPE_FLTOVF;
1479 break;
e1833e1f 1480 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1481 info.si_code = TARGET_FPE_FLTUND;
1482 break;
e1833e1f
JM		 1483 case POWERPC_EXCP_FP_ZX:
1484 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1485 info.si_code = TARGET_FPE_FLTDIV;
1486 break;
e1833e1f 1487 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1488 info.si_code = TARGET_FPE_FLTRES;
1489 break;
e1833e1f 1490 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1491 info.si_code = TARGET_FPE_FLTINV;
1492 break;
7c58044c 1493 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1494 case POWERPC_EXCP_FP_VXISI:
1495 case POWERPC_EXCP_FP_VXIDI:
1496 case POWERPC_EXCP_FP_VXIMZ:
1497 case POWERPC_EXCP_FP_VXVC:
1498 case POWERPC_EXCP_FP_VXSQRT:
1499 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1500 info.si_code = TARGET_FPE_FLTSUB;
1501 break;
1502 default:
e1833e1f
JM		 1503 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1504 env->error_code);
1505 break;
61190b14 1506 }
e1833e1f
JM		 1507 break;
1508 case POWERPC_EXCP_INVAL:
1509 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1510 info.si_signo = TARGET_SIGILL;
1511 info.si_errno = 0;
1512 switch (env->error_code & 0xF) {
e1833e1f 1513 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1514 info.si_code = TARGET_ILL_ILLOPC;
1515 break;
e1833e1f 1516 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1517 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1518 break;
e1833e1f 1519 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1520 info.si_code = TARGET_ILL_PRVREG;
1521 break;
e1833e1f 1522 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1523 info.si_code = TARGET_ILL_COPROC;
1524 break;
1525 default:
e1833e1f
JM		 1526 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1527 env->error_code & 0xF);
61190b14
FB		 1528 info.si_code = TARGET_ILL_ILLADR;
1529 break;
1530 }
1531 break;
e1833e1f
JM		 1532 case POWERPC_EXCP_PRIV:
1533 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1534 info.si_signo = TARGET_SIGILL;
1535 info.si_errno = 0;
1536 switch (env->error_code & 0xF) {
e1833e1f 1537 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1538 info.si_code = TARGET_ILL_PRVOPC;
1539 break;
e1833e1f 1540 case POWERPC_EXCP_PRIV_REG:
61190b14 1541 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1542 break;
61190b14 1543 default:
e1833e1f
JM		 1544 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1545 env->error_code & 0xF);
61190b14
FB		 1546 info.si_code = TARGET_ILL_PRVOPC;
1547 break;
1548 }
1549 break;
e1833e1f
JM		 1550 case POWERPC_EXCP_TRAP:
1551 cpu_abort(env, "Tried to call a TRAP\n");
1552 break;
61190b14
FB		 1553 default:
1554 /* Should not happen ! */
e1833e1f
JM		 1555 cpu_abort(env, "Unknown program exception (%02x)\n",
1556 env->error_code);
1557 break;
61190b14
FB		 1558 }
1559 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1560 queue_signal(env, info.si_signo, &info);
67867308 1561 break;
e1833e1f
JM		 1562 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1563 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1564 info.si_signo = TARGET_SIGILL;
67867308 1565 info.si_errno = 0;
61190b14
FB		 1566 info.si_code = TARGET_ILL_COPROC;
1567 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1568 queue_signal(env, info.si_signo, &info);
67867308 1569 break;
e1833e1f
JM		 1570 case POWERPC_EXCP_SYSCALL: /* System call exception */
1571 cpu_abort(env, "Syscall exception while in user mode. "
1572 "Aborting\n");
61190b14 1573 break;
e1833e1f
JM		 1574 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1575 EXCP_DUMP(env, "No APU instruction allowed\n");
1576 info.si_signo = TARGET_SIGILL;
1577 info.si_errno = 0;
1578 info.si_code = TARGET_ILL_COPROC;
1579 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1580 queue_signal(env, info.si_signo, &info);
61190b14 1581 break;
e1833e1f
JM		 1582 case POWERPC_EXCP_DECR: /* Decrementer exception */
1583 cpu_abort(env, "Decrementer interrupt while in user mode. "
1584 "Aborting\n");
61190b14 1585 break;
e1833e1f
JM		 1586 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1587 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1588 "Aborting\n");
1589 break;
1590 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1591 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1592 "Aborting\n");
1593 break;
1594 case POWERPC_EXCP_DTLB: /* Data TLB error */
1595 cpu_abort(env, "Data TLB exception while in user mode. "
1596 "Aborting\n");
1597 break;
1598 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1599 cpu_abort(env, "Instruction TLB exception while in user mode. "
1600 "Aborting\n");
1601 break;
e1833e1f
JM		 1602 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1603 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1604 info.si_signo = TARGET_SIGILL;
1605 info.si_errno = 0;
1606 info.si_code = TARGET_ILL_COPROC;
1607 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1608 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1609 break;
1610 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1611 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1612 break;
1613 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1614 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1615 break;
1616 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1617 cpu_abort(env, "Performance monitor exception not handled\n");
1618 break;
1619 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1620 cpu_abort(env, "Doorbell interrupt while in user mode. "
1621 "Aborting\n");
1622 break;
1623 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1624 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1625 "Aborting\n");
1626 break;
1627 case POWERPC_EXCP_RESET: /* System reset exception */
1628 cpu_abort(env, "Reset interrupt while in user mode. "
1629 "Aborting\n");
1630 break;
e1833e1f
JM		 1631 case POWERPC_EXCP_DSEG: /* Data segment exception */
1632 cpu_abort(env, "Data segment exception while in user mode. "
1633 "Aborting\n");
1634 break;
1635 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1636 cpu_abort(env, "Instruction segment exception "
1637 "while in user mode. Aborting\n");
1638 break;
e85e7c6e 1639 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1640 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1641 cpu_abort(env, "Hypervisor decrementer interrupt "
1642 "while in user mode. Aborting\n");
1643 break;
e1833e1f
JM		 1644 case POWERPC_EXCP_TRACE: /* Trace exception */
1645 /* Nothing to do:
1646 * we use this exception to emulate step-by-step execution mode.
1647 */
1648 break;
e85e7c6e 1649 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1650 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1651 cpu_abort(env, "Hypervisor data storage exception "
1652 "while in user mode. Aborting\n");
1653 break;
1654 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1655 cpu_abort(env, "Hypervisor instruction storage exception "
1656 "while in user mode. Aborting\n");
1657 break;
1658 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1659 cpu_abort(env, "Hypervisor data segment exception "
1660 "while in user mode. Aborting\n");
1661 break;
1662 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1663 cpu_abort(env, "Hypervisor instruction segment exception "
1664 "while in user mode. Aborting\n");
1665 break;
e1833e1f
JM		 1666 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1667 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1668 info.si_signo = TARGET_SIGILL;
1669 info.si_errno = 0;
1670 info.si_code = TARGET_ILL_COPROC;
1671 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1672 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1673 break;
1674 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1675 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1676 "while in user mode. Aborting\n");
1677 break;
1678 case POWERPC_EXCP_IO: /* IO error exception */
1679 cpu_abort(env, "IO error exception while in user mode. "
1680 "Aborting\n");
1681 break;
1682 case POWERPC_EXCP_RUNM: /* Run mode exception */
1683 cpu_abort(env, "Run mode exception while in user mode. "
1684 "Aborting\n");
1685 break;
1686 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1687 cpu_abort(env, "Emulation trap exception not handled\n");
1688 break;
1689 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1690 cpu_abort(env, "Instruction fetch TLB exception "
1691 "while in user-mode. Aborting");
1692 break;
1693 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1694 cpu_abort(env, "Data load TLB exception while in user-mode. "
1695 "Aborting");
1696 break;
1697 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1698 cpu_abort(env, "Data store TLB exception while in user-mode. "
1699 "Aborting");
1700 break;
1701 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1702 cpu_abort(env, "Floating-point assist exception not handled\n");
1703 break;
1704 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1705 cpu_abort(env, "Instruction address breakpoint exception "
1706 "not handled\n");
1707 break;
1708 case POWERPC_EXCP_SMI: /* System management interrupt */
1709 cpu_abort(env, "System management interrupt while in user mode. "
1710 "Aborting\n");
1711 break;
1712 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1713 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1714 "Aborting\n");
1715 break;
1716 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1717 cpu_abort(env, "Performance monitor exception not handled\n");
1718 break;
1719 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1720 cpu_abort(env, "Vector assist exception not handled\n");
1721 break;
1722 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1723 cpu_abort(env, "Soft patch exception not handled\n");
1724 break;
1725 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1726 cpu_abort(env, "Maintenance exception while in user mode. "
1727 "Aborting\n");
1728 break;
1729 case POWERPC_EXCP_STOP: /* stop translation */
1730 /* We did invalidate the instruction cache. Go on */
1731 break;
1732 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1733 /* We just stopped because of a branch. Go on */
1734 break;
1735 case POWERPC_EXCP_SYSCALL_USER:
1736 /* system call in user-mode emulation */
1737 /* WARNING:
1738 * PPC ABI uses overflow flag in cr0 to signal an error
1739 * in syscalls.
1740 */
e1833e1f
JM		 1741 env->crf[0] &= ~0x1;
1742 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1743 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1744 env->gpr[8], 0, 0);
9e0e2f96 1745 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1746 /* Returning from a successful sigreturn syscall.
1747 Avoid corrupting register state. */
1748 break;
1749 }
9e0e2f96 1750 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1751 env->crf[0] |= 0x1;
1752 ret = -ret;
61190b14 1753 }
e1833e1f 1754 env->gpr[3] = ret;
e1833e1f 1755 break;
56f066bb
NF		 1756 case POWERPC_EXCP_STCX:
1757 if (do_store_exclusive(env)) {
1758 info.si_signo = TARGET_SIGSEGV;
1759 info.si_errno = 0;
1760 info.si_code = TARGET_SEGV_MAPERR;
1761 info._sifields._sigfault._addr = env->nip;
1762 queue_signal(env, info.si_signo, &info);
1763 }
1764 break;
71f75756
AJ		 1765 case EXCP_DEBUG:
1766 {
1767 int sig;
1768
1769 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1770 if (sig) {
1771 info.si_signo = sig;
1772 info.si_errno = 0;
1773 info.si_code = TARGET_TRAP_BRKPT;
1774 queue_signal(env, info.si_signo, &info);
1775 }
1776 }
1777 break;
56ba31ff
JM		 1778 case EXCP_INTERRUPT:
1779 /* just indicate that signals should be handled asap */
1780 break;
e1833e1f
JM		 1781 default:
1782 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1783 break;
67867308
FB		 1784 }
1785 process_pending_signals(env);
1786 }
1787}
1788#endif
1789
048f6b4d
FB		 1790#ifdef TARGET_MIPS
1791
1792#define MIPS_SYS(name, args) args,
1793
1794static const uint8_t mips_syscall_args[] = {
29fb0f25 1795 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1796 MIPS_SYS(sys_exit , 1)
1797 MIPS_SYS(sys_fork , 0)
1798 MIPS_SYS(sys_read , 3)
1799 MIPS_SYS(sys_write , 3)
1800 MIPS_SYS(sys_open , 3) /* 4005 */
1801 MIPS_SYS(sys_close , 1)
1802 MIPS_SYS(sys_waitpid , 3)
1803 MIPS_SYS(sys_creat , 2)
1804 MIPS_SYS(sys_link , 2)
1805 MIPS_SYS(sys_unlink , 1) /* 4010 */
1806 MIPS_SYS(sys_execve , 0)
1807 MIPS_SYS(sys_chdir , 1)
1808 MIPS_SYS(sys_time , 1)
1809 MIPS_SYS(sys_mknod , 3)
1810 MIPS_SYS(sys_chmod , 2) /* 4015 */
1811 MIPS_SYS(sys_lchown , 3)
1812 MIPS_SYS(sys_ni_syscall , 0)
1813 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1814 MIPS_SYS(sys_lseek , 3)
1815 MIPS_SYS(sys_getpid , 0) /* 4020 */
1816 MIPS_SYS(sys_mount , 5)
1817 MIPS_SYS(sys_oldumount , 1)
1818 MIPS_SYS(sys_setuid , 1)
1819 MIPS_SYS(sys_getuid , 0)
1820 MIPS_SYS(sys_stime , 1) /* 4025 */
1821 MIPS_SYS(sys_ptrace , 4)
1822 MIPS_SYS(sys_alarm , 1)
1823 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1824 MIPS_SYS(sys_pause , 0)
1825 MIPS_SYS(sys_utime , 2) /* 4030 */
1826 MIPS_SYS(sys_ni_syscall , 0)
1827 MIPS_SYS(sys_ni_syscall , 0)
1828 MIPS_SYS(sys_access , 2)
1829 MIPS_SYS(sys_nice , 1)
1830 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1831 MIPS_SYS(sys_sync , 0)
1832 MIPS_SYS(sys_kill , 2)
1833 MIPS_SYS(sys_rename , 2)
1834 MIPS_SYS(sys_mkdir , 2)
1835 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1836 MIPS_SYS(sys_dup , 1)
1837 MIPS_SYS(sys_pipe , 0)
1838 MIPS_SYS(sys_times , 1)
1839 MIPS_SYS(sys_ni_syscall , 0)
1840 MIPS_SYS(sys_brk , 1) /* 4045 */
1841 MIPS_SYS(sys_setgid , 1)
1842 MIPS_SYS(sys_getgid , 0)
1843 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1844 MIPS_SYS(sys_geteuid , 0)
1845 MIPS_SYS(sys_getegid , 0) /* 4050 */
1846 MIPS_SYS(sys_acct , 0)
1847 MIPS_SYS(sys_umount , 2)
1848 MIPS_SYS(sys_ni_syscall , 0)
1849 MIPS_SYS(sys_ioctl , 3)
1850 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1851 MIPS_SYS(sys_ni_syscall , 2)
1852 MIPS_SYS(sys_setpgid , 2)
1853 MIPS_SYS(sys_ni_syscall , 0)
1854 MIPS_SYS(sys_olduname , 1)
1855 MIPS_SYS(sys_umask , 1) /* 4060 */
1856 MIPS_SYS(sys_chroot , 1)
1857 MIPS_SYS(sys_ustat , 2)
1858 MIPS_SYS(sys_dup2 , 2)
1859 MIPS_SYS(sys_getppid , 0)
1860 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1861 MIPS_SYS(sys_setsid , 0)
1862 MIPS_SYS(sys_sigaction , 3)
1863 MIPS_SYS(sys_sgetmask , 0)
1864 MIPS_SYS(sys_ssetmask , 1)
1865 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1866 MIPS_SYS(sys_setregid , 2)
1867 MIPS_SYS(sys_sigsuspend , 0)
1868 MIPS_SYS(sys_sigpending , 1)
1869 MIPS_SYS(sys_sethostname , 2)
1870 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1871 MIPS_SYS(sys_getrlimit , 2)
1872 MIPS_SYS(sys_getrusage , 2)
1873 MIPS_SYS(sys_gettimeofday, 2)
1874 MIPS_SYS(sys_settimeofday, 2)
1875 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1876 MIPS_SYS(sys_setgroups , 2)
1877 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1878 MIPS_SYS(sys_symlink , 2)
1879 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1880 MIPS_SYS(sys_readlink , 3) /* 4085 */
1881 MIPS_SYS(sys_uselib , 1)
1882 MIPS_SYS(sys_swapon , 2)
1883 MIPS_SYS(sys_reboot , 3)
1884 MIPS_SYS(old_readdir , 3)
1885 MIPS_SYS(old_mmap , 6) /* 4090 */
1886 MIPS_SYS(sys_munmap , 2)
1887 MIPS_SYS(sys_truncate , 2)
1888 MIPS_SYS(sys_ftruncate , 2)
1889 MIPS_SYS(sys_fchmod , 2)
1890 MIPS_SYS(sys_fchown , 3) /* 4095 */
1891 MIPS_SYS(sys_getpriority , 2)
1892 MIPS_SYS(sys_setpriority , 3)
1893 MIPS_SYS(sys_ni_syscall , 0)
1894 MIPS_SYS(sys_statfs , 2)
1895 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1896 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1897 MIPS_SYS(sys_socketcall , 2)
1898 MIPS_SYS(sys_syslog , 3)
1899 MIPS_SYS(sys_setitimer , 3)
1900 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1901 MIPS_SYS(sys_newstat , 2)
1902 MIPS_SYS(sys_newlstat , 2)
1903 MIPS_SYS(sys_newfstat , 2)
1904 MIPS_SYS(sys_uname , 1)
1905 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1906 MIPS_SYS(sys_vhangup , 0)
1907 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1908 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1909 MIPS_SYS(sys_wait4 , 4)
1910 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1911 MIPS_SYS(sys_sysinfo , 1)
1912 MIPS_SYS(sys_ipc , 6)
1913 MIPS_SYS(sys_fsync , 1)
1914 MIPS_SYS(sys_sigreturn , 0)
18113962 1915 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1916 MIPS_SYS(sys_setdomainname, 2)
1917 MIPS_SYS(sys_newuname , 1)
1918 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1919 MIPS_SYS(sys_adjtimex , 1)
1920 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1921 MIPS_SYS(sys_sigprocmask , 3)
1922 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1923 MIPS_SYS(sys_init_module , 5)
1924 MIPS_SYS(sys_delete_module, 1)
1925 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1926 MIPS_SYS(sys_quotactl , 0)
1927 MIPS_SYS(sys_getpgid , 1)
1928 MIPS_SYS(sys_fchdir , 1)
1929 MIPS_SYS(sys_bdflush , 2)
1930 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1931 MIPS_SYS(sys_personality , 1)
1932 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1933 MIPS_SYS(sys_setfsuid , 1)
1934 MIPS_SYS(sys_setfsgid , 1)
1935 MIPS_SYS(sys_llseek , 5) /* 4140 */
1936 MIPS_SYS(sys_getdents , 3)
1937 MIPS_SYS(sys_select , 5)
1938 MIPS_SYS(sys_flock , 2)
1939 MIPS_SYS(sys_msync , 3)
1940 MIPS_SYS(sys_readv , 3) /* 4145 */
1941 MIPS_SYS(sys_writev , 3)
1942 MIPS_SYS(sys_cacheflush , 3)
1943 MIPS_SYS(sys_cachectl , 3)
1944 MIPS_SYS(sys_sysmips , 4)
1945 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1946 MIPS_SYS(sys_getsid , 1)
1947 MIPS_SYS(sys_fdatasync , 0)
1948 MIPS_SYS(sys_sysctl , 1)
1949 MIPS_SYS(sys_mlock , 2)
1950 MIPS_SYS(sys_munlock , 2) /* 4155 */
1951 MIPS_SYS(sys_mlockall , 1)
1952 MIPS_SYS(sys_munlockall , 0)
1953 MIPS_SYS(sys_sched_setparam, 2)
1954 MIPS_SYS(sys_sched_getparam, 2)
1955 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1956 MIPS_SYS(sys_sched_getscheduler, 1)
1957 MIPS_SYS(sys_sched_yield , 0)
1958 MIPS_SYS(sys_sched_get_priority_max, 1)
1959 MIPS_SYS(sys_sched_get_priority_min, 1)
1960 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1961 MIPS_SYS(sys_nanosleep, 2)
1962 MIPS_SYS(sys_mremap , 4)
1963 MIPS_SYS(sys_accept , 3)
1964 MIPS_SYS(sys_bind , 3)
1965 MIPS_SYS(sys_connect , 3) /* 4170 */
1966 MIPS_SYS(sys_getpeername , 3)
1967 MIPS_SYS(sys_getsockname , 3)
1968 MIPS_SYS(sys_getsockopt , 5)
1969 MIPS_SYS(sys_listen , 2)
1970 MIPS_SYS(sys_recv , 4) /* 4175 */
1971 MIPS_SYS(sys_recvfrom , 6)
1972 MIPS_SYS(sys_recvmsg , 3)
1973 MIPS_SYS(sys_send , 4)
1974 MIPS_SYS(sys_sendmsg , 3)
1975 MIPS_SYS(sys_sendto , 6) /* 4180 */
1976 MIPS_SYS(sys_setsockopt , 5)
1977 MIPS_SYS(sys_shutdown , 2)
1978 MIPS_SYS(sys_socket , 3)
1979 MIPS_SYS(sys_socketpair , 4)
1980 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1981 MIPS_SYS(sys_getresuid , 3)
1982 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1983 MIPS_SYS(sys_poll , 3)
1984 MIPS_SYS(sys_nfsservctl , 3)
1985 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1986 MIPS_SYS(sys_getresgid , 3)
1987 MIPS_SYS(sys_prctl , 5)
1988 MIPS_SYS(sys_rt_sigreturn, 0)
1989 MIPS_SYS(sys_rt_sigaction, 4)
1990 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1991 MIPS_SYS(sys_rt_sigpending, 2)
1992 MIPS_SYS(sys_rt_sigtimedwait, 4)
1993 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1994 MIPS_SYS(sys_rt_sigsuspend, 0)
1995 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1996 MIPS_SYS(sys_pwrite64 , 6)
1997 MIPS_SYS(sys_chown , 3)
1998 MIPS_SYS(sys_getcwd , 2)
1999 MIPS_SYS(sys_capget , 2)
2000 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2001 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2002 MIPS_SYS(sys_sendfile , 4)
2003 MIPS_SYS(sys_ni_syscall , 0)
2004 MIPS_SYS(sys_ni_syscall , 0)
2005 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2006 MIPS_SYS(sys_truncate64 , 4)
2007 MIPS_SYS(sys_ftruncate64 , 4)
2008 MIPS_SYS(sys_stat64 , 2)
2009 MIPS_SYS(sys_lstat64 , 2)
2010 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2011 MIPS_SYS(sys_pivot_root , 2)
2012 MIPS_SYS(sys_mincore , 3)
2013 MIPS_SYS(sys_madvise , 3)
2014 MIPS_SYS(sys_getdents64 , 3)
2015 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2016 MIPS_SYS(sys_ni_syscall , 0)
2017 MIPS_SYS(sys_gettid , 0)
2018 MIPS_SYS(sys_readahead , 5)
2019 MIPS_SYS(sys_setxattr , 5)
2020 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2021 MIPS_SYS(sys_fsetxattr , 5)
2022 MIPS_SYS(sys_getxattr , 4)
2023 MIPS_SYS(sys_lgetxattr , 4)
2024 MIPS_SYS(sys_fgetxattr , 4)
2025 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2026 MIPS_SYS(sys_llistxattr , 3)
2027 MIPS_SYS(sys_flistxattr , 3)
2028 MIPS_SYS(sys_removexattr , 2)
2029 MIPS_SYS(sys_lremovexattr, 2)
2030 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2031 MIPS_SYS(sys_tkill , 2)
2032 MIPS_SYS(sys_sendfile64 , 5)
2033 MIPS_SYS(sys_futex , 2)
2034 MIPS_SYS(sys_sched_setaffinity, 3)
2035 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2036 MIPS_SYS(sys_io_setup , 2)
2037 MIPS_SYS(sys_io_destroy , 1)
2038 MIPS_SYS(sys_io_getevents, 5)
2039 MIPS_SYS(sys_io_submit , 3)
2040 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2041 MIPS_SYS(sys_exit_group , 1)
2042 MIPS_SYS(sys_lookup_dcookie, 3)
2043 MIPS_SYS(sys_epoll_create, 1)
2044 MIPS_SYS(sys_epoll_ctl , 4)
2045 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2046 MIPS_SYS(sys_remap_file_pages, 5)
2047 MIPS_SYS(sys_set_tid_address, 1)
2048 MIPS_SYS(sys_restart_syscall, 0)
2049 MIPS_SYS(sys_fadvise64_64, 7)
2050 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2051 MIPS_SYS(sys_fstatfs64 , 2)
2052 MIPS_SYS(sys_timer_create, 3)
2053 MIPS_SYS(sys_timer_settime, 4)
2054 MIPS_SYS(sys_timer_gettime, 2)
2055 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2056 MIPS_SYS(sys_timer_delete, 1)
2057 MIPS_SYS(sys_clock_settime, 2)
2058 MIPS_SYS(sys_clock_gettime, 2)
2059 MIPS_SYS(sys_clock_getres, 2)
2060 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2061 MIPS_SYS(sys_tgkill , 3)
2062 MIPS_SYS(sys_utimes , 2)
2063 MIPS_SYS(sys_mbind , 4)
2064 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2065 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2066 MIPS_SYS(sys_mq_open , 4)
2067 MIPS_SYS(sys_mq_unlink , 1)
2068 MIPS_SYS(sys_mq_timedsend, 5)
2069 MIPS_SYS(sys_mq_timedreceive, 5)
2070 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2071 MIPS_SYS(sys_mq_getsetattr, 3)
2072 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2073 MIPS_SYS(sys_waitid , 4)
2074 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2075 MIPS_SYS(sys_add_key , 5)
388bb21a 2076 MIPS_SYS(sys_request_key, 4)
048f6b4d 2077 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2078 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2079 MIPS_SYS(sys_inotify_init, 0)
2080 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2081 MIPS_SYS(sys_inotify_rm_watch, 2)
2082 MIPS_SYS(sys_migrate_pages, 4)
2083 MIPS_SYS(sys_openat, 4)
2084 MIPS_SYS(sys_mkdirat, 3)
2085 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2086 MIPS_SYS(sys_fchownat, 5)
2087 MIPS_SYS(sys_futimesat, 3)
2088 MIPS_SYS(sys_fstatat64, 4)
2089 MIPS_SYS(sys_unlinkat, 3)
2090 MIPS_SYS(sys_renameat, 4) /* 4295 */
2091 MIPS_SYS(sys_linkat, 5)
2092 MIPS_SYS(sys_symlinkat, 3)
2093 MIPS_SYS(sys_readlinkat, 4)
2094 MIPS_SYS(sys_fchmodat, 3)
2095 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2096 MIPS_SYS(sys_pselect6, 6)
2097 MIPS_SYS(sys_ppoll, 5)
2098 MIPS_SYS(sys_unshare, 1)
2099 MIPS_SYS(sys_splice, 4)
2100 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2101 MIPS_SYS(sys_tee, 4)
2102 MIPS_SYS(sys_vmsplice, 4)
2103 MIPS_SYS(sys_move_pages, 6)
2104 MIPS_SYS(sys_set_robust_list, 2)
2105 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2106 MIPS_SYS(sys_kexec_load, 4)
2107 MIPS_SYS(sys_getcpu, 3)
2108 MIPS_SYS(sys_epoll_pwait, 6)
2109 MIPS_SYS(sys_ioprio_set, 3)
2110 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2111 MIPS_SYS(sys_utimensat, 4)
2112 MIPS_SYS(sys_signalfd, 3)
2113 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2114 MIPS_SYS(sys_eventfd, 1)
2115 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2116 MIPS_SYS(sys_timerfd_create, 2)
2117 MIPS_SYS(sys_timerfd_gettime, 2)
2118 MIPS_SYS(sys_timerfd_settime, 4)
2119 MIPS_SYS(sys_signalfd4, 4)
2120 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2121 MIPS_SYS(sys_epoll_create1, 1)
2122 MIPS_SYS(sys_dup3, 3)
2123 MIPS_SYS(sys_pipe2, 2)
2124 MIPS_SYS(sys_inotify_init1, 1)
2125 MIPS_SYS(sys_preadv, 6) /* 4330 */
2126 MIPS_SYS(sys_pwritev, 6)
2127 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2128 MIPS_SYS(sys_perf_event_open, 5)
2129 MIPS_SYS(sys_accept4, 4)
2130 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2131 MIPS_SYS(sys_fanotify_init, 2)
2132 MIPS_SYS(sys_fanotify_mark, 6)
2133 MIPS_SYS(sys_prlimit64, 4)
2134 MIPS_SYS(sys_name_to_handle_at, 5)
2135 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2136 MIPS_SYS(sys_clock_adjtime, 2)
2137 MIPS_SYS(sys_syncfs, 1)
048f6b4d
FB		 2138};
2139
2140#undef MIPS_SYS
2141
590bc601
PB		 2142static int do_store_exclusive(CPUMIPSState *env)
2143{
2144 target_ulong addr;
2145 target_ulong page_addr;
2146 target_ulong val;
2147 int flags;
2148 int segv = 0;
2149 int reg;
2150 int d;
2151
5499b6ff 2152 addr = env->lladdr;
590bc601
PB		 2153 page_addr = addr & TARGET_PAGE_MASK;
2154 start_exclusive();
2155 mmap_lock();
2156 flags = page_get_flags(page_addr);
2157 if ((flags & PAGE_READ) == 0) {
2158 segv = 1;
2159 } else {
2160 reg = env->llreg & 0x1f;
2161 d = (env->llreg & 0x20) != 0;
2162 if (d) {
2163 segv = get_user_s64(val, addr);
2164 } else {
2165 segv = get_user_s32(val, addr);
2166 }
2167 if (!segv) {
2168 if (val != env->llval) {
2169 env->active_tc.gpr[reg] = 0;
2170 } else {
2171 if (d) {
2172 segv = put_user_u64(env->llnewval, addr);
2173 } else {
2174 segv = put_user_u32(env->llnewval, addr);
2175 }
2176 if (!segv) {
2177 env->active_tc.gpr[reg] = 1;
2178 }
2179 }
2180 }
2181 }
5499b6ff 2182 env->lladdr = -1;
590bc601
PB		 2183 if (!segv) {
2184 env->active_tc.PC += 4;
2185 }
2186 mmap_unlock();
2187 end_exclusive();
2188 return segv;
2189}
2190
048f6b4d
FB		 2191void cpu_loop(CPUMIPSState *env)
2192{
0315c31c 2193 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2194 target_siginfo_t info;
388bb21a 2195 int trapnr, ret;
048f6b4d 2196 unsigned int syscall_num;
048f6b4d
FB		 2197
2198 for(;;) {
0315c31c 2199 cpu_exec_start(cs);
048f6b4d 2200 trapnr = cpu_mips_exec(env);
0315c31c 2201 cpu_exec_end(cs);
048f6b4d
FB		 2202 switch(trapnr) {
2203 case EXCP_SYSCALL:
b5dc7732
TS		 2204 syscall_num = env->active_tc.gpr[2] - 4000;
2205 env->active_tc.PC += 4;
388bb21a 2206 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2207 ret = -TARGET_ENOSYS;
388bb21a
TS		 2208 } else {
2209 int nb_args;
992f48a0
BS		 2210 abi_ulong sp_reg;
2211 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2212
2213 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2214 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2215 switch (nb_args) {
2216 /* these arguments are taken from the stack */
94c19610
ACH		 2217 case 8:
2218 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2219 goto done_syscall;
2220 }
2221 case 7:
2222 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2223 goto done_syscall;
2224 }
2225 case 6:
2226 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2227 goto done_syscall;
2228 }
2229 case 5:
2230 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2231 goto done_syscall;
2232 }
388bb21a
TS		 2233 default:
2234 break;
048f6b4d 2235 }
b5dc7732
TS		 2236 ret = do_syscall(env, env->active_tc.gpr[2],
2237 env->active_tc.gpr[4],
2238 env->active_tc.gpr[5],
2239 env->active_tc.gpr[6],
2240 env->active_tc.gpr[7],
5945cfcb 2241 arg5, arg6, arg7, arg8);
388bb21a 2242 }
94c19610 2243done_syscall:
0b1bcb00
PB		 2244 if (ret == -TARGET_QEMU_ESIGRETURN) {
2245 /* Returning from a successful sigreturn syscall.
2246 Avoid clobbering register state. */
2247 break;
2248 }
388bb21a 2249 if ((unsigned int)ret >= (unsigned int)(-1133)) {
b5dc7732 2250 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2251 ret = -ret;
2252 } else {
b5dc7732 2253 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2254 }
b5dc7732 2255 env->active_tc.gpr[2] = ret;
048f6b4d 2256 break;
ca7c2b1b
TS		 2257 case EXCP_TLBL:
2258 case EXCP_TLBS:
e6e5bd2d
WT		 2259 case EXCP_AdEL:
2260 case EXCP_AdES:
e4474235
PB		 2261 info.si_signo = TARGET_SIGSEGV;
2262 info.si_errno = 0;
2263 /* XXX: check env->error_code */
2264 info.si_code = TARGET_SEGV_MAPERR;
2265 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2266 queue_signal(env, info.si_signo, &info);
2267 break;
6900e84b 2268 case EXCP_CpU:
048f6b4d 2269 case EXCP_RI:
bc1ad2de
FB		 2270 info.si_signo = TARGET_SIGILL;
2271 info.si_errno = 0;
2272 info.si_code = 0;
624f7979 2273 queue_signal(env, info.si_signo, &info);
048f6b4d 2274 break;
106ec879
FB		 2275 case EXCP_INTERRUPT:
2276 /* just indicate that signals should be handled asap */
2277 break;
d08b2a28
PB		 2278 case EXCP_DEBUG:
2279 {
2280 int sig;
2281
2282 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2283 if (sig)
2284 {
2285 info.si_signo = sig;
2286 info.si_errno = 0;
2287 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2288 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2289 }
2290 }
2291 break;
590bc601
PB		 2292 case EXCP_SC:
2293 if (do_store_exclusive(env)) {
2294 info.si_signo = TARGET_SIGSEGV;
2295 info.si_errno = 0;
2296 info.si_code = TARGET_SEGV_MAPERR;
2297 info._sifields._sigfault._addr = env->active_tc.PC;
2298 queue_signal(env, info.si_signo, &info);
2299 }
2300 break;
853c3240
JL		 2301 case EXCP_DSPDIS:
2302 info.si_signo = TARGET_SIGILL;
2303 info.si_errno = 0;
2304 info.si_code = TARGET_ILL_ILLOPC;
2305 queue_signal(env, info.si_signo, &info);
2306 break;
048f6b4d
FB		 2307 default:
2308 // error:
5fafdf24 2309 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d
FB		 2310 trapnr);
2311 cpu_dump_state(env, stderr, fprintf, 0);
2312 abort();
2313 }
2314 process_pending_signals(env);
2315 }
2316}
2317#endif
2318
d962783e
JL		 2319#ifdef TARGET_OPENRISC
2320
2321void cpu_loop(CPUOpenRISCState *env)
2322{
2323 int trapnr, gdbsig;
2324
2325 for (;;) {
2326 trapnr = cpu_exec(env);
2327 gdbsig = 0;
2328
2329 switch (trapnr) {
2330 case EXCP_RESET:
2331 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2332 exit(1);
2333 break;
2334 case EXCP_BUSERR:
2335 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2336 gdbsig = SIGBUS;
2337 break;
2338 case EXCP_DPF:
2339 case EXCP_IPF:
2340 cpu_dump_state(env, stderr, fprintf, 0);
2341 gdbsig = TARGET_SIGSEGV;
2342 break;
2343 case EXCP_TICK:
2344 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2345 break;
2346 case EXCP_ALIGN:
2347 qemu_log("\nAlignment pc is %#x\n", env->pc);
2348 gdbsig = SIGBUS;
2349 break;
2350 case EXCP_ILLEGAL:
2351 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2352 gdbsig = SIGILL;
2353 break;
2354 case EXCP_INT:
2355 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2356 break;
2357 case EXCP_DTLBMISS:
2358 case EXCP_ITLBMISS:
2359 qemu_log("\nTLB miss\n");
2360 break;
2361 case EXCP_RANGE:
2362 qemu_log("\nRange\n");
2363 gdbsig = SIGSEGV;
2364 break;
2365 case EXCP_SYSCALL:
2366 env->pc += 4; /* 0xc00; */
2367 env->gpr[11] = do_syscall(env,
2368 env->gpr[11], /* return value */
2369 env->gpr[3], /* r3 - r7 are params */
2370 env->gpr[4],
2371 env->gpr[5],
2372 env->gpr[6],
2373 env->gpr[7],
2374 env->gpr[8], 0, 0);
2375 break;
2376 case EXCP_FPE:
2377 qemu_log("\nFloating point error\n");
2378 break;
2379 case EXCP_TRAP:
2380 qemu_log("\nTrap\n");
2381 gdbsig = SIGTRAP;
2382 break;
2383 case EXCP_NR:
2384 qemu_log("\nNR\n");
2385 break;
2386 default:
2387 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2388 trapnr);
2389 cpu_dump_state(env, stderr, fprintf, 0);
2390 gdbsig = TARGET_SIGILL;
2391 break;
2392 }
2393 if (gdbsig) {
2394 gdb_handlesig(env, gdbsig);
2395 if (gdbsig != TARGET_SIGTRAP) {
2396 exit(1);
2397 }
2398 }
2399
2400 process_pending_signals(env);
2401 }
2402}
2403
2404#endif /* TARGET_OPENRISC */
2405
fdf9b3e8 2406#ifdef TARGET_SH4
05390248 2407void cpu_loop(CPUSH4State *env)
fdf9b3e8
FB		 2408{
2409 int trapnr, ret;
c227f099 2410 target_siginfo_t info;
3b46e624 2411
fdf9b3e8
FB		 2412 while (1) {
2413 trapnr = cpu_sh4_exec (env);
3b46e624 2414
fdf9b3e8
FB		 2415 switch (trapnr) {
2416 case 0x160:
0b6d3ae0 2417 env->pc += 2;
5fafdf24
TS		 2418 ret = do_syscall(env,
2419 env->gregs[3],
2420 env->gregs[4],
2421 env->gregs[5],
2422 env->gregs[6],
2423 env->gregs[7],
2424 env->gregs[0],
5945cfcb
PM		 2425 env->gregs[1],
2426 0, 0);
9c2a9ea1 2427 env->gregs[0] = ret;
fdf9b3e8 2428 break;
c3b5bc8a
TS		 2429 case EXCP_INTERRUPT:
2430 /* just indicate that signals should be handled asap */
2431 break;
355fb23d
PB		 2432 case EXCP_DEBUG:
2433 {
2434 int sig;
2435
2436 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2437 if (sig)
2438 {
2439 info.si_signo = sig;
2440 info.si_errno = 0;
2441 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2442 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2443 }
2444 }
2445 break;
c3b5bc8a
TS		 2446 case 0xa0:
2447 case 0xc0:
2448 info.si_signo = SIGSEGV;
2449 info.si_errno = 0;
2450 info.si_code = TARGET_SEGV_MAPERR;
2451 info._sifields._sigfault._addr = env->tea;
624f7979 2452 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2453 break;
2454
fdf9b3e8
FB		 2455 default:
2456 printf ("Unhandled trap: 0x%x\n", trapnr);
2457 cpu_dump_state(env, stderr, fprintf, 0);
2458 exit (1);
2459 }
2460 process_pending_signals (env);
2461 }
2462}
2463#endif
2464
48733d19 2465#ifdef TARGET_CRIS
05390248 2466void cpu_loop(CPUCRISState *env)
48733d19
TS		 2467{
2468 int trapnr, ret;
c227f099 2469 target_siginfo_t info;
48733d19
TS		 2470
2471 while (1) {
2472 trapnr = cpu_cris_exec (env);
2473 switch (trapnr) {
2474 case 0xaa:
2475 {
2476 info.si_signo = SIGSEGV;
2477 info.si_errno = 0;
2478 /* XXX: check env->error_code */
2479 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2480 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2481 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2482 }
2483 break;
b6d3abda
EI		 2484 case EXCP_INTERRUPT:
2485 /* just indicate that signals should be handled asap */
2486 break;
48733d19
TS		 2487 case EXCP_BREAK:
2488 ret = do_syscall(env,
2489 env->regs[9],
2490 env->regs[10],
2491 env->regs[11],
2492 env->regs[12],
2493 env->regs[13],
2494 env->pregs[7],
5945cfcb
PM		 2495 env->pregs[11],
2496 0, 0);
48733d19 2497 env->regs[10] = ret;
48733d19
TS		 2498 break;
2499 case EXCP_DEBUG:
2500 {
2501 int sig;
2502
2503 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2504 if (sig)
2505 {
2506 info.si_signo = sig;
2507 info.si_errno = 0;
2508 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2509 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2510 }
2511 }
2512 break;
2513 default:
2514 printf ("Unhandled trap: 0x%x\n", trapnr);
2515 cpu_dump_state(env, stderr, fprintf, 0);
2516 exit (1);
2517 }
2518 process_pending_signals (env);
2519 }
2520}
2521#endif
2522
b779e29e 2523#ifdef TARGET_MICROBLAZE
05390248 2524void cpu_loop(CPUMBState *env)
b779e29e
EI		 2525{
2526 int trapnr, ret;
c227f099 2527 target_siginfo_t info;
b779e29e
EI		 2528
2529 while (1) {
2530 trapnr = cpu_mb_exec (env);
2531 switch (trapnr) {
2532 case 0xaa:
2533 {
2534 info.si_signo = SIGSEGV;
2535 info.si_errno = 0;
2536 /* XXX: check env->error_code */
2537 info.si_code = TARGET_SEGV_MAPERR;
2538 info._sifields._sigfault._addr = 0;
2539 queue_signal(env, info.si_signo, &info);
2540 }
2541 break;
2542 case EXCP_INTERRUPT:
2543 /* just indicate that signals should be handled asap */
2544 break;
2545 case EXCP_BREAK:
2546 /* Return address is 4 bytes after the call. */
2547 env->regs[14] += 4;
d7dce494 2548 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2549 ret = do_syscall(env,
2550 env->regs[12],
2551 env->regs[5],
2552 env->regs[6],
2553 env->regs[7],
2554 env->regs[8],
2555 env->regs[9],
5945cfcb
PM		 2556 env->regs[10],
2557 0, 0);
b779e29e 2558 env->regs[3] = ret;
b779e29e 2559 break;
b76da7e3
EI		 2560 case EXCP_HW_EXCP:
2561 env->regs[17] = env->sregs[SR_PC] + 4;
2562 if (env->iflags & D_FLAG) {
2563 env->sregs[SR_ESR] |= 1 << 12;
2564 env->sregs[SR_PC] -= 4;
b4916d7b 2565 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2566 }
2567
2568 env->iflags &= ~(IMM_FLAG | D_FLAG);
2569
2570 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2571 case ESR_EC_DIVZERO:
2572 info.si_signo = SIGFPE;
2573 info.si_errno = 0;
2574 info.si_code = TARGET_FPE_FLTDIV;
2575 info._sifields._sigfault._addr = 0;
2576 queue_signal(env, info.si_signo, &info);
2577 break;
b76da7e3
EI		 2578 case ESR_EC_FPU:
2579 info.si_signo = SIGFPE;
2580 info.si_errno = 0;
2581 if (env->sregs[SR_FSR] & FSR_IO) {
2582 info.si_code = TARGET_FPE_FLTINV;
2583 }
2584 if (env->sregs[SR_FSR] & FSR_DZ) {
2585 info.si_code = TARGET_FPE_FLTDIV;
2586 }
2587 info._sifields._sigfault._addr = 0;
2588 queue_signal(env, info.si_signo, &info);
2589 break;
2590 default:
2591 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2592 env->sregs[SR_ESR] & ESR_EC_MASK);
b76da7e3
EI		 2593 cpu_dump_state(env, stderr, fprintf, 0);
2594 exit (1);
2595 break;
2596 }
2597 break;
b779e29e
EI		 2598 case EXCP_DEBUG:
2599 {
2600 int sig;
2601
2602 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2603 if (sig)
2604 {
2605 info.si_signo = sig;
2606 info.si_errno = 0;
2607 info.si_code = TARGET_TRAP_BRKPT;
2608 queue_signal(env, info.si_signo, &info);
2609 }
2610 }
2611 break;
2612 default:
2613 printf ("Unhandled trap: 0x%x\n", trapnr);
2614 cpu_dump_state(env, stderr, fprintf, 0);
2615 exit (1);
2616 }
2617 process_pending_signals (env);
2618 }
2619}
2620#endif
2621
e6e5906b
PB		 2622#ifdef TARGET_M68K
2623
2624void cpu_loop(CPUM68KState *env)
2625{
2626 int trapnr;
2627 unsigned int n;
c227f099 2628 target_siginfo_t info;
e6e5906b 2629 TaskState *ts = env->opaque;
3b46e624 2630
e6e5906b
PB		 2631 for(;;) {
2632 trapnr = cpu_m68k_exec(env);
2633 switch(trapnr) {
2634 case EXCP_ILLEGAL:
2635 {
2636 if (ts->sim_syscalls) {
2637 uint16_t nr;
2638 nr = lduw(env->pc + 2);
2639 env->pc += 4;
2640 do_m68k_simcall(env, nr);
2641 } else {
2642 goto do_sigill;
2643 }
2644 }
2645 break;
a87295e8 2646 case EXCP_HALT_INSN:
e6e5906b 2647 /* Semihosing syscall. */
a87295e8 2648 env->pc += 4;
e6e5906b
PB		 2649 do_m68k_semihosting(env, env->dregs[0]);
2650 break;
2651 case EXCP_LINEA:
2652 case EXCP_LINEF:
2653 case EXCP_UNSUPPORTED:
2654 do_sigill:
2655 info.si_signo = SIGILL;
2656 info.si_errno = 0;
2657 info.si_code = TARGET_ILL_ILLOPN;
2658 info._sifields._sigfault._addr = env->pc;
624f7979 2659 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2660 break;
2661 case EXCP_TRAP0:
2662 {
2663 ts->sim_syscalls = 0;
2664 n = env->dregs[0];
2665 env->pc += 2;
5fafdf24
TS		 2666 env->dregs[0] = do_syscall(env,
2667 n,
e6e5906b
PB		 2668 env->dregs[1],
2669 env->dregs[2],
2670 env->dregs[3],
2671 env->dregs[4],
2672 env->dregs[5],
5945cfcb
PM		 2673 env->aregs[0],
2674 0, 0);
e6e5906b
PB		 2675 }
2676 break;
2677 case EXCP_INTERRUPT:
2678 /* just indicate that signals should be handled asap */
2679 break;
2680 case EXCP_ACCESS:
2681 {
2682 info.si_signo = SIGSEGV;
2683 info.si_errno = 0;
2684 /* XXX: check env->error_code */
2685 info.si_code = TARGET_SEGV_MAPERR;
2686 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2687 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2688 }
2689 break;
2690 case EXCP_DEBUG:
2691 {
2692 int sig;
2693
2694 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2695 if (sig)
2696 {
2697 info.si_signo = sig;
2698 info.si_errno = 0;
2699 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2700 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2701 }
2702 }
2703 break;
2704 default:
5fafdf24 2705 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b
PB		 2706 trapnr);
2707 cpu_dump_state(env, stderr, fprintf, 0);
2708 abort();
2709 }
2710 process_pending_signals(env);
2711 }
2712}
2713#endif /* TARGET_M68K */
2714
7a3148a9 2715#ifdef TARGET_ALPHA
6910b8f6
RH		 2716static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2717{
2718 target_ulong addr, val, tmp;
2719 target_siginfo_t info;
2720 int ret = 0;
2721
2722 addr = env->lock_addr;
2723 tmp = env->lock_st_addr;
2724 env->lock_addr = -1;
2725 env->lock_st_addr = 0;
2726
2727 start_exclusive();
2728 mmap_lock();
2729
2730 if (addr == tmp) {
2731 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2732 goto do_sigsegv;
2733 }
2734
2735 if (val == env->lock_value) {
2736 tmp = env->ir[reg];
2737 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2738 goto do_sigsegv;
2739 }
2740 ret = 1;
2741 }
2742 }
2743 env->ir[reg] = ret;
2744 env->pc += 4;
2745
2746 mmap_unlock();
2747 end_exclusive();
2748 return;
2749
2750 do_sigsegv:
2751 mmap_unlock();
2752 end_exclusive();
2753
2754 info.si_signo = TARGET_SIGSEGV;
2755 info.si_errno = 0;
2756 info.si_code = TARGET_SEGV_MAPERR;
2757 info._sifields._sigfault._addr = addr;
2758 queue_signal(env, TARGET_SIGSEGV, &info);
2759}
2760
05390248 2761void cpu_loop(CPUAlphaState *env)
7a3148a9 2762{
e96efcfc 2763 int trapnr;
c227f099 2764 target_siginfo_t info;
6049f4f8 2765 abi_long sysret;
3b46e624 2766
7a3148a9
JM		 2767 while (1) {
2768 trapnr = cpu_alpha_exec (env);
3b46e624 2769
ac316ca4
RH		 2770 /* All of the traps imply a transition through PALcode, which
2771 implies an REI instruction has been executed. Which means
2772 that the intr_flag should be cleared. */
2773 env->intr_flag = 0;
2774
7a3148a9
JM		 2775 switch (trapnr) {
2776 case EXCP_RESET:
2777 fprintf(stderr, "Reset requested. Exit\n");
2778 exit(1);
2779 break;
2780 case EXCP_MCHK:
2781 fprintf(stderr, "Machine check exception. Exit\n");
2782 exit(1);
2783 break;
07b6c13b
RH		 2784 case EXCP_SMP_INTERRUPT:
2785 case EXCP_CLK_INTERRUPT:
2786 case EXCP_DEV_INTERRUPT:
5fafdf24 2787 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2788 exit(1);
2789 break;
07b6c13b 2790 case EXCP_MMFAULT:
6910b8f6 2791 env->lock_addr = -1;
6049f4f8
RH		 2792 info.si_signo = TARGET_SIGSEGV;
2793 info.si_errno = 0;
129d8aa5 2794 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2795 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2796 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2797 queue_signal(env, info.si_signo, &info);
7a3148a9 2798 break;
7a3148a9 2799 case EXCP_UNALIGN:
6910b8f6 2800 env->lock_addr = -1;
6049f4f8
RH		 2801 info.si_signo = TARGET_SIGBUS;
2802 info.si_errno = 0;
2803 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2804 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2805 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2806 break;
2807 case EXCP_OPCDEC:
6049f4f8 2808 do_sigill:
6910b8f6 2809 env->lock_addr = -1;
6049f4f8
RH		 2810 info.si_signo = TARGET_SIGILL;
2811 info.si_errno = 0;
2812 info.si_code = TARGET_ILL_ILLOPC;
2813 info._sifields._sigfault._addr = env->pc;
2814 queue_signal(env, info.si_signo, &info);
7a3148a9 2815 break;
07b6c13b
RH		 2816 case EXCP_ARITH:
2817 env->lock_addr = -1;
2818 info.si_signo = TARGET_SIGFPE;
2819 info.si_errno = 0;
2820 info.si_code = TARGET_FPE_FLTINV;
2821 info._sifields._sigfault._addr = env->pc;
2822 queue_signal(env, info.si_signo, &info);
2823 break;
7a3148a9 2824 case EXCP_FEN:
6049f4f8 2825 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2826 break;
07b6c13b 2827 case EXCP_CALL_PAL:
6910b8f6 2828 env->lock_addr = -1;
07b6c13b 2829 switch (env->error_code) {
6049f4f8
RH		 2830 case 0x80:
2831 /* BPT */
2832 info.si_signo = TARGET_SIGTRAP;
2833 info.si_errno = 0;
2834 info.si_code = TARGET_TRAP_BRKPT;
2835 info._sifields._sigfault._addr = env->pc;
2836 queue_signal(env, info.si_signo, &info);
2837 break;
2838 case 0x81:
2839 /* BUGCHK */
2840 info.si_signo = TARGET_SIGTRAP;
2841 info.si_errno = 0;
2842 info.si_code = 0;
2843 info._sifields._sigfault._addr = env->pc;
2844 queue_signal(env, info.si_signo, &info);
2845 break;
2846 case 0x83:
2847 /* CALLSYS */
2848 trapnr = env->ir[IR_V0];
2849 sysret = do_syscall(env, trapnr,
2850 env->ir[IR_A0], env->ir[IR_A1],
2851 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 2852 env->ir[IR_A4], env->ir[IR_A5],
2853 0, 0);
a5b3b13b
RH		 2854 if (trapnr == TARGET_NR_sigreturn
2855 || trapnr == TARGET_NR_rt_sigreturn) {
2856 break;
2857 }
2858 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 2859 to how this is handled internal to Linux kernel.
2860 (Ab)use trapnr temporarily as boolean indicating error. */
2861 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2862 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2863 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 2864 break;
2865 case 0x86:
2866 /* IMB */
2867 /* ??? We can probably elide the code using page_unprotect
2868 that is checking for self-modifying code. Instead we
2869 could simply call tb_flush here. Until we work out the
2870 changes required to turn off the extra write protection,
2871 this can be a no-op. */
2872 break;
2873 case 0x9E:
2874 /* RDUNIQUE */
2875 /* Handled in the translator for usermode. */
2876 abort();
2877 case 0x9F:
2878 /* WRUNIQUE */
2879 /* Handled in the translator for usermode. */
2880 abort();
2881 case 0xAA:
2882 /* GENTRAP */
2883 info.si_signo = TARGET_SIGFPE;
2884 switch (env->ir[IR_A0]) {
2885 case TARGET_GEN_INTOVF:
2886 info.si_code = TARGET_FPE_INTOVF;
2887 break;
2888 case TARGET_GEN_INTDIV:
2889 info.si_code = TARGET_FPE_INTDIV;
2890 break;
2891 case TARGET_GEN_FLTOVF:
2892 info.si_code = TARGET_FPE_FLTOVF;
2893 break;
2894 case TARGET_GEN_FLTUND:
2895 info.si_code = TARGET_FPE_FLTUND;
2896 break;
2897 case TARGET_GEN_FLTINV:
2898 info.si_code = TARGET_FPE_FLTINV;
2899 break;
2900 case TARGET_GEN_FLTINE:
2901 info.si_code = TARGET_FPE_FLTRES;
2902 break;
2903 case TARGET_GEN_ROPRAND:
2904 info.si_code = 0;
2905 break;
2906 default:
2907 info.si_signo = TARGET_SIGTRAP;
2908 info.si_code = 0;
2909 break;
2910 }
2911 info.si_errno = 0;
2912 info._sifields._sigfault._addr = env->pc;
2913 queue_signal(env, info.si_signo, &info);
2914 break;
2915 default:
2916 goto do_sigill;
2917 }
7a3148a9 2918 break;
7a3148a9 2919 case EXCP_DEBUG:
6049f4f8
RH		 2920 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2921 if (info.si_signo) {
6910b8f6 2922 env->lock_addr = -1;
6049f4f8
RH		 2923 info.si_errno = 0;
2924 info.si_code = TARGET_TRAP_BRKPT;
2925 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2926 }
2927 break;
6910b8f6
RH		 2928 case EXCP_STL_C:
2929 case EXCP_STQ_C:
2930 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2931 break;
d0f20495
RH		 2932 case EXCP_INTERRUPT:
2933 /* Just indicate that signals should be handled asap. */
2934 break;
7a3148a9
JM		 2935 default:
2936 printf ("Unhandled trap: 0x%x\n", trapnr);
2937 cpu_dump_state(env, stderr, fprintf, 0);
2938 exit (1);
2939 }
2940 process_pending_signals (env);
2941 }
2942}
2943#endif /* TARGET_ALPHA */
2944
a4c075f1
UH		 2945#ifdef TARGET_S390X
2946void cpu_loop(CPUS390XState *env)
2947{
d5a103cd 2948 int trapnr, n, sig;
a4c075f1 2949 target_siginfo_t info;
d5a103cd 2950 target_ulong addr;
a4c075f1
UH		 2951
2952 while (1) {
d5a103cd 2953 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 2954 switch (trapnr) {
2955 case EXCP_INTERRUPT:
d5a103cd 2956 /* Just indicate that signals should be handled asap. */
a4c075f1 2957 break;
a4c075f1 2958
d5a103cd
RH		 2959 case EXCP_SVC:
2960 n = env->int_svc_code;
2961 if (!n) {
2962 /* syscalls > 255 */
2963 n = env->regs[1];
a4c075f1 2964 }
d5a103cd
RH		 2965 env->psw.addr += env->int_svc_ilen;
2966 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
2967 env->regs[4], env->regs[5],
2968 env->regs[6], env->regs[7], 0, 0);
a4c075f1 2969 break;
d5a103cd
RH		 2970
2971 case EXCP_DEBUG:
2972 sig = gdb_handlesig(env, TARGET_SIGTRAP);
2973 if (sig) {
2974 n = TARGET_TRAP_BRKPT;
2975 goto do_signal_pc;
a4c075f1
UH		 2976 }
2977 break;
d5a103cd
RH		 2978 case EXCP_PGM:
2979 n = env->int_pgm_code;
2980 switch (n) {
2981 case PGM_OPERATION:
2982 case PGM_PRIVILEGED:
2983 sig = SIGILL;
2984 n = TARGET_ILL_ILLOPC;
2985 goto do_signal_pc;
2986 case PGM_PROTECTION:
2987 case PGM_ADDRESSING:
2988 sig = SIGSEGV;
a4c075f1 2989 /* XXX: check env->error_code */
d5a103cd
RH		 2990 n = TARGET_SEGV_MAPERR;
2991 addr = env->__excp_addr;
2992 goto do_signal;
2993 case PGM_EXECUTE:
2994 case PGM_SPECIFICATION:
2995 case PGM_SPECIAL_OP:
2996 case PGM_OPERAND:
2997 do_sigill_opn:
2998 sig = SIGILL;
2999 n = TARGET_ILL_ILLOPN;
3000 goto do_signal_pc;
3001
3002 case PGM_FIXPT_OVERFLOW:
3003 sig = SIGFPE;
3004 n = TARGET_FPE_INTOVF;
3005 goto do_signal_pc;
3006 case PGM_FIXPT_DIVIDE:
3007 sig = SIGFPE;
3008 n = TARGET_FPE_INTDIV;
3009 goto do_signal_pc;
3010
3011 case PGM_DATA:
3012 n = (env->fpc >> 8) & 0xff;
3013 if (n == 0xff) {
3014 /* compare-and-trap */
3015 goto do_sigill_opn;
3016 } else {
3017 /* An IEEE exception, simulated or otherwise. */
3018 if (n & 0x80) {
3019 n = TARGET_FPE_FLTINV;
3020 } else if (n & 0x40) {
3021 n = TARGET_FPE_FLTDIV;
3022 } else if (n & 0x20) {
3023 n = TARGET_FPE_FLTOVF;
3024 } else if (n & 0x10) {
3025 n = TARGET_FPE_FLTUND;
3026 } else if (n & 0x08) {
3027 n = TARGET_FPE_FLTRES;
3028 } else {
3029 /* ??? Quantum exception; BFP, DFP error. */
3030 goto do_sigill_opn;
3031 }
3032 sig = SIGFPE;
3033 goto do_signal_pc;
3034 }
3035
3036 default:
3037 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3038 cpu_dump_state(env, stderr, fprintf, 0);
3039 exit(1);
a4c075f1
UH		 3040 }
3041 break;
d5a103cd
RH		 3042
3043 do_signal_pc:
3044 addr = env->psw.addr;
3045 do_signal:
3046 info.si_signo = sig;
3047 info.si_errno = 0;
3048 info.si_code = n;
3049 info._sifields._sigfault._addr = addr;
3050 queue_signal(env, info.si_signo, &info);
a4c075f1 3051 break;
d5a103cd 3052
a4c075f1 3053 default:
d5a103cd 3054 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
a4c075f1 3055 cpu_dump_state(env, stderr, fprintf, 0);
d5a103cd 3056 exit(1);
a4c075f1
UH		 3057 }
3058 process_pending_signals (env);
3059 }
3060}
3061
3062#endif /* TARGET_S390X */
3063
9349b4f9 3064THREAD CPUArchState *thread_env;
59faf6d6 3065
edf8e2af
MW		 3066void task_settid(TaskState *ts)
3067{
3068 if (ts->ts_tid == 0) {
2f7bb878 3069#ifdef CONFIG_USE_NPTL
edf8e2af
MW		 3070 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3071#else
3072 /* when no threads are used, tid becomes pid */
3073 ts->ts_tid = getpid();
3074#endif
3075 }
3076}
3077
3078void stop_all_tasks(void)
3079{
3080 /*
3081 * We trust that when using NPTL, start_exclusive()
3082 * handles thread stopping correctly.
3083 */
3084 start_exclusive();
3085}
3086
c3a92833 3087/* Assumes contents are already zeroed. */
624f7979
PB		 3088void init_task_state(TaskState *ts)
3089{
3090 int i;
3091
624f7979
PB		 3092 ts->used = 1;
3093 ts->first_free = ts->sigqueue_table;
3094 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3095 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3096 }
3097 ts->sigqueue_table[i].next = NULL;
3098}
fc9c5412
JS		 3099
3100static void handle_arg_help(const char *arg)
3101{
3102 usage();
3103}
3104
3105static void handle_arg_log(const char *arg)
3106{
3107 int mask;
fc9c5412 3108
4fde1eba 3109 mask = qemu_str_to_log_mask(arg);
fc9c5412 3110 if (!mask) {
59a6fa6e 3111 qemu_print_log_usage(stdout);
fc9c5412
JS		 3112 exit(1);
3113 }
24537a01 3114 qemu_set_log(mask);
fc9c5412
JS		 3115}
3116
50171d42 3117static void handle_arg_log_filename(const char *arg)
3118{
9a7e5424 3119 qemu_set_log_filename(arg);
50171d42 3120}
3121
fc9c5412
JS		 3122static void handle_arg_set_env(const char *arg)
3123{
3124 char *r, *p, *token;
3125 r = p = strdup(arg);
3126 while ((token = strsep(&p, ",")) != NULL) {
3127 if (envlist_setenv(envlist, token) != 0) {
3128 usage();
3129 }
3130 }
3131 free(r);
3132}
3133
3134static void handle_arg_unset_env(const char *arg)
3135{
3136 char *r, *p, *token;
3137 r = p = strdup(arg);
3138 while ((token = strsep(&p, ",")) != NULL) {
3139 if (envlist_unsetenv(envlist, token) != 0) {
3140 usage();
3141 }
3142 }
3143 free(r);
3144}
3145
3146static void handle_arg_argv0(const char *arg)
3147{
3148 argv0 = strdup(arg);
3149}
3150
3151static void handle_arg_stack_size(const char *arg)
3152{
3153 char *p;
3154 guest_stack_size = strtoul(arg, &p, 0);
3155 if (guest_stack_size == 0) {
3156 usage();
3157 }
3158
3159 if (*p == 'M') {
3160 guest_stack_size *= 1024 * 1024;
3161 } else if (*p == 'k' || *p == 'K') {
3162 guest_stack_size *= 1024;
3163 }
3164}
3165
3166static void handle_arg_ld_prefix(const char *arg)
3167{
3168 interp_prefix = strdup(arg);
3169}
3170
3171static void handle_arg_pagesize(const char *arg)
3172{
3173 qemu_host_page_size = atoi(arg);
3174 if (qemu_host_page_size == 0 ||
3175 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3176 fprintf(stderr, "page size must be a power of two\n");
3177 exit(1);
3178 }
3179}
3180
3181static void handle_arg_gdb(const char *arg)
3182{
3183 gdbstub_port = atoi(arg);
3184}
3185
3186static void handle_arg_uname(const char *arg)
3187{
3188 qemu_uname_release = strdup(arg);
3189}
3190
3191static void handle_arg_cpu(const char *arg)
3192{
3193 cpu_model = strdup(arg);
c8057f95 3194 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3195 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3196#if defined(cpu_list)
3197 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3198#endif
3199 exit(1);
3200 }
3201}
3202
3203#if defined(CONFIG_USE_GUEST_BASE)
3204static void handle_arg_guest_base(const char *arg)
3205{
3206 guest_base = strtol(arg, NULL, 0);
3207 have_guest_base = 1;
3208}
3209
3210static void handle_arg_reserved_va(const char *arg)
3211{
3212 char *p;
3213 int shift = 0;
3214 reserved_va = strtoul(arg, &p, 0);
3215 switch (*p) {
3216 case 'k':
3217 case 'K':
3218 shift = 10;
3219 break;
3220 case 'M':
3221 shift = 20;
3222 break;
3223 case 'G':
3224 shift = 30;
3225 break;
3226 }
3227 if (shift) {
3228 unsigned long unshifted = reserved_va;
3229 p++;
3230 reserved_va <<= shift;
3231 if (((reserved_va >> shift) != unshifted)
3232#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3233 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3234#endif
3235 ) {
3236 fprintf(stderr, "Reserved virtual address too big\n");
3237 exit(1);
3238 }
3239 }
3240 if (*p) {
3241 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3242 exit(1);
3243 }
3244}
3245#endif
3246
3247static void handle_arg_singlestep(const char *arg)
3248{
3249 singlestep = 1;
3250}
3251
3252static void handle_arg_strace(const char *arg)
3253{
3254 do_strace = 1;
3255}
3256
3257static void handle_arg_version(const char *arg)
3258{
3259 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
3260 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3261 exit(0);
fc9c5412
JS		 3262}
3263
3264struct qemu_argument {
3265 const char *argv;
3266 const char *env;
3267 bool has_arg;
3268 void (*handle_opt)(const char *arg);
3269 const char *example;
3270 const char *help;
3271};
3272
42644cee 3273static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3274 {"h", "", false, handle_arg_help,
3275 "", "print this help"},
3276 {"g", "QEMU_GDB", true, handle_arg_gdb,
3277 "port", "wait gdb connection to 'port'"},
3278 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3279 "path", "set the elf interpreter prefix to 'path'"},
3280 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3281 "size", "set the stack size to 'size' bytes"},
3282 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3283 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3284 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3285 "var=value", "sets targets environment variable (see below)"},
3286 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3287 "var", "unsets targets environment variable (see below)"},
3288 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3289 "argv0", "forces target process argv[0] to be 'argv0'"},
3290 {"r", "QEMU_UNAME", true, handle_arg_uname,
3291 "uname", "set qemu uname release string to 'uname'"},
3292#if defined(CONFIG_USE_GUEST_BASE)
3293 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3294 "address", "set guest_base address to 'address'"},
3295 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3296 "size", "reserve 'size' bytes for guest virtual address space"},
3297#endif
3298 {"d", "QEMU_LOG", true, handle_arg_log,
3299 "options", "activate log"},
50171d42 3300 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3301 "logfile", "override default logfile location"},
fc9c5412
JS		 3302 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3303 "pagesize", "set the host page size to 'pagesize'"},
3304 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3305 "", "run in singlestep mode"},
3306 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3307 "", "log system calls"},
3308 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3309 "", "display version information and exit"},
fc9c5412
JS		 3310 {NULL, NULL, false, NULL, NULL, NULL}
3311};
3312
3313static void usage(void)
3314{
42644cee 3315 const struct qemu_argument *arginfo;
fc9c5412
JS		 3316 int maxarglen;
3317 int maxenvlen;
3318
3319 printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
3320 "Linux CPU emulator (compiled for " TARGET_ARCH " emulation)\n"
3321 "\n"
3322 "Options and associated environment variables:\n"
3323 "\n");
3324
3325 maxarglen = maxenvlen = 0;
3326
3327 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3328 if (strlen(arginfo->env) > maxenvlen) {
3329 maxenvlen = strlen(arginfo->env);
3330 }
3331 if (strlen(arginfo->argv) > maxarglen) {
3332 maxarglen = strlen(arginfo->argv);
3333 }
3334 }
3335
3336 printf("%-*s%-*sDescription\n", maxarglen+3, "Argument",
3337 maxenvlen+1, "Env-variable");
3338
3339 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3340 if (arginfo->has_arg) {
3341 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3342 (int)(maxarglen-strlen(arginfo->argv)), arginfo->example,
3343 maxenvlen, arginfo->env, arginfo->help);
3344 } else {
3345 printf("-%-*s %-*s %s\n", maxarglen+1, arginfo->argv,
3346 maxenvlen, arginfo->env,
3347 arginfo->help);
3348 }
3349 }
3350
3351 printf("\n"
3352 "Defaults:\n"
3353 "QEMU_LD_PREFIX = %s\n"
3354 "QEMU_STACK_SIZE = %ld byte\n"
3355 "QEMU_LOG = %s\n",
3356 interp_prefix,
3357 guest_stack_size,
3358 DEBUG_LOGFILE);
3359
3360 printf("\n"
3361 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3362 "QEMU_UNSET_ENV environment variables to set and unset\n"
3363 "environment variables for the target process.\n"
3364 "It is possible to provide several variables by separating them\n"
3365 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3366 "provide the -E and -U options multiple times.\n"
3367 "The following lines are equivalent:\n"
3368 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3369 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3370 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3371 "Note that if you provide several changes to a single variable\n"
3372 "the last change will stay in effect.\n");
3373
3374 exit(1);
3375}
3376
3377static int parse_args(int argc, char **argv)
3378{
3379 const char *r;
3380 int optind;
42644cee 3381 const struct qemu_argument *arginfo;
fc9c5412
JS		 3382
3383 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3384 if (arginfo->env == NULL) {
3385 continue;
3386 }
3387
3388 r = getenv(arginfo->env);
3389 if (r != NULL) {
3390 arginfo->handle_opt(r);
3391 }
3392 }
3393
3394 optind = 1;
3395 for (;;) {
3396 if (optind >= argc) {
3397 break;
3398 }
3399 r = argv[optind];
3400 if (r[0] != '-') {
3401 break;
3402 }
3403 optind++;
3404 r++;
3405 if (!strcmp(r, "-")) {
3406 break;
3407 }
3408
3409 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3410 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3411 if (arginfo->has_arg) {
1386d4c0
PM		 3412 if (optind >= argc) {
3413 usage();
3414 }
3415 arginfo->handle_opt(argv[optind]);
fc9c5412 3416 optind++;
1386d4c0
PM		 3417 } else {
3418 arginfo->handle_opt(NULL);
fc9c5412 3419 }
fc9c5412
JS		 3420 break;
3421 }
3422 }
3423
3424 /* no option matched the current argv */
3425 if (arginfo->handle_opt == NULL) {
3426 usage();
3427 }
3428 }
3429
3430 if (optind >= argc) {
3431 usage();
3432 }
3433
3434 filename = argv[optind];
3435 exec_path = argv[optind];
3436
3437 return optind;
3438}
3439
902b3d5c 3440int main(int argc, char **argv, char **envp)
31e31b8a 3441{
c235d738 3442 const char *log_file = DEBUG_LOGFILE;
01ffc75b 3443 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3444 struct image_info info1, *info = &info1;
edf8e2af 3445 struct linux_binprm bprm;
48e15fc2 3446 TaskState *ts;
9349b4f9 3447 CPUArchState *env;
586314f2 3448 int optind;
04a6dfeb 3449 char **target_environ, **wrk;
7d8cec95
AJ		 3450 char **target_argv;
3451 int target_argc;
7d8cec95 3452 int i;
fd4d81dd 3453 int ret;
b12b6a18 3454
ce008c1f
AF		 3455 module_call_init(MODULE_INIT_QOM);
3456
902b3d5c 3457 qemu_cache_utils_init(envp);
3458
04a6dfeb
AJ		 3459 if ((envlist = envlist_create()) == NULL) {
3460 (void) fprintf(stderr, "Unable to allocate envlist\n");
3461 exit(1);
3462 }
3463
3464 /* add current environment into the list */
3465 for (wrk = environ; *wrk != NULL; wrk++) {
3466 (void) envlist_setenv(envlist, *wrk);
3467 }
3468
703e0e89
RH		 3469 /* Read the stack limit from the kernel. If it's "unlimited",
3470 then we can do little else besides use the default. */
3471 {
3472 struct rlimit lim;
3473 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906 3474 && lim.rlim_cur != RLIM_INFINITY
3475 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3476 guest_stack_size = lim.rlim_cur;
3477 }
3478 }
3479
b1f9be31 3480 cpu_model = NULL;
b5ec5ce0 3481#if defined(cpudef_setup)
3482 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3483#endif
3484
c235d738 3485 /* init debug */
9a7e5424 3486 qemu_set_log_filename(log_file);
fc9c5412 3487 optind = parse_args(argc, argv);
586314f2 3488
31e31b8a 3489 /* Zero out regs */
01ffc75b 3490 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3491
3492 /* Zero out image_info */
3493 memset(info, 0, sizeof(struct image_info));
3494
edf8e2af
MW		 3495 memset(&bprm, 0, sizeof (bprm));
3496
74cd30b8
FB		 3497 /* Scan interp_prefix dir for replacement files. */
3498 init_paths(interp_prefix);
3499
46027c07 3500 if (cpu_model == NULL) {
aaed909a 3501#if defined(TARGET_I386)
46027c07
FB		 3502#ifdef TARGET_X86_64
3503 cpu_model = "qemu64";
3504#else
3505 cpu_model = "qemu32";
3506#endif
aaed909a 3507#elif defined(TARGET_ARM)
088ab16c 3508 cpu_model = "any";
d2fbca94
GX		 3509#elif defined(TARGET_UNICORE32)
3510 cpu_model = "any";
aaed909a
FB		 3511#elif defined(TARGET_M68K)
3512 cpu_model = "any";
3513#elif defined(TARGET_SPARC)
3514#ifdef TARGET_SPARC64
3515 cpu_model = "TI UltraSparc II";
3516#else
3517 cpu_model = "Fujitsu MB86904";
46027c07 3518#endif
aaed909a
FB		 3519#elif defined(TARGET_MIPS)
3520#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3521 cpu_model = "20Kc";
3522#else
3523 cpu_model = "24Kf";
3524#endif
d962783e
JL		 3525#elif defined TARGET_OPENRISC
3526 cpu_model = "or1200";
aaed909a 3527#elif defined(TARGET_PPC)
7ded4f52 3528#ifdef TARGET_PPC64
f7177937 3529 cpu_model = "970fx";
7ded4f52 3530#else
aaed909a 3531 cpu_model = "750";
7ded4f52 3532#endif
aaed909a
FB		 3533#else
3534 cpu_model = "any";
3535#endif
3536 }
d5ab9713
JK		 3537 tcg_exec_init(0);
3538 cpu_exec_init_all();
83fb7adf
FB		 3539 /* NOTE: we need to init the CPU at this stage to get
3540 qemu_host_page_size */
aaed909a
FB		 3541 env = cpu_init(cpu_model);
3542 if (!env) {
3543 fprintf(stderr, "Unable to find CPU definition\n");
3544 exit(1);
3545 }
77868120 3546#if defined(TARGET_SPARC) || defined(TARGET_PPC)
ff18b762 3547 cpu_reset(ENV_GET_CPU(env));
b55a37c9
BS		 3548#endif
3549
d5975363 3550 thread_env = env;
3b46e624 3551
b6741956
FB		 3552 if (getenv("QEMU_STRACE")) {
3553 do_strace = 1;
b92c47c1
TS		 3554 }
3555
04a6dfeb
AJ		 3556 target_environ = envlist_to_environ(envlist, NULL);
3557 envlist_free(envlist);
b12b6a18 3558
379f6698
PB		 3559#if defined(CONFIG_USE_GUEST_BASE)
3560 /*
3561 * Now that page sizes are configured in cpu_init() we can do
3562 * proper page alignment for guest_base.
3563 */
3564 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3565
806d1021
MI		 3566 if (reserved_va || have_guest_base) {
3567 guest_base = init_guest_space(guest_base, reserved_va, 0,
3568 have_guest_base);
3569 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3570 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3571 "space for use as guest address space (check your virtual "
3572 "memory ulimit setting or reserve less using -R option)\n",
3573 reserved_va);
68a1c816
PB		 3574 exit(1);
3575 }
97cc7560 3576
806d1021
MI		 3577 if (reserved_va) {
3578 mmap_next_start = reserved_va;
97cc7560
DDAG		 3579 }
3580 }
14f24e14 3581#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3582
3583 /*
3584 * Read in mmap_min_addr kernel parameter. This value is used
3585 * When loading the ELF image to determine whether guest_base
14f24e14 3586 * is needed. It is also used in mmap_find_vma.
379f6698 3587 */
14f24e14 3588 {
379f6698
PB		 3589 FILE *fp;
3590
3591 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3592 unsigned long tmp;
3593 if (fscanf(fp, "%lu", &tmp) == 1) {
3594 mmap_min_addr = tmp;
3595 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3596 }
3597 fclose(fp);
3598 }
3599 }
379f6698 3600
7d8cec95
AJ		 3601 /*
3602 * Prepare copy of argv vector for target.
3603 */
3604 target_argc = argc - optind;
3605 target_argv = calloc(target_argc + 1, sizeof (char *));
3606 if (target_argv == NULL) {
3607 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3608 exit(1);
3609 }
3610
3611 /*
3612 * If argv0 is specified (using '-0' switch) we replace
3613 * argv[0] pointer with the given one.
3614 */
3615 i = 0;
3616 if (argv0 != NULL) {
3617 target_argv[i++] = strdup(argv0);
3618 }
3619 for (; i < target_argc; i++) {
3620 target_argv[i] = strdup(argv[optind + i]);
3621 }
3622 target_argv[target_argc] = NULL;
3623
7267c094 3624 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3625 init_task_state(ts);
3626 /* build Task State */
3627 ts->info = info;
3628 ts->bprm = &bprm;
3629 env->opaque = ts;
3630 task_settid(ts);
3631
fd4d81dd
AP		 3632 ret = loader_exec(filename, target_argv, target_environ, regs,
3633 info, &bprm);
3634 if (ret != 0) {
885c1d10 3635 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3636 _exit(1);
3637 }
3638
3639 for (wrk = target_environ; *wrk; wrk++) {
3640 free(*wrk);
31e31b8a 3641 }
3b46e624 3642
b12b6a18
TS		 3643 free(target_environ);
3644
2e77eac6 3645 if (qemu_log_enabled()) {
379f6698
PB		 3646#if defined(CONFIG_USE_GUEST_BASE)
3647 qemu_log("guest_base 0x%lx\n", guest_base);
3648#endif
2e77eac6
BS		 3649 log_page_dump();
3650
3651 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3652 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3653 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3654 info->start_code);
3655 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3656 info->start_data);
3657 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3658 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3659 info->start_stack);
3660 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3661 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3662 }
31e31b8a 3663
53a5960a 3664 target_set_brk(info->brk);
31e31b8a 3665 syscall_init();
66fb9763 3666 signal_init();
31e31b8a 3667
9002ec79
RH		 3668#if defined(CONFIG_USE_GUEST_BASE)
3669 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3670 generating the prologue until now so that the prologue can take
3671 the real value of GUEST_BASE into account. */
3672 tcg_prologue_init(&tcg_ctx);
3673#endif
3674
b346ff46 3675#if defined(TARGET_I386)
2e255c6b
FB		 3676 cpu_x86_set_cpl(env, 3);
3677
3802ce26 3678 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e
FB		 3679 env->hflags |= HF_PE_MASK;
3680 if (env->cpuid_features & CPUID_SSE) {
3681 env->cr[4] |= CR4_OSFXSR_MASK;
3682 env->hflags |= HF_OSFXSR_MASK;
3683 }
d2fd1af7 3684#ifndef TARGET_ABI32
4dbc422b
FB		 3685 /* enable 64 bit mode if possible */
3686 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
3687 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3688 exit(1);
3689 }
d2fd1af7 3690 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3691 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3692 env->hflags |= HF_LMA_MASK;
3693#endif
1bde465e 3694
415e561f
FB		 3695 /* flags setup : we activate the IRQs by default as in user mode */
3696 env->eflags |= IF_MASK;
3b46e624 3697
6dbad63e 3698 /* linux register setup */
d2fd1af7 3699#ifndef TARGET_ABI32
84409ddb
JM		 3700 env->regs[R_EAX] = regs->rax;
3701 env->regs[R_EBX] = regs->rbx;
3702 env->regs[R_ECX] = regs->rcx;
3703 env->regs[R_EDX] = regs->rdx;
3704 env->regs[R_ESI] = regs->rsi;
3705 env->regs[R_EDI] = regs->rdi;
3706 env->regs[R_EBP] = regs->rbp;
3707 env->regs[R_ESP] = regs->rsp;
3708 env->eip = regs->rip;
3709#else
0ecfa993
FB		 3710 env->regs[R_EAX] = regs->eax;
3711 env->regs[R_EBX] = regs->ebx;
3712 env->regs[R_ECX] = regs->ecx;
3713 env->regs[R_EDX] = regs->edx;
3714 env->regs[R_ESI] = regs->esi;
3715 env->regs[R_EDI] = regs->edi;
3716 env->regs[R_EBP] = regs->ebp;
3717 env->regs[R_ESP] = regs->esp;
dab2ed99 3718 env->eip = regs->eip;
84409ddb 3719#endif
31e31b8a 3720
f4beb510 3721 /* linux interrupt setup */
e441570f
AZ		 3722#ifndef TARGET_ABI32
3723 env->idt.limit = 511;
3724#else
3725 env->idt.limit = 255;
3726#endif
3727 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3728 PROT_READ|PROT_WRITE,
3729 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3730 idt_table = g2h(env->idt.base);
f4beb510
FB		 3731 set_idt(0, 0);
3732 set_idt(1, 0);
3733 set_idt(2, 0);
3734 set_idt(3, 3);
3735 set_idt(4, 3);
ec95da6c 3736 set_idt(5, 0);
f4beb510
FB		 3737 set_idt(6, 0);
3738 set_idt(7, 0);
3739 set_idt(8, 0);
3740 set_idt(9, 0);
3741 set_idt(10, 0);
3742 set_idt(11, 0);
3743 set_idt(12, 0);
3744 set_idt(13, 0);
3745 set_idt(14, 0);
3746 set_idt(15, 0);
3747 set_idt(16, 0);
3748 set_idt(17, 0);
3749 set_idt(18, 0);
3750 set_idt(19, 0);
3751 set_idt(0x80, 3);
3752
6dbad63e 3753 /* linux segment setup */
8d18e893
FB		 3754 {
3755 uint64_t *gdt_table;
e441570f
AZ		 3756 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3757 PROT_READ|PROT_WRITE,
3758 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3759 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3760 gdt_table = g2h(env->gdt.base);
d2fd1af7 3761#ifdef TARGET_ABI32
8d18e893
FB		 3762 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3763 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3764 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3765#else
3766 /* 64 bit code segment */
3767 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3768 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3769 DESC_L_MASK |
3770 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3771#endif
8d18e893
FB		 3772 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3773 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3774 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3775 }
6dbad63e 3776 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3777 cpu_x86_load_seg(env, R_SS, __USER_DS);
3778#ifdef TARGET_ABI32
6dbad63e
FB		 3779 cpu_x86_load_seg(env, R_DS, __USER_DS);
3780 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3781 cpu_x86_load_seg(env, R_FS, __USER_DS);
3782 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3783 /* This hack makes Wine work... */
3784 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3785#else
3786 cpu_x86_load_seg(env, R_DS, 0);
3787 cpu_x86_load_seg(env, R_ES, 0);
3788 cpu_x86_load_seg(env, R_FS, 0);
3789 cpu_x86_load_seg(env, R_GS, 0);
3790#endif
b346ff46
FB		 3791#elif defined(TARGET_ARM)
3792 {
3793 int i;
b5ff1b31 3794 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3795 for(i = 0; i < 16; i++) {
3796 env->regs[i] = regs->uregs[i];
3797 }
d8fd2954
PB		 3798 /* Enable BE8. */
3799 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3800 && (info->elf_flags & EF_ARM_BE8)) {
3801 env->bswap_code = 1;
3802 }
b346ff46 3803 }
d2fbca94
GX		 3804#elif defined(TARGET_UNICORE32)
3805 {
3806 int i;
3807 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3808 for (i = 0; i < 32; i++) {
3809 env->regs[i] = regs->uregs[i];
3810 }
3811 }
93ac68bc 3812#elif defined(TARGET_SPARC)
060366c5
FB		 3813 {
3814 int i;
3815 env->pc = regs->pc;
3816 env->npc = regs->npc;
3817 env->y = regs->y;
3818 for(i = 0; i < 8; i++)
3819 env->gregs[i] = regs->u_regs[i];
3820 for(i = 0; i < 8; i++)
3821 env->regwptr[i] = regs->u_regs[i + 8];
3822 }
67867308
FB		 3823#elif defined(TARGET_PPC)
3824 {
3825 int i;
3fc6c082 3826
0411a972
JM		 3827#if defined(TARGET_PPC64)
3828#if defined(TARGET_ABI32)
3829 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3830#else
0411a972
JM		 3831 env->msr |= (target_ulong)1 << MSR_SF;
3832#endif
84409ddb 3833#endif
67867308
FB		 3834 env->nip = regs->nip;
3835 for(i = 0; i < 32; i++) {
3836 env->gpr[i] = regs->gpr[i];
3837 }
3838 }
e6e5906b
PB		 3839#elif defined(TARGET_M68K)
3840 {
e6e5906b
PB		 3841 env->pc = regs->pc;
3842 env->dregs[0] = regs->d0;
3843 env->dregs[1] = regs->d1;
3844 env->dregs[2] = regs->d2;
3845 env->dregs[3] = regs->d3;
3846 env->dregs[4] = regs->d4;
3847 env->dregs[5] = regs->d5;
3848 env->dregs[6] = regs->d6;
3849 env->dregs[7] = regs->d7;
3850 env->aregs[0] = regs->a0;
3851 env->aregs[1] = regs->a1;
3852 env->aregs[2] = regs->a2;
3853 env->aregs[3] = regs->a3;
3854 env->aregs[4] = regs->a4;
3855 env->aregs[5] = regs->a5;
3856 env->aregs[6] = regs->a6;
3857 env->aregs[7] = regs->usp;
3858 env->sr = regs->sr;
3859 ts->sim_syscalls = 1;
3860 }
b779e29e
EI		 3861#elif defined(TARGET_MICROBLAZE)
3862 {
3863 env->regs[0] = regs->r0;
3864 env->regs[1] = regs->r1;
3865 env->regs[2] = regs->r2;
3866 env->regs[3] = regs->r3;
3867 env->regs[4] = regs->r4;
3868 env->regs[5] = regs->r5;
3869 env->regs[6] = regs->r6;
3870 env->regs[7] = regs->r7;
3871 env->regs[8] = regs->r8;
3872 env->regs[9] = regs->r9;
3873 env->regs[10] = regs->r10;
3874 env->regs[11] = regs->r11;
3875 env->regs[12] = regs->r12;
3876 env->regs[13] = regs->r13;
3877 env->regs[14] = regs->r14;
3878 env->regs[15] = regs->r15;
3879 env->regs[16] = regs->r16;
3880 env->regs[17] = regs->r17;
3881 env->regs[18] = regs->r18;
3882 env->regs[19] = regs->r19;
3883 env->regs[20] = regs->r20;
3884 env->regs[21] = regs->r21;
3885 env->regs[22] = regs->r22;
3886 env->regs[23] = regs->r23;
3887 env->regs[24] = regs->r24;
3888 env->regs[25] = regs->r25;
3889 env->regs[26] = regs->r26;
3890 env->regs[27] = regs->r27;
3891 env->regs[28] = regs->r28;
3892 env->regs[29] = regs->r29;
3893 env->regs[30] = regs->r30;
3894 env->regs[31] = regs->r31;
3895 env->sregs[SR_PC] = regs->pc;
3896 }
048f6b4d
FB		 3897#elif defined(TARGET_MIPS)
3898 {
3899 int i;
3900
3901 for(i = 0; i < 32; i++) {
b5dc7732 3902 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3903 }
0fddbbf2
NF		 3904 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3905 if (regs->cp0_epc & 1) {
3906 env->hflags |= MIPS_HFLAG_M16;
3907 }
048f6b4d 3908 }
d962783e
JL		 3909#elif defined(TARGET_OPENRISC)
3910 {
3911 int i;
3912
3913 for (i = 0; i < 32; i++) {
3914 env->gpr[i] = regs->gpr[i];
3915 }
3916
3917 env->sr = regs->sr;
3918 env->pc = regs->pc;
3919 }
fdf9b3e8
FB		 3920#elif defined(TARGET_SH4)
3921 {
3922 int i;
3923
3924 for(i = 0; i < 16; i++) {
3925 env->gregs[i] = regs->regs[i];
3926 }
3927 env->pc = regs->pc;
3928 }
7a3148a9
JM		 3929#elif defined(TARGET_ALPHA)
3930 {
3931 int i;
3932
3933 for(i = 0; i < 28; i++) {
992f48a0 3934 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 3935 }
dad081ee 3936 env->ir[IR_SP] = regs->usp;
7a3148a9 3937 env->pc = regs->pc;
7a3148a9 3938 }
48733d19
TS		 3939#elif defined(TARGET_CRIS)
3940 {
3941 env->regs[0] = regs->r0;
3942 env->regs[1] = regs->r1;
3943 env->regs[2] = regs->r2;
3944 env->regs[3] = regs->r3;
3945 env->regs[4] = regs->r4;
3946 env->regs[5] = regs->r5;
3947 env->regs[6] = regs->r6;
3948 env->regs[7] = regs->r7;
3949 env->regs[8] = regs->r8;
3950 env->regs[9] = regs->r9;
3951 env->regs[10] = regs->r10;
3952 env->regs[11] = regs->r11;
3953 env->regs[12] = regs->r12;
3954 env->regs[13] = regs->r13;
3955 env->regs[14] = info->start_stack;
3956 env->regs[15] = regs->acr;
3957 env->pc = regs->erp;
3958 }
a4c075f1
UH		 3959#elif defined(TARGET_S390X)
3960 {
3961 int i;
3962 for (i = 0; i < 16; i++) {
3963 env->regs[i] = regs->gprs[i];
3964 }
3965 env->psw.mask = regs->psw.mask;
3966 env->psw.addr = regs->psw.addr;
3967 }
b346ff46
FB		 3968#else
3969#error unsupported target CPU
3970#endif
31e31b8a 3971
d2fbca94 3972#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 3973 ts->stack_base = info->start_stack;
3974 ts->heap_base = info->brk;
3975 /* This will be filled in on the first SYS_HEAPINFO call. */
3976 ts->heap_limit = 0;
3977#endif
3978
74c33bed 3979 if (gdbstub_port) {
ff7a981a
PM		 3980 if (gdbserver_start(gdbstub_port) < 0) {
3981 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
3982 gdbstub_port);
3983 exit(1);
3984 }
1fddef4b
FB		 3985 gdb_handlesig(env, 0);
3986 }
1b6b029e
FB		 3987 cpu_loop(env);
3988 /* never exits */
31e31b8a
FB		 3989 return 0;
3990}
Qemu copy for testing