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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
3ef693a0 38#define DEBUG_LOGFILE "/tmp/qemu.log"
586314f2 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
fc9c5412
JS		 43const char *filename;
44const char *argv0;
45int gdbstub_port;
46envlist_t *envlist;
47const char *cpu_model;
379f6698 48unsigned long mmap_min_addr;
14f24e14 49#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 50unsigned long guest_base;
51int have_guest_base;
288e65b9
AG		 52#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
53/*
54 * When running 32-on-64 we should make sure we can fit all of the possible
55 * guest address space into a contiguous chunk of virtual host memory.
56 *
57 * This way we will never overlap with our own libraries or binaries or stack
58 * or anything else that QEMU maps.
59 */
60unsigned long reserved_va = 0xf7000000;
61#else
68a1c816 62unsigned long reserved_va;
379f6698 63#endif
288e65b9 64#endif
1b530a6d 65
fc9c5412
JS		 66static void usage(void);
67
7ee2822c 68static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 69const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 70
9de5e440
FB		 71/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
703e0e89 74unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 75
76void gemu_log(const char *fmt, ...)
77{
78 va_list ap;
79
80 va_start(ap, fmt);
81 vfprintf(stderr, fmt, ap);
82 va_end(ap);
83}
84
8fcd3692 85#if defined(TARGET_I386)
05390248 86int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 87{
88 return -1;
89}
8fcd3692 90#endif
92ccca6a 91
2f7bb878 92#if defined(CONFIG_USE_NPTL)
d5975363
PB		 93/***********************************************************/
94/* Helper routines for implementing atomic operations. */
95
96/* To implement exclusive operations we force all cpus to syncronise.
97 We don't require a full sync, only that no cpus are executing guest code.
98 The alternative is to map target atomic ops onto host equivalents,
99 which requires quite a lot of per host/target work. */
c2764719 100static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 101static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
102static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
103static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
104static int pending_cpus;
105
106/* Make sure everything is in a consistent state for calling fork(). */
107void fork_start(void)
108{
d5975363
PB		 109 pthread_mutex_lock(&tb_lock);
110 pthread_mutex_lock(&exclusive_lock);
d032d1b4 111 mmap_fork_start();
d5975363
PB		 112}
113
114void fork_end(int child)
115{
d032d1b4 116 mmap_fork_end(child);
d5975363
PB		 117 if (child) {
118 /* Child processes created by fork() only have a single thread.
119 Discard information about the parent threads. */
120 first_cpu = thread_env;
121 thread_env->next_cpu = NULL;
122 pending_cpus = 0;
123 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 124 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 125 pthread_cond_init(&exclusive_cond, NULL);
126 pthread_cond_init(&exclusive_resume, NULL);
127 pthread_mutex_init(&tb_lock, NULL);
2b1319c8 128 gdbserver_fork(thread_env);
d5975363
PB		 129 } else {
130 pthread_mutex_unlock(&exclusive_lock);
131 pthread_mutex_unlock(&tb_lock);
132 }
d5975363
PB		 133}
134
135/* Wait for pending exclusive operations to complete. The exclusive lock
136 must be held. */
137static inline void exclusive_idle(void)
138{
139 while (pending_cpus) {
140 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
141 }
142}
143
144/* Start an exclusive operation.
145 Must only be called from outside cpu_arm_exec. */
146static inline void start_exclusive(void)
147{
9349b4f9 148 CPUArchState *other;
d5975363
PB		 149 pthread_mutex_lock(&exclusive_lock);
150 exclusive_idle();
151
152 pending_cpus = 1;
153 /* Make all other cpus stop executing. */
154 for (other = first_cpu; other; other = other->next_cpu) {
155 if (other->running) {
156 pending_cpus++;
3098dba0 157 cpu_exit(other);
d5975363
PB		 158 }
159 }
160 if (pending_cpus > 1) {
161 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
162 }
163}
164
165/* Finish an exclusive operation. */
166static inline void end_exclusive(void)
167{
168 pending_cpus = 0;
169 pthread_cond_broadcast(&exclusive_resume);
170 pthread_mutex_unlock(&exclusive_lock);
171}
172
173/* Wait for exclusive ops to finish, and begin cpu execution. */
9349b4f9 174static inline void cpu_exec_start(CPUArchState *env)
d5975363
PB		 175{
176 pthread_mutex_lock(&exclusive_lock);
177 exclusive_idle();
178 env->running = 1;
179 pthread_mutex_unlock(&exclusive_lock);
180}
181
182/* Mark cpu as not executing, and release pending exclusive ops. */
9349b4f9 183static inline void cpu_exec_end(CPUArchState *env)
d5975363
PB		 184{
185 pthread_mutex_lock(&exclusive_lock);
186 env->running = 0;
187 if (pending_cpus > 1) {
188 pending_cpus--;
189 if (pending_cpus == 1) {
190 pthread_cond_signal(&exclusive_cond);
191 }
192 }
193 exclusive_idle();
194 pthread_mutex_unlock(&exclusive_lock);
195}
c2764719
PB		 196
197void cpu_list_lock(void)
198{
199 pthread_mutex_lock(&cpu_list_mutex);
200}
201
202void cpu_list_unlock(void)
203{
204 pthread_mutex_unlock(&cpu_list_mutex);
205}
2f7bb878 206#else /* if !CONFIG_USE_NPTL */
d5975363 207/* These are no-ops because we are not threadsafe. */
9349b4f9 208static inline void cpu_exec_start(CPUArchState *env)
d5975363
PB		 209{
210}
211
9349b4f9 212static inline void cpu_exec_end(CPUArchState *env)
d5975363
PB		 213{
214}
215
216static inline void start_exclusive(void)
217{
218}
219
220static inline void end_exclusive(void)
221{
222}
223
224void fork_start(void)
225{
226}
227
228void fork_end(int child)
229{
2b1319c8
AJ		 230 if (child) {
231 gdbserver_fork(thread_env);
232 }
d5975363 233}
c2764719
PB		 234
235void cpu_list_lock(void)
236{
237}
238
239void cpu_list_unlock(void)
240{
241}
d5975363
PB		 242#endif
243
244
a541f297
FB		 245#ifdef TARGET_I386
246/***********************************************************/
247/* CPUX86 core interface */
248
05390248 249void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 250{
251}
252
28ab0e2e
FB		 253uint64_t cpu_get_tsc(CPUX86State *env)
254{
255 return cpu_get_real_ticks();
256}
257
5fafdf24 258static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 259 int flags)
6dbad63e 260{
f4beb510 261 unsigned int e1, e2;
53a5960a 262 uint32_t *p;
6dbad63e
FB		 263 e1 = (addr << 16) | (limit & 0xffff);
264 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 265 e2 |= flags;
53a5960a 266 p = ptr;
d538e8f5 267 p[0] = tswap32(e1);
268 p[1] = tswap32(e2);
f4beb510
FB		 269}
270
e441570f 271static uint64_t *idt_table;
eb38c52c 272#ifdef TARGET_X86_64
d2fd1af7
FB		 273static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
274 uint64_t addr, unsigned int sel)
f4beb510 275{
4dbc422b 276 uint32_t *p, e1, e2;
f4beb510
FB		 277 e1 = (addr & 0xffff) | (sel << 16);
278 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 279 p = ptr;
4dbc422b
FB		 280 p[0] = tswap32(e1);
281 p[1] = tswap32(e2);
282 p[2] = tswap32(addr >> 32);
283 p[3] = 0;
6dbad63e 284}
d2fd1af7
FB		 285/* only dpl matters as we do only user space emulation */
286static void set_idt(int n, unsigned int dpl)
287{
288 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
289}
290#else
d2fd1af7
FB		 291static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
292 uint32_t addr, unsigned int sel)
293{
4dbc422b 294 uint32_t *p, e1, e2;
d2fd1af7
FB		 295 e1 = (addr & 0xffff) | (sel << 16);
296 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
297 p = ptr;
4dbc422b
FB		 298 p[0] = tswap32(e1);
299 p[1] = tswap32(e2);
d2fd1af7
FB		 300}
301
f4beb510
FB		 302/* only dpl matters as we do only user space emulation */
303static void set_idt(int n, unsigned int dpl)
304{
305 set_gate(idt_table + n, 0, dpl, 0, 0);
306}
d2fd1af7 307#endif
31e31b8a 308
89e957e7 309void cpu_loop(CPUX86State *env)
1b6b029e 310{
bc8a22cc 311 int trapnr;
992f48a0 312 abi_ulong pc;
c227f099 313 target_siginfo_t info;
851e67a1 314
1b6b029e 315 for(;;) {
bc8a22cc 316 trapnr = cpu_x86_exec(env);
bc8a22cc 317 switch(trapnr) {
f4beb510 318 case 0x80:
d2fd1af7 319 /* linux syscall from int $0x80 */
5fafdf24
TS		 320 env->regs[R_EAX] = do_syscall(env,
321 env->regs[R_EAX],
f4beb510
FB		 322 env->regs[R_EBX],
323 env->regs[R_ECX],
324 env->regs[R_EDX],
325 env->regs[R_ESI],
326 env->regs[R_EDI],
5945cfcb
PM		 327 env->regs[R_EBP],
328 0, 0);
f4beb510 329 break;
d2fd1af7
FB		 330#ifndef TARGET_ABI32
331 case EXCP_SYSCALL:
5ba18547 332 /* linux syscall from syscall instruction */
d2fd1af7
FB		 333 env->regs[R_EAX] = do_syscall(env,
334 env->regs[R_EAX],
335 env->regs[R_EDI],
336 env->regs[R_ESI],
337 env->regs[R_EDX],
338 env->regs[10],
339 env->regs[8],
5945cfcb
PM		 340 env->regs[9],
341 0, 0);
d2fd1af7
FB		 342 env->eip = env->exception_next_eip;
343 break;
344#endif
f4beb510
FB		 345 case EXCP0B_NOSEG:
346 case EXCP0C_STACK:
347 info.si_signo = SIGBUS;
348 info.si_errno = 0;
349 info.si_code = TARGET_SI_KERNEL;
350 info._sifields._sigfault._addr = 0;
624f7979 351 queue_signal(env, info.si_signo, &info);
f4beb510 352 break;
1b6b029e 353 case EXCP0D_GPF:
d2fd1af7 354 /* XXX: potential problem if ABI32 */
84409ddb 355#ifndef TARGET_X86_64
851e67a1 356 if (env->eflags & VM_MASK) {
89e957e7 357 handle_vm86_fault(env);
84409ddb
JM		 358 } else
359#endif
360 {
f4beb510
FB		 361 info.si_signo = SIGSEGV;
362 info.si_errno = 0;
363 info.si_code = TARGET_SI_KERNEL;
364 info._sifields._sigfault._addr = 0;
624f7979 365 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 366 }
367 break;
b689bc57
FB		 368 case EXCP0E_PAGE:
369 info.si_signo = SIGSEGV;
370 info.si_errno = 0;
371 if (!(env->error_code & 1))
372 info.si_code = TARGET_SEGV_MAPERR;
373 else
374 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 375 info._sifields._sigfault._addr = env->cr[2];
624f7979 376 queue_signal(env, info.si_signo, &info);
b689bc57 377 break;
9de5e440 378 case EXCP00_DIVZ:
84409ddb 379#ifndef TARGET_X86_64
bc8a22cc 380 if (env->eflags & VM_MASK) {
447db213 381 handle_vm86_trap(env, trapnr);
84409ddb
JM		 382 } else
383#endif
384 {
bc8a22cc
FB		 385 /* division by zero */
386 info.si_signo = SIGFPE;
387 info.si_errno = 0;
388 info.si_code = TARGET_FPE_INTDIV;
389 info._sifields._sigfault._addr = env->eip;
624f7979 390 queue_signal(env, info.si_signo, &info);
bc8a22cc 391 }
9de5e440 392 break;
01df040b 393 case EXCP01_DB:
447db213 394 case EXCP03_INT3:
84409ddb 395#ifndef TARGET_X86_64
447db213
FB		 396 if (env->eflags & VM_MASK) {
397 handle_vm86_trap(env, trapnr);
84409ddb
JM		 398 } else
399#endif
400 {
447db213
FB		 401 info.si_signo = SIGTRAP;
402 info.si_errno = 0;
01df040b 403 if (trapnr == EXCP01_DB) {
447db213
FB		 404 info.si_code = TARGET_TRAP_BRKPT;
405 info._sifields._sigfault._addr = env->eip;
406 } else {
407 info.si_code = TARGET_SI_KERNEL;
408 info._sifields._sigfault._addr = 0;
409 }
624f7979 410 queue_signal(env, info.si_signo, &info);
447db213
FB		 411 }
412 break;
9de5e440
FB		 413 case EXCP04_INTO:
414 case EXCP05_BOUND:
84409ddb 415#ifndef TARGET_X86_64
bc8a22cc 416 if (env->eflags & VM_MASK) {
447db213 417 handle_vm86_trap(env, trapnr);
84409ddb
JM		 418 } else
419#endif
420 {
bc8a22cc
FB		 421 info.si_signo = SIGSEGV;
422 info.si_errno = 0;
b689bc57 423 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 424 info._sifields._sigfault._addr = 0;
624f7979 425 queue_signal(env, info.si_signo, &info);
bc8a22cc 426 }
9de5e440
FB		 427 break;
428 case EXCP06_ILLOP:
429 info.si_signo = SIGILL;
430 info.si_errno = 0;
431 info.si_code = TARGET_ILL_ILLOPN;
432 info._sifields._sigfault._addr = env->eip;
624f7979 433 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 434 break;
435 case EXCP_INTERRUPT:
436 /* just indicate that signals should be handled asap */
437 break;
1fddef4b
FB		 438 case EXCP_DEBUG:
439 {
440 int sig;
441
442 sig = gdb_handlesig (env, TARGET_SIGTRAP);
443 if (sig)
444 {
445 info.si_signo = sig;
446 info.si_errno = 0;
447 info.si_code = TARGET_TRAP_BRKPT;
624f7979 448 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 449 }
450 }
451 break;
1b6b029e 452 default:
970a87a6 453 pc = env->segs[R_CS].base + env->eip;
5fafdf24 454 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 455 (long)pc, trapnr);
1b6b029e
FB		 456 abort();
457 }
66fb9763 458 process_pending_signals(env);
1b6b029e
FB		 459 }
460}
b346ff46
FB		 461#endif
462
463#ifdef TARGET_ARM
464
d8fd2954
PB		 465#define get_user_code_u32(x, gaddr, doswap) \
466 ({ abi_long __r = get_user_u32((x), (gaddr)); \
467 if (!__r && (doswap)) { \
468 (x) = bswap32(x); \
469 } \
470 __r; \
471 })
472
473#define get_user_code_u16(x, gaddr, doswap) \
474 ({ abi_long __r = get_user_u16((x), (gaddr)); \
475 if (!__r && (doswap)) { \
476 (x) = bswap16(x); \
477 } \
478 __r; \
479 })
480
97cc7560
DDAG		 481/*
482 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
483 * Input:
484 * r0 = pointer to oldval
485 * r1 = pointer to newval
486 * r2 = pointer to target value
487 *
488 * Output:
489 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
490 * C set if *ptr was changed, clear if no exchange happened
491 *
492 * Note segv's in kernel helpers are a bit tricky, we can set the
493 * data address sensibly but the PC address is just the entry point.
494 */
495static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
496{
497 uint64_t oldval, newval, val;
498 uint32_t addr, cpsr;
499 target_siginfo_t info;
500
501 /* Based on the 32 bit code in do_kernel_trap */
502
503 /* XXX: This only works between threads, not between processes.
504 It's probably possible to implement this with native host
505 operations. However things like ldrex/strex are much harder so
506 there's not much point trying. */
507 start_exclusive();
508 cpsr = cpsr_read(env);
509 addr = env->regs[2];
510
511 if (get_user_u64(oldval, env->regs[0])) {
512 env->cp15.c6_data = env->regs[0];
513 goto segv;
514 };
515
516 if (get_user_u64(newval, env->regs[1])) {
517 env->cp15.c6_data = env->regs[1];
518 goto segv;
519 };
520
521 if (get_user_u64(val, addr)) {
522 env->cp15.c6_data = addr;
523 goto segv;
524 }
525
526 if (val == oldval) {
527 val = newval;
528
529 if (put_user_u64(val, addr)) {
530 env->cp15.c6_data = addr;
531 goto segv;
532 };
533
534 env->regs[0] = 0;
535 cpsr |= CPSR_C;
536 } else {
537 env->regs[0] = -1;
538 cpsr &= ~CPSR_C;
539 }
540 cpsr_write(env, cpsr, CPSR_C);
541 end_exclusive();
542 return;
543
544segv:
545 end_exclusive();
546 /* We get the PC of the entry address - which is as good as anything,
547 on a real kernel what you get depends on which mode it uses. */
548 info.si_signo = SIGSEGV;
549 info.si_errno = 0;
550 /* XXX: check env->error_code */
551 info.si_code = TARGET_SEGV_MAPERR;
552 info._sifields._sigfault._addr = env->cp15.c6_data;
553 queue_signal(env, info.si_signo, &info);
554
555 end_exclusive();
556}
557
fbb4a2e3
PB		 558/* Handle a jump to the kernel code page. */
559static int
560do_kernel_trap(CPUARMState *env)
561{
562 uint32_t addr;
563 uint32_t cpsr;
564 uint32_t val;
565
566 switch (env->regs[15]) {
567 case 0xffff0fa0: /* __kernel_memory_barrier */
568 /* ??? No-op. Will need to do better for SMP. */
569 break;
570 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 571 /* XXX: This only works between threads, not between processes.
572 It's probably possible to implement this with native host
573 operations. However things like ldrex/strex are much harder so
574 there's not much point trying. */
575 start_exclusive();
fbb4a2e3
PB		 576 cpsr = cpsr_read(env);
577 addr = env->regs[2];
578 /* FIXME: This should SEGV if the access fails. */
579 if (get_user_u32(val, addr))
580 val = ~env->regs[0];
581 if (val == env->regs[0]) {
582 val = env->regs[1];
583 /* FIXME: Check for segfaults. */
584 put_user_u32(val, addr);
585 env->regs[0] = 0;
586 cpsr |= CPSR_C;
587 } else {
588 env->regs[0] = -1;
589 cpsr &= ~CPSR_C;
590 }
591 cpsr_write(env, cpsr, CPSR_C);
d5975363 592 end_exclusive();
fbb4a2e3
PB		 593 break;
594 case 0xffff0fe0: /* __kernel_get_tls */
595 env->regs[0] = env->cp15.c13_tls2;
596 break;
97cc7560
DDAG		 597 case 0xffff0f60: /* __kernel_cmpxchg64 */
598 arm_kernel_cmpxchg64_helper(env);
599 break;
600
fbb4a2e3
PB		 601 default:
602 return 1;
603 }
604 /* Jump back to the caller. */
605 addr = env->regs[14];
606 if (addr & 1) {
607 env->thumb = 1;
608 addr &= ~1;
609 }
610 env->regs[15] = addr;
611
612 return 0;
613}
614
426f5abc
PB		 615static int do_strex(CPUARMState *env)
616{
617 uint32_t val;
618 int size;
619 int rc = 1;
620 int segv = 0;
621 uint32_t addr;
622 start_exclusive();
623 addr = env->exclusive_addr;
624 if (addr != env->exclusive_test) {
625 goto fail;
626 }
627 size = env->exclusive_info & 0xf;
628 switch (size) {
629 case 0:
630 segv = get_user_u8(val, addr);
631 break;
632 case 1:
633 segv = get_user_u16(val, addr);
634 break;
635 case 2:
636 case 3:
637 segv = get_user_u32(val, addr);
638 break;
f7001a3b
AJ		 639 default:
640 abort();
426f5abc
PB		 641 }
642 if (segv) {
643 env->cp15.c6_data = addr;
644 goto done;
645 }
646 if (val != env->exclusive_val) {
647 goto fail;
648 }
649 if (size == 3) {
650 segv = get_user_u32(val, addr + 4);
651 if (segv) {
652 env->cp15.c6_data = addr + 4;
653 goto done;
654 }
655 if (val != env->exclusive_high) {
656 goto fail;
657 }
658 }
659 val = env->regs[(env->exclusive_info >> 8) & 0xf];
660 switch (size) {
661 case 0:
662 segv = put_user_u8(val, addr);
663 break;
664 case 1:
665 segv = put_user_u16(val, addr);
666 break;
667 case 2:
668 case 3:
669 segv = put_user_u32(val, addr);
670 break;
671 }
672 if (segv) {
673 env->cp15.c6_data = addr;
674 goto done;
675 }
676 if (size == 3) {
677 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 678 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 679 if (segv) {
680 env->cp15.c6_data = addr + 4;
681 goto done;
682 }
683 }
684 rc = 0;
685fail:
725b8a69 686 env->regs[15] += 4;
426f5abc
PB		 687 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
688done:
689 end_exclusive();
690 return segv;
691}
692
b346ff46
FB		 693void cpu_loop(CPUARMState *env)
694{
695 int trapnr;
696 unsigned int n, insn;
c227f099 697 target_siginfo_t info;
b5ff1b31 698 uint32_t addr;
3b46e624 699
b346ff46 700 for(;;) {
d5975363 701 cpu_exec_start(env);
b346ff46 702 trapnr = cpu_arm_exec(env);
d5975363 703 cpu_exec_end(env);
b346ff46
FB		 704 switch(trapnr) {
705 case EXCP_UDEF:
c6981055
FB		 706 {
707 TaskState *ts = env->opaque;
708 uint32_t opcode;
6d9a42be 709 int rc;
c6981055
FB		 710
711 /* we handle the FPU emulation here, as Linux */
712 /* we get the opcode */
2f619698 713 /* FIXME - what to do if get_user() fails? */
d8fd2954 714 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 715
6d9a42be
AJ		 716 rc = EmulateAll(opcode, &ts->fpa, env);
717 if (rc == 0) { /* illegal instruction */
c6981055
FB		 718 info.si_signo = SIGILL;
719 info.si_errno = 0;
720 info.si_code = TARGET_ILL_ILLOPN;
721 info._sifields._sigfault._addr = env->regs[15];
624f7979 722 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 723 } else if (rc < 0) { /* FP exception */
724 int arm_fpe=0;
725
726 /* translate softfloat flags to FPSR flags */
727 if (-rc & float_flag_invalid)
728 arm_fpe |= BIT_IOC;
729 if (-rc & float_flag_divbyzero)
730 arm_fpe |= BIT_DZC;
731 if (-rc & float_flag_overflow)
732 arm_fpe |= BIT_OFC;
733 if (-rc & float_flag_underflow)
734 arm_fpe |= BIT_UFC;
735 if (-rc & float_flag_inexact)
736 arm_fpe |= BIT_IXC;
737
738 FPSR fpsr = ts->fpa.fpsr;
739 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
740
741 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
742 info.si_signo = SIGFPE;
743 info.si_errno = 0;
744
745 /* ordered by priority, least first */
746 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
747 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
748 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
749 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
750 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
751
752 info._sifields._sigfault._addr = env->regs[15];
624f7979 753 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 754 } else {
755 env->regs[15] += 4;
756 }
757
758 /* accumulate unenabled exceptions */
759 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
760 fpsr |= BIT_IXC;
761 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
762 fpsr |= BIT_UFC;
763 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
764 fpsr |= BIT_OFC;
765 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
766 fpsr |= BIT_DZC;
767 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
768 fpsr |= BIT_IOC;
769 ts->fpa.fpsr=fpsr;
770 } else { /* everything OK */
c6981055
FB		 771 /* increment PC */
772 env->regs[15] += 4;
773 }
774 }
b346ff46
FB		 775 break;
776 case EXCP_SWI:
06c949e6 777 case EXCP_BKPT:
b346ff46 778 {
ce4defa0 779 env->eabi = 1;
b346ff46 780 /* system call */
06c949e6
PB		 781 if (trapnr == EXCP_BKPT) {
782 if (env->thumb) {
2f619698 783 /* FIXME - what to do if get_user() fails? */
d8fd2954 784 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 785 n = insn & 0xff;
786 env->regs[15] += 2;
787 } else {
2f619698 788 /* FIXME - what to do if get_user() fails? */
d8fd2954 789 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 790 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
791 env->regs[15] += 4;
792 }
192c7bd9 793 } else {
06c949e6 794 if (env->thumb) {
2f619698 795 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 796 get_user_code_u16(insn, env->regs[15] - 2,
797 env->bswap_code);
06c949e6
PB		 798 n = insn & 0xff;
799 } else {
2f619698 800 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 801 get_user_code_u32(insn, env->regs[15] - 4,
802 env->bswap_code);
06c949e6
PB		 803 n = insn & 0xffffff;
804 }
192c7bd9
FB		 805 }
806
6f1f31c0 807 if (n == ARM_NR_cacheflush) {
dcfd14b3 808 /* nop */
a4f81979
FB		 809 } else if (n == ARM_NR_semihosting
810 || n == ARM_NR_thumb_semihosting) {
811 env->regs[0] = do_arm_semihosting (env);
3a1363ac 812 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 813 /* linux syscall */
ce4defa0 814 if (env->thumb || n == 0) {
192c7bd9
FB		 815 n = env->regs[7];
816 } else {
817 n -= ARM_SYSCALL_BASE;
ce4defa0 818 env->eabi = 0;
192c7bd9 819 }
fbb4a2e3
PB		 820 if ( n > ARM_NR_BASE) {
821 switch (n) {
822 case ARM_NR_cacheflush:
dcfd14b3 823 /* nop */
fbb4a2e3
PB		 824 break;
825 case ARM_NR_set_tls:
826 cpu_set_tls(env, env->regs[0]);
827 env->regs[0] = 0;
828 break;
829 default:
830 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
831 n);
832 env->regs[0] = -TARGET_ENOSYS;
833 break;
834 }
835 } else {
836 env->regs[0] = do_syscall(env,
837 n,
838 env->regs[0],
839 env->regs[1],
840 env->regs[2],
841 env->regs[3],
842 env->regs[4],
5945cfcb
PM		 843 env->regs[5],
844 0, 0);
fbb4a2e3 845 }
b346ff46
FB		 846 } else {
847 goto error;
848 }
849 }
850 break;
43fff238
FB		 851 case EXCP_INTERRUPT:
852 /* just indicate that signals should be handled asap */
853 break;
68016c62 854 case EXCP_PREFETCH_ABORT:
eae473c1 855 addr = env->cp15.c6_insn;
b5ff1b31 856 goto do_segv;
68016c62 857 case EXCP_DATA_ABORT:
eae473c1 858 addr = env->cp15.c6_data;
b5ff1b31 859 do_segv:
68016c62
FB		 860 {
861 info.si_signo = SIGSEGV;
862 info.si_errno = 0;
863 /* XXX: check env->error_code */
864 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 865 info._sifields._sigfault._addr = addr;
624f7979 866 queue_signal(env, info.si_signo, &info);
68016c62
FB		 867 }
868 break;
1fddef4b
FB		 869 case EXCP_DEBUG:
870 {
871 int sig;
872
873 sig = gdb_handlesig (env, TARGET_SIGTRAP);
874 if (sig)
875 {
876 info.si_signo = sig;
877 info.si_errno = 0;
878 info.si_code = TARGET_TRAP_BRKPT;
624f7979 879 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 880 }
881 }
882 break;
fbb4a2e3
PB		 883 case EXCP_KERNEL_TRAP:
884 if (do_kernel_trap(env))
885 goto error;
886 break;
426f5abc
PB		 887 case EXCP_STREX:
888 if (do_strex(env)) {
889 addr = env->cp15.c6_data;
890 goto do_segv;
891 }
e9273455 892 break;
b346ff46
FB		 893 default:
894 error:
5fafdf24 895 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 896 trapnr);
7fe48483 897 cpu_dump_state(env, stderr, fprintf, 0);
b346ff46
FB		 898 abort();
899 }
900 process_pending_signals(env);
901 }
902}
903
904#endif
1b6b029e 905
d2fbca94
GX		 906#ifdef TARGET_UNICORE32
907
05390248 908void cpu_loop(CPUUniCore32State *env)
d2fbca94
GX		 909{
910 int trapnr;
911 unsigned int n, insn;
912 target_siginfo_t info;
913
914 for (;;) {
915 cpu_exec_start(env);
916 trapnr = uc32_cpu_exec(env);
917 cpu_exec_end(env);
918 switch (trapnr) {
919 case UC32_EXCP_PRIV:
920 {
921 /* system call */
922 get_user_u32(insn, env->regs[31] - 4);
923 n = insn & 0xffffff;
924
925 if (n >= UC32_SYSCALL_BASE) {
926 /* linux syscall */
927 n -= UC32_SYSCALL_BASE;
928 if (n == UC32_SYSCALL_NR_set_tls) {
929 cpu_set_tls(env, env->regs[0]);
930 env->regs[0] = 0;
931 } else {
932 env->regs[0] = do_syscall(env,
933 n,
934 env->regs[0],
935 env->regs[1],
936 env->regs[2],
937 env->regs[3],
938 env->regs[4],
5945cfcb
PM		 939 env->regs[5],
940 0, 0);
d2fbca94
GX		 941 }
942 } else {
943 goto error;
944 }
945 }
946 break;
d48813dd
GX		 947 case UC32_EXCP_DTRAP:
948 case UC32_EXCP_ITRAP:
d2fbca94
GX		 949 info.si_signo = SIGSEGV;
950 info.si_errno = 0;
951 /* XXX: check env->error_code */
952 info.si_code = TARGET_SEGV_MAPERR;
953 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
954 queue_signal(env, info.si_signo, &info);
955 break;
956 case EXCP_INTERRUPT:
957 /* just indicate that signals should be handled asap */
958 break;
959 case EXCP_DEBUG:
960 {
961 int sig;
962
963 sig = gdb_handlesig(env, TARGET_SIGTRAP);
964 if (sig) {
965 info.si_signo = sig;
966 info.si_errno = 0;
967 info.si_code = TARGET_TRAP_BRKPT;
968 queue_signal(env, info.si_signo, &info);
969 }
970 }
971 break;
972 default:
973 goto error;
974 }
975 process_pending_signals(env);
976 }
977
978error:
979 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
980 cpu_dump_state(env, stderr, fprintf, 0);
981 abort();
982}
983#endif
984
93ac68bc 985#ifdef TARGET_SPARC
ed23fbd9 986#define SPARC64_STACK_BIAS 2047
93ac68bc 987
060366c5
FB		 988//#define DEBUG_WIN
989
2623cbaf
FB		 990/* WARNING: dealing with register windows _is_ complicated. More info
991 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 992static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
993{
1a14026e 994 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 995 /* wrap handling : if cwp is on the last window, then we use the
996 registers 'after' the end */
1a14026e
BS		 997 if (index < 8 && env->cwp == env->nwindows - 1)
998 index += 16 * env->nwindows;
060366c5
FB		 999 return index;
1000}
1001
2623cbaf
FB		 1002/* save the register window 'cwp1' */
1003static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1004{
2623cbaf 1005 unsigned int i;
992f48a0 1006 abi_ulong sp_ptr;
3b46e624 1007
53a5960a 1008 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1009#ifdef TARGET_SPARC64
1010 if (sp_ptr & 3)
1011 sp_ptr += SPARC64_STACK_BIAS;
1012#endif
060366c5 1013#if defined(DEBUG_WIN)
2daf0284
BS		 1014 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1015 sp_ptr, cwp1);
060366c5 1016#endif
2623cbaf 1017 for(i = 0; i < 16; i++) {
2f619698
FB		 1018 /* FIXME - what to do if put_user() fails? */
1019 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1020 sp_ptr += sizeof(abi_ulong);
2623cbaf 1021 }
060366c5
FB		 1022}
1023
1024static void save_window(CPUSPARCState *env)
1025{
5ef54116 1026#ifndef TARGET_SPARC64
2623cbaf 1027 unsigned int new_wim;
1a14026e
BS		 1028 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1029 ((1LL << env->nwindows) - 1);
1030 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1031 env->wim = new_wim;
5ef54116 1032#else
1a14026e 1033 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1034 env->cansave++;
1035 env->canrestore--;
1036#endif
060366c5
FB		 1037}
1038
1039static void restore_window(CPUSPARCState *env)
1040{
eda52953
BS		 1041#ifndef TARGET_SPARC64
1042 unsigned int new_wim;
1043#endif
1044 unsigned int i, cwp1;
992f48a0 1045 abi_ulong sp_ptr;
3b46e624 1046
eda52953 1047#ifndef TARGET_SPARC64
1a14026e
BS		 1048 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1049 ((1LL << env->nwindows) - 1);
eda52953 1050#endif
3b46e624 1051
060366c5 1052 /* restore the invalid window */
1a14026e 1053 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1054 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1055#ifdef TARGET_SPARC64
1056 if (sp_ptr & 3)
1057 sp_ptr += SPARC64_STACK_BIAS;
1058#endif
060366c5 1059#if defined(DEBUG_WIN)
2daf0284
BS		 1060 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1061 sp_ptr, cwp1);
060366c5 1062#endif
2623cbaf 1063 for(i = 0; i < 16; i++) {
2f619698
FB		 1064 /* FIXME - what to do if get_user() fails? */
1065 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1066 sp_ptr += sizeof(abi_ulong);
2623cbaf 1067 }
5ef54116
FB		 1068#ifdef TARGET_SPARC64
1069 env->canrestore++;
1a14026e
BS		 1070 if (env->cleanwin < env->nwindows - 1)
1071 env->cleanwin++;
5ef54116 1072 env->cansave--;
eda52953
BS		 1073#else
1074 env->wim = new_wim;
5ef54116 1075#endif
060366c5
FB		 1076}
1077
1078static void flush_windows(CPUSPARCState *env)
1079{
1080 int offset, cwp1;
2623cbaf
FB		 1081
1082 offset = 1;
060366c5
FB		 1083 for(;;) {
1084 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1085 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1086#ifndef TARGET_SPARC64
060366c5
FB		 1087 if (env->wim & (1 << cwp1))
1088 break;
eda52953
BS		 1089#else
1090 if (env->canrestore == 0)
1091 break;
1092 env->cansave++;
1093 env->canrestore--;
1094#endif
2623cbaf 1095 save_window_offset(env, cwp1);
060366c5
FB		 1096 offset++;
1097 }
1a14026e 1098 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1099#ifndef TARGET_SPARC64
1100 /* set wim so that restore will reload the registers */
2623cbaf 1101 env->wim = 1 << cwp1;
eda52953 1102#endif
2623cbaf
FB		 1103#if defined(DEBUG_WIN)
1104 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1105#endif
2623cbaf 1106}
060366c5 1107
93ac68bc
FB		 1108void cpu_loop (CPUSPARCState *env)
1109{
2cc20260
RH		 1110 int trapnr;
1111 abi_long ret;
c227f099 1112 target_siginfo_t info;
3b46e624 1113
060366c5
FB		 1114 while (1) {
1115 trapnr = cpu_sparc_exec (env);
3b46e624 1116
20132b96
RH		 1117 /* Compute PSR before exposing state. */
1118 if (env->cc_op != CC_OP_FLAGS) {
1119 cpu_get_psr(env);
1120 }
1121
060366c5 1122 switch (trapnr) {
5ef54116 1123#ifndef TARGET_SPARC64
5fafdf24 1124 case 0x88:
060366c5 1125 case 0x90:
5ef54116 1126#else
cb33da57 1127 case 0x110:
5ef54116
FB		 1128 case 0x16d:
1129#endif
060366c5 1130 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1131 env->regwptr[0], env->regwptr[1],
1132 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1133 env->regwptr[4], env->regwptr[5],
1134 0, 0);
2cc20260 1135 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1136#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1137 env->xcc |= PSR_CARRY;
1138#else
060366c5 1139 env->psr |= PSR_CARRY;
27908725 1140#endif
060366c5
FB		 1141 ret = -ret;
1142 } else {
992f48a0 1143#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1144 env->xcc &= ~PSR_CARRY;
1145#else
060366c5 1146 env->psr &= ~PSR_CARRY;
27908725 1147#endif
060366c5
FB		 1148 }
1149 env->regwptr[0] = ret;
1150 /* next instruction */
1151 env->pc = env->npc;
1152 env->npc = env->npc + 4;
1153 break;
1154 case 0x83: /* flush windows */
992f48a0
BS		 1155#ifdef TARGET_ABI32
1156 case 0x103:
1157#endif
2623cbaf 1158 flush_windows(env);
060366c5
FB		 1159 /* next instruction */
1160 env->pc = env->npc;
1161 env->npc = env->npc + 4;
1162 break;
3475187d 1163#ifndef TARGET_SPARC64
060366c5
FB		 1164 case TT_WIN_OVF: /* window overflow */
1165 save_window(env);
1166 break;
1167 case TT_WIN_UNF: /* window underflow */
1168 restore_window(env);
1169 break;
61ff6f58
FB		 1170 case TT_TFAULT:
1171 case TT_DFAULT:
1172 {
59f7182f 1173 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1174 info.si_errno = 0;
1175 /* XXX: check env->error_code */
1176 info.si_code = TARGET_SEGV_MAPERR;
1177 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1178 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1179 }
1180 break;
3475187d 1181#else
5ef54116
FB		 1182 case TT_SPILL: /* window overflow */
1183 save_window(env);
1184 break;
1185 case TT_FILL: /* window underflow */
1186 restore_window(env);
1187 break;
7f84a729
BS		 1188 case TT_TFAULT:
1189 case TT_DFAULT:
1190 {
59f7182f 1191 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1192 info.si_errno = 0;
1193 /* XXX: check env->error_code */
1194 info.si_code = TARGET_SEGV_MAPERR;
1195 if (trapnr == TT_DFAULT)
1196 info._sifields._sigfault._addr = env->dmmuregs[4];
1197 else
8194f35a 1198 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1199 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1200 }
1201 break;
27524dc3 1202#ifndef TARGET_ABI32
5bfb56b2
BS		 1203 case 0x16e:
1204 flush_windows(env);
1205 sparc64_get_context(env);
1206 break;
1207 case 0x16f:
1208 flush_windows(env);
1209 sparc64_set_context(env);
1210 break;
27524dc3 1211#endif
3475187d 1212#endif
48dc41eb
FB		 1213 case EXCP_INTERRUPT:
1214 /* just indicate that signals should be handled asap */
1215 break;
75f22e4e
RH		 1216 case TT_ILL_INSN:
1217 {
1218 info.si_signo = TARGET_SIGILL;
1219 info.si_errno = 0;
1220 info.si_code = TARGET_ILL_ILLOPC;
1221 info._sifields._sigfault._addr = env->pc;
1222 queue_signal(env, info.si_signo, &info);
1223 }
1224 break;
1fddef4b
FB		 1225 case EXCP_DEBUG:
1226 {
1227 int sig;
1228
1229 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1230 if (sig)
1231 {
1232 info.si_signo = sig;
1233 info.si_errno = 0;
1234 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1235 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1236 }
1237 }
1238 break;
060366c5
FB		 1239 default:
1240 printf ("Unhandled trap: 0x%x\n", trapnr);
7fe48483 1241 cpu_dump_state(env, stderr, fprintf, 0);
060366c5
FB		 1242 exit (1);
1243 }
1244 process_pending_signals (env);
1245 }
93ac68bc
FB		 1246}
1247
1248#endif
1249
67867308 1250#ifdef TARGET_PPC
05390248 1251static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1252{
1253 /* TO FIX */
1254 return 0;
1255}
3b46e624 1256
05390248 1257uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1258{
e3ea6529 1259 return cpu_ppc_get_tb(env);
9fddaa0c 1260}
3b46e624 1261
05390248 1262uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1263{
1264 return cpu_ppc_get_tb(env) >> 32;
1265}
3b46e624 1266
05390248 1267uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1268{
b711de95 1269 return cpu_ppc_get_tb(env);
9fddaa0c 1270}
5fafdf24 1271
05390248 1272uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1273{
a062e36c 1274 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1275}
76a66253 1276
05390248 1277uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1278__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1279
05390248 1280uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1281{
76a66253 1282 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1283}
76a66253 1284
a750fc0b 1285/* XXX: to be fixed */
73b01960 1286int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1287{
1288 return -1;
1289}
1290
73b01960 1291int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1292{
1293 return -1;
1294}
1295
001faf32
BS		 1296#define EXCP_DUMP(env, fmt, ...) \
1297do { \
1298 fprintf(stderr, fmt , ## __VA_ARGS__); \
1299 cpu_dump_state(env, stderr, fprintf, 0); \
1300 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1301 if (qemu_log_enabled()) { \
430c7ec7 1302 log_cpu_state(env, 0); \
eeacee4d 1303 } \
e1833e1f
JM		 1304} while (0)
1305
56f066bb
NF		 1306static int do_store_exclusive(CPUPPCState *env)
1307{
1308 target_ulong addr;
1309 target_ulong page_addr;
1310 target_ulong val;
1311 int flags;
1312 int segv = 0;
1313
1314 addr = env->reserve_ea;
1315 page_addr = addr & TARGET_PAGE_MASK;
1316 start_exclusive();
1317 mmap_lock();
1318 flags = page_get_flags(page_addr);
1319 if ((flags & PAGE_READ) == 0) {
1320 segv = 1;
1321 } else {
1322 int reg = env->reserve_info & 0x1f;
1323 int size = (env->reserve_info >> 5) & 0xf;
1324 int stored = 0;
1325
1326 if (addr == env->reserve_addr) {
1327 switch (size) {
1328 case 1: segv = get_user_u8(val, addr); break;
1329 case 2: segv = get_user_u16(val, addr); break;
1330 case 4: segv = get_user_u32(val, addr); break;
1331#if defined(TARGET_PPC64)
1332 case 8: segv = get_user_u64(val, addr); break;
1333#endif
1334 default: abort();
1335 }
1336 if (!segv && val == env->reserve_val) {
1337 val = env->gpr[reg];
1338 switch (size) {
1339 case 1: segv = put_user_u8(val, addr); break;
1340 case 2: segv = put_user_u16(val, addr); break;
1341 case 4: segv = put_user_u32(val, addr); break;
1342#if defined(TARGET_PPC64)
1343 case 8: segv = put_user_u64(val, addr); break;
1344#endif
1345 default: abort();
1346 }
1347 if (!segv) {
1348 stored = 1;
1349 }
1350 }
1351 }
1352 env->crf[0] = (stored << 1) | xer_so;
1353 env->reserve_addr = (target_ulong)-1;
1354 }
1355 if (!segv) {
1356 env->nip += 4;
1357 }
1358 mmap_unlock();
1359 end_exclusive();
1360 return segv;
1361}
1362
67867308
FB		 1363void cpu_loop(CPUPPCState *env)
1364{
c227f099 1365 target_siginfo_t info;
61190b14 1366 int trapnr;
9e0e2f96 1367 target_ulong ret;
3b46e624 1368
67867308 1369 for(;;) {
56f066bb 1370 cpu_exec_start(env);
67867308 1371 trapnr = cpu_ppc_exec(env);
56f066bb 1372 cpu_exec_end(env);
67867308 1373 switch(trapnr) {
e1833e1f
JM		 1374 case POWERPC_EXCP_NONE:
1375 /* Just go on */
67867308 1376 break;
e1833e1f
JM		 1377 case POWERPC_EXCP_CRITICAL: /* Critical input */
1378 cpu_abort(env, "Critical interrupt while in user mode. "
1379 "Aborting\n");
61190b14 1380 break;
e1833e1f
JM		 1381 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1382 cpu_abort(env, "Machine check exception while in user mode. "
1383 "Aborting\n");
1384 break;
1385 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1386 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1387 env->spr[SPR_DAR]);
1388 /* XXX: check this. Seems bugged */
2be0071f
FB		 1389 switch (env->error_code & 0xFF000000) {
1390 case 0x40000000:
61190b14
FB		 1391 info.si_signo = TARGET_SIGSEGV;
1392 info.si_errno = 0;
1393 info.si_code = TARGET_SEGV_MAPERR;
1394 break;
2be0071f 1395 case 0x04000000:
61190b14
FB		 1396 info.si_signo = TARGET_SIGILL;
1397 info.si_errno = 0;
1398 info.si_code = TARGET_ILL_ILLADR;
1399 break;
2be0071f 1400 case 0x08000000:
61190b14
FB		 1401 info.si_signo = TARGET_SIGSEGV;
1402 info.si_errno = 0;
1403 info.si_code = TARGET_SEGV_ACCERR;
1404 break;
61190b14
FB		 1405 default:
1406 /* Let's send a regular segfault... */
e1833e1f
JM		 1407 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1408 env->error_code);
61190b14
FB		 1409 info.si_signo = TARGET_SIGSEGV;
1410 info.si_errno = 0;
1411 info.si_code = TARGET_SEGV_MAPERR;
1412 break;
1413 }
67867308 1414 info._sifields._sigfault._addr = env->nip;
624f7979 1415 queue_signal(env, info.si_signo, &info);
67867308 1416 break;
e1833e1f 1417 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1418 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1419 "\n", env->spr[SPR_SRR0]);
e1833e1f 1420 /* XXX: check this */
2be0071f
FB		 1421 switch (env->error_code & 0xFF000000) {
1422 case 0x40000000:
61190b14 1423 info.si_signo = TARGET_SIGSEGV;
67867308 1424 info.si_errno = 0;
61190b14
FB		 1425 info.si_code = TARGET_SEGV_MAPERR;
1426 break;
2be0071f
FB		 1427 case 0x10000000:
1428 case 0x08000000:
61190b14
FB		 1429 info.si_signo = TARGET_SIGSEGV;
1430 info.si_errno = 0;
1431 info.si_code = TARGET_SEGV_ACCERR;
1432 break;
1433 default:
1434 /* Let's send a regular segfault... */
e1833e1f
JM		 1435 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1436 env->error_code);
61190b14
FB		 1437 info.si_signo = TARGET_SIGSEGV;
1438 info.si_errno = 0;
1439 info.si_code = TARGET_SEGV_MAPERR;
1440 break;
1441 }
1442 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1443 queue_signal(env, info.si_signo, &info);
67867308 1444 break;
e1833e1f
JM		 1445 case POWERPC_EXCP_EXTERNAL: /* External input */
1446 cpu_abort(env, "External interrupt while in user mode. "
1447 "Aborting\n");
1448 break;
1449 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1450 EXCP_DUMP(env, "Unaligned memory access\n");
1451 /* XXX: check this */
61190b14 1452 info.si_signo = TARGET_SIGBUS;
67867308 1453 info.si_errno = 0;
61190b14
FB		 1454 info.si_code = TARGET_BUS_ADRALN;
1455 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1456 queue_signal(env, info.si_signo, &info);
67867308 1457 break;
e1833e1f
JM		 1458 case POWERPC_EXCP_PROGRAM: /* Program exception */
1459 /* XXX: check this */
61190b14 1460 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1461 case POWERPC_EXCP_FP:
1462 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1463 info.si_signo = TARGET_SIGFPE;
1464 info.si_errno = 0;
1465 switch (env->error_code & 0xF) {
e1833e1f 1466 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1467 info.si_code = TARGET_FPE_FLTOVF;
1468 break;
e1833e1f 1469 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1470 info.si_code = TARGET_FPE_FLTUND;
1471 break;
e1833e1f
JM		 1472 case POWERPC_EXCP_FP_ZX:
1473 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1474 info.si_code = TARGET_FPE_FLTDIV;
1475 break;
e1833e1f 1476 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1477 info.si_code = TARGET_FPE_FLTRES;
1478 break;
e1833e1f 1479 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1480 info.si_code = TARGET_FPE_FLTINV;
1481 break;
7c58044c 1482 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1483 case POWERPC_EXCP_FP_VXISI:
1484 case POWERPC_EXCP_FP_VXIDI:
1485 case POWERPC_EXCP_FP_VXIMZ:
1486 case POWERPC_EXCP_FP_VXVC:
1487 case POWERPC_EXCP_FP_VXSQRT:
1488 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1489 info.si_code = TARGET_FPE_FLTSUB;
1490 break;
1491 default:
e1833e1f
JM		 1492 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1493 env->error_code);
1494 break;
61190b14 1495 }
e1833e1f
JM		 1496 break;
1497 case POWERPC_EXCP_INVAL:
1498 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1499 info.si_signo = TARGET_SIGILL;
1500 info.si_errno = 0;
1501 switch (env->error_code & 0xF) {
e1833e1f 1502 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1503 info.si_code = TARGET_ILL_ILLOPC;
1504 break;
e1833e1f 1505 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1506 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1507 break;
e1833e1f 1508 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1509 info.si_code = TARGET_ILL_PRVREG;
1510 break;
e1833e1f 1511 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1512 info.si_code = TARGET_ILL_COPROC;
1513 break;
1514 default:
e1833e1f
JM		 1515 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1516 env->error_code & 0xF);
61190b14
FB		 1517 info.si_code = TARGET_ILL_ILLADR;
1518 break;
1519 }
1520 break;
e1833e1f
JM		 1521 case POWERPC_EXCP_PRIV:
1522 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1523 info.si_signo = TARGET_SIGILL;
1524 info.si_errno = 0;
1525 switch (env->error_code & 0xF) {
e1833e1f 1526 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1527 info.si_code = TARGET_ILL_PRVOPC;
1528 break;
e1833e1f 1529 case POWERPC_EXCP_PRIV_REG:
61190b14 1530 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1531 break;
61190b14 1532 default:
e1833e1f
JM		 1533 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1534 env->error_code & 0xF);
61190b14
FB		 1535 info.si_code = TARGET_ILL_PRVOPC;
1536 break;
1537 }
1538 break;
e1833e1f
JM		 1539 case POWERPC_EXCP_TRAP:
1540 cpu_abort(env, "Tried to call a TRAP\n");
1541 break;
61190b14
FB		 1542 default:
1543 /* Should not happen ! */
e1833e1f
JM		 1544 cpu_abort(env, "Unknown program exception (%02x)\n",
1545 env->error_code);
1546 break;
61190b14
FB		 1547 }
1548 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1549 queue_signal(env, info.si_signo, &info);
67867308 1550 break;
e1833e1f
JM		 1551 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1552 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1553 info.si_signo = TARGET_SIGILL;
67867308 1554 info.si_errno = 0;
61190b14
FB		 1555 info.si_code = TARGET_ILL_COPROC;
1556 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1557 queue_signal(env, info.si_signo, &info);
67867308 1558 break;
e1833e1f
JM		 1559 case POWERPC_EXCP_SYSCALL: /* System call exception */
1560 cpu_abort(env, "Syscall exception while in user mode. "
1561 "Aborting\n");
61190b14 1562 break;
e1833e1f
JM		 1563 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1564 EXCP_DUMP(env, "No APU instruction allowed\n");
1565 info.si_signo = TARGET_SIGILL;
1566 info.si_errno = 0;
1567 info.si_code = TARGET_ILL_COPROC;
1568 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1569 queue_signal(env, info.si_signo, &info);
61190b14 1570 break;
e1833e1f
JM		 1571 case POWERPC_EXCP_DECR: /* Decrementer exception */
1572 cpu_abort(env, "Decrementer interrupt while in user mode. "
1573 "Aborting\n");
61190b14 1574 break;
e1833e1f
JM		 1575 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1576 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1577 "Aborting\n");
1578 break;
1579 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1580 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_DTLB: /* Data TLB error */
1584 cpu_abort(env, "Data TLB exception while in user mode. "
1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1588 cpu_abort(env, "Instruction TLB exception while in user mode. "
1589 "Aborting\n");
1590 break;
e1833e1f
JM		 1591 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1592 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1593 info.si_signo = TARGET_SIGILL;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_ILL_COPROC;
1596 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1597 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1598 break;
1599 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1600 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1601 break;
1602 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1603 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1604 break;
1605 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1606 cpu_abort(env, "Performance monitor exception not handled\n");
1607 break;
1608 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1609 cpu_abort(env, "Doorbell interrupt while in user mode. "
1610 "Aborting\n");
1611 break;
1612 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1613 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1614 "Aborting\n");
1615 break;
1616 case POWERPC_EXCP_RESET: /* System reset exception */
1617 cpu_abort(env, "Reset interrupt while in user mode. "
1618 "Aborting\n");
1619 break;
e1833e1f
JM		 1620 case POWERPC_EXCP_DSEG: /* Data segment exception */
1621 cpu_abort(env, "Data segment exception while in user mode. "
1622 "Aborting\n");
1623 break;
1624 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1625 cpu_abort(env, "Instruction segment exception "
1626 "while in user mode. Aborting\n");
1627 break;
e85e7c6e 1628 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1629 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1630 cpu_abort(env, "Hypervisor decrementer interrupt "
1631 "while in user mode. Aborting\n");
1632 break;
e1833e1f
JM		 1633 case POWERPC_EXCP_TRACE: /* Trace exception */
1634 /* Nothing to do:
1635 * we use this exception to emulate step-by-step execution mode.
1636 */
1637 break;
e85e7c6e 1638 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1639 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1640 cpu_abort(env, "Hypervisor data storage exception "
1641 "while in user mode. Aborting\n");
1642 break;
1643 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1644 cpu_abort(env, "Hypervisor instruction storage exception "
1645 "while in user mode. Aborting\n");
1646 break;
1647 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1648 cpu_abort(env, "Hypervisor data segment exception "
1649 "while in user mode. Aborting\n");
1650 break;
1651 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1652 cpu_abort(env, "Hypervisor instruction segment exception "
1653 "while in user mode. Aborting\n");
1654 break;
e1833e1f
JM		 1655 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1656 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1657 info.si_signo = TARGET_SIGILL;
1658 info.si_errno = 0;
1659 info.si_code = TARGET_ILL_COPROC;
1660 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1661 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1662 break;
1663 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1664 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1665 "while in user mode. Aborting\n");
1666 break;
1667 case POWERPC_EXCP_IO: /* IO error exception */
1668 cpu_abort(env, "IO error exception while in user mode. "
1669 "Aborting\n");
1670 break;
1671 case POWERPC_EXCP_RUNM: /* Run mode exception */
1672 cpu_abort(env, "Run mode exception while in user mode. "
1673 "Aborting\n");
1674 break;
1675 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1676 cpu_abort(env, "Emulation trap exception not handled\n");
1677 break;
1678 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1679 cpu_abort(env, "Instruction fetch TLB exception "
1680 "while in user-mode. Aborting");
1681 break;
1682 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1683 cpu_abort(env, "Data load TLB exception while in user-mode. "
1684 "Aborting");
1685 break;
1686 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1687 cpu_abort(env, "Data store TLB exception while in user-mode. "
1688 "Aborting");
1689 break;
1690 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1691 cpu_abort(env, "Floating-point assist exception not handled\n");
1692 break;
1693 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1694 cpu_abort(env, "Instruction address breakpoint exception "
1695 "not handled\n");
1696 break;
1697 case POWERPC_EXCP_SMI: /* System management interrupt */
1698 cpu_abort(env, "System management interrupt while in user mode. "
1699 "Aborting\n");
1700 break;
1701 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1702 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1703 "Aborting\n");
1704 break;
1705 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1706 cpu_abort(env, "Performance monitor exception not handled\n");
1707 break;
1708 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1709 cpu_abort(env, "Vector assist exception not handled\n");
1710 break;
1711 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1712 cpu_abort(env, "Soft patch exception not handled\n");
1713 break;
1714 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1715 cpu_abort(env, "Maintenance exception while in user mode. "
1716 "Aborting\n");
1717 break;
1718 case POWERPC_EXCP_STOP: /* stop translation */
1719 /* We did invalidate the instruction cache. Go on */
1720 break;
1721 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1722 /* We just stopped because of a branch. Go on */
1723 break;
1724 case POWERPC_EXCP_SYSCALL_USER:
1725 /* system call in user-mode emulation */
1726 /* WARNING:
1727 * PPC ABI uses overflow flag in cr0 to signal an error
1728 * in syscalls.
1729 */
e1833e1f
JM		 1730 env->crf[0] &= ~0x1;
1731 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1732 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1733 env->gpr[8], 0, 0);
9e0e2f96 1734 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1735 /* Returning from a successful sigreturn syscall.
1736 Avoid corrupting register state. */
1737 break;
1738 }
9e0e2f96 1739 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1740 env->crf[0] |= 0x1;
1741 ret = -ret;
61190b14 1742 }
e1833e1f 1743 env->gpr[3] = ret;
e1833e1f 1744 break;
56f066bb
NF		 1745 case POWERPC_EXCP_STCX:
1746 if (do_store_exclusive(env)) {
1747 info.si_signo = TARGET_SIGSEGV;
1748 info.si_errno = 0;
1749 info.si_code = TARGET_SEGV_MAPERR;
1750 info._sifields._sigfault._addr = env->nip;
1751 queue_signal(env, info.si_signo, &info);
1752 }
1753 break;
71f75756
AJ		 1754 case EXCP_DEBUG:
1755 {
1756 int sig;
1757
1758 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1759 if (sig) {
1760 info.si_signo = sig;
1761 info.si_errno = 0;
1762 info.si_code = TARGET_TRAP_BRKPT;
1763 queue_signal(env, info.si_signo, &info);
1764 }
1765 }
1766 break;
56ba31ff
JM		 1767 case EXCP_INTERRUPT:
1768 /* just indicate that signals should be handled asap */
1769 break;
e1833e1f
JM		 1770 default:
1771 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1772 break;
67867308
FB		 1773 }
1774 process_pending_signals(env);
1775 }
1776}
1777#endif
1778
048f6b4d
FB		 1779#ifdef TARGET_MIPS
1780
1781#define MIPS_SYS(name, args) args,
1782
1783static const uint8_t mips_syscall_args[] = {
29fb0f25 1784 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1785 MIPS_SYS(sys_exit , 1)
1786 MIPS_SYS(sys_fork , 0)
1787 MIPS_SYS(sys_read , 3)
1788 MIPS_SYS(sys_write , 3)
1789 MIPS_SYS(sys_open , 3) /* 4005 */
1790 MIPS_SYS(sys_close , 1)
1791 MIPS_SYS(sys_waitpid , 3)
1792 MIPS_SYS(sys_creat , 2)
1793 MIPS_SYS(sys_link , 2)
1794 MIPS_SYS(sys_unlink , 1) /* 4010 */
1795 MIPS_SYS(sys_execve , 0)
1796 MIPS_SYS(sys_chdir , 1)
1797 MIPS_SYS(sys_time , 1)
1798 MIPS_SYS(sys_mknod , 3)
1799 MIPS_SYS(sys_chmod , 2) /* 4015 */
1800 MIPS_SYS(sys_lchown , 3)
1801 MIPS_SYS(sys_ni_syscall , 0)
1802 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1803 MIPS_SYS(sys_lseek , 3)
1804 MIPS_SYS(sys_getpid , 0) /* 4020 */
1805 MIPS_SYS(sys_mount , 5)
1806 MIPS_SYS(sys_oldumount , 1)
1807 MIPS_SYS(sys_setuid , 1)
1808 MIPS_SYS(sys_getuid , 0)
1809 MIPS_SYS(sys_stime , 1) /* 4025 */
1810 MIPS_SYS(sys_ptrace , 4)
1811 MIPS_SYS(sys_alarm , 1)
1812 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1813 MIPS_SYS(sys_pause , 0)
1814 MIPS_SYS(sys_utime , 2) /* 4030 */
1815 MIPS_SYS(sys_ni_syscall , 0)
1816 MIPS_SYS(sys_ni_syscall , 0)
1817 MIPS_SYS(sys_access , 2)
1818 MIPS_SYS(sys_nice , 1)
1819 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1820 MIPS_SYS(sys_sync , 0)
1821 MIPS_SYS(sys_kill , 2)
1822 MIPS_SYS(sys_rename , 2)
1823 MIPS_SYS(sys_mkdir , 2)
1824 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1825 MIPS_SYS(sys_dup , 1)
1826 MIPS_SYS(sys_pipe , 0)
1827 MIPS_SYS(sys_times , 1)
1828 MIPS_SYS(sys_ni_syscall , 0)
1829 MIPS_SYS(sys_brk , 1) /* 4045 */
1830 MIPS_SYS(sys_setgid , 1)
1831 MIPS_SYS(sys_getgid , 0)
1832 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1833 MIPS_SYS(sys_geteuid , 0)
1834 MIPS_SYS(sys_getegid , 0) /* 4050 */
1835 MIPS_SYS(sys_acct , 0)
1836 MIPS_SYS(sys_umount , 2)
1837 MIPS_SYS(sys_ni_syscall , 0)
1838 MIPS_SYS(sys_ioctl , 3)
1839 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1840 MIPS_SYS(sys_ni_syscall , 2)
1841 MIPS_SYS(sys_setpgid , 2)
1842 MIPS_SYS(sys_ni_syscall , 0)
1843 MIPS_SYS(sys_olduname , 1)
1844 MIPS_SYS(sys_umask , 1) /* 4060 */
1845 MIPS_SYS(sys_chroot , 1)
1846 MIPS_SYS(sys_ustat , 2)
1847 MIPS_SYS(sys_dup2 , 2)
1848 MIPS_SYS(sys_getppid , 0)
1849 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1850 MIPS_SYS(sys_setsid , 0)
1851 MIPS_SYS(sys_sigaction , 3)
1852 MIPS_SYS(sys_sgetmask , 0)
1853 MIPS_SYS(sys_ssetmask , 1)
1854 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1855 MIPS_SYS(sys_setregid , 2)
1856 MIPS_SYS(sys_sigsuspend , 0)
1857 MIPS_SYS(sys_sigpending , 1)
1858 MIPS_SYS(sys_sethostname , 2)
1859 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1860 MIPS_SYS(sys_getrlimit , 2)
1861 MIPS_SYS(sys_getrusage , 2)
1862 MIPS_SYS(sys_gettimeofday, 2)
1863 MIPS_SYS(sys_settimeofday, 2)
1864 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1865 MIPS_SYS(sys_setgroups , 2)
1866 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1867 MIPS_SYS(sys_symlink , 2)
1868 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1869 MIPS_SYS(sys_readlink , 3) /* 4085 */
1870 MIPS_SYS(sys_uselib , 1)
1871 MIPS_SYS(sys_swapon , 2)
1872 MIPS_SYS(sys_reboot , 3)
1873 MIPS_SYS(old_readdir , 3)
1874 MIPS_SYS(old_mmap , 6) /* 4090 */
1875 MIPS_SYS(sys_munmap , 2)
1876 MIPS_SYS(sys_truncate , 2)
1877 MIPS_SYS(sys_ftruncate , 2)
1878 MIPS_SYS(sys_fchmod , 2)
1879 MIPS_SYS(sys_fchown , 3) /* 4095 */
1880 MIPS_SYS(sys_getpriority , 2)
1881 MIPS_SYS(sys_setpriority , 3)
1882 MIPS_SYS(sys_ni_syscall , 0)
1883 MIPS_SYS(sys_statfs , 2)
1884 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1885 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1886 MIPS_SYS(sys_socketcall , 2)
1887 MIPS_SYS(sys_syslog , 3)
1888 MIPS_SYS(sys_setitimer , 3)
1889 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1890 MIPS_SYS(sys_newstat , 2)
1891 MIPS_SYS(sys_newlstat , 2)
1892 MIPS_SYS(sys_newfstat , 2)
1893 MIPS_SYS(sys_uname , 1)
1894 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1895 MIPS_SYS(sys_vhangup , 0)
1896 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1897 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1898 MIPS_SYS(sys_wait4 , 4)
1899 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1900 MIPS_SYS(sys_sysinfo , 1)
1901 MIPS_SYS(sys_ipc , 6)
1902 MIPS_SYS(sys_fsync , 1)
1903 MIPS_SYS(sys_sigreturn , 0)
18113962 1904 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1905 MIPS_SYS(sys_setdomainname, 2)
1906 MIPS_SYS(sys_newuname , 1)
1907 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1908 MIPS_SYS(sys_adjtimex , 1)
1909 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1910 MIPS_SYS(sys_sigprocmask , 3)
1911 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1912 MIPS_SYS(sys_init_module , 5)
1913 MIPS_SYS(sys_delete_module, 1)
1914 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1915 MIPS_SYS(sys_quotactl , 0)
1916 MIPS_SYS(sys_getpgid , 1)
1917 MIPS_SYS(sys_fchdir , 1)
1918 MIPS_SYS(sys_bdflush , 2)
1919 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1920 MIPS_SYS(sys_personality , 1)
1921 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1922 MIPS_SYS(sys_setfsuid , 1)
1923 MIPS_SYS(sys_setfsgid , 1)
1924 MIPS_SYS(sys_llseek , 5) /* 4140 */
1925 MIPS_SYS(sys_getdents , 3)
1926 MIPS_SYS(sys_select , 5)
1927 MIPS_SYS(sys_flock , 2)
1928 MIPS_SYS(sys_msync , 3)
1929 MIPS_SYS(sys_readv , 3) /* 4145 */
1930 MIPS_SYS(sys_writev , 3)
1931 MIPS_SYS(sys_cacheflush , 3)
1932 MIPS_SYS(sys_cachectl , 3)
1933 MIPS_SYS(sys_sysmips , 4)
1934 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1935 MIPS_SYS(sys_getsid , 1)
1936 MIPS_SYS(sys_fdatasync , 0)
1937 MIPS_SYS(sys_sysctl , 1)
1938 MIPS_SYS(sys_mlock , 2)
1939 MIPS_SYS(sys_munlock , 2) /* 4155 */
1940 MIPS_SYS(sys_mlockall , 1)
1941 MIPS_SYS(sys_munlockall , 0)
1942 MIPS_SYS(sys_sched_setparam, 2)
1943 MIPS_SYS(sys_sched_getparam, 2)
1944 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1945 MIPS_SYS(sys_sched_getscheduler, 1)
1946 MIPS_SYS(sys_sched_yield , 0)
1947 MIPS_SYS(sys_sched_get_priority_max, 1)
1948 MIPS_SYS(sys_sched_get_priority_min, 1)
1949 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1950 MIPS_SYS(sys_nanosleep, 2)
1951 MIPS_SYS(sys_mremap , 4)
1952 MIPS_SYS(sys_accept , 3)
1953 MIPS_SYS(sys_bind , 3)
1954 MIPS_SYS(sys_connect , 3) /* 4170 */
1955 MIPS_SYS(sys_getpeername , 3)
1956 MIPS_SYS(sys_getsockname , 3)
1957 MIPS_SYS(sys_getsockopt , 5)
1958 MIPS_SYS(sys_listen , 2)
1959 MIPS_SYS(sys_recv , 4) /* 4175 */
1960 MIPS_SYS(sys_recvfrom , 6)
1961 MIPS_SYS(sys_recvmsg , 3)
1962 MIPS_SYS(sys_send , 4)
1963 MIPS_SYS(sys_sendmsg , 3)
1964 MIPS_SYS(sys_sendto , 6) /* 4180 */
1965 MIPS_SYS(sys_setsockopt , 5)
1966 MIPS_SYS(sys_shutdown , 2)
1967 MIPS_SYS(sys_socket , 3)
1968 MIPS_SYS(sys_socketpair , 4)
1969 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1970 MIPS_SYS(sys_getresuid , 3)
1971 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1972 MIPS_SYS(sys_poll , 3)
1973 MIPS_SYS(sys_nfsservctl , 3)
1974 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1975 MIPS_SYS(sys_getresgid , 3)
1976 MIPS_SYS(sys_prctl , 5)
1977 MIPS_SYS(sys_rt_sigreturn, 0)
1978 MIPS_SYS(sys_rt_sigaction, 4)
1979 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1980 MIPS_SYS(sys_rt_sigpending, 2)
1981 MIPS_SYS(sys_rt_sigtimedwait, 4)
1982 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1983 MIPS_SYS(sys_rt_sigsuspend, 0)
1984 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1985 MIPS_SYS(sys_pwrite64 , 6)
1986 MIPS_SYS(sys_chown , 3)
1987 MIPS_SYS(sys_getcwd , 2)
1988 MIPS_SYS(sys_capget , 2)
1989 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 1990 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 1991 MIPS_SYS(sys_sendfile , 4)
1992 MIPS_SYS(sys_ni_syscall , 0)
1993 MIPS_SYS(sys_ni_syscall , 0)
1994 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1995 MIPS_SYS(sys_truncate64 , 4)
1996 MIPS_SYS(sys_ftruncate64 , 4)
1997 MIPS_SYS(sys_stat64 , 2)
1998 MIPS_SYS(sys_lstat64 , 2)
1999 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2000 MIPS_SYS(sys_pivot_root , 2)
2001 MIPS_SYS(sys_mincore , 3)
2002 MIPS_SYS(sys_madvise , 3)
2003 MIPS_SYS(sys_getdents64 , 3)
2004 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2005 MIPS_SYS(sys_ni_syscall , 0)
2006 MIPS_SYS(sys_gettid , 0)
2007 MIPS_SYS(sys_readahead , 5)
2008 MIPS_SYS(sys_setxattr , 5)
2009 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2010 MIPS_SYS(sys_fsetxattr , 5)
2011 MIPS_SYS(sys_getxattr , 4)
2012 MIPS_SYS(sys_lgetxattr , 4)
2013 MIPS_SYS(sys_fgetxattr , 4)
2014 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2015 MIPS_SYS(sys_llistxattr , 3)
2016 MIPS_SYS(sys_flistxattr , 3)
2017 MIPS_SYS(sys_removexattr , 2)
2018 MIPS_SYS(sys_lremovexattr, 2)
2019 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2020 MIPS_SYS(sys_tkill , 2)
2021 MIPS_SYS(sys_sendfile64 , 5)
2022 MIPS_SYS(sys_futex , 2)
2023 MIPS_SYS(sys_sched_setaffinity, 3)
2024 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2025 MIPS_SYS(sys_io_setup , 2)
2026 MIPS_SYS(sys_io_destroy , 1)
2027 MIPS_SYS(sys_io_getevents, 5)
2028 MIPS_SYS(sys_io_submit , 3)
2029 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2030 MIPS_SYS(sys_exit_group , 1)
2031 MIPS_SYS(sys_lookup_dcookie, 3)
2032 MIPS_SYS(sys_epoll_create, 1)
2033 MIPS_SYS(sys_epoll_ctl , 4)
2034 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2035 MIPS_SYS(sys_remap_file_pages, 5)
2036 MIPS_SYS(sys_set_tid_address, 1)
2037 MIPS_SYS(sys_restart_syscall, 0)
2038 MIPS_SYS(sys_fadvise64_64, 7)
2039 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2040 MIPS_SYS(sys_fstatfs64 , 2)
2041 MIPS_SYS(sys_timer_create, 3)
2042 MIPS_SYS(sys_timer_settime, 4)
2043 MIPS_SYS(sys_timer_gettime, 2)
2044 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2045 MIPS_SYS(sys_timer_delete, 1)
2046 MIPS_SYS(sys_clock_settime, 2)
2047 MIPS_SYS(sys_clock_gettime, 2)
2048 MIPS_SYS(sys_clock_getres, 2)
2049 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2050 MIPS_SYS(sys_tgkill , 3)
2051 MIPS_SYS(sys_utimes , 2)
2052 MIPS_SYS(sys_mbind , 4)
2053 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2054 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2055 MIPS_SYS(sys_mq_open , 4)
2056 MIPS_SYS(sys_mq_unlink , 1)
2057 MIPS_SYS(sys_mq_timedsend, 5)
2058 MIPS_SYS(sys_mq_timedreceive, 5)
2059 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2060 MIPS_SYS(sys_mq_getsetattr, 3)
2061 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2062 MIPS_SYS(sys_waitid , 4)
2063 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2064 MIPS_SYS(sys_add_key , 5)
388bb21a 2065 MIPS_SYS(sys_request_key, 4)
048f6b4d 2066 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2067 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2068 MIPS_SYS(sys_inotify_init, 0)
2069 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2070 MIPS_SYS(sys_inotify_rm_watch, 2)
2071 MIPS_SYS(sys_migrate_pages, 4)
2072 MIPS_SYS(sys_openat, 4)
2073 MIPS_SYS(sys_mkdirat, 3)
2074 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2075 MIPS_SYS(sys_fchownat, 5)
2076 MIPS_SYS(sys_futimesat, 3)
2077 MIPS_SYS(sys_fstatat64, 4)
2078 MIPS_SYS(sys_unlinkat, 3)
2079 MIPS_SYS(sys_renameat, 4) /* 4295 */
2080 MIPS_SYS(sys_linkat, 5)
2081 MIPS_SYS(sys_symlinkat, 3)
2082 MIPS_SYS(sys_readlinkat, 4)
2083 MIPS_SYS(sys_fchmodat, 3)
2084 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2085 MIPS_SYS(sys_pselect6, 6)
2086 MIPS_SYS(sys_ppoll, 5)
2087 MIPS_SYS(sys_unshare, 1)
2088 MIPS_SYS(sys_splice, 4)
2089 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2090 MIPS_SYS(sys_tee, 4)
2091 MIPS_SYS(sys_vmsplice, 4)
2092 MIPS_SYS(sys_move_pages, 6)
2093 MIPS_SYS(sys_set_robust_list, 2)
2094 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2095 MIPS_SYS(sys_kexec_load, 4)
2096 MIPS_SYS(sys_getcpu, 3)
2097 MIPS_SYS(sys_epoll_pwait, 6)
2098 MIPS_SYS(sys_ioprio_set, 3)
2099 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2100 MIPS_SYS(sys_utimensat, 4)
2101 MIPS_SYS(sys_signalfd, 3)
2102 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2103 MIPS_SYS(sys_eventfd, 1)
2104 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2105 MIPS_SYS(sys_timerfd_create, 2)
2106 MIPS_SYS(sys_timerfd_gettime, 2)
2107 MIPS_SYS(sys_timerfd_settime, 4)
2108 MIPS_SYS(sys_signalfd4, 4)
2109 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2110 MIPS_SYS(sys_epoll_create1, 1)
2111 MIPS_SYS(sys_dup3, 3)
2112 MIPS_SYS(sys_pipe2, 2)
2113 MIPS_SYS(sys_inotify_init1, 1)
2114 MIPS_SYS(sys_preadv, 6) /* 4330 */
2115 MIPS_SYS(sys_pwritev, 6)
2116 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2117 MIPS_SYS(sys_perf_event_open, 5)
2118 MIPS_SYS(sys_accept4, 4)
2119 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2120 MIPS_SYS(sys_fanotify_init, 2)
2121 MIPS_SYS(sys_fanotify_mark, 6)
2122 MIPS_SYS(sys_prlimit64, 4)
2123 MIPS_SYS(sys_name_to_handle_at, 5)
2124 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2125 MIPS_SYS(sys_clock_adjtime, 2)
2126 MIPS_SYS(sys_syncfs, 1)
048f6b4d
FB		 2127};
2128
2129#undef MIPS_SYS
2130
590bc601
PB		 2131static int do_store_exclusive(CPUMIPSState *env)
2132{
2133 target_ulong addr;
2134 target_ulong page_addr;
2135 target_ulong val;
2136 int flags;
2137 int segv = 0;
2138 int reg;
2139 int d;
2140
5499b6ff 2141 addr = env->lladdr;
590bc601
PB		 2142 page_addr = addr & TARGET_PAGE_MASK;
2143 start_exclusive();
2144 mmap_lock();
2145 flags = page_get_flags(page_addr);
2146 if ((flags & PAGE_READ) == 0) {
2147 segv = 1;
2148 } else {
2149 reg = env->llreg & 0x1f;
2150 d = (env->llreg & 0x20) != 0;
2151 if (d) {
2152 segv = get_user_s64(val, addr);
2153 } else {
2154 segv = get_user_s32(val, addr);
2155 }
2156 if (!segv) {
2157 if (val != env->llval) {
2158 env->active_tc.gpr[reg] = 0;
2159 } else {
2160 if (d) {
2161 segv = put_user_u64(env->llnewval, addr);
2162 } else {
2163 segv = put_user_u32(env->llnewval, addr);
2164 }
2165 if (!segv) {
2166 env->active_tc.gpr[reg] = 1;
2167 }
2168 }
2169 }
2170 }
5499b6ff 2171 env->lladdr = -1;
590bc601
PB		 2172 if (!segv) {
2173 env->active_tc.PC += 4;
2174 }
2175 mmap_unlock();
2176 end_exclusive();
2177 return segv;
2178}
2179
048f6b4d
FB		 2180void cpu_loop(CPUMIPSState *env)
2181{
c227f099 2182 target_siginfo_t info;
388bb21a 2183 int trapnr, ret;
048f6b4d 2184 unsigned int syscall_num;
048f6b4d
FB		 2185
2186 for(;;) {
590bc601 2187 cpu_exec_start(env);
048f6b4d 2188 trapnr = cpu_mips_exec(env);
590bc601 2189 cpu_exec_end(env);
048f6b4d
FB		 2190 switch(trapnr) {
2191 case EXCP_SYSCALL:
b5dc7732
TS		 2192 syscall_num = env->active_tc.gpr[2] - 4000;
2193 env->active_tc.PC += 4;
388bb21a 2194 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2195 ret = -TARGET_ENOSYS;
388bb21a
TS		 2196 } else {
2197 int nb_args;
992f48a0
BS		 2198 abi_ulong sp_reg;
2199 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2200
2201 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2202 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2203 switch (nb_args) {
2204 /* these arguments are taken from the stack */
94c19610
ACH		 2205 case 8:
2206 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2207 goto done_syscall;
2208 }
2209 case 7:
2210 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2211 goto done_syscall;
2212 }
2213 case 6:
2214 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2215 goto done_syscall;
2216 }
2217 case 5:
2218 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2219 goto done_syscall;
2220 }
388bb21a
TS		 2221 default:
2222 break;
048f6b4d 2223 }
b5dc7732
TS		 2224 ret = do_syscall(env, env->active_tc.gpr[2],
2225 env->active_tc.gpr[4],
2226 env->active_tc.gpr[5],
2227 env->active_tc.gpr[6],
2228 env->active_tc.gpr[7],
5945cfcb 2229 arg5, arg6, arg7, arg8);
388bb21a 2230 }
94c19610 2231done_syscall:
0b1bcb00
PB		 2232 if (ret == -TARGET_QEMU_ESIGRETURN) {
2233 /* Returning from a successful sigreturn syscall.
2234 Avoid clobbering register state. */
2235 break;
2236 }
388bb21a 2237 if ((unsigned int)ret >= (unsigned int)(-1133)) {
b5dc7732 2238 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2239 ret = -ret;
2240 } else {
b5dc7732 2241 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2242 }
b5dc7732 2243 env->active_tc.gpr[2] = ret;
048f6b4d 2244 break;
ca7c2b1b
TS		 2245 case EXCP_TLBL:
2246 case EXCP_TLBS:
e6e5bd2d
WT		 2247 case EXCP_AdEL:
2248 case EXCP_AdES:
e4474235
PB		 2249 info.si_signo = TARGET_SIGSEGV;
2250 info.si_errno = 0;
2251 /* XXX: check env->error_code */
2252 info.si_code = TARGET_SEGV_MAPERR;
2253 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2254 queue_signal(env, info.si_signo, &info);
2255 break;
6900e84b 2256 case EXCP_CpU:
048f6b4d 2257 case EXCP_RI:
bc1ad2de
FB		 2258 info.si_signo = TARGET_SIGILL;
2259 info.si_errno = 0;
2260 info.si_code = 0;
624f7979 2261 queue_signal(env, info.si_signo, &info);
048f6b4d 2262 break;
106ec879
FB		 2263 case EXCP_INTERRUPT:
2264 /* just indicate that signals should be handled asap */
2265 break;
d08b2a28
PB		 2266 case EXCP_DEBUG:
2267 {
2268 int sig;
2269
2270 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2271 if (sig)
2272 {
2273 info.si_signo = sig;
2274 info.si_errno = 0;
2275 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2276 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2277 }
2278 }
2279 break;
590bc601
PB		 2280 case EXCP_SC:
2281 if (do_store_exclusive(env)) {
2282 info.si_signo = TARGET_SIGSEGV;
2283 info.si_errno = 0;
2284 info.si_code = TARGET_SEGV_MAPERR;
2285 info._sifields._sigfault._addr = env->active_tc.PC;
2286 queue_signal(env, info.si_signo, &info);
2287 }
2288 break;
853c3240
JL		 2289 case EXCP_DSPDIS:
2290 info.si_signo = TARGET_SIGILL;
2291 info.si_errno = 0;
2292 info.si_code = TARGET_ILL_ILLOPC;
2293 queue_signal(env, info.si_signo, &info);
2294 break;
048f6b4d
FB		 2295 default:
2296 // error:
5fafdf24 2297 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d
FB		 2298 trapnr);
2299 cpu_dump_state(env, stderr, fprintf, 0);
2300 abort();
2301 }
2302 process_pending_signals(env);
2303 }
2304}
2305#endif
2306
d962783e
JL		 2307#ifdef TARGET_OPENRISC
2308
2309void cpu_loop(CPUOpenRISCState *env)
2310{
2311 int trapnr, gdbsig;
2312
2313 for (;;) {
2314 trapnr = cpu_exec(env);
2315 gdbsig = 0;
2316
2317 switch (trapnr) {
2318 case EXCP_RESET:
2319 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2320 exit(1);
2321 break;
2322 case EXCP_BUSERR:
2323 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2324 gdbsig = SIGBUS;
2325 break;
2326 case EXCP_DPF:
2327 case EXCP_IPF:
2328 cpu_dump_state(env, stderr, fprintf, 0);
2329 gdbsig = TARGET_SIGSEGV;
2330 break;
2331 case EXCP_TICK:
2332 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2333 break;
2334 case EXCP_ALIGN:
2335 qemu_log("\nAlignment pc is %#x\n", env->pc);
2336 gdbsig = SIGBUS;
2337 break;
2338 case EXCP_ILLEGAL:
2339 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2340 gdbsig = SIGILL;
2341 break;
2342 case EXCP_INT:
2343 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2344 break;
2345 case EXCP_DTLBMISS:
2346 case EXCP_ITLBMISS:
2347 qemu_log("\nTLB miss\n");
2348 break;
2349 case EXCP_RANGE:
2350 qemu_log("\nRange\n");
2351 gdbsig = SIGSEGV;
2352 break;
2353 case EXCP_SYSCALL:
2354 env->pc += 4; /* 0xc00; */
2355 env->gpr[11] = do_syscall(env,
2356 env->gpr[11], /* return value */
2357 env->gpr[3], /* r3 - r7 are params */
2358 env->gpr[4],
2359 env->gpr[5],
2360 env->gpr[6],
2361 env->gpr[7],
2362 env->gpr[8], 0, 0);
2363 break;
2364 case EXCP_FPE:
2365 qemu_log("\nFloating point error\n");
2366 break;
2367 case EXCP_TRAP:
2368 qemu_log("\nTrap\n");
2369 gdbsig = SIGTRAP;
2370 break;
2371 case EXCP_NR:
2372 qemu_log("\nNR\n");
2373 break;
2374 default:
2375 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2376 trapnr);
2377 cpu_dump_state(env, stderr, fprintf, 0);
2378 gdbsig = TARGET_SIGILL;
2379 break;
2380 }
2381 if (gdbsig) {
2382 gdb_handlesig(env, gdbsig);
2383 if (gdbsig != TARGET_SIGTRAP) {
2384 exit(1);
2385 }
2386 }
2387
2388 process_pending_signals(env);
2389 }
2390}
2391
2392#endif /* TARGET_OPENRISC */
2393
fdf9b3e8 2394#ifdef TARGET_SH4
05390248 2395void cpu_loop(CPUSH4State *env)
fdf9b3e8
FB		 2396{
2397 int trapnr, ret;
c227f099 2398 target_siginfo_t info;
3b46e624 2399
fdf9b3e8
FB		 2400 while (1) {
2401 trapnr = cpu_sh4_exec (env);
3b46e624 2402
fdf9b3e8
FB		 2403 switch (trapnr) {
2404 case 0x160:
0b6d3ae0 2405 env->pc += 2;
5fafdf24
TS		 2406 ret = do_syscall(env,
2407 env->gregs[3],
2408 env->gregs[4],
2409 env->gregs[5],
2410 env->gregs[6],
2411 env->gregs[7],
2412 env->gregs[0],
5945cfcb
PM		 2413 env->gregs[1],
2414 0, 0);
9c2a9ea1 2415 env->gregs[0] = ret;
fdf9b3e8 2416 break;
c3b5bc8a
TS		 2417 case EXCP_INTERRUPT:
2418 /* just indicate that signals should be handled asap */
2419 break;
355fb23d
PB		 2420 case EXCP_DEBUG:
2421 {
2422 int sig;
2423
2424 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2425 if (sig)
2426 {
2427 info.si_signo = sig;
2428 info.si_errno = 0;
2429 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2430 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2431 }
2432 }
2433 break;
c3b5bc8a
TS		 2434 case 0xa0:
2435 case 0xc0:
2436 info.si_signo = SIGSEGV;
2437 info.si_errno = 0;
2438 info.si_code = TARGET_SEGV_MAPERR;
2439 info._sifields._sigfault._addr = env->tea;
624f7979 2440 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2441 break;
2442
fdf9b3e8
FB		 2443 default:
2444 printf ("Unhandled trap: 0x%x\n", trapnr);
2445 cpu_dump_state(env, stderr, fprintf, 0);
2446 exit (1);
2447 }
2448 process_pending_signals (env);
2449 }
2450}
2451#endif
2452
48733d19 2453#ifdef TARGET_CRIS
05390248 2454void cpu_loop(CPUCRISState *env)
48733d19
TS		 2455{
2456 int trapnr, ret;
c227f099 2457 target_siginfo_t info;
48733d19
TS		 2458
2459 while (1) {
2460 trapnr = cpu_cris_exec (env);
2461 switch (trapnr) {
2462 case 0xaa:
2463 {
2464 info.si_signo = SIGSEGV;
2465 info.si_errno = 0;
2466 /* XXX: check env->error_code */
2467 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2468 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2469 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2470 }
2471 break;
b6d3abda
EI		 2472 case EXCP_INTERRUPT:
2473 /* just indicate that signals should be handled asap */
2474 break;
48733d19
TS		 2475 case EXCP_BREAK:
2476 ret = do_syscall(env,
2477 env->regs[9],
2478 env->regs[10],
2479 env->regs[11],
2480 env->regs[12],
2481 env->regs[13],
2482 env->pregs[7],
5945cfcb
PM		 2483 env->pregs[11],
2484 0, 0);
48733d19 2485 env->regs[10] = ret;
48733d19
TS		 2486 break;
2487 case EXCP_DEBUG:
2488 {
2489 int sig;
2490
2491 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2492 if (sig)
2493 {
2494 info.si_signo = sig;
2495 info.si_errno = 0;
2496 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2497 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2498 }
2499 }
2500 break;
2501 default:
2502 printf ("Unhandled trap: 0x%x\n", trapnr);
2503 cpu_dump_state(env, stderr, fprintf, 0);
2504 exit (1);
2505 }
2506 process_pending_signals (env);
2507 }
2508}
2509#endif
2510
b779e29e 2511#ifdef TARGET_MICROBLAZE
05390248 2512void cpu_loop(CPUMBState *env)
b779e29e
EI		 2513{
2514 int trapnr, ret;
c227f099 2515 target_siginfo_t info;
b779e29e
EI		 2516
2517 while (1) {
2518 trapnr = cpu_mb_exec (env);
2519 switch (trapnr) {
2520 case 0xaa:
2521 {
2522 info.si_signo = SIGSEGV;
2523 info.si_errno = 0;
2524 /* XXX: check env->error_code */
2525 info.si_code = TARGET_SEGV_MAPERR;
2526 info._sifields._sigfault._addr = 0;
2527 queue_signal(env, info.si_signo, &info);
2528 }
2529 break;
2530 case EXCP_INTERRUPT:
2531 /* just indicate that signals should be handled asap */
2532 break;
2533 case EXCP_BREAK:
2534 /* Return address is 4 bytes after the call. */
2535 env->regs[14] += 4;
d7dce494 2536 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2537 ret = do_syscall(env,
2538 env->regs[12],
2539 env->regs[5],
2540 env->regs[6],
2541 env->regs[7],
2542 env->regs[8],
2543 env->regs[9],
5945cfcb
PM		 2544 env->regs[10],
2545 0, 0);
b779e29e 2546 env->regs[3] = ret;
b779e29e 2547 break;
b76da7e3
EI		 2548 case EXCP_HW_EXCP:
2549 env->regs[17] = env->sregs[SR_PC] + 4;
2550 if (env->iflags & D_FLAG) {
2551 env->sregs[SR_ESR] |= 1 << 12;
2552 env->sregs[SR_PC] -= 4;
b4916d7b 2553 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2554 }
2555
2556 env->iflags &= ~(IMM_FLAG | D_FLAG);
2557
2558 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2559 case ESR_EC_DIVZERO:
2560 info.si_signo = SIGFPE;
2561 info.si_errno = 0;
2562 info.si_code = TARGET_FPE_FLTDIV;
2563 info._sifields._sigfault._addr = 0;
2564 queue_signal(env, info.si_signo, &info);
2565 break;
b76da7e3
EI		 2566 case ESR_EC_FPU:
2567 info.si_signo = SIGFPE;
2568 info.si_errno = 0;
2569 if (env->sregs[SR_FSR] & FSR_IO) {
2570 info.si_code = TARGET_FPE_FLTINV;
2571 }
2572 if (env->sregs[SR_FSR] & FSR_DZ) {
2573 info.si_code = TARGET_FPE_FLTDIV;
2574 }
2575 info._sifields._sigfault._addr = 0;
2576 queue_signal(env, info.si_signo, &info);
2577 break;
2578 default:
2579 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2580 env->sregs[SR_ESR] & ESR_EC_MASK);
b76da7e3
EI		 2581 cpu_dump_state(env, stderr, fprintf, 0);
2582 exit (1);
2583 break;
2584 }
2585 break;
b779e29e
EI		 2586 case EXCP_DEBUG:
2587 {
2588 int sig;
2589
2590 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2591 if (sig)
2592 {
2593 info.si_signo = sig;
2594 info.si_errno = 0;
2595 info.si_code = TARGET_TRAP_BRKPT;
2596 queue_signal(env, info.si_signo, &info);
2597 }
2598 }
2599 break;
2600 default:
2601 printf ("Unhandled trap: 0x%x\n", trapnr);
2602 cpu_dump_state(env, stderr, fprintf, 0);
2603 exit (1);
2604 }
2605 process_pending_signals (env);
2606 }
2607}
2608#endif
2609
e6e5906b
PB		 2610#ifdef TARGET_M68K
2611
2612void cpu_loop(CPUM68KState *env)
2613{
2614 int trapnr;
2615 unsigned int n;
c227f099 2616 target_siginfo_t info;
e6e5906b 2617 TaskState *ts = env->opaque;
3b46e624 2618
e6e5906b
PB		 2619 for(;;) {
2620 trapnr = cpu_m68k_exec(env);
2621 switch(trapnr) {
2622 case EXCP_ILLEGAL:
2623 {
2624 if (ts->sim_syscalls) {
2625 uint16_t nr;
2626 nr = lduw(env->pc + 2);
2627 env->pc += 4;
2628 do_m68k_simcall(env, nr);
2629 } else {
2630 goto do_sigill;
2631 }
2632 }
2633 break;
a87295e8 2634 case EXCP_HALT_INSN:
e6e5906b 2635 /* Semihosing syscall. */
a87295e8 2636 env->pc += 4;
e6e5906b
PB		 2637 do_m68k_semihosting(env, env->dregs[0]);
2638 break;
2639 case EXCP_LINEA:
2640 case EXCP_LINEF:
2641 case EXCP_UNSUPPORTED:
2642 do_sigill:
2643 info.si_signo = SIGILL;
2644 info.si_errno = 0;
2645 info.si_code = TARGET_ILL_ILLOPN;
2646 info._sifields._sigfault._addr = env->pc;
624f7979 2647 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2648 break;
2649 case EXCP_TRAP0:
2650 {
2651 ts->sim_syscalls = 0;
2652 n = env->dregs[0];
2653 env->pc += 2;
5fafdf24
TS		 2654 env->dregs[0] = do_syscall(env,
2655 n,
e6e5906b
PB		 2656 env->dregs[1],
2657 env->dregs[2],
2658 env->dregs[3],
2659 env->dregs[4],
2660 env->dregs[5],
5945cfcb
PM		 2661 env->aregs[0],
2662 0, 0);
e6e5906b
PB		 2663 }
2664 break;
2665 case EXCP_INTERRUPT:
2666 /* just indicate that signals should be handled asap */
2667 break;
2668 case EXCP_ACCESS:
2669 {
2670 info.si_signo = SIGSEGV;
2671 info.si_errno = 0;
2672 /* XXX: check env->error_code */
2673 info.si_code = TARGET_SEGV_MAPERR;
2674 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2675 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2676 }
2677 break;
2678 case EXCP_DEBUG:
2679 {
2680 int sig;
2681
2682 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2683 if (sig)
2684 {
2685 info.si_signo = sig;
2686 info.si_errno = 0;
2687 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2688 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2689 }
2690 }
2691 break;
2692 default:
5fafdf24 2693 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b
PB		 2694 trapnr);
2695 cpu_dump_state(env, stderr, fprintf, 0);
2696 abort();
2697 }
2698 process_pending_signals(env);
2699 }
2700}
2701#endif /* TARGET_M68K */
2702
7a3148a9 2703#ifdef TARGET_ALPHA
6910b8f6
RH		 2704static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2705{
2706 target_ulong addr, val, tmp;
2707 target_siginfo_t info;
2708 int ret = 0;
2709
2710 addr = env->lock_addr;
2711 tmp = env->lock_st_addr;
2712 env->lock_addr = -1;
2713 env->lock_st_addr = 0;
2714
2715 start_exclusive();
2716 mmap_lock();
2717
2718 if (addr == tmp) {
2719 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2720 goto do_sigsegv;
2721 }
2722
2723 if (val == env->lock_value) {
2724 tmp = env->ir[reg];
2725 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2726 goto do_sigsegv;
2727 }
2728 ret = 1;
2729 }
2730 }
2731 env->ir[reg] = ret;
2732 env->pc += 4;
2733
2734 mmap_unlock();
2735 end_exclusive();
2736 return;
2737
2738 do_sigsegv:
2739 mmap_unlock();
2740 end_exclusive();
2741
2742 info.si_signo = TARGET_SIGSEGV;
2743 info.si_errno = 0;
2744 info.si_code = TARGET_SEGV_MAPERR;
2745 info._sifields._sigfault._addr = addr;
2746 queue_signal(env, TARGET_SIGSEGV, &info);
2747}
2748
05390248 2749void cpu_loop(CPUAlphaState *env)
7a3148a9 2750{
e96efcfc 2751 int trapnr;
c227f099 2752 target_siginfo_t info;
6049f4f8 2753 abi_long sysret;
3b46e624 2754
7a3148a9
JM		 2755 while (1) {
2756 trapnr = cpu_alpha_exec (env);
3b46e624 2757
ac316ca4
RH		 2758 /* All of the traps imply a transition through PALcode, which
2759 implies an REI instruction has been executed. Which means
2760 that the intr_flag should be cleared. */
2761 env->intr_flag = 0;
2762
7a3148a9
JM		 2763 switch (trapnr) {
2764 case EXCP_RESET:
2765 fprintf(stderr, "Reset requested. Exit\n");
2766 exit(1);
2767 break;
2768 case EXCP_MCHK:
2769 fprintf(stderr, "Machine check exception. Exit\n");
2770 exit(1);
2771 break;
07b6c13b
RH		 2772 case EXCP_SMP_INTERRUPT:
2773 case EXCP_CLK_INTERRUPT:
2774 case EXCP_DEV_INTERRUPT:
5fafdf24 2775 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2776 exit(1);
2777 break;
07b6c13b 2778 case EXCP_MMFAULT:
6910b8f6 2779 env->lock_addr = -1;
6049f4f8
RH		 2780 info.si_signo = TARGET_SIGSEGV;
2781 info.si_errno = 0;
129d8aa5 2782 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2783 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2784 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2785 queue_signal(env, info.si_signo, &info);
7a3148a9 2786 break;
7a3148a9 2787 case EXCP_UNALIGN:
6910b8f6 2788 env->lock_addr = -1;
6049f4f8
RH		 2789 info.si_signo = TARGET_SIGBUS;
2790 info.si_errno = 0;
2791 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2792 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2793 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2794 break;
2795 case EXCP_OPCDEC:
6049f4f8 2796 do_sigill:
6910b8f6 2797 env->lock_addr = -1;
6049f4f8
RH		 2798 info.si_signo = TARGET_SIGILL;
2799 info.si_errno = 0;
2800 info.si_code = TARGET_ILL_ILLOPC;
2801 info._sifields._sigfault._addr = env->pc;
2802 queue_signal(env, info.si_signo, &info);
7a3148a9 2803 break;
07b6c13b
RH		 2804 case EXCP_ARITH:
2805 env->lock_addr = -1;
2806 info.si_signo = TARGET_SIGFPE;
2807 info.si_errno = 0;
2808 info.si_code = TARGET_FPE_FLTINV;
2809 info._sifields._sigfault._addr = env->pc;
2810 queue_signal(env, info.si_signo, &info);
2811 break;
7a3148a9 2812 case EXCP_FEN:
6049f4f8 2813 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2814 break;
07b6c13b 2815 case EXCP_CALL_PAL:
6910b8f6 2816 env->lock_addr = -1;
07b6c13b 2817 switch (env->error_code) {
6049f4f8
RH		 2818 case 0x80:
2819 /* BPT */
2820 info.si_signo = TARGET_SIGTRAP;
2821 info.si_errno = 0;
2822 info.si_code = TARGET_TRAP_BRKPT;
2823 info._sifields._sigfault._addr = env->pc;
2824 queue_signal(env, info.si_signo, &info);
2825 break;
2826 case 0x81:
2827 /* BUGCHK */
2828 info.si_signo = TARGET_SIGTRAP;
2829 info.si_errno = 0;
2830 info.si_code = 0;
2831 info._sifields._sigfault._addr = env->pc;
2832 queue_signal(env, info.si_signo, &info);
2833 break;
2834 case 0x83:
2835 /* CALLSYS */
2836 trapnr = env->ir[IR_V0];
2837 sysret = do_syscall(env, trapnr,
2838 env->ir[IR_A0], env->ir[IR_A1],
2839 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 2840 env->ir[IR_A4], env->ir[IR_A5],
2841 0, 0);
a5b3b13b
RH		 2842 if (trapnr == TARGET_NR_sigreturn
2843 || trapnr == TARGET_NR_rt_sigreturn) {
2844 break;
2845 }
2846 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 2847 to how this is handled internal to Linux kernel.
2848 (Ab)use trapnr temporarily as boolean indicating error. */
2849 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2850 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2851 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 2852 break;
2853 case 0x86:
2854 /* IMB */
2855 /* ??? We can probably elide the code using page_unprotect
2856 that is checking for self-modifying code. Instead we
2857 could simply call tb_flush here. Until we work out the
2858 changes required to turn off the extra write protection,
2859 this can be a no-op. */
2860 break;
2861 case 0x9E:
2862 /* RDUNIQUE */
2863 /* Handled in the translator for usermode. */
2864 abort();
2865 case 0x9F:
2866 /* WRUNIQUE */
2867 /* Handled in the translator for usermode. */
2868 abort();
2869 case 0xAA:
2870 /* GENTRAP */
2871 info.si_signo = TARGET_SIGFPE;
2872 switch (env->ir[IR_A0]) {
2873 case TARGET_GEN_INTOVF:
2874 info.si_code = TARGET_FPE_INTOVF;
2875 break;
2876 case TARGET_GEN_INTDIV:
2877 info.si_code = TARGET_FPE_INTDIV;
2878 break;
2879 case TARGET_GEN_FLTOVF:
2880 info.si_code = TARGET_FPE_FLTOVF;
2881 break;
2882 case TARGET_GEN_FLTUND:
2883 info.si_code = TARGET_FPE_FLTUND;
2884 break;
2885 case TARGET_GEN_FLTINV:
2886 info.si_code = TARGET_FPE_FLTINV;
2887 break;
2888 case TARGET_GEN_FLTINE:
2889 info.si_code = TARGET_FPE_FLTRES;
2890 break;
2891 case TARGET_GEN_ROPRAND:
2892 info.si_code = 0;
2893 break;
2894 default:
2895 info.si_signo = TARGET_SIGTRAP;
2896 info.si_code = 0;
2897 break;
2898 }
2899 info.si_errno = 0;
2900 info._sifields._sigfault._addr = env->pc;
2901 queue_signal(env, info.si_signo, &info);
2902 break;
2903 default:
2904 goto do_sigill;
2905 }
7a3148a9 2906 break;
7a3148a9 2907 case EXCP_DEBUG:
6049f4f8
RH		 2908 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2909 if (info.si_signo) {
6910b8f6 2910 env->lock_addr = -1;
6049f4f8
RH		 2911 info.si_errno = 0;
2912 info.si_code = TARGET_TRAP_BRKPT;
2913 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2914 }
2915 break;
6910b8f6
RH		 2916 case EXCP_STL_C:
2917 case EXCP_STQ_C:
2918 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2919 break;
d0f20495
RH		 2920 case EXCP_INTERRUPT:
2921 /* Just indicate that signals should be handled asap. */
2922 break;
7a3148a9
JM		 2923 default:
2924 printf ("Unhandled trap: 0x%x\n", trapnr);
2925 cpu_dump_state(env, stderr, fprintf, 0);
2926 exit (1);
2927 }
2928 process_pending_signals (env);
2929 }
2930}
2931#endif /* TARGET_ALPHA */
2932
a4c075f1
UH		 2933#ifdef TARGET_S390X
2934void cpu_loop(CPUS390XState *env)
2935{
2936 int trapnr;
2937 target_siginfo_t info;
2938
2939 while (1) {
2940 trapnr = cpu_s390x_exec (env);
2941
2942 switch (trapnr) {
2943 case EXCP_INTERRUPT:
2944 /* just indicate that signals should be handled asap */
2945 break;
2946 case EXCP_DEBUG:
2947 {
2948 int sig;
2949
2950 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2951 if (sig) {
2952 info.si_signo = sig;
2953 info.si_errno = 0;
2954 info.si_code = TARGET_TRAP_BRKPT;
2955 queue_signal(env, info.si_signo, &info);
2956 }
2957 }
2958 break;
2959 case EXCP_SVC:
2960 {
2961 int n = env->int_svc_code;
2962 if (!n) {
2963 /* syscalls > 255 */
2964 n = env->regs[1];
2965 }
2966 env->psw.addr += env->int_svc_ilc;
2967 env->regs[2] = do_syscall(env, n,
2968 env->regs[2],
2969 env->regs[3],
2970 env->regs[4],
2971 env->regs[5],
2972 env->regs[6],
5945cfcb
PM		 2973 env->regs[7],
2974 0, 0);
a4c075f1
UH		 2975 }
2976 break;
2977 case EXCP_ADDR:
2978 {
2979 info.si_signo = SIGSEGV;
2980 info.si_errno = 0;
2981 /* XXX: check env->error_code */
2982 info.si_code = TARGET_SEGV_MAPERR;
2983 info._sifields._sigfault._addr = env->__excp_addr;
2984 queue_signal(env, info.si_signo, &info);
2985 }
2986 break;
2987 case EXCP_SPEC:
2988 {
2989 fprintf(stderr,"specification exception insn 0x%08x%04x\n", ldl(env->psw.addr), lduw(env->psw.addr + 4));
2990 info.si_signo = SIGILL;
2991 info.si_errno = 0;
2992 info.si_code = TARGET_ILL_ILLOPC;
2993 info._sifields._sigfault._addr = env->__excp_addr;
2994 queue_signal(env, info.si_signo, &info);
2995 }
2996 break;
2997 default:
2998 printf ("Unhandled trap: 0x%x\n", trapnr);
2999 cpu_dump_state(env, stderr, fprintf, 0);
3000 exit (1);
3001 }
3002 process_pending_signals (env);
3003 }
3004}
3005
3006#endif /* TARGET_S390X */
3007
9349b4f9 3008THREAD CPUArchState *thread_env;
59faf6d6 3009
edf8e2af
MW		 3010void task_settid(TaskState *ts)
3011{
3012 if (ts->ts_tid == 0) {
2f7bb878 3013#ifdef CONFIG_USE_NPTL
edf8e2af
MW		 3014 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3015#else
3016 /* when no threads are used, tid becomes pid */
3017 ts->ts_tid = getpid();
3018#endif
3019 }
3020}
3021
3022void stop_all_tasks(void)
3023{
3024 /*
3025 * We trust that when using NPTL, start_exclusive()
3026 * handles thread stopping correctly.
3027 */
3028 start_exclusive();
3029}
3030
c3a92833 3031/* Assumes contents are already zeroed. */
624f7979
PB		 3032void init_task_state(TaskState *ts)
3033{
3034 int i;
3035
624f7979
PB		 3036 ts->used = 1;
3037 ts->first_free = ts->sigqueue_table;
3038 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3039 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3040 }
3041 ts->sigqueue_table[i].next = NULL;
3042}
fc9c5412
JS		 3043
3044static void handle_arg_help(const char *arg)
3045{
3046 usage();
3047}
3048
3049static void handle_arg_log(const char *arg)
3050{
3051 int mask;
3052 const CPULogItem *item;
3053
3054 mask = cpu_str_to_log_mask(arg);
3055 if (!mask) {
3056 printf("Log items (comma separated):\n");
3057 for (item = cpu_log_items; item->mask != 0; item++) {
3058 printf("%-10s %s\n", item->name, item->help);
3059 }
3060 exit(1);
3061 }
3062 cpu_set_log(mask);
3063}
3064
50171d42 3065static void handle_arg_log_filename(const char *arg)
3066{
3067 cpu_set_log_filename(arg);
3068}
3069
fc9c5412
JS		 3070static void handle_arg_set_env(const char *arg)
3071{
3072 char *r, *p, *token;
3073 r = p = strdup(arg);
3074 while ((token = strsep(&p, ",")) != NULL) {
3075 if (envlist_setenv(envlist, token) != 0) {
3076 usage();
3077 }
3078 }
3079 free(r);
3080}
3081
3082static void handle_arg_unset_env(const char *arg)
3083{
3084 char *r, *p, *token;
3085 r = p = strdup(arg);
3086 while ((token = strsep(&p, ",")) != NULL) {
3087 if (envlist_unsetenv(envlist, token) != 0) {
3088 usage();
3089 }
3090 }
3091 free(r);
3092}
3093
3094static void handle_arg_argv0(const char *arg)
3095{
3096 argv0 = strdup(arg);
3097}
3098
3099static void handle_arg_stack_size(const char *arg)
3100{
3101 char *p;
3102 guest_stack_size = strtoul(arg, &p, 0);
3103 if (guest_stack_size == 0) {
3104 usage();
3105 }
3106
3107 if (*p == 'M') {
3108 guest_stack_size *= 1024 * 1024;
3109 } else if (*p == 'k' || *p == 'K') {
3110 guest_stack_size *= 1024;
3111 }
3112}
3113
3114static void handle_arg_ld_prefix(const char *arg)
3115{
3116 interp_prefix = strdup(arg);
3117}
3118
3119static void handle_arg_pagesize(const char *arg)
3120{
3121 qemu_host_page_size = atoi(arg);
3122 if (qemu_host_page_size == 0 ||
3123 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3124 fprintf(stderr, "page size must be a power of two\n");
3125 exit(1);
3126 }
3127}
3128
3129static void handle_arg_gdb(const char *arg)
3130{
3131 gdbstub_port = atoi(arg);
3132}
3133
3134static void handle_arg_uname(const char *arg)
3135{
3136 qemu_uname_release = strdup(arg);
3137}
3138
3139static void handle_arg_cpu(const char *arg)
3140{
3141 cpu_model = strdup(arg);
c8057f95 3142 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3143 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3144#if defined(cpu_list)
3145 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3146#endif
3147 exit(1);
3148 }
3149}
3150
3151#if defined(CONFIG_USE_GUEST_BASE)
3152static void handle_arg_guest_base(const char *arg)
3153{
3154 guest_base = strtol(arg, NULL, 0);
3155 have_guest_base = 1;
3156}
3157
3158static void handle_arg_reserved_va(const char *arg)
3159{
3160 char *p;
3161 int shift = 0;
3162 reserved_va = strtoul(arg, &p, 0);
3163 switch (*p) {
3164 case 'k':
3165 case 'K':
3166 shift = 10;
3167 break;
3168 case 'M':
3169 shift = 20;
3170 break;
3171 case 'G':
3172 shift = 30;
3173 break;
3174 }
3175 if (shift) {
3176 unsigned long unshifted = reserved_va;
3177 p++;
3178 reserved_va <<= shift;
3179 if (((reserved_va >> shift) != unshifted)
3180#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3181 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3182#endif
3183 ) {
3184 fprintf(stderr, "Reserved virtual address too big\n");
3185 exit(1);
3186 }
3187 }
3188 if (*p) {
3189 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3190 exit(1);
3191 }
3192}
3193#endif
3194
3195static void handle_arg_singlestep(const char *arg)
3196{
3197 singlestep = 1;
3198}
3199
3200static void handle_arg_strace(const char *arg)
3201{
3202 do_strace = 1;
3203}
3204
3205static void handle_arg_version(const char *arg)
3206{
3207 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
3208 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3209 exit(0);
fc9c5412
JS		 3210}
3211
3212struct qemu_argument {
3213 const char *argv;
3214 const char *env;
3215 bool has_arg;
3216 void (*handle_opt)(const char *arg);
3217 const char *example;
3218 const char *help;
3219};
3220
42644cee 3221static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3222 {"h", "", false, handle_arg_help,
3223 "", "print this help"},
3224 {"g", "QEMU_GDB", true, handle_arg_gdb,
3225 "port", "wait gdb connection to 'port'"},
3226 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3227 "path", "set the elf interpreter prefix to 'path'"},
3228 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3229 "size", "set the stack size to 'size' bytes"},
3230 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3231 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3232 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3233 "var=value", "sets targets environment variable (see below)"},
3234 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3235 "var", "unsets targets environment variable (see below)"},
3236 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3237 "argv0", "forces target process argv[0] to be 'argv0'"},
3238 {"r", "QEMU_UNAME", true, handle_arg_uname,
3239 "uname", "set qemu uname release string to 'uname'"},
3240#if defined(CONFIG_USE_GUEST_BASE)
3241 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3242 "address", "set guest_base address to 'address'"},
3243 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3244 "size", "reserve 'size' bytes for guest virtual address space"},
3245#endif
3246 {"d", "QEMU_LOG", true, handle_arg_log,
3247 "options", "activate log"},
50171d42 3248 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3249 "logfile", "override default logfile location"},
fc9c5412
JS		 3250 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3251 "pagesize", "set the host page size to 'pagesize'"},
3252 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3253 "", "run in singlestep mode"},
3254 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3255 "", "log system calls"},
3256 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3257 "", "display version information and exit"},
fc9c5412
JS		 3258 {NULL, NULL, false, NULL, NULL, NULL}
3259};
3260
3261static void usage(void)
3262{
42644cee 3263 const struct qemu_argument *arginfo;
fc9c5412
JS		 3264 int maxarglen;
3265 int maxenvlen;
3266
3267 printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
3268 "Linux CPU emulator (compiled for " TARGET_ARCH " emulation)\n"
3269 "\n"
3270 "Options and associated environment variables:\n"
3271 "\n");
3272
3273 maxarglen = maxenvlen = 0;
3274
3275 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3276 if (strlen(arginfo->env) > maxenvlen) {
3277 maxenvlen = strlen(arginfo->env);
3278 }
3279 if (strlen(arginfo->argv) > maxarglen) {
3280 maxarglen = strlen(arginfo->argv);
3281 }
3282 }
3283
3284 printf("%-*s%-*sDescription\n", maxarglen+3, "Argument",
3285 maxenvlen+1, "Env-variable");
3286
3287 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3288 if (arginfo->has_arg) {
3289 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3290 (int)(maxarglen-strlen(arginfo->argv)), arginfo->example,
3291 maxenvlen, arginfo->env, arginfo->help);
3292 } else {
3293 printf("-%-*s %-*s %s\n", maxarglen+1, arginfo->argv,
3294 maxenvlen, arginfo->env,
3295 arginfo->help);
3296 }
3297 }
3298
3299 printf("\n"
3300 "Defaults:\n"
3301 "QEMU_LD_PREFIX = %s\n"
3302 "QEMU_STACK_SIZE = %ld byte\n"
3303 "QEMU_LOG = %s\n",
3304 interp_prefix,
3305 guest_stack_size,
3306 DEBUG_LOGFILE);
3307
3308 printf("\n"
3309 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3310 "QEMU_UNSET_ENV environment variables to set and unset\n"
3311 "environment variables for the target process.\n"
3312 "It is possible to provide several variables by separating them\n"
3313 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3314 "provide the -E and -U options multiple times.\n"
3315 "The following lines are equivalent:\n"
3316 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3317 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3318 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3319 "Note that if you provide several changes to a single variable\n"
3320 "the last change will stay in effect.\n");
3321
3322 exit(1);
3323}
3324
3325static int parse_args(int argc, char **argv)
3326{
3327 const char *r;
3328 int optind;
42644cee 3329 const struct qemu_argument *arginfo;
fc9c5412
JS		 3330
3331 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3332 if (arginfo->env == NULL) {
3333 continue;
3334 }
3335
3336 r = getenv(arginfo->env);
3337 if (r != NULL) {
3338 arginfo->handle_opt(r);
3339 }
3340 }
3341
3342 optind = 1;
3343 for (;;) {
3344 if (optind >= argc) {
3345 break;
3346 }
3347 r = argv[optind];
3348 if (r[0] != '-') {
3349 break;
3350 }
3351 optind++;
3352 r++;
3353 if (!strcmp(r, "-")) {
3354 break;
3355 }
3356
3357 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3358 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3359 if (arginfo->has_arg) {
1386d4c0
PM		 3360 if (optind >= argc) {
3361 usage();
3362 }
3363 arginfo->handle_opt(argv[optind]);
fc9c5412 3364 optind++;
1386d4c0
PM		 3365 } else {
3366 arginfo->handle_opt(NULL);
fc9c5412 3367 }
fc9c5412
JS		 3368 break;
3369 }
3370 }
3371
3372 /* no option matched the current argv */
3373 if (arginfo->handle_opt == NULL) {
3374 usage();
3375 }
3376 }
3377
3378 if (optind >= argc) {
3379 usage();
3380 }
3381
3382 filename = argv[optind];
3383 exec_path = argv[optind];
3384
3385 return optind;
3386}
3387
902b3d5c 3388int main(int argc, char **argv, char **envp)
31e31b8a 3389{
c235d738 3390 const char *log_file = DEBUG_LOGFILE;
01ffc75b 3391 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3392 struct image_info info1, *info = &info1;
edf8e2af 3393 struct linux_binprm bprm;
48e15fc2 3394 TaskState *ts;
9349b4f9 3395 CPUArchState *env;
586314f2 3396 int optind;
04a6dfeb 3397 char **target_environ, **wrk;
7d8cec95
AJ		 3398 char **target_argv;
3399 int target_argc;
7d8cec95 3400 int i;
fd4d81dd 3401 int ret;
b12b6a18 3402
ce008c1f
AF		 3403 module_call_init(MODULE_INIT_QOM);
3404
902b3d5c 3405 qemu_cache_utils_init(envp);
3406
04a6dfeb
AJ		 3407 if ((envlist = envlist_create()) == NULL) {
3408 (void) fprintf(stderr, "Unable to allocate envlist\n");
3409 exit(1);
3410 }
3411
3412 /* add current environment into the list */
3413 for (wrk = environ; *wrk != NULL; wrk++) {
3414 (void) envlist_setenv(envlist, *wrk);
3415 }
3416
703e0e89
RH		 3417 /* Read the stack limit from the kernel. If it's "unlimited",
3418 then we can do little else besides use the default. */
3419 {
3420 struct rlimit lim;
3421 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906 3422 && lim.rlim_cur != RLIM_INFINITY
3423 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3424 guest_stack_size = lim.rlim_cur;
3425 }
3426 }
3427
b1f9be31 3428 cpu_model = NULL;
b5ec5ce0 3429#if defined(cpudef_setup)
3430 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3431#endif
3432
c235d738
MF		 3433 /* init debug */
3434 cpu_set_log_filename(log_file);
fc9c5412 3435 optind = parse_args(argc, argv);
586314f2 3436
31e31b8a 3437 /* Zero out regs */
01ffc75b 3438 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3439
3440 /* Zero out image_info */
3441 memset(info, 0, sizeof(struct image_info));
3442
edf8e2af
MW		 3443 memset(&bprm, 0, sizeof (bprm));
3444
74cd30b8
FB		 3445 /* Scan interp_prefix dir for replacement files. */
3446 init_paths(interp_prefix);
3447
46027c07 3448 if (cpu_model == NULL) {
aaed909a 3449#if defined(TARGET_I386)
46027c07
FB		 3450#ifdef TARGET_X86_64
3451 cpu_model = "qemu64";
3452#else
3453 cpu_model = "qemu32";
3454#endif
aaed909a 3455#elif defined(TARGET_ARM)
088ab16c 3456 cpu_model = "any";
d2fbca94
GX		 3457#elif defined(TARGET_UNICORE32)
3458 cpu_model = "any";
aaed909a
FB		 3459#elif defined(TARGET_M68K)
3460 cpu_model = "any";
3461#elif defined(TARGET_SPARC)
3462#ifdef TARGET_SPARC64
3463 cpu_model = "TI UltraSparc II";
3464#else
3465 cpu_model = "Fujitsu MB86904";
46027c07 3466#endif
aaed909a
FB		 3467#elif defined(TARGET_MIPS)
3468#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3469 cpu_model = "20Kc";
3470#else
3471 cpu_model = "24Kf";
3472#endif
d962783e
JL		 3473#elif defined TARGET_OPENRISC
3474 cpu_model = "or1200";
aaed909a 3475#elif defined(TARGET_PPC)
7ded4f52 3476#ifdef TARGET_PPC64
f7177937 3477 cpu_model = "970fx";
7ded4f52 3478#else
aaed909a 3479 cpu_model = "750";
7ded4f52 3480#endif
aaed909a
FB		 3481#else
3482 cpu_model = "any";
3483#endif
3484 }
d5ab9713
JK		 3485 tcg_exec_init(0);
3486 cpu_exec_init_all();
83fb7adf
FB		 3487 /* NOTE: we need to init the CPU at this stage to get
3488 qemu_host_page_size */
aaed909a
FB		 3489 env = cpu_init(cpu_model);
3490 if (!env) {
3491 fprintf(stderr, "Unable to find CPU definition\n");
3492 exit(1);
3493 }
b55a37c9 3494#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
ff18b762 3495 cpu_reset(ENV_GET_CPU(env));
b55a37c9
BS		 3496#endif
3497
d5975363 3498 thread_env = env;
3b46e624 3499
b6741956
FB		 3500 if (getenv("QEMU_STRACE")) {
3501 do_strace = 1;
b92c47c1
TS		 3502 }
3503
04a6dfeb
AJ		 3504 target_environ = envlist_to_environ(envlist, NULL);
3505 envlist_free(envlist);
b12b6a18 3506
379f6698
PB		 3507#if defined(CONFIG_USE_GUEST_BASE)
3508 /*
3509 * Now that page sizes are configured in cpu_init() we can do
3510 * proper page alignment for guest_base.
3511 */
3512 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3513
806d1021
MI		 3514 if (reserved_va || have_guest_base) {
3515 guest_base = init_guest_space(guest_base, reserved_va, 0,
3516 have_guest_base);
3517 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3518 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3519 "space for use as guest address space (check your virtual "
3520 "memory ulimit setting or reserve less using -R option)\n",
3521 reserved_va);
68a1c816
PB		 3522 exit(1);
3523 }
97cc7560 3524
806d1021
MI		 3525 if (reserved_va) {
3526 mmap_next_start = reserved_va;
97cc7560
DDAG		 3527 }
3528 }
14f24e14 3529#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3530
3531 /*
3532 * Read in mmap_min_addr kernel parameter. This value is used
3533 * When loading the ELF image to determine whether guest_base
14f24e14 3534 * is needed. It is also used in mmap_find_vma.
379f6698 3535 */
14f24e14 3536 {
379f6698
PB		 3537 FILE *fp;
3538
3539 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3540 unsigned long tmp;
3541 if (fscanf(fp, "%lu", &tmp) == 1) {
3542 mmap_min_addr = tmp;
3543 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3544 }
3545 fclose(fp);
3546 }
3547 }
379f6698 3548
7d8cec95
AJ		 3549 /*
3550 * Prepare copy of argv vector for target.
3551 */
3552 target_argc = argc - optind;
3553 target_argv = calloc(target_argc + 1, sizeof (char *));
3554 if (target_argv == NULL) {
3555 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3556 exit(1);
3557 }
3558
3559 /*
3560 * If argv0 is specified (using '-0' switch) we replace
3561 * argv[0] pointer with the given one.
3562 */
3563 i = 0;
3564 if (argv0 != NULL) {
3565 target_argv[i++] = strdup(argv0);
3566 }
3567 for (; i < target_argc; i++) {
3568 target_argv[i] = strdup(argv[optind + i]);
3569 }
3570 target_argv[target_argc] = NULL;
3571
7267c094 3572 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3573 init_task_state(ts);
3574 /* build Task State */
3575 ts->info = info;
3576 ts->bprm = &bprm;
3577 env->opaque = ts;
3578 task_settid(ts);
3579
fd4d81dd
AP		 3580 ret = loader_exec(filename, target_argv, target_environ, regs,
3581 info, &bprm);
3582 if (ret != 0) {
885c1d10 3583 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3584 _exit(1);
3585 }
3586
3587 for (wrk = target_environ; *wrk; wrk++) {
3588 free(*wrk);
31e31b8a 3589 }
3b46e624 3590
b12b6a18
TS		 3591 free(target_environ);
3592
2e77eac6 3593 if (qemu_log_enabled()) {
379f6698
PB		 3594#if defined(CONFIG_USE_GUEST_BASE)
3595 qemu_log("guest_base 0x%lx\n", guest_base);
3596#endif
2e77eac6
BS		 3597 log_page_dump();
3598
3599 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3600 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3601 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3602 info->start_code);
3603 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3604 info->start_data);
3605 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3606 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3607 info->start_stack);
3608 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3609 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3610 }
31e31b8a 3611
53a5960a 3612 target_set_brk(info->brk);
31e31b8a 3613 syscall_init();
66fb9763 3614 signal_init();
31e31b8a 3615
9002ec79
RH		 3616#if defined(CONFIG_USE_GUEST_BASE)
3617 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3618 generating the prologue until now so that the prologue can take
3619 the real value of GUEST_BASE into account. */
3620 tcg_prologue_init(&tcg_ctx);
3621#endif
3622
b346ff46 3623#if defined(TARGET_I386)
2e255c6b
FB		 3624 cpu_x86_set_cpl(env, 3);
3625
3802ce26 3626 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e
FB		 3627 env->hflags |= HF_PE_MASK;
3628 if (env->cpuid_features & CPUID_SSE) {
3629 env->cr[4] |= CR4_OSFXSR_MASK;
3630 env->hflags |= HF_OSFXSR_MASK;
3631 }
d2fd1af7 3632#ifndef TARGET_ABI32
4dbc422b
FB		 3633 /* enable 64 bit mode if possible */
3634 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
3635 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3636 exit(1);
3637 }
d2fd1af7 3638 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3639 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3640 env->hflags |= HF_LMA_MASK;
3641#endif
1bde465e 3642
415e561f
FB		 3643 /* flags setup : we activate the IRQs by default as in user mode */
3644 env->eflags |= IF_MASK;
3b46e624 3645
6dbad63e 3646 /* linux register setup */
d2fd1af7 3647#ifndef TARGET_ABI32
84409ddb
JM		 3648 env->regs[R_EAX] = regs->rax;
3649 env->regs[R_EBX] = regs->rbx;
3650 env->regs[R_ECX] = regs->rcx;
3651 env->regs[R_EDX] = regs->rdx;
3652 env->regs[R_ESI] = regs->rsi;
3653 env->regs[R_EDI] = regs->rdi;
3654 env->regs[R_EBP] = regs->rbp;
3655 env->regs[R_ESP] = regs->rsp;
3656 env->eip = regs->rip;
3657#else
0ecfa993
FB		 3658 env->regs[R_EAX] = regs->eax;
3659 env->regs[R_EBX] = regs->ebx;
3660 env->regs[R_ECX] = regs->ecx;
3661 env->regs[R_EDX] = regs->edx;
3662 env->regs[R_ESI] = regs->esi;
3663 env->regs[R_EDI] = regs->edi;
3664 env->regs[R_EBP] = regs->ebp;
3665 env->regs[R_ESP] = regs->esp;
dab2ed99 3666 env->eip = regs->eip;
84409ddb 3667#endif
31e31b8a 3668
f4beb510 3669 /* linux interrupt setup */
e441570f
AZ		 3670#ifndef TARGET_ABI32
3671 env->idt.limit = 511;
3672#else
3673 env->idt.limit = 255;
3674#endif
3675 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3676 PROT_READ|PROT_WRITE,
3677 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3678 idt_table = g2h(env->idt.base);
f4beb510
FB		 3679 set_idt(0, 0);
3680 set_idt(1, 0);
3681 set_idt(2, 0);
3682 set_idt(3, 3);
3683 set_idt(4, 3);
ec95da6c 3684 set_idt(5, 0);
f4beb510
FB		 3685 set_idt(6, 0);
3686 set_idt(7, 0);
3687 set_idt(8, 0);
3688 set_idt(9, 0);
3689 set_idt(10, 0);
3690 set_idt(11, 0);
3691 set_idt(12, 0);
3692 set_idt(13, 0);
3693 set_idt(14, 0);
3694 set_idt(15, 0);
3695 set_idt(16, 0);
3696 set_idt(17, 0);
3697 set_idt(18, 0);
3698 set_idt(19, 0);
3699 set_idt(0x80, 3);
3700
6dbad63e 3701 /* linux segment setup */
8d18e893
FB		 3702 {
3703 uint64_t *gdt_table;
e441570f
AZ		 3704 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3705 PROT_READ|PROT_WRITE,
3706 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3707 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3708 gdt_table = g2h(env->gdt.base);
d2fd1af7 3709#ifdef TARGET_ABI32
8d18e893
FB		 3710 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3711 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3712 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3713#else
3714 /* 64 bit code segment */
3715 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3716 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3717 DESC_L_MASK |
3718 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3719#endif
8d18e893
FB		 3720 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3721 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3722 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3723 }
6dbad63e 3724 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3725 cpu_x86_load_seg(env, R_SS, __USER_DS);
3726#ifdef TARGET_ABI32
6dbad63e
FB		 3727 cpu_x86_load_seg(env, R_DS, __USER_DS);
3728 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3729 cpu_x86_load_seg(env, R_FS, __USER_DS);
3730 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3731 /* This hack makes Wine work... */
3732 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3733#else
3734 cpu_x86_load_seg(env, R_DS, 0);
3735 cpu_x86_load_seg(env, R_ES, 0);
3736 cpu_x86_load_seg(env, R_FS, 0);
3737 cpu_x86_load_seg(env, R_GS, 0);
3738#endif
b346ff46
FB		 3739#elif defined(TARGET_ARM)
3740 {
3741 int i;
b5ff1b31 3742 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3743 for(i = 0; i < 16; i++) {
3744 env->regs[i] = regs->uregs[i];
3745 }
d8fd2954
PB		 3746 /* Enable BE8. */
3747 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3748 && (info->elf_flags & EF_ARM_BE8)) {
3749 env->bswap_code = 1;
3750 }
b346ff46 3751 }
d2fbca94
GX		 3752#elif defined(TARGET_UNICORE32)
3753 {
3754 int i;
3755 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3756 for (i = 0; i < 32; i++) {
3757 env->regs[i] = regs->uregs[i];
3758 }
3759 }
93ac68bc 3760#elif defined(TARGET_SPARC)
060366c5
FB		 3761 {
3762 int i;
3763 env->pc = regs->pc;
3764 env->npc = regs->npc;
3765 env->y = regs->y;
3766 for(i = 0; i < 8; i++)
3767 env->gregs[i] = regs->u_regs[i];
3768 for(i = 0; i < 8; i++)
3769 env->regwptr[i] = regs->u_regs[i + 8];
3770 }
67867308
FB		 3771#elif defined(TARGET_PPC)
3772 {
3773 int i;
3fc6c082 3774
0411a972
JM		 3775#if defined(TARGET_PPC64)
3776#if defined(TARGET_ABI32)
3777 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3778#else
0411a972
JM		 3779 env->msr |= (target_ulong)1 << MSR_SF;
3780#endif
84409ddb 3781#endif
67867308
FB		 3782 env->nip = regs->nip;
3783 for(i = 0; i < 32; i++) {
3784 env->gpr[i] = regs->gpr[i];
3785 }
3786 }
e6e5906b
PB		 3787#elif defined(TARGET_M68K)
3788 {
e6e5906b
PB		 3789 env->pc = regs->pc;
3790 env->dregs[0] = regs->d0;
3791 env->dregs[1] = regs->d1;
3792 env->dregs[2] = regs->d2;
3793 env->dregs[3] = regs->d3;
3794 env->dregs[4] = regs->d4;
3795 env->dregs[5] = regs->d5;
3796 env->dregs[6] = regs->d6;
3797 env->dregs[7] = regs->d7;
3798 env->aregs[0] = regs->a0;
3799 env->aregs[1] = regs->a1;
3800 env->aregs[2] = regs->a2;
3801 env->aregs[3] = regs->a3;
3802 env->aregs[4] = regs->a4;
3803 env->aregs[5] = regs->a5;
3804 env->aregs[6] = regs->a6;
3805 env->aregs[7] = regs->usp;
3806 env->sr = regs->sr;
3807 ts->sim_syscalls = 1;
3808 }
b779e29e
EI		 3809#elif defined(TARGET_MICROBLAZE)
3810 {
3811 env->regs[0] = regs->r0;
3812 env->regs[1] = regs->r1;
3813 env->regs[2] = regs->r2;
3814 env->regs[3] = regs->r3;
3815 env->regs[4] = regs->r4;
3816 env->regs[5] = regs->r5;
3817 env->regs[6] = regs->r6;
3818 env->regs[7] = regs->r7;
3819 env->regs[8] = regs->r8;
3820 env->regs[9] = regs->r9;
3821 env->regs[10] = regs->r10;
3822 env->regs[11] = regs->r11;
3823 env->regs[12] = regs->r12;
3824 env->regs[13] = regs->r13;
3825 env->regs[14] = regs->r14;
3826 env->regs[15] = regs->r15;
3827 env->regs[16] = regs->r16;
3828 env->regs[17] = regs->r17;
3829 env->regs[18] = regs->r18;
3830 env->regs[19] = regs->r19;
3831 env->regs[20] = regs->r20;
3832 env->regs[21] = regs->r21;
3833 env->regs[22] = regs->r22;
3834 env->regs[23] = regs->r23;
3835 env->regs[24] = regs->r24;
3836 env->regs[25] = regs->r25;
3837 env->regs[26] = regs->r26;
3838 env->regs[27] = regs->r27;
3839 env->regs[28] = regs->r28;
3840 env->regs[29] = regs->r29;
3841 env->regs[30] = regs->r30;
3842 env->regs[31] = regs->r31;
3843 env->sregs[SR_PC] = regs->pc;
3844 }
048f6b4d
FB		 3845#elif defined(TARGET_MIPS)
3846 {
3847 int i;
3848
3849 for(i = 0; i < 32; i++) {
b5dc7732 3850 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3851 }
0fddbbf2
NF		 3852 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3853 if (regs->cp0_epc & 1) {
3854 env->hflags |= MIPS_HFLAG_M16;
3855 }
048f6b4d 3856 }
d962783e
JL		 3857#elif defined(TARGET_OPENRISC)
3858 {
3859 int i;
3860
3861 for (i = 0; i < 32; i++) {
3862 env->gpr[i] = regs->gpr[i];
3863 }
3864
3865 env->sr = regs->sr;
3866 env->pc = regs->pc;
3867 }
fdf9b3e8
FB		 3868#elif defined(TARGET_SH4)
3869 {
3870 int i;
3871
3872 for(i = 0; i < 16; i++) {
3873 env->gregs[i] = regs->regs[i];
3874 }
3875 env->pc = regs->pc;
3876 }
7a3148a9
JM		 3877#elif defined(TARGET_ALPHA)
3878 {
3879 int i;
3880
3881 for(i = 0; i < 28; i++) {
992f48a0 3882 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 3883 }
dad081ee 3884 env->ir[IR_SP] = regs->usp;
7a3148a9 3885 env->pc = regs->pc;
7a3148a9 3886 }
48733d19
TS		 3887#elif defined(TARGET_CRIS)
3888 {
3889 env->regs[0] = regs->r0;
3890 env->regs[1] = regs->r1;
3891 env->regs[2] = regs->r2;
3892 env->regs[3] = regs->r3;
3893 env->regs[4] = regs->r4;
3894 env->regs[5] = regs->r5;
3895 env->regs[6] = regs->r6;
3896 env->regs[7] = regs->r7;
3897 env->regs[8] = regs->r8;
3898 env->regs[9] = regs->r9;
3899 env->regs[10] = regs->r10;
3900 env->regs[11] = regs->r11;
3901 env->regs[12] = regs->r12;
3902 env->regs[13] = regs->r13;
3903 env->regs[14] = info->start_stack;
3904 env->regs[15] = regs->acr;
3905 env->pc = regs->erp;
3906 }
a4c075f1
UH		 3907#elif defined(TARGET_S390X)
3908 {
3909 int i;
3910 for (i = 0; i < 16; i++) {
3911 env->regs[i] = regs->gprs[i];
3912 }
3913 env->psw.mask = regs->psw.mask;
3914 env->psw.addr = regs->psw.addr;
3915 }
b346ff46
FB		 3916#else
3917#error unsupported target CPU
3918#endif
31e31b8a 3919
d2fbca94 3920#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 3921 ts->stack_base = info->start_stack;
3922 ts->heap_base = info->brk;
3923 /* This will be filled in on the first SYS_HEAPINFO call. */
3924 ts->heap_limit = 0;
3925#endif
3926
74c33bed 3927 if (gdbstub_port) {
ff7a981a
PM		 3928 if (gdbserver_start(gdbstub_port) < 0) {
3929 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
3930 gdbstub_port);
3931 exit(1);
3932 }
1fddef4b
FB		 3933 gdb_handlesig(env, 0);
3934 }
1b6b029e
FB		 3935 cpu_loop(env);
3936 /* never exits */
31e31b8a
FB		 3937 return 0;
3938}
Qemu copy for testing