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cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
[qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
45const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 72const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
2f7bb878 95#if defined(CONFIG_USE_NPTL)
d5975363
PB		 96/***********************************************************/
97/* Helper routines for implementing atomic operations. */
98
99/* To implement exclusive operations we force all cpus to syncronise.
100 We don't require a full sync, only that no cpus are executing guest code.
101 The alternative is to map target atomic ops onto host equivalents,
102 which requires quite a lot of per host/target work. */
c2764719 103static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 104static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
105static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
106static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
107static int pending_cpus;
108
109/* Make sure everything is in a consistent state for calling fork(). */
110void fork_start(void)
111{
5e5f07e0 112 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 113 pthread_mutex_lock(&exclusive_lock);
d032d1b4 114 mmap_fork_start();
d5975363
PB		 115}
116
117void fork_end(int child)
118{
d032d1b4 119 mmap_fork_end(child);
d5975363
PB		 120 if (child) {
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 first_cpu = thread_env;
124 thread_env->next_cpu = NULL;
125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 127 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
2b1319c8 131 gdbserver_fork(thread_env);
d5975363
PB		 132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 135 }
d5975363
PB		 136}
137
138/* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140static inline void exclusive_idle(void)
141{
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145}
146
147/* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149static inline void start_exclusive(void)
150{
9349b4f9 151 CPUArchState *other;
0315c31c
AF		 152 CPUState *other_cpu;
153
d5975363
PB		 154 pthread_mutex_lock(&exclusive_lock);
155 exclusive_idle();
156
157 pending_cpus = 1;
158 /* Make all other cpus stop executing. */
159 for (other = first_cpu; other; other = other->next_cpu) {
0315c31c
AF		 160 other_cpu = ENV_GET_CPU(other);
161 if (other_cpu->running) {
d5975363 162 pending_cpus++;
60a3e17a 163 cpu_exit(other_cpu);
d5975363
PB		 164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169}
170
171/* Finish an exclusive operation. */
172static inline void end_exclusive(void)
173{
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177}
178
179/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 180static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 181{
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
0315c31c 184 cpu->running = true;
d5975363
PB		 185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 189static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
0315c31c 192 cpu->running = false;
d5975363
PB		 193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201}
c2764719
PB		 202
203void cpu_list_lock(void)
204{
205 pthread_mutex_lock(&cpu_list_mutex);
206}
207
208void cpu_list_unlock(void)
209{
210 pthread_mutex_unlock(&cpu_list_mutex);
211}
2f7bb878 212#else /* if !CONFIG_USE_NPTL */
d5975363 213/* These are no-ops because we are not threadsafe. */
0315c31c 214static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 215{
216}
217
0315c31c 218static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 219{
220}
221
222static inline void start_exclusive(void)
223{
224}
225
226static inline void end_exclusive(void)
227{
228}
229
230void fork_start(void)
231{
232}
233
234void fork_end(int child)
235{
2b1319c8
AJ		 236 if (child) {
237 gdbserver_fork(thread_env);
238 }
d5975363 239}
c2764719
PB		 240
241void cpu_list_lock(void)
242{
243}
244
245void cpu_list_unlock(void)
246{
247}
d5975363
PB		 248#endif
249
250
a541f297
FB		 251#ifdef TARGET_I386
252/***********************************************************/
253/* CPUX86 core interface */
254
05390248 255void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 256{
257}
258
28ab0e2e
FB		 259uint64_t cpu_get_tsc(CPUX86State *env)
260{
261 return cpu_get_real_ticks();
262}
263
5fafdf24 264static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 265 int flags)
6dbad63e 266{
f4beb510 267 unsigned int e1, e2;
53a5960a 268 uint32_t *p;
6dbad63e
FB		 269 e1 = (addr << 16) | (limit & 0xffff);
270 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 271 e2 |= flags;
53a5960a 272 p = ptr;
d538e8f5 273 p[0] = tswap32(e1);
274 p[1] = tswap32(e2);
f4beb510
FB		 275}
276
e441570f 277static uint64_t *idt_table;
eb38c52c 278#ifdef TARGET_X86_64
d2fd1af7
FB		 279static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
280 uint64_t addr, unsigned int sel)
f4beb510 281{
4dbc422b 282 uint32_t *p, e1, e2;
f4beb510
FB		 283 e1 = (addr & 0xffff) | (sel << 16);
284 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 285 p = ptr;
4dbc422b
FB		 286 p[0] = tswap32(e1);
287 p[1] = tswap32(e2);
288 p[2] = tswap32(addr >> 32);
289 p[3] = 0;
6dbad63e 290}
d2fd1af7
FB		 291/* only dpl matters as we do only user space emulation */
292static void set_idt(int n, unsigned int dpl)
293{
294 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
295}
296#else
d2fd1af7
FB		 297static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
298 uint32_t addr, unsigned int sel)
299{
4dbc422b 300 uint32_t *p, e1, e2;
d2fd1af7
FB		 301 e1 = (addr & 0xffff) | (sel << 16);
302 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
303 p = ptr;
4dbc422b
FB		 304 p[0] = tswap32(e1);
305 p[1] = tswap32(e2);
d2fd1af7
FB		 306}
307
f4beb510
FB		 308/* only dpl matters as we do only user space emulation */
309static void set_idt(int n, unsigned int dpl)
310{
311 set_gate(idt_table + n, 0, dpl, 0, 0);
312}
d2fd1af7 313#endif
31e31b8a 314
89e957e7 315void cpu_loop(CPUX86State *env)
1b6b029e 316{
bc8a22cc 317 int trapnr;
992f48a0 318 abi_ulong pc;
c227f099 319 target_siginfo_t info;
851e67a1 320
1b6b029e 321 for(;;) {
bc8a22cc 322 trapnr = cpu_x86_exec(env);
bc8a22cc 323 switch(trapnr) {
f4beb510 324 case 0x80:
d2fd1af7 325 /* linux syscall from int $0x80 */
5fafdf24
TS		 326 env->regs[R_EAX] = do_syscall(env,
327 env->regs[R_EAX],
f4beb510
FB		 328 env->regs[R_EBX],
329 env->regs[R_ECX],
330 env->regs[R_EDX],
331 env->regs[R_ESI],
332 env->regs[R_EDI],
5945cfcb
PM		 333 env->regs[R_EBP],
334 0, 0);
f4beb510 335 break;
d2fd1af7
FB		 336#ifndef TARGET_ABI32
337 case EXCP_SYSCALL:
5ba18547 338 /* linux syscall from syscall instruction */
d2fd1af7
FB		 339 env->regs[R_EAX] = do_syscall(env,
340 env->regs[R_EAX],
341 env->regs[R_EDI],
342 env->regs[R_ESI],
343 env->regs[R_EDX],
344 env->regs[10],
345 env->regs[8],
5945cfcb
PM		 346 env->regs[9],
347 0, 0);
d2fd1af7
FB		 348 env->eip = env->exception_next_eip;
349 break;
350#endif
f4beb510
FB		 351 case EXCP0B_NOSEG:
352 case EXCP0C_STACK:
353 info.si_signo = SIGBUS;
354 info.si_errno = 0;
355 info.si_code = TARGET_SI_KERNEL;
356 info._sifields._sigfault._addr = 0;
624f7979 357 queue_signal(env, info.si_signo, &info);
f4beb510 358 break;
1b6b029e 359 case EXCP0D_GPF:
d2fd1af7 360 /* XXX: potential problem if ABI32 */
84409ddb 361#ifndef TARGET_X86_64
851e67a1 362 if (env->eflags & VM_MASK) {
89e957e7 363 handle_vm86_fault(env);
84409ddb
JM		 364 } else
365#endif
366 {
f4beb510
FB		 367 info.si_signo = SIGSEGV;
368 info.si_errno = 0;
369 info.si_code = TARGET_SI_KERNEL;
370 info._sifields._sigfault._addr = 0;
624f7979 371 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 372 }
373 break;
b689bc57
FB		 374 case EXCP0E_PAGE:
375 info.si_signo = SIGSEGV;
376 info.si_errno = 0;
377 if (!(env->error_code & 1))
378 info.si_code = TARGET_SEGV_MAPERR;
379 else
380 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 381 info._sifields._sigfault._addr = env->cr[2];
624f7979 382 queue_signal(env, info.si_signo, &info);
b689bc57 383 break;
9de5e440 384 case EXCP00_DIVZ:
84409ddb 385#ifndef TARGET_X86_64
bc8a22cc 386 if (env->eflags & VM_MASK) {
447db213 387 handle_vm86_trap(env, trapnr);
84409ddb
JM		 388 } else
389#endif
390 {
bc8a22cc
FB		 391 /* division by zero */
392 info.si_signo = SIGFPE;
393 info.si_errno = 0;
394 info.si_code = TARGET_FPE_INTDIV;
395 info._sifields._sigfault._addr = env->eip;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440 398 break;
01df040b 399 case EXCP01_DB:
447db213 400 case EXCP03_INT3:
84409ddb 401#ifndef TARGET_X86_64
447db213
FB		 402 if (env->eflags & VM_MASK) {
403 handle_vm86_trap(env, trapnr);
84409ddb
JM		 404 } else
405#endif
406 {
447db213
FB		 407 info.si_signo = SIGTRAP;
408 info.si_errno = 0;
01df040b 409 if (trapnr == EXCP01_DB) {
447db213
FB		 410 info.si_code = TARGET_TRAP_BRKPT;
411 info._sifields._sigfault._addr = env->eip;
412 } else {
413 info.si_code = TARGET_SI_KERNEL;
414 info._sifields._sigfault._addr = 0;
415 }
624f7979 416 queue_signal(env, info.si_signo, &info);
447db213
FB		 417 }
418 break;
9de5e440
FB		 419 case EXCP04_INTO:
420 case EXCP05_BOUND:
84409ddb 421#ifndef TARGET_X86_64
bc8a22cc 422 if (env->eflags & VM_MASK) {
447db213 423 handle_vm86_trap(env, trapnr);
84409ddb
JM		 424 } else
425#endif
426 {
bc8a22cc
FB		 427 info.si_signo = SIGSEGV;
428 info.si_errno = 0;
b689bc57 429 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 430 info._sifields._sigfault._addr = 0;
624f7979 431 queue_signal(env, info.si_signo, &info);
bc8a22cc 432 }
9de5e440
FB		 433 break;
434 case EXCP06_ILLOP:
435 info.si_signo = SIGILL;
436 info.si_errno = 0;
437 info.si_code = TARGET_ILL_ILLOPN;
438 info._sifields._sigfault._addr = env->eip;
624f7979 439 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 440 break;
441 case EXCP_INTERRUPT:
442 /* just indicate that signals should be handled asap */
443 break;
1fddef4b
FB		 444 case EXCP_DEBUG:
445 {
446 int sig;
447
448 sig = gdb_handlesig (env, TARGET_SIGTRAP);
449 if (sig)
450 {
451 info.si_signo = sig;
452 info.si_errno = 0;
453 info.si_code = TARGET_TRAP_BRKPT;
624f7979 454 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 455 }
456 }
457 break;
1b6b029e 458 default:
970a87a6 459 pc = env->segs[R_CS].base + env->eip;
5fafdf24 460 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 461 (long)pc, trapnr);
1b6b029e
FB		 462 abort();
463 }
66fb9763 464 process_pending_signals(env);
1b6b029e
FB		 465 }
466}
b346ff46
FB		 467#endif
468
469#ifdef TARGET_ARM
470
d8fd2954
PB		 471#define get_user_code_u32(x, gaddr, doswap) \
472 ({ abi_long __r = get_user_u32((x), (gaddr)); \
473 if (!__r && (doswap)) { \
474 (x) = bswap32(x); \
475 } \
476 __r; \
477 })
478
479#define get_user_code_u16(x, gaddr, doswap) \
480 ({ abi_long __r = get_user_u16((x), (gaddr)); \
481 if (!__r && (doswap)) { \
482 (x) = bswap16(x); \
483 } \
484 __r; \
485 })
486
97cc7560
DDAG		 487/*
488 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
489 * Input:
490 * r0 = pointer to oldval
491 * r1 = pointer to newval
492 * r2 = pointer to target value
493 *
494 * Output:
495 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
496 * C set if *ptr was changed, clear if no exchange happened
497 *
498 * Note segv's in kernel helpers are a bit tricky, we can set the
499 * data address sensibly but the PC address is just the entry point.
500 */
501static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
502{
503 uint64_t oldval, newval, val;
504 uint32_t addr, cpsr;
505 target_siginfo_t info;
506
507 /* Based on the 32 bit code in do_kernel_trap */
508
509 /* XXX: This only works between threads, not between processes.
510 It's probably possible to implement this with native host
511 operations. However things like ldrex/strex are much harder so
512 there's not much point trying. */
513 start_exclusive();
514 cpsr = cpsr_read(env);
515 addr = env->regs[2];
516
517 if (get_user_u64(oldval, env->regs[0])) {
518 env->cp15.c6_data = env->regs[0];
519 goto segv;
520 };
521
522 if (get_user_u64(newval, env->regs[1])) {
523 env->cp15.c6_data = env->regs[1];
524 goto segv;
525 };
526
527 if (get_user_u64(val, addr)) {
528 env->cp15.c6_data = addr;
529 goto segv;
530 }
531
532 if (val == oldval) {
533 val = newval;
534
535 if (put_user_u64(val, addr)) {
536 env->cp15.c6_data = addr;
537 goto segv;
538 };
539
540 env->regs[0] = 0;
541 cpsr |= CPSR_C;
542 } else {
543 env->regs[0] = -1;
544 cpsr &= ~CPSR_C;
545 }
546 cpsr_write(env, cpsr, CPSR_C);
547 end_exclusive();
548 return;
549
550segv:
551 end_exclusive();
552 /* We get the PC of the entry address - which is as good as anything,
553 on a real kernel what you get depends on which mode it uses. */
554 info.si_signo = SIGSEGV;
555 info.si_errno = 0;
556 /* XXX: check env->error_code */
557 info.si_code = TARGET_SEGV_MAPERR;
558 info._sifields._sigfault._addr = env->cp15.c6_data;
559 queue_signal(env, info.si_signo, &info);
560
561 end_exclusive();
562}
563
fbb4a2e3
PB		 564/* Handle a jump to the kernel code page. */
565static int
566do_kernel_trap(CPUARMState *env)
567{
568 uint32_t addr;
569 uint32_t cpsr;
570 uint32_t val;
571
572 switch (env->regs[15]) {
573 case 0xffff0fa0: /* __kernel_memory_barrier */
574 /* ??? No-op. Will need to do better for SMP. */
575 break;
576 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 577 /* XXX: This only works between threads, not between processes.
578 It's probably possible to implement this with native host
579 operations. However things like ldrex/strex are much harder so
580 there's not much point trying. */
581 start_exclusive();
fbb4a2e3
PB		 582 cpsr = cpsr_read(env);
583 addr = env->regs[2];
584 /* FIXME: This should SEGV if the access fails. */
585 if (get_user_u32(val, addr))
586 val = ~env->regs[0];
587 if (val == env->regs[0]) {
588 val = env->regs[1];
589 /* FIXME: Check for segfaults. */
590 put_user_u32(val, addr);
591 env->regs[0] = 0;
592 cpsr |= CPSR_C;
593 } else {
594 env->regs[0] = -1;
595 cpsr &= ~CPSR_C;
596 }
597 cpsr_write(env, cpsr, CPSR_C);
d5975363 598 end_exclusive();
fbb4a2e3
PB		 599 break;
600 case 0xffff0fe0: /* __kernel_get_tls */
601 env->regs[0] = env->cp15.c13_tls2;
602 break;
97cc7560
DDAG		 603 case 0xffff0f60: /* __kernel_cmpxchg64 */
604 arm_kernel_cmpxchg64_helper(env);
605 break;
606
fbb4a2e3
PB		 607 default:
608 return 1;
609 }
610 /* Jump back to the caller. */
611 addr = env->regs[14];
612 if (addr & 1) {
613 env->thumb = 1;
614 addr &= ~1;
615 }
616 env->regs[15] = addr;
617
618 return 0;
619}
620
426f5abc
PB		 621static int do_strex(CPUARMState *env)
622{
623 uint32_t val;
624 int size;
625 int rc = 1;
626 int segv = 0;
627 uint32_t addr;
628 start_exclusive();
629 addr = env->exclusive_addr;
630 if (addr != env->exclusive_test) {
631 goto fail;
632 }
633 size = env->exclusive_info & 0xf;
634 switch (size) {
635 case 0:
636 segv = get_user_u8(val, addr);
637 break;
638 case 1:
639 segv = get_user_u16(val, addr);
640 break;
641 case 2:
642 case 3:
643 segv = get_user_u32(val, addr);
644 break;
f7001a3b
AJ		 645 default:
646 abort();
426f5abc
PB		 647 }
648 if (segv) {
649 env->cp15.c6_data = addr;
650 goto done;
651 }
652 if (val != env->exclusive_val) {
653 goto fail;
654 }
655 if (size == 3) {
656 segv = get_user_u32(val, addr + 4);
657 if (segv) {
658 env->cp15.c6_data = addr + 4;
659 goto done;
660 }
661 if (val != env->exclusive_high) {
662 goto fail;
663 }
664 }
665 val = env->regs[(env->exclusive_info >> 8) & 0xf];
666 switch (size) {
667 case 0:
668 segv = put_user_u8(val, addr);
669 break;
670 case 1:
671 segv = put_user_u16(val, addr);
672 break;
673 case 2:
674 case 3:
675 segv = put_user_u32(val, addr);
676 break;
677 }
678 if (segv) {
679 env->cp15.c6_data = addr;
680 goto done;
681 }
682 if (size == 3) {
683 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 684 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 685 if (segv) {
686 env->cp15.c6_data = addr + 4;
687 goto done;
688 }
689 }
690 rc = 0;
691fail:
725b8a69 692 env->regs[15] += 4;
426f5abc
PB		 693 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
694done:
695 end_exclusive();
696 return segv;
697}
698
b346ff46
FB		 699void cpu_loop(CPUARMState *env)
700{
0315c31c 701 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 702 int trapnr;
703 unsigned int n, insn;
c227f099 704 target_siginfo_t info;
b5ff1b31 705 uint32_t addr;
3b46e624 706
b346ff46 707 for(;;) {
0315c31c 708 cpu_exec_start(cs);
b346ff46 709 trapnr = cpu_arm_exec(env);
0315c31c 710 cpu_exec_end(cs);
b346ff46
FB		 711 switch(trapnr) {
712 case EXCP_UDEF:
c6981055
FB		 713 {
714 TaskState *ts = env->opaque;
715 uint32_t opcode;
6d9a42be 716 int rc;
c6981055
FB		 717
718 /* we handle the FPU emulation here, as Linux */
719 /* we get the opcode */
2f619698 720 /* FIXME - what to do if get_user() fails? */
d8fd2954 721 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 722
6d9a42be
AJ		 723 rc = EmulateAll(opcode, &ts->fpa, env);
724 if (rc == 0) { /* illegal instruction */
c6981055
FB		 725 info.si_signo = SIGILL;
726 info.si_errno = 0;
727 info.si_code = TARGET_ILL_ILLOPN;
728 info._sifields._sigfault._addr = env->regs[15];
624f7979 729 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 730 } else if (rc < 0) { /* FP exception */
731 int arm_fpe=0;
732
733 /* translate softfloat flags to FPSR flags */
734 if (-rc & float_flag_invalid)
735 arm_fpe |= BIT_IOC;
736 if (-rc & float_flag_divbyzero)
737 arm_fpe |= BIT_DZC;
738 if (-rc & float_flag_overflow)
739 arm_fpe |= BIT_OFC;
740 if (-rc & float_flag_underflow)
741 arm_fpe |= BIT_UFC;
742 if (-rc & float_flag_inexact)
743 arm_fpe |= BIT_IXC;
744
745 FPSR fpsr = ts->fpa.fpsr;
746 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
747
748 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
749 info.si_signo = SIGFPE;
750 info.si_errno = 0;
751
752 /* ordered by priority, least first */
753 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
754 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
755 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
756 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
757 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
758
759 info._sifields._sigfault._addr = env->regs[15];
624f7979 760 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 761 } else {
762 env->regs[15] += 4;
763 }
764
765 /* accumulate unenabled exceptions */
766 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
767 fpsr |= BIT_IXC;
768 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
769 fpsr |= BIT_UFC;
770 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
771 fpsr |= BIT_OFC;
772 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
773 fpsr |= BIT_DZC;
774 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
775 fpsr |= BIT_IOC;
776 ts->fpa.fpsr=fpsr;
777 } else { /* everything OK */
c6981055
FB		 778 /* increment PC */
779 env->regs[15] += 4;
780 }
781 }
b346ff46
FB		 782 break;
783 case EXCP_SWI:
06c949e6 784 case EXCP_BKPT:
b346ff46 785 {
ce4defa0 786 env->eabi = 1;
b346ff46 787 /* system call */
06c949e6
PB		 788 if (trapnr == EXCP_BKPT) {
789 if (env->thumb) {
2f619698 790 /* FIXME - what to do if get_user() fails? */
d8fd2954 791 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 792 n = insn & 0xff;
793 env->regs[15] += 2;
794 } else {
2f619698 795 /* FIXME - what to do if get_user() fails? */
d8fd2954 796 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 797 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
798 env->regs[15] += 4;
799 }
192c7bd9 800 } else {
06c949e6 801 if (env->thumb) {
2f619698 802 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 803 get_user_code_u16(insn, env->regs[15] - 2,
804 env->bswap_code);
06c949e6
PB		 805 n = insn & 0xff;
806 } else {
2f619698 807 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 808 get_user_code_u32(insn, env->regs[15] - 4,
809 env->bswap_code);
06c949e6
PB		 810 n = insn & 0xffffff;
811 }
192c7bd9
FB		 812 }
813
6f1f31c0 814 if (n == ARM_NR_cacheflush) {
dcfd14b3 815 /* nop */
a4f81979
FB		 816 } else if (n == ARM_NR_semihosting
817 || n == ARM_NR_thumb_semihosting) {
818 env->regs[0] = do_arm_semihosting (env);
3a1363ac 819 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 820 /* linux syscall */
ce4defa0 821 if (env->thumb || n == 0) {
192c7bd9
FB		 822 n = env->regs[7];
823 } else {
824 n -= ARM_SYSCALL_BASE;
ce4defa0 825 env->eabi = 0;
192c7bd9 826 }
fbb4a2e3
PB		 827 if ( n > ARM_NR_BASE) {
828 switch (n) {
829 case ARM_NR_cacheflush:
dcfd14b3 830 /* nop */
fbb4a2e3
PB		 831 break;
832 case ARM_NR_set_tls:
833 cpu_set_tls(env, env->regs[0]);
834 env->regs[0] = 0;
835 break;
836 default:
837 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
838 n);
839 env->regs[0] = -TARGET_ENOSYS;
840 break;
841 }
842 } else {
843 env->regs[0] = do_syscall(env,
844 n,
845 env->regs[0],
846 env->regs[1],
847 env->regs[2],
848 env->regs[3],
849 env->regs[4],
5945cfcb
PM		 850 env->regs[5],
851 0, 0);
fbb4a2e3 852 }
b346ff46
FB		 853 } else {
854 goto error;
855 }
856 }
857 break;
43fff238
FB		 858 case EXCP_INTERRUPT:
859 /* just indicate that signals should be handled asap */
860 break;
68016c62 861 case EXCP_PREFETCH_ABORT:
eae473c1 862 addr = env->cp15.c6_insn;
b5ff1b31 863 goto do_segv;
68016c62 864 case EXCP_DATA_ABORT:
eae473c1 865 addr = env->cp15.c6_data;
b5ff1b31 866 do_segv:
68016c62
FB		 867 {
868 info.si_signo = SIGSEGV;
869 info.si_errno = 0;
870 /* XXX: check env->error_code */
871 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 872 info._sifields._sigfault._addr = addr;
624f7979 873 queue_signal(env, info.si_signo, &info);
68016c62
FB		 874 }
875 break;
1fddef4b
FB		 876 case EXCP_DEBUG:
877 {
878 int sig;
879
880 sig = gdb_handlesig (env, TARGET_SIGTRAP);
881 if (sig)
882 {
883 info.si_signo = sig;
884 info.si_errno = 0;
885 info.si_code = TARGET_TRAP_BRKPT;
624f7979 886 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 887 }
888 }
889 break;
fbb4a2e3
PB		 890 case EXCP_KERNEL_TRAP:
891 if (do_kernel_trap(env))
892 goto error;
893 break;
426f5abc
PB		 894 case EXCP_STREX:
895 if (do_strex(env)) {
896 addr = env->cp15.c6_data;
897 goto do_segv;
898 }
e9273455 899 break;
b346ff46
FB		 900 default:
901 error:
5fafdf24 902 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 903 trapnr);
878096ee 904 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 905 abort();
906 }
907 process_pending_signals(env);
908 }
909}
910
911#endif
1b6b029e 912
d2fbca94
GX		 913#ifdef TARGET_UNICORE32
914
05390248 915void cpu_loop(CPUUniCore32State *env)
d2fbca94 916{
0315c31c 917 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 918 int trapnr;
919 unsigned int n, insn;
920 target_siginfo_t info;
921
922 for (;;) {
0315c31c 923 cpu_exec_start(cs);
d2fbca94 924 trapnr = uc32_cpu_exec(env);
0315c31c 925 cpu_exec_end(cs);
d2fbca94
GX		 926 switch (trapnr) {
927 case UC32_EXCP_PRIV:
928 {
929 /* system call */
930 get_user_u32(insn, env->regs[31] - 4);
931 n = insn & 0xffffff;
932
933 if (n >= UC32_SYSCALL_BASE) {
934 /* linux syscall */
935 n -= UC32_SYSCALL_BASE;
936 if (n == UC32_SYSCALL_NR_set_tls) {
937 cpu_set_tls(env, env->regs[0]);
938 env->regs[0] = 0;
939 } else {
940 env->regs[0] = do_syscall(env,
941 n,
942 env->regs[0],
943 env->regs[1],
944 env->regs[2],
945 env->regs[3],
946 env->regs[4],
5945cfcb
PM		 947 env->regs[5],
948 0, 0);
d2fbca94
GX		 949 }
950 } else {
951 goto error;
952 }
953 }
954 break;
d48813dd
GX		 955 case UC32_EXCP_DTRAP:
956 case UC32_EXCP_ITRAP:
d2fbca94
GX		 957 info.si_signo = SIGSEGV;
958 info.si_errno = 0;
959 /* XXX: check env->error_code */
960 info.si_code = TARGET_SEGV_MAPERR;
961 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
962 queue_signal(env, info.si_signo, &info);
963 break;
964 case EXCP_INTERRUPT:
965 /* just indicate that signals should be handled asap */
966 break;
967 case EXCP_DEBUG:
968 {
969 int sig;
970
971 sig = gdb_handlesig(env, TARGET_SIGTRAP);
972 if (sig) {
973 info.si_signo = sig;
974 info.si_errno = 0;
975 info.si_code = TARGET_TRAP_BRKPT;
976 queue_signal(env, info.si_signo, &info);
977 }
978 }
979 break;
980 default:
981 goto error;
982 }
983 process_pending_signals(env);
984 }
985
986error:
987 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 988 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 989 abort();
990}
991#endif
992
93ac68bc 993#ifdef TARGET_SPARC
ed23fbd9 994#define SPARC64_STACK_BIAS 2047
93ac68bc 995
060366c5
FB		 996//#define DEBUG_WIN
997
2623cbaf
FB		 998/* WARNING: dealing with register windows _is_ complicated. More info
999 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1000static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1001{
1a14026e 1002 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1003 /* wrap handling : if cwp is on the last window, then we use the
1004 registers 'after' the end */
1a14026e
BS		 1005 if (index < 8 && env->cwp == env->nwindows - 1)
1006 index += 16 * env->nwindows;
060366c5
FB		 1007 return index;
1008}
1009
2623cbaf
FB		 1010/* save the register window 'cwp1' */
1011static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1012{
2623cbaf 1013 unsigned int i;
992f48a0 1014 abi_ulong sp_ptr;
3b46e624 1015
53a5960a 1016 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1017#ifdef TARGET_SPARC64
1018 if (sp_ptr & 3)
1019 sp_ptr += SPARC64_STACK_BIAS;
1020#endif
060366c5 1021#if defined(DEBUG_WIN)
2daf0284
BS		 1022 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1023 sp_ptr, cwp1);
060366c5 1024#endif
2623cbaf 1025 for(i = 0; i < 16; i++) {
2f619698
FB		 1026 /* FIXME - what to do if put_user() fails? */
1027 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1028 sp_ptr += sizeof(abi_ulong);
2623cbaf 1029 }
060366c5
FB		 1030}
1031
1032static void save_window(CPUSPARCState *env)
1033{
5ef54116 1034#ifndef TARGET_SPARC64
2623cbaf 1035 unsigned int new_wim;
1a14026e
BS		 1036 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1037 ((1LL << env->nwindows) - 1);
1038 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1039 env->wim = new_wim;
5ef54116 1040#else
1a14026e 1041 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1042 env->cansave++;
1043 env->canrestore--;
1044#endif
060366c5
FB		 1045}
1046
1047static void restore_window(CPUSPARCState *env)
1048{
eda52953
BS		 1049#ifndef TARGET_SPARC64
1050 unsigned int new_wim;
1051#endif
1052 unsigned int i, cwp1;
992f48a0 1053 abi_ulong sp_ptr;
3b46e624 1054
eda52953 1055#ifndef TARGET_SPARC64
1a14026e
BS		 1056 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1057 ((1LL << env->nwindows) - 1);
eda52953 1058#endif
3b46e624 1059
060366c5 1060 /* restore the invalid window */
1a14026e 1061 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1062 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1063#ifdef TARGET_SPARC64
1064 if (sp_ptr & 3)
1065 sp_ptr += SPARC64_STACK_BIAS;
1066#endif
060366c5 1067#if defined(DEBUG_WIN)
2daf0284
BS		 1068 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1069 sp_ptr, cwp1);
060366c5 1070#endif
2623cbaf 1071 for(i = 0; i < 16; i++) {
2f619698
FB		 1072 /* FIXME - what to do if get_user() fails? */
1073 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1074 sp_ptr += sizeof(abi_ulong);
2623cbaf 1075 }
5ef54116
FB		 1076#ifdef TARGET_SPARC64
1077 env->canrestore++;
1a14026e
BS		 1078 if (env->cleanwin < env->nwindows - 1)
1079 env->cleanwin++;
5ef54116 1080 env->cansave--;
eda52953
BS		 1081#else
1082 env->wim = new_wim;
5ef54116 1083#endif
060366c5
FB		 1084}
1085
1086static void flush_windows(CPUSPARCState *env)
1087{
1088 int offset, cwp1;
2623cbaf
FB		 1089
1090 offset = 1;
060366c5
FB		 1091 for(;;) {
1092 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1093 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1094#ifndef TARGET_SPARC64
060366c5
FB		 1095 if (env->wim & (1 << cwp1))
1096 break;
eda52953
BS		 1097#else
1098 if (env->canrestore == 0)
1099 break;
1100 env->cansave++;
1101 env->canrestore--;
1102#endif
2623cbaf 1103 save_window_offset(env, cwp1);
060366c5
FB		 1104 offset++;
1105 }
1a14026e 1106 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1107#ifndef TARGET_SPARC64
1108 /* set wim so that restore will reload the registers */
2623cbaf 1109 env->wim = 1 << cwp1;
eda52953 1110#endif
2623cbaf
FB		 1111#if defined(DEBUG_WIN)
1112 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1113#endif
2623cbaf 1114}
060366c5 1115
93ac68bc
FB		 1116void cpu_loop (CPUSPARCState *env)
1117{
878096ee 1118 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1119 int trapnr;
1120 abi_long ret;
c227f099 1121 target_siginfo_t info;
3b46e624 1122
060366c5
FB		 1123 while (1) {
1124 trapnr = cpu_sparc_exec (env);
3b46e624 1125
20132b96
RH		 1126 /* Compute PSR before exposing state. */
1127 if (env->cc_op != CC_OP_FLAGS) {
1128 cpu_get_psr(env);
1129 }
1130
060366c5 1131 switch (trapnr) {
5ef54116 1132#ifndef TARGET_SPARC64
5fafdf24 1133 case 0x88:
060366c5 1134 case 0x90:
5ef54116 1135#else
cb33da57 1136 case 0x110:
5ef54116
FB		 1137 case 0x16d:
1138#endif
060366c5 1139 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1140 env->regwptr[0], env->regwptr[1],
1141 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1142 env->regwptr[4], env->regwptr[5],
1143 0, 0);
2cc20260 1144 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1145#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1146 env->xcc |= PSR_CARRY;
1147#else
060366c5 1148 env->psr |= PSR_CARRY;
27908725 1149#endif
060366c5
FB		 1150 ret = -ret;
1151 } else {
992f48a0 1152#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1153 env->xcc &= ~PSR_CARRY;
1154#else
060366c5 1155 env->psr &= ~PSR_CARRY;
27908725 1156#endif
060366c5
FB		 1157 }
1158 env->regwptr[0] = ret;
1159 /* next instruction */
1160 env->pc = env->npc;
1161 env->npc = env->npc + 4;
1162 break;
1163 case 0x83: /* flush windows */
992f48a0
BS		 1164#ifdef TARGET_ABI32
1165 case 0x103:
1166#endif
2623cbaf 1167 flush_windows(env);
060366c5
FB		 1168 /* next instruction */
1169 env->pc = env->npc;
1170 env->npc = env->npc + 4;
1171 break;
3475187d 1172#ifndef TARGET_SPARC64
060366c5
FB		 1173 case TT_WIN_OVF: /* window overflow */
1174 save_window(env);
1175 break;
1176 case TT_WIN_UNF: /* window underflow */
1177 restore_window(env);
1178 break;
61ff6f58
FB		 1179 case TT_TFAULT:
1180 case TT_DFAULT:
1181 {
59f7182f 1182 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1183 info.si_errno = 0;
1184 /* XXX: check env->error_code */
1185 info.si_code = TARGET_SEGV_MAPERR;
1186 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1187 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1188 }
1189 break;
3475187d 1190#else
5ef54116
FB		 1191 case TT_SPILL: /* window overflow */
1192 save_window(env);
1193 break;
1194 case TT_FILL: /* window underflow */
1195 restore_window(env);
1196 break;
7f84a729
BS		 1197 case TT_TFAULT:
1198 case TT_DFAULT:
1199 {
59f7182f 1200 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1201 info.si_errno = 0;
1202 /* XXX: check env->error_code */
1203 info.si_code = TARGET_SEGV_MAPERR;
1204 if (trapnr == TT_DFAULT)
1205 info._sifields._sigfault._addr = env->dmmuregs[4];
1206 else
8194f35a 1207 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1208 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1209 }
1210 break;
27524dc3 1211#ifndef TARGET_ABI32
5bfb56b2
BS		 1212 case 0x16e:
1213 flush_windows(env);
1214 sparc64_get_context(env);
1215 break;
1216 case 0x16f:
1217 flush_windows(env);
1218 sparc64_set_context(env);
1219 break;
27524dc3 1220#endif
3475187d 1221#endif
48dc41eb
FB		 1222 case EXCP_INTERRUPT:
1223 /* just indicate that signals should be handled asap */
1224 break;
75f22e4e
RH		 1225 case TT_ILL_INSN:
1226 {
1227 info.si_signo = TARGET_SIGILL;
1228 info.si_errno = 0;
1229 info.si_code = TARGET_ILL_ILLOPC;
1230 info._sifields._sigfault._addr = env->pc;
1231 queue_signal(env, info.si_signo, &info);
1232 }
1233 break;
1fddef4b
FB		 1234 case EXCP_DEBUG:
1235 {
1236 int sig;
1237
1238 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1239 if (sig)
1240 {
1241 info.si_signo = sig;
1242 info.si_errno = 0;
1243 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1244 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1245 }
1246 }
1247 break;
060366c5
FB		 1248 default:
1249 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1250 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1251 exit (1);
1252 }
1253 process_pending_signals (env);
1254 }
93ac68bc
FB		 1255}
1256
1257#endif
1258
67867308 1259#ifdef TARGET_PPC
05390248 1260static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1261{
1262 /* TO FIX */
1263 return 0;
1264}
3b46e624 1265
05390248 1266uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1267{
e3ea6529 1268 return cpu_ppc_get_tb(env);
9fddaa0c 1269}
3b46e624 1270
05390248 1271uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1272{
1273 return cpu_ppc_get_tb(env) >> 32;
1274}
3b46e624 1275
05390248 1276uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1277{
b711de95 1278 return cpu_ppc_get_tb(env);
9fddaa0c 1279}
5fafdf24 1280
05390248 1281uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1282{
a062e36c 1283 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1284}
76a66253 1285
05390248 1286uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1287__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1288
05390248 1289uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1290{
76a66253 1291 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1292}
76a66253 1293
a750fc0b 1294/* XXX: to be fixed */
73b01960 1295int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1296{
1297 return -1;
1298}
1299
73b01960 1300int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1301{
1302 return -1;
1303}
1304
001faf32
BS		 1305#define EXCP_DUMP(env, fmt, ...) \
1306do { \
1307 fprintf(stderr, fmt , ## __VA_ARGS__); \
878096ee 1308 cpu_dump_state(ENV_GET_CPU(env), stderr, fprintf, 0); \
001faf32 1309 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1310 if (qemu_log_enabled()) { \
430c7ec7 1311 log_cpu_state(env, 0); \
eeacee4d 1312 } \
e1833e1f
JM		 1313} while (0)
1314
56f066bb
NF		 1315static int do_store_exclusive(CPUPPCState *env)
1316{
1317 target_ulong addr;
1318 target_ulong page_addr;
1319 target_ulong val;
1320 int flags;
1321 int segv = 0;
1322
1323 addr = env->reserve_ea;
1324 page_addr = addr & TARGET_PAGE_MASK;
1325 start_exclusive();
1326 mmap_lock();
1327 flags = page_get_flags(page_addr);
1328 if ((flags & PAGE_READ) == 0) {
1329 segv = 1;
1330 } else {
1331 int reg = env->reserve_info & 0x1f;
1332 int size = (env->reserve_info >> 5) & 0xf;
1333 int stored = 0;
1334
1335 if (addr == env->reserve_addr) {
1336 switch (size) {
1337 case 1: segv = get_user_u8(val, addr); break;
1338 case 2: segv = get_user_u16(val, addr); break;
1339 case 4: segv = get_user_u32(val, addr); break;
1340#if defined(TARGET_PPC64)
1341 case 8: segv = get_user_u64(val, addr); break;
1342#endif
1343 default: abort();
1344 }
1345 if (!segv && val == env->reserve_val) {
1346 val = env->gpr[reg];
1347 switch (size) {
1348 case 1: segv = put_user_u8(val, addr); break;
1349 case 2: segv = put_user_u16(val, addr); break;
1350 case 4: segv = put_user_u32(val, addr); break;
1351#if defined(TARGET_PPC64)
1352 case 8: segv = put_user_u64(val, addr); break;
1353#endif
1354 default: abort();
1355 }
1356 if (!segv) {
1357 stored = 1;
1358 }
1359 }
1360 }
1361 env->crf[0] = (stored << 1) | xer_so;
1362 env->reserve_addr = (target_ulong)-1;
1363 }
1364 if (!segv) {
1365 env->nip += 4;
1366 }
1367 mmap_unlock();
1368 end_exclusive();
1369 return segv;
1370}
1371
67867308
FB		 1372void cpu_loop(CPUPPCState *env)
1373{
0315c31c 1374 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1375 target_siginfo_t info;
61190b14 1376 int trapnr;
9e0e2f96 1377 target_ulong ret;
3b46e624 1378
67867308 1379 for(;;) {
0315c31c 1380 cpu_exec_start(cs);
67867308 1381 trapnr = cpu_ppc_exec(env);
0315c31c 1382 cpu_exec_end(cs);
67867308 1383 switch(trapnr) {
e1833e1f
JM		 1384 case POWERPC_EXCP_NONE:
1385 /* Just go on */
67867308 1386 break;
e1833e1f
JM		 1387 case POWERPC_EXCP_CRITICAL: /* Critical input */
1388 cpu_abort(env, "Critical interrupt while in user mode. "
1389 "Aborting\n");
61190b14 1390 break;
e1833e1f
JM		 1391 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1392 cpu_abort(env, "Machine check exception while in user mode. "
1393 "Aborting\n");
1394 break;
1395 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1396 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1397 env->spr[SPR_DAR]);
1398 /* XXX: check this. Seems bugged */
2be0071f
FB		 1399 switch (env->error_code & 0xFF000000) {
1400 case 0x40000000:
61190b14
FB		 1401 info.si_signo = TARGET_SIGSEGV;
1402 info.si_errno = 0;
1403 info.si_code = TARGET_SEGV_MAPERR;
1404 break;
2be0071f 1405 case 0x04000000:
61190b14
FB		 1406 info.si_signo = TARGET_SIGILL;
1407 info.si_errno = 0;
1408 info.si_code = TARGET_ILL_ILLADR;
1409 break;
2be0071f 1410 case 0x08000000:
61190b14
FB		 1411 info.si_signo = TARGET_SIGSEGV;
1412 info.si_errno = 0;
1413 info.si_code = TARGET_SEGV_ACCERR;
1414 break;
61190b14
FB		 1415 default:
1416 /* Let's send a regular segfault... */
e1833e1f
JM		 1417 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1418 env->error_code);
61190b14
FB		 1419 info.si_signo = TARGET_SIGSEGV;
1420 info.si_errno = 0;
1421 info.si_code = TARGET_SEGV_MAPERR;
1422 break;
1423 }
67867308 1424 info._sifields._sigfault._addr = env->nip;
624f7979 1425 queue_signal(env, info.si_signo, &info);
67867308 1426 break;
e1833e1f 1427 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1428 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1429 "\n", env->spr[SPR_SRR0]);
e1833e1f 1430 /* XXX: check this */
2be0071f
FB		 1431 switch (env->error_code & 0xFF000000) {
1432 case 0x40000000:
61190b14 1433 info.si_signo = TARGET_SIGSEGV;
67867308 1434 info.si_errno = 0;
61190b14
FB		 1435 info.si_code = TARGET_SEGV_MAPERR;
1436 break;
2be0071f
FB		 1437 case 0x10000000:
1438 case 0x08000000:
61190b14
FB		 1439 info.si_signo = TARGET_SIGSEGV;
1440 info.si_errno = 0;
1441 info.si_code = TARGET_SEGV_ACCERR;
1442 break;
1443 default:
1444 /* Let's send a regular segfault... */
e1833e1f
JM		 1445 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1446 env->error_code);
61190b14
FB		 1447 info.si_signo = TARGET_SIGSEGV;
1448 info.si_errno = 0;
1449 info.si_code = TARGET_SEGV_MAPERR;
1450 break;
1451 }
1452 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1453 queue_signal(env, info.si_signo, &info);
67867308 1454 break;
e1833e1f
JM		 1455 case POWERPC_EXCP_EXTERNAL: /* External input */
1456 cpu_abort(env, "External interrupt while in user mode. "
1457 "Aborting\n");
1458 break;
1459 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1460 EXCP_DUMP(env, "Unaligned memory access\n");
1461 /* XXX: check this */
61190b14 1462 info.si_signo = TARGET_SIGBUS;
67867308 1463 info.si_errno = 0;
61190b14
FB		 1464 info.si_code = TARGET_BUS_ADRALN;
1465 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1466 queue_signal(env, info.si_signo, &info);
67867308 1467 break;
e1833e1f
JM		 1468 case POWERPC_EXCP_PROGRAM: /* Program exception */
1469 /* XXX: check this */
61190b14 1470 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1471 case POWERPC_EXCP_FP:
1472 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1473 info.si_signo = TARGET_SIGFPE;
1474 info.si_errno = 0;
1475 switch (env->error_code & 0xF) {
e1833e1f 1476 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1477 info.si_code = TARGET_FPE_FLTOVF;
1478 break;
e1833e1f 1479 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1480 info.si_code = TARGET_FPE_FLTUND;
1481 break;
e1833e1f
JM		 1482 case POWERPC_EXCP_FP_ZX:
1483 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1484 info.si_code = TARGET_FPE_FLTDIV;
1485 break;
e1833e1f 1486 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1487 info.si_code = TARGET_FPE_FLTRES;
1488 break;
e1833e1f 1489 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1490 info.si_code = TARGET_FPE_FLTINV;
1491 break;
7c58044c 1492 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1493 case POWERPC_EXCP_FP_VXISI:
1494 case POWERPC_EXCP_FP_VXIDI:
1495 case POWERPC_EXCP_FP_VXIMZ:
1496 case POWERPC_EXCP_FP_VXVC:
1497 case POWERPC_EXCP_FP_VXSQRT:
1498 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1499 info.si_code = TARGET_FPE_FLTSUB;
1500 break;
1501 default:
e1833e1f
JM		 1502 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1503 env->error_code);
1504 break;
61190b14 1505 }
e1833e1f
JM		 1506 break;
1507 case POWERPC_EXCP_INVAL:
1508 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1509 info.si_signo = TARGET_SIGILL;
1510 info.si_errno = 0;
1511 switch (env->error_code & 0xF) {
e1833e1f 1512 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1513 info.si_code = TARGET_ILL_ILLOPC;
1514 break;
e1833e1f 1515 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1516 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1517 break;
e1833e1f 1518 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1519 info.si_code = TARGET_ILL_PRVREG;
1520 break;
e1833e1f 1521 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1522 info.si_code = TARGET_ILL_COPROC;
1523 break;
1524 default:
e1833e1f
JM		 1525 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1526 env->error_code & 0xF);
61190b14
FB		 1527 info.si_code = TARGET_ILL_ILLADR;
1528 break;
1529 }
1530 break;
e1833e1f
JM		 1531 case POWERPC_EXCP_PRIV:
1532 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1533 info.si_signo = TARGET_SIGILL;
1534 info.si_errno = 0;
1535 switch (env->error_code & 0xF) {
e1833e1f 1536 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1537 info.si_code = TARGET_ILL_PRVOPC;
1538 break;
e1833e1f 1539 case POWERPC_EXCP_PRIV_REG:
61190b14 1540 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1541 break;
61190b14 1542 default:
e1833e1f
JM		 1543 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1544 env->error_code & 0xF);
61190b14
FB		 1545 info.si_code = TARGET_ILL_PRVOPC;
1546 break;
1547 }
1548 break;
e1833e1f
JM		 1549 case POWERPC_EXCP_TRAP:
1550 cpu_abort(env, "Tried to call a TRAP\n");
1551 break;
61190b14
FB		 1552 default:
1553 /* Should not happen ! */
e1833e1f
JM		 1554 cpu_abort(env, "Unknown program exception (%02x)\n",
1555 env->error_code);
1556 break;
61190b14
FB		 1557 }
1558 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1559 queue_signal(env, info.si_signo, &info);
67867308 1560 break;
e1833e1f
JM		 1561 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1562 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1563 info.si_signo = TARGET_SIGILL;
67867308 1564 info.si_errno = 0;
61190b14
FB		 1565 info.si_code = TARGET_ILL_COPROC;
1566 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1567 queue_signal(env, info.si_signo, &info);
67867308 1568 break;
e1833e1f
JM		 1569 case POWERPC_EXCP_SYSCALL: /* System call exception */
1570 cpu_abort(env, "Syscall exception while in user mode. "
1571 "Aborting\n");
61190b14 1572 break;
e1833e1f
JM		 1573 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1574 EXCP_DUMP(env, "No APU instruction allowed\n");
1575 info.si_signo = TARGET_SIGILL;
1576 info.si_errno = 0;
1577 info.si_code = TARGET_ILL_COPROC;
1578 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1579 queue_signal(env, info.si_signo, &info);
61190b14 1580 break;
e1833e1f
JM		 1581 case POWERPC_EXCP_DECR: /* Decrementer exception */
1582 cpu_abort(env, "Decrementer interrupt while in user mode. "
1583 "Aborting\n");
61190b14 1584 break;
e1833e1f
JM		 1585 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1586 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1587 "Aborting\n");
1588 break;
1589 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1590 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1591 "Aborting\n");
1592 break;
1593 case POWERPC_EXCP_DTLB: /* Data TLB error */
1594 cpu_abort(env, "Data TLB exception while in user mode. "
1595 "Aborting\n");
1596 break;
1597 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1598 cpu_abort(env, "Instruction TLB exception while in user mode. "
1599 "Aborting\n");
1600 break;
e1833e1f
JM		 1601 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1602 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1603 info.si_signo = TARGET_SIGILL;
1604 info.si_errno = 0;
1605 info.si_code = TARGET_ILL_COPROC;
1606 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1607 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1608 break;
1609 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1610 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1611 break;
1612 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1613 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1614 break;
1615 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1616 cpu_abort(env, "Performance monitor exception not handled\n");
1617 break;
1618 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1619 cpu_abort(env, "Doorbell interrupt while in user mode. "
1620 "Aborting\n");
1621 break;
1622 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1623 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1624 "Aborting\n");
1625 break;
1626 case POWERPC_EXCP_RESET: /* System reset exception */
1627 cpu_abort(env, "Reset interrupt while in user mode. "
1628 "Aborting\n");
1629 break;
e1833e1f
JM		 1630 case POWERPC_EXCP_DSEG: /* Data segment exception */
1631 cpu_abort(env, "Data segment exception while in user mode. "
1632 "Aborting\n");
1633 break;
1634 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1635 cpu_abort(env, "Instruction segment exception "
1636 "while in user mode. Aborting\n");
1637 break;
e85e7c6e 1638 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1639 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1640 cpu_abort(env, "Hypervisor decrementer interrupt "
1641 "while in user mode. Aborting\n");
1642 break;
e1833e1f
JM		 1643 case POWERPC_EXCP_TRACE: /* Trace exception */
1644 /* Nothing to do:
1645 * we use this exception to emulate step-by-step execution mode.
1646 */
1647 break;
e85e7c6e 1648 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1649 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1650 cpu_abort(env, "Hypervisor data storage exception "
1651 "while in user mode. Aborting\n");
1652 break;
1653 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1654 cpu_abort(env, "Hypervisor instruction storage exception "
1655 "while in user mode. Aborting\n");
1656 break;
1657 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1658 cpu_abort(env, "Hypervisor data segment exception "
1659 "while in user mode. Aborting\n");
1660 break;
1661 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1662 cpu_abort(env, "Hypervisor instruction segment exception "
1663 "while in user mode. Aborting\n");
1664 break;
e1833e1f
JM		 1665 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1666 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1667 info.si_signo = TARGET_SIGILL;
1668 info.si_errno = 0;
1669 info.si_code = TARGET_ILL_COPROC;
1670 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1671 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1672 break;
1673 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1674 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1675 "while in user mode. Aborting\n");
1676 break;
1677 case POWERPC_EXCP_IO: /* IO error exception */
1678 cpu_abort(env, "IO error exception while in user mode. "
1679 "Aborting\n");
1680 break;
1681 case POWERPC_EXCP_RUNM: /* Run mode exception */
1682 cpu_abort(env, "Run mode exception while in user mode. "
1683 "Aborting\n");
1684 break;
1685 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1686 cpu_abort(env, "Emulation trap exception not handled\n");
1687 break;
1688 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1689 cpu_abort(env, "Instruction fetch TLB exception "
1690 "while in user-mode. Aborting");
1691 break;
1692 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1693 cpu_abort(env, "Data load TLB exception while in user-mode. "
1694 "Aborting");
1695 break;
1696 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1697 cpu_abort(env, "Data store TLB exception while in user-mode. "
1698 "Aborting");
1699 break;
1700 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1701 cpu_abort(env, "Floating-point assist exception not handled\n");
1702 break;
1703 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1704 cpu_abort(env, "Instruction address breakpoint exception "
1705 "not handled\n");
1706 break;
1707 case POWERPC_EXCP_SMI: /* System management interrupt */
1708 cpu_abort(env, "System management interrupt while in user mode. "
1709 "Aborting\n");
1710 break;
1711 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1712 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1713 "Aborting\n");
1714 break;
1715 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1716 cpu_abort(env, "Performance monitor exception not handled\n");
1717 break;
1718 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1719 cpu_abort(env, "Vector assist exception not handled\n");
1720 break;
1721 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1722 cpu_abort(env, "Soft patch exception not handled\n");
1723 break;
1724 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1725 cpu_abort(env, "Maintenance exception while in user mode. "
1726 "Aborting\n");
1727 break;
1728 case POWERPC_EXCP_STOP: /* stop translation */
1729 /* We did invalidate the instruction cache. Go on */
1730 break;
1731 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1732 /* We just stopped because of a branch. Go on */
1733 break;
1734 case POWERPC_EXCP_SYSCALL_USER:
1735 /* system call in user-mode emulation */
1736 /* WARNING:
1737 * PPC ABI uses overflow flag in cr0 to signal an error
1738 * in syscalls.
1739 */
e1833e1f
JM		 1740 env->crf[0] &= ~0x1;
1741 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1742 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1743 env->gpr[8], 0, 0);
9e0e2f96 1744 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1745 /* Returning from a successful sigreturn syscall.
1746 Avoid corrupting register state. */
1747 break;
1748 }
9e0e2f96 1749 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1750 env->crf[0] |= 0x1;
1751 ret = -ret;
61190b14 1752 }
e1833e1f 1753 env->gpr[3] = ret;
e1833e1f 1754 break;
56f066bb
NF		 1755 case POWERPC_EXCP_STCX:
1756 if (do_store_exclusive(env)) {
1757 info.si_signo = TARGET_SIGSEGV;
1758 info.si_errno = 0;
1759 info.si_code = TARGET_SEGV_MAPERR;
1760 info._sifields._sigfault._addr = env->nip;
1761 queue_signal(env, info.si_signo, &info);
1762 }
1763 break;
71f75756
AJ		 1764 case EXCP_DEBUG:
1765 {
1766 int sig;
1767
1768 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1769 if (sig) {
1770 info.si_signo = sig;
1771 info.si_errno = 0;
1772 info.si_code = TARGET_TRAP_BRKPT;
1773 queue_signal(env, info.si_signo, &info);
1774 }
1775 }
1776 break;
56ba31ff
JM		 1777 case EXCP_INTERRUPT:
1778 /* just indicate that signals should be handled asap */
1779 break;
e1833e1f
JM		 1780 default:
1781 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1782 break;
67867308
FB		 1783 }
1784 process_pending_signals(env);
1785 }
1786}
1787#endif
1788
048f6b4d
FB		 1789#ifdef TARGET_MIPS
1790
ff4f7382
RH		 1791# ifdef TARGET_ABI_MIPSO32
1792# define MIPS_SYS(name, args) args,
048f6b4d 1793static const uint8_t mips_syscall_args[] = {
29fb0f25 1794 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1795 MIPS_SYS(sys_exit , 1)
1796 MIPS_SYS(sys_fork , 0)
1797 MIPS_SYS(sys_read , 3)
1798 MIPS_SYS(sys_write , 3)
1799 MIPS_SYS(sys_open , 3) /* 4005 */
1800 MIPS_SYS(sys_close , 1)
1801 MIPS_SYS(sys_waitpid , 3)
1802 MIPS_SYS(sys_creat , 2)
1803 MIPS_SYS(sys_link , 2)
1804 MIPS_SYS(sys_unlink , 1) /* 4010 */
1805 MIPS_SYS(sys_execve , 0)
1806 MIPS_SYS(sys_chdir , 1)
1807 MIPS_SYS(sys_time , 1)
1808 MIPS_SYS(sys_mknod , 3)
1809 MIPS_SYS(sys_chmod , 2) /* 4015 */
1810 MIPS_SYS(sys_lchown , 3)
1811 MIPS_SYS(sys_ni_syscall , 0)
1812 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1813 MIPS_SYS(sys_lseek , 3)
1814 MIPS_SYS(sys_getpid , 0) /* 4020 */
1815 MIPS_SYS(sys_mount , 5)
1816 MIPS_SYS(sys_oldumount , 1)
1817 MIPS_SYS(sys_setuid , 1)
1818 MIPS_SYS(sys_getuid , 0)
1819 MIPS_SYS(sys_stime , 1) /* 4025 */
1820 MIPS_SYS(sys_ptrace , 4)
1821 MIPS_SYS(sys_alarm , 1)
1822 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1823 MIPS_SYS(sys_pause , 0)
1824 MIPS_SYS(sys_utime , 2) /* 4030 */
1825 MIPS_SYS(sys_ni_syscall , 0)
1826 MIPS_SYS(sys_ni_syscall , 0)
1827 MIPS_SYS(sys_access , 2)
1828 MIPS_SYS(sys_nice , 1)
1829 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1830 MIPS_SYS(sys_sync , 0)
1831 MIPS_SYS(sys_kill , 2)
1832 MIPS_SYS(sys_rename , 2)
1833 MIPS_SYS(sys_mkdir , 2)
1834 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1835 MIPS_SYS(sys_dup , 1)
1836 MIPS_SYS(sys_pipe , 0)
1837 MIPS_SYS(sys_times , 1)
1838 MIPS_SYS(sys_ni_syscall , 0)
1839 MIPS_SYS(sys_brk , 1) /* 4045 */
1840 MIPS_SYS(sys_setgid , 1)
1841 MIPS_SYS(sys_getgid , 0)
1842 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1843 MIPS_SYS(sys_geteuid , 0)
1844 MIPS_SYS(sys_getegid , 0) /* 4050 */
1845 MIPS_SYS(sys_acct , 0)
1846 MIPS_SYS(sys_umount , 2)
1847 MIPS_SYS(sys_ni_syscall , 0)
1848 MIPS_SYS(sys_ioctl , 3)
1849 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1850 MIPS_SYS(sys_ni_syscall , 2)
1851 MIPS_SYS(sys_setpgid , 2)
1852 MIPS_SYS(sys_ni_syscall , 0)
1853 MIPS_SYS(sys_olduname , 1)
1854 MIPS_SYS(sys_umask , 1) /* 4060 */
1855 MIPS_SYS(sys_chroot , 1)
1856 MIPS_SYS(sys_ustat , 2)
1857 MIPS_SYS(sys_dup2 , 2)
1858 MIPS_SYS(sys_getppid , 0)
1859 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1860 MIPS_SYS(sys_setsid , 0)
1861 MIPS_SYS(sys_sigaction , 3)
1862 MIPS_SYS(sys_sgetmask , 0)
1863 MIPS_SYS(sys_ssetmask , 1)
1864 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1865 MIPS_SYS(sys_setregid , 2)
1866 MIPS_SYS(sys_sigsuspend , 0)
1867 MIPS_SYS(sys_sigpending , 1)
1868 MIPS_SYS(sys_sethostname , 2)
1869 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1870 MIPS_SYS(sys_getrlimit , 2)
1871 MIPS_SYS(sys_getrusage , 2)
1872 MIPS_SYS(sys_gettimeofday, 2)
1873 MIPS_SYS(sys_settimeofday, 2)
1874 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1875 MIPS_SYS(sys_setgroups , 2)
1876 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1877 MIPS_SYS(sys_symlink , 2)
1878 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1879 MIPS_SYS(sys_readlink , 3) /* 4085 */
1880 MIPS_SYS(sys_uselib , 1)
1881 MIPS_SYS(sys_swapon , 2)
1882 MIPS_SYS(sys_reboot , 3)
1883 MIPS_SYS(old_readdir , 3)
1884 MIPS_SYS(old_mmap , 6) /* 4090 */
1885 MIPS_SYS(sys_munmap , 2)
1886 MIPS_SYS(sys_truncate , 2)
1887 MIPS_SYS(sys_ftruncate , 2)
1888 MIPS_SYS(sys_fchmod , 2)
1889 MIPS_SYS(sys_fchown , 3) /* 4095 */
1890 MIPS_SYS(sys_getpriority , 2)
1891 MIPS_SYS(sys_setpriority , 3)
1892 MIPS_SYS(sys_ni_syscall , 0)
1893 MIPS_SYS(sys_statfs , 2)
1894 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1895 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1896 MIPS_SYS(sys_socketcall , 2)
1897 MIPS_SYS(sys_syslog , 3)
1898 MIPS_SYS(sys_setitimer , 3)
1899 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1900 MIPS_SYS(sys_newstat , 2)
1901 MIPS_SYS(sys_newlstat , 2)
1902 MIPS_SYS(sys_newfstat , 2)
1903 MIPS_SYS(sys_uname , 1)
1904 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1905 MIPS_SYS(sys_vhangup , 0)
1906 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1907 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1908 MIPS_SYS(sys_wait4 , 4)
1909 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1910 MIPS_SYS(sys_sysinfo , 1)
1911 MIPS_SYS(sys_ipc , 6)
1912 MIPS_SYS(sys_fsync , 1)
1913 MIPS_SYS(sys_sigreturn , 0)
18113962 1914 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1915 MIPS_SYS(sys_setdomainname, 2)
1916 MIPS_SYS(sys_newuname , 1)
1917 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1918 MIPS_SYS(sys_adjtimex , 1)
1919 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1920 MIPS_SYS(sys_sigprocmask , 3)
1921 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1922 MIPS_SYS(sys_init_module , 5)
1923 MIPS_SYS(sys_delete_module, 1)
1924 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1925 MIPS_SYS(sys_quotactl , 0)
1926 MIPS_SYS(sys_getpgid , 1)
1927 MIPS_SYS(sys_fchdir , 1)
1928 MIPS_SYS(sys_bdflush , 2)
1929 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1930 MIPS_SYS(sys_personality , 1)
1931 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1932 MIPS_SYS(sys_setfsuid , 1)
1933 MIPS_SYS(sys_setfsgid , 1)
1934 MIPS_SYS(sys_llseek , 5) /* 4140 */
1935 MIPS_SYS(sys_getdents , 3)
1936 MIPS_SYS(sys_select , 5)
1937 MIPS_SYS(sys_flock , 2)
1938 MIPS_SYS(sys_msync , 3)
1939 MIPS_SYS(sys_readv , 3) /* 4145 */
1940 MIPS_SYS(sys_writev , 3)
1941 MIPS_SYS(sys_cacheflush , 3)
1942 MIPS_SYS(sys_cachectl , 3)
1943 MIPS_SYS(sys_sysmips , 4)
1944 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1945 MIPS_SYS(sys_getsid , 1)
1946 MIPS_SYS(sys_fdatasync , 0)
1947 MIPS_SYS(sys_sysctl , 1)
1948 MIPS_SYS(sys_mlock , 2)
1949 MIPS_SYS(sys_munlock , 2) /* 4155 */
1950 MIPS_SYS(sys_mlockall , 1)
1951 MIPS_SYS(sys_munlockall , 0)
1952 MIPS_SYS(sys_sched_setparam, 2)
1953 MIPS_SYS(sys_sched_getparam, 2)
1954 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1955 MIPS_SYS(sys_sched_getscheduler, 1)
1956 MIPS_SYS(sys_sched_yield , 0)
1957 MIPS_SYS(sys_sched_get_priority_max, 1)
1958 MIPS_SYS(sys_sched_get_priority_min, 1)
1959 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1960 MIPS_SYS(sys_nanosleep, 2)
1961 MIPS_SYS(sys_mremap , 4)
1962 MIPS_SYS(sys_accept , 3)
1963 MIPS_SYS(sys_bind , 3)
1964 MIPS_SYS(sys_connect , 3) /* 4170 */
1965 MIPS_SYS(sys_getpeername , 3)
1966 MIPS_SYS(sys_getsockname , 3)
1967 MIPS_SYS(sys_getsockopt , 5)
1968 MIPS_SYS(sys_listen , 2)
1969 MIPS_SYS(sys_recv , 4) /* 4175 */
1970 MIPS_SYS(sys_recvfrom , 6)
1971 MIPS_SYS(sys_recvmsg , 3)
1972 MIPS_SYS(sys_send , 4)
1973 MIPS_SYS(sys_sendmsg , 3)
1974 MIPS_SYS(sys_sendto , 6) /* 4180 */
1975 MIPS_SYS(sys_setsockopt , 5)
1976 MIPS_SYS(sys_shutdown , 2)
1977 MIPS_SYS(sys_socket , 3)
1978 MIPS_SYS(sys_socketpair , 4)
1979 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1980 MIPS_SYS(sys_getresuid , 3)
1981 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1982 MIPS_SYS(sys_poll , 3)
1983 MIPS_SYS(sys_nfsservctl , 3)
1984 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1985 MIPS_SYS(sys_getresgid , 3)
1986 MIPS_SYS(sys_prctl , 5)
1987 MIPS_SYS(sys_rt_sigreturn, 0)
1988 MIPS_SYS(sys_rt_sigaction, 4)
1989 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1990 MIPS_SYS(sys_rt_sigpending, 2)
1991 MIPS_SYS(sys_rt_sigtimedwait, 4)
1992 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1993 MIPS_SYS(sys_rt_sigsuspend, 0)
1994 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1995 MIPS_SYS(sys_pwrite64 , 6)
1996 MIPS_SYS(sys_chown , 3)
1997 MIPS_SYS(sys_getcwd , 2)
1998 MIPS_SYS(sys_capget , 2)
1999 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2000 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2001 MIPS_SYS(sys_sendfile , 4)
2002 MIPS_SYS(sys_ni_syscall , 0)
2003 MIPS_SYS(sys_ni_syscall , 0)
2004 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2005 MIPS_SYS(sys_truncate64 , 4)
2006 MIPS_SYS(sys_ftruncate64 , 4)
2007 MIPS_SYS(sys_stat64 , 2)
2008 MIPS_SYS(sys_lstat64 , 2)
2009 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2010 MIPS_SYS(sys_pivot_root , 2)
2011 MIPS_SYS(sys_mincore , 3)
2012 MIPS_SYS(sys_madvise , 3)
2013 MIPS_SYS(sys_getdents64 , 3)
2014 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2015 MIPS_SYS(sys_ni_syscall , 0)
2016 MIPS_SYS(sys_gettid , 0)
2017 MIPS_SYS(sys_readahead , 5)
2018 MIPS_SYS(sys_setxattr , 5)
2019 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2020 MIPS_SYS(sys_fsetxattr , 5)
2021 MIPS_SYS(sys_getxattr , 4)
2022 MIPS_SYS(sys_lgetxattr , 4)
2023 MIPS_SYS(sys_fgetxattr , 4)
2024 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2025 MIPS_SYS(sys_llistxattr , 3)
2026 MIPS_SYS(sys_flistxattr , 3)
2027 MIPS_SYS(sys_removexattr , 2)
2028 MIPS_SYS(sys_lremovexattr, 2)
2029 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2030 MIPS_SYS(sys_tkill , 2)
2031 MIPS_SYS(sys_sendfile64 , 5)
2032 MIPS_SYS(sys_futex , 2)
2033 MIPS_SYS(sys_sched_setaffinity, 3)
2034 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2035 MIPS_SYS(sys_io_setup , 2)
2036 MIPS_SYS(sys_io_destroy , 1)
2037 MIPS_SYS(sys_io_getevents, 5)
2038 MIPS_SYS(sys_io_submit , 3)
2039 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2040 MIPS_SYS(sys_exit_group , 1)
2041 MIPS_SYS(sys_lookup_dcookie, 3)
2042 MIPS_SYS(sys_epoll_create, 1)
2043 MIPS_SYS(sys_epoll_ctl , 4)
2044 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2045 MIPS_SYS(sys_remap_file_pages, 5)
2046 MIPS_SYS(sys_set_tid_address, 1)
2047 MIPS_SYS(sys_restart_syscall, 0)
2048 MIPS_SYS(sys_fadvise64_64, 7)
2049 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2050 MIPS_SYS(sys_fstatfs64 , 2)
2051 MIPS_SYS(sys_timer_create, 3)
2052 MIPS_SYS(sys_timer_settime, 4)
2053 MIPS_SYS(sys_timer_gettime, 2)
2054 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2055 MIPS_SYS(sys_timer_delete, 1)
2056 MIPS_SYS(sys_clock_settime, 2)
2057 MIPS_SYS(sys_clock_gettime, 2)
2058 MIPS_SYS(sys_clock_getres, 2)
2059 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2060 MIPS_SYS(sys_tgkill , 3)
2061 MIPS_SYS(sys_utimes , 2)
2062 MIPS_SYS(sys_mbind , 4)
2063 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2064 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2065 MIPS_SYS(sys_mq_open , 4)
2066 MIPS_SYS(sys_mq_unlink , 1)
2067 MIPS_SYS(sys_mq_timedsend, 5)
2068 MIPS_SYS(sys_mq_timedreceive, 5)
2069 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2070 MIPS_SYS(sys_mq_getsetattr, 3)
2071 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2072 MIPS_SYS(sys_waitid , 4)
2073 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2074 MIPS_SYS(sys_add_key , 5)
388bb21a 2075 MIPS_SYS(sys_request_key, 4)
048f6b4d 2076 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2077 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2078 MIPS_SYS(sys_inotify_init, 0)
2079 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2080 MIPS_SYS(sys_inotify_rm_watch, 2)
2081 MIPS_SYS(sys_migrate_pages, 4)
2082 MIPS_SYS(sys_openat, 4)
2083 MIPS_SYS(sys_mkdirat, 3)
2084 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2085 MIPS_SYS(sys_fchownat, 5)
2086 MIPS_SYS(sys_futimesat, 3)
2087 MIPS_SYS(sys_fstatat64, 4)
2088 MIPS_SYS(sys_unlinkat, 3)
2089 MIPS_SYS(sys_renameat, 4) /* 4295 */
2090 MIPS_SYS(sys_linkat, 5)
2091 MIPS_SYS(sys_symlinkat, 3)
2092 MIPS_SYS(sys_readlinkat, 4)
2093 MIPS_SYS(sys_fchmodat, 3)
2094 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2095 MIPS_SYS(sys_pselect6, 6)
2096 MIPS_SYS(sys_ppoll, 5)
2097 MIPS_SYS(sys_unshare, 1)
2098 MIPS_SYS(sys_splice, 4)
2099 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2100 MIPS_SYS(sys_tee, 4)
2101 MIPS_SYS(sys_vmsplice, 4)
2102 MIPS_SYS(sys_move_pages, 6)
2103 MIPS_SYS(sys_set_robust_list, 2)
2104 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2105 MIPS_SYS(sys_kexec_load, 4)
2106 MIPS_SYS(sys_getcpu, 3)
2107 MIPS_SYS(sys_epoll_pwait, 6)
2108 MIPS_SYS(sys_ioprio_set, 3)
2109 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2110 MIPS_SYS(sys_utimensat, 4)
2111 MIPS_SYS(sys_signalfd, 3)
2112 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2113 MIPS_SYS(sys_eventfd, 1)
2114 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2115 MIPS_SYS(sys_timerfd_create, 2)
2116 MIPS_SYS(sys_timerfd_gettime, 2)
2117 MIPS_SYS(sys_timerfd_settime, 4)
2118 MIPS_SYS(sys_signalfd4, 4)
2119 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2120 MIPS_SYS(sys_epoll_create1, 1)
2121 MIPS_SYS(sys_dup3, 3)
2122 MIPS_SYS(sys_pipe2, 2)
2123 MIPS_SYS(sys_inotify_init1, 1)
2124 MIPS_SYS(sys_preadv, 6) /* 4330 */
2125 MIPS_SYS(sys_pwritev, 6)
2126 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2127 MIPS_SYS(sys_perf_event_open, 5)
2128 MIPS_SYS(sys_accept4, 4)
2129 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2130 MIPS_SYS(sys_fanotify_init, 2)
2131 MIPS_SYS(sys_fanotify_mark, 6)
2132 MIPS_SYS(sys_prlimit64, 4)
2133 MIPS_SYS(sys_name_to_handle_at, 5)
2134 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2135 MIPS_SYS(sys_clock_adjtime, 2)
2136 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2137};
ff4f7382
RH		 2138# undef MIPS_SYS
2139# endif /* O32 */
048f6b4d 2140
590bc601
PB		 2141static int do_store_exclusive(CPUMIPSState *env)
2142{
2143 target_ulong addr;
2144 target_ulong page_addr;
2145 target_ulong val;
2146 int flags;
2147 int segv = 0;
2148 int reg;
2149 int d;
2150
5499b6ff 2151 addr = env->lladdr;
590bc601
PB		 2152 page_addr = addr & TARGET_PAGE_MASK;
2153 start_exclusive();
2154 mmap_lock();
2155 flags = page_get_flags(page_addr);
2156 if ((flags & PAGE_READ) == 0) {
2157 segv = 1;
2158 } else {
2159 reg = env->llreg & 0x1f;
2160 d = (env->llreg & 0x20) != 0;
2161 if (d) {
2162 segv = get_user_s64(val, addr);
2163 } else {
2164 segv = get_user_s32(val, addr);
2165 }
2166 if (!segv) {
2167 if (val != env->llval) {
2168 env->active_tc.gpr[reg] = 0;
2169 } else {
2170 if (d) {
2171 segv = put_user_u64(env->llnewval, addr);
2172 } else {
2173 segv = put_user_u32(env->llnewval, addr);
2174 }
2175 if (!segv) {
2176 env->active_tc.gpr[reg] = 1;
2177 }
2178 }
2179 }
2180 }
5499b6ff 2181 env->lladdr = -1;
590bc601
PB		 2182 if (!segv) {
2183 env->active_tc.PC += 4;
2184 }
2185 mmap_unlock();
2186 end_exclusive();
2187 return segv;
2188}
2189
54b2f42c
MI		 2190/* Break codes */
2191enum {
2192 BRK_OVERFLOW = 6,
2193 BRK_DIVZERO = 7
2194};
2195
2196static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2197 unsigned int code)
2198{
2199 int ret = -1;
2200
2201 switch (code) {
2202 case BRK_OVERFLOW:
2203 case BRK_DIVZERO:
2204 info->si_signo = TARGET_SIGFPE;
2205 info->si_errno = 0;
2206 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2207 queue_signal(env, info->si_signo, &*info);
2208 ret = 0;
2209 break;
2210 default:
2211 break;
2212 }
2213
2214 return ret;
2215}
2216
048f6b4d
FB		 2217void cpu_loop(CPUMIPSState *env)
2218{
0315c31c 2219 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2220 target_siginfo_t info;
ff4f7382
RH		 2221 int trapnr;
2222 abi_long ret;
2223# ifdef TARGET_ABI_MIPSO32
048f6b4d 2224 unsigned int syscall_num;
ff4f7382 2225# endif
048f6b4d
FB		 2226
2227 for(;;) {
0315c31c 2228 cpu_exec_start(cs);
048f6b4d 2229 trapnr = cpu_mips_exec(env);
0315c31c 2230 cpu_exec_end(cs);
048f6b4d
FB		 2231 switch(trapnr) {
2232 case EXCP_SYSCALL:
b5dc7732 2233 env->active_tc.PC += 4;
ff4f7382
RH		 2234# ifdef TARGET_ABI_MIPSO32
2235 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2236 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2237 ret = -TARGET_ENOSYS;
388bb21a
TS		 2238 } else {
2239 int nb_args;
992f48a0
BS		 2240 abi_ulong sp_reg;
2241 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2242
2243 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2244 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2245 switch (nb_args) {
2246 /* these arguments are taken from the stack */
94c19610
ACH		 2247 case 8:
2248 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2249 goto done_syscall;
2250 }
2251 case 7:
2252 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2253 goto done_syscall;
2254 }
2255 case 6:
2256 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2257 goto done_syscall;
2258 }
2259 case 5:
2260 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2261 goto done_syscall;
2262 }
388bb21a
TS		 2263 default:
2264 break;
048f6b4d 2265 }
b5dc7732
TS		 2266 ret = do_syscall(env, env->active_tc.gpr[2],
2267 env->active_tc.gpr[4],
2268 env->active_tc.gpr[5],
2269 env->active_tc.gpr[6],
2270 env->active_tc.gpr[7],
5945cfcb 2271 arg5, arg6, arg7, arg8);
388bb21a 2272 }
94c19610 2273done_syscall:
ff4f7382
RH		 2274# else
2275 ret = do_syscall(env, env->active_tc.gpr[2],
2276 env->active_tc.gpr[4], env->active_tc.gpr[5],
2277 env->active_tc.gpr[6], env->active_tc.gpr[7],
2278 env->active_tc.gpr[8], env->active_tc.gpr[9],
2279 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2280# endif /* O32 */
0b1bcb00
PB		 2281 if (ret == -TARGET_QEMU_ESIGRETURN) {
2282 /* Returning from a successful sigreturn syscall.
2283 Avoid clobbering register state. */
2284 break;
2285 }
ff4f7382 2286 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2287 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2288 ret = -ret;
2289 } else {
b5dc7732 2290 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2291 }
b5dc7732 2292 env->active_tc.gpr[2] = ret;
048f6b4d 2293 break;
ca7c2b1b
TS		 2294 case EXCP_TLBL:
2295 case EXCP_TLBS:
e6e5bd2d
WT		 2296 case EXCP_AdEL:
2297 case EXCP_AdES:
e4474235
PB		 2298 info.si_signo = TARGET_SIGSEGV;
2299 info.si_errno = 0;
2300 /* XXX: check env->error_code */
2301 info.si_code = TARGET_SEGV_MAPERR;
2302 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2303 queue_signal(env, info.si_signo, &info);
2304 break;
6900e84b 2305 case EXCP_CpU:
048f6b4d 2306 case EXCP_RI:
bc1ad2de
FB		 2307 info.si_signo = TARGET_SIGILL;
2308 info.si_errno = 0;
2309 info.si_code = 0;
624f7979 2310 queue_signal(env, info.si_signo, &info);
048f6b4d 2311 break;
106ec879
FB		 2312 case EXCP_INTERRUPT:
2313 /* just indicate that signals should be handled asap */
2314 break;
d08b2a28
PB		 2315 case EXCP_DEBUG:
2316 {
2317 int sig;
2318
2319 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2320 if (sig)
2321 {
2322 info.si_signo = sig;
2323 info.si_errno = 0;
2324 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2325 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2326 }
2327 }
2328 break;
590bc601
PB		 2329 case EXCP_SC:
2330 if (do_store_exclusive(env)) {
2331 info.si_signo = TARGET_SIGSEGV;
2332 info.si_errno = 0;
2333 info.si_code = TARGET_SEGV_MAPERR;
2334 info._sifields._sigfault._addr = env->active_tc.PC;
2335 queue_signal(env, info.si_signo, &info);
2336 }
2337 break;
853c3240
JL		 2338 case EXCP_DSPDIS:
2339 info.si_signo = TARGET_SIGILL;
2340 info.si_errno = 0;
2341 info.si_code = TARGET_ILL_ILLOPC;
2342 queue_signal(env, info.si_signo, &info);
2343 break;
54b2f42c
MI		 2344 /* The code below was inspired by the MIPS Linux kernel trap
2345 * handling code in arch/mips/kernel/traps.c.
2346 */
2347 case EXCP_BREAK:
2348 {
2349 abi_ulong trap_instr;
2350 unsigned int code;
2351
2352 ret = get_user_ual(trap_instr, env->active_tc.PC);
2353 if (ret != 0) {
2354 goto error;
2355 }
2356
2357 /* As described in the original Linux kernel code, the
2358 * below checks on 'code' are to work around an old
2359 * assembly bug.
2360 */
2361 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2362 if (code >= (1 << 10)) {
2363 code >>= 10;
2364 }
2365
2366 if (do_break(env, &info, code) != 0) {
2367 goto error;
2368 }
2369 }
2370 break;
2371 case EXCP_TRAP:
2372 {
2373 abi_ulong trap_instr;
2374 unsigned int code = 0;
2375
2376 ret = get_user_ual(trap_instr, env->active_tc.PC);
2377 if (ret != 0) {
2378 goto error;
2379 }
2380
2381 /* The immediate versions don't provide a code. */
2382 if (!(trap_instr & 0xFC000000)) {
2383 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2384 }
2385
2386 if (do_break(env, &info, code) != 0) {
2387 goto error;
2388 }
2389 }
2390 break;
048f6b4d 2391 default:
54b2f42c 2392error:
5fafdf24 2393 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2394 trapnr);
878096ee 2395 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2396 abort();
2397 }
2398 process_pending_signals(env);
2399 }
2400}
2401#endif
2402
d962783e
JL		 2403#ifdef TARGET_OPENRISC
2404
2405void cpu_loop(CPUOpenRISCState *env)
2406{
878096ee 2407 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2408 int trapnr, gdbsig;
2409
2410 for (;;) {
2411 trapnr = cpu_exec(env);
2412 gdbsig = 0;
2413
2414 switch (trapnr) {
2415 case EXCP_RESET:
2416 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2417 exit(1);
2418 break;
2419 case EXCP_BUSERR:
2420 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2421 gdbsig = SIGBUS;
2422 break;
2423 case EXCP_DPF:
2424 case EXCP_IPF:
878096ee 2425 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2426 gdbsig = TARGET_SIGSEGV;
2427 break;
2428 case EXCP_TICK:
2429 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2430 break;
2431 case EXCP_ALIGN:
2432 qemu_log("\nAlignment pc is %#x\n", env->pc);
2433 gdbsig = SIGBUS;
2434 break;
2435 case EXCP_ILLEGAL:
2436 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2437 gdbsig = SIGILL;
2438 break;
2439 case EXCP_INT:
2440 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2441 break;
2442 case EXCP_DTLBMISS:
2443 case EXCP_ITLBMISS:
2444 qemu_log("\nTLB miss\n");
2445 break;
2446 case EXCP_RANGE:
2447 qemu_log("\nRange\n");
2448 gdbsig = SIGSEGV;
2449 break;
2450 case EXCP_SYSCALL:
2451 env->pc += 4; /* 0xc00; */
2452 env->gpr[11] = do_syscall(env,
2453 env->gpr[11], /* return value */
2454 env->gpr[3], /* r3 - r7 are params */
2455 env->gpr[4],
2456 env->gpr[5],
2457 env->gpr[6],
2458 env->gpr[7],
2459 env->gpr[8], 0, 0);
2460 break;
2461 case EXCP_FPE:
2462 qemu_log("\nFloating point error\n");
2463 break;
2464 case EXCP_TRAP:
2465 qemu_log("\nTrap\n");
2466 gdbsig = SIGTRAP;
2467 break;
2468 case EXCP_NR:
2469 qemu_log("\nNR\n");
2470 break;
2471 default:
2472 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2473 trapnr);
878096ee 2474 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2475 gdbsig = TARGET_SIGILL;
2476 break;
2477 }
2478 if (gdbsig) {
2479 gdb_handlesig(env, gdbsig);
2480 if (gdbsig != TARGET_SIGTRAP) {
2481 exit(1);
2482 }
2483 }
2484
2485 process_pending_signals(env);
2486 }
2487}
2488
2489#endif /* TARGET_OPENRISC */
2490
fdf9b3e8 2491#ifdef TARGET_SH4
05390248 2492void cpu_loop(CPUSH4State *env)
fdf9b3e8 2493{
878096ee 2494 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2495 int trapnr, ret;
c227f099 2496 target_siginfo_t info;
3b46e624 2497
fdf9b3e8
FB		 2498 while (1) {
2499 trapnr = cpu_sh4_exec (env);
3b46e624 2500
fdf9b3e8
FB		 2501 switch (trapnr) {
2502 case 0x160:
0b6d3ae0 2503 env->pc += 2;
5fafdf24
TS		 2504 ret = do_syscall(env,
2505 env->gregs[3],
2506 env->gregs[4],
2507 env->gregs[5],
2508 env->gregs[6],
2509 env->gregs[7],
2510 env->gregs[0],
5945cfcb
PM		 2511 env->gregs[1],
2512 0, 0);
9c2a9ea1 2513 env->gregs[0] = ret;
fdf9b3e8 2514 break;
c3b5bc8a
TS		 2515 case EXCP_INTERRUPT:
2516 /* just indicate that signals should be handled asap */
2517 break;
355fb23d
PB		 2518 case EXCP_DEBUG:
2519 {
2520 int sig;
2521
2522 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2523 if (sig)
2524 {
2525 info.si_signo = sig;
2526 info.si_errno = 0;
2527 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2528 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2529 }
2530 }
2531 break;
c3b5bc8a
TS		 2532 case 0xa0:
2533 case 0xc0:
2534 info.si_signo = SIGSEGV;
2535 info.si_errno = 0;
2536 info.si_code = TARGET_SEGV_MAPERR;
2537 info._sifields._sigfault._addr = env->tea;
624f7979 2538 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2539 break;
2540
fdf9b3e8
FB		 2541 default:
2542 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2543 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2544 exit (1);
2545 }
2546 process_pending_signals (env);
2547 }
2548}
2549#endif
2550
48733d19 2551#ifdef TARGET_CRIS
05390248 2552void cpu_loop(CPUCRISState *env)
48733d19 2553{
878096ee 2554 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2555 int trapnr, ret;
c227f099 2556 target_siginfo_t info;
48733d19
TS		 2557
2558 while (1) {
2559 trapnr = cpu_cris_exec (env);
2560 switch (trapnr) {
2561 case 0xaa:
2562 {
2563 info.si_signo = SIGSEGV;
2564 info.si_errno = 0;
2565 /* XXX: check env->error_code */
2566 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2567 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2568 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2569 }
2570 break;
b6d3abda
EI		 2571 case EXCP_INTERRUPT:
2572 /* just indicate that signals should be handled asap */
2573 break;
48733d19
TS		 2574 case EXCP_BREAK:
2575 ret = do_syscall(env,
2576 env->regs[9],
2577 env->regs[10],
2578 env->regs[11],
2579 env->regs[12],
2580 env->regs[13],
2581 env->pregs[7],
5945cfcb
PM		 2582 env->pregs[11],
2583 0, 0);
48733d19 2584 env->regs[10] = ret;
48733d19
TS		 2585 break;
2586 case EXCP_DEBUG:
2587 {
2588 int sig;
2589
2590 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2591 if (sig)
2592 {
2593 info.si_signo = sig;
2594 info.si_errno = 0;
2595 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2596 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2597 }
2598 }
2599 break;
2600 default:
2601 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2602 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2603 exit (1);
2604 }
2605 process_pending_signals (env);
2606 }
2607}
2608#endif
2609
b779e29e 2610#ifdef TARGET_MICROBLAZE
05390248 2611void cpu_loop(CPUMBState *env)
b779e29e 2612{
878096ee 2613 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2614 int trapnr, ret;
c227f099 2615 target_siginfo_t info;
b779e29e
EI		 2616
2617 while (1) {
2618 trapnr = cpu_mb_exec (env);
2619 switch (trapnr) {
2620 case 0xaa:
2621 {
2622 info.si_signo = SIGSEGV;
2623 info.si_errno = 0;
2624 /* XXX: check env->error_code */
2625 info.si_code = TARGET_SEGV_MAPERR;
2626 info._sifields._sigfault._addr = 0;
2627 queue_signal(env, info.si_signo, &info);
2628 }
2629 break;
2630 case EXCP_INTERRUPT:
2631 /* just indicate that signals should be handled asap */
2632 break;
2633 case EXCP_BREAK:
2634 /* Return address is 4 bytes after the call. */
2635 env->regs[14] += 4;
d7dce494 2636 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2637 ret = do_syscall(env,
2638 env->regs[12],
2639 env->regs[5],
2640 env->regs[6],
2641 env->regs[7],
2642 env->regs[8],
2643 env->regs[9],
5945cfcb
PM		 2644 env->regs[10],
2645 0, 0);
b779e29e 2646 env->regs[3] = ret;
b779e29e 2647 break;
b76da7e3
EI		 2648 case EXCP_HW_EXCP:
2649 env->regs[17] = env->sregs[SR_PC] + 4;
2650 if (env->iflags & D_FLAG) {
2651 env->sregs[SR_ESR] |= 1 << 12;
2652 env->sregs[SR_PC] -= 4;
b4916d7b 2653 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2654 }
2655
2656 env->iflags &= ~(IMM_FLAG | D_FLAG);
2657
2658 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2659 case ESR_EC_DIVZERO:
2660 info.si_signo = SIGFPE;
2661 info.si_errno = 0;
2662 info.si_code = TARGET_FPE_FLTDIV;
2663 info._sifields._sigfault._addr = 0;
2664 queue_signal(env, info.si_signo, &info);
2665 break;
b76da7e3
EI		 2666 case ESR_EC_FPU:
2667 info.si_signo = SIGFPE;
2668 info.si_errno = 0;
2669 if (env->sregs[SR_FSR] & FSR_IO) {
2670 info.si_code = TARGET_FPE_FLTINV;
2671 }
2672 if (env->sregs[SR_FSR] & FSR_DZ) {
2673 info.si_code = TARGET_FPE_FLTDIV;
2674 }
2675 info._sifields._sigfault._addr = 0;
2676 queue_signal(env, info.si_signo, &info);
2677 break;
2678 default:
2679 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2680 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2681 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2682 exit (1);
2683 break;
2684 }
2685 break;
b779e29e
EI		 2686 case EXCP_DEBUG:
2687 {
2688 int sig;
2689
2690 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2691 if (sig)
2692 {
2693 info.si_signo = sig;
2694 info.si_errno = 0;
2695 info.si_code = TARGET_TRAP_BRKPT;
2696 queue_signal(env, info.si_signo, &info);
2697 }
2698 }
2699 break;
2700 default:
2701 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2702 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2703 exit (1);
2704 }
2705 process_pending_signals (env);
2706 }
2707}
2708#endif
2709
e6e5906b
PB		 2710#ifdef TARGET_M68K
2711
2712void cpu_loop(CPUM68KState *env)
2713{
878096ee 2714 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2715 int trapnr;
2716 unsigned int n;
c227f099 2717 target_siginfo_t info;
e6e5906b 2718 TaskState *ts = env->opaque;
3b46e624 2719
e6e5906b
PB		 2720 for(;;) {
2721 trapnr = cpu_m68k_exec(env);
2722 switch(trapnr) {
2723 case EXCP_ILLEGAL:
2724 {
2725 if (ts->sim_syscalls) {
2726 uint16_t nr;
2727 nr = lduw(env->pc + 2);
2728 env->pc += 4;
2729 do_m68k_simcall(env, nr);
2730 } else {
2731 goto do_sigill;
2732 }
2733 }
2734 break;
a87295e8 2735 case EXCP_HALT_INSN:
e6e5906b 2736 /* Semihosing syscall. */
a87295e8 2737 env->pc += 4;
e6e5906b
PB		 2738 do_m68k_semihosting(env, env->dregs[0]);
2739 break;
2740 case EXCP_LINEA:
2741 case EXCP_LINEF:
2742 case EXCP_UNSUPPORTED:
2743 do_sigill:
2744 info.si_signo = SIGILL;
2745 info.si_errno = 0;
2746 info.si_code = TARGET_ILL_ILLOPN;
2747 info._sifields._sigfault._addr = env->pc;
624f7979 2748 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2749 break;
2750 case EXCP_TRAP0:
2751 {
2752 ts->sim_syscalls = 0;
2753 n = env->dregs[0];
2754 env->pc += 2;
5fafdf24
TS		 2755 env->dregs[0] = do_syscall(env,
2756 n,
e6e5906b
PB		 2757 env->dregs[1],
2758 env->dregs[2],
2759 env->dregs[3],
2760 env->dregs[4],
2761 env->dregs[5],
5945cfcb
PM		 2762 env->aregs[0],
2763 0, 0);
e6e5906b
PB		 2764 }
2765 break;
2766 case EXCP_INTERRUPT:
2767 /* just indicate that signals should be handled asap */
2768 break;
2769 case EXCP_ACCESS:
2770 {
2771 info.si_signo = SIGSEGV;
2772 info.si_errno = 0;
2773 /* XXX: check env->error_code */
2774 info.si_code = TARGET_SEGV_MAPERR;
2775 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2776 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2777 }
2778 break;
2779 case EXCP_DEBUG:
2780 {
2781 int sig;
2782
2783 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2784 if (sig)
2785 {
2786 info.si_signo = sig;
2787 info.si_errno = 0;
2788 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2789 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2790 }
2791 }
2792 break;
2793 default:
5fafdf24 2794 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 2795 trapnr);
878096ee 2796 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 2797 abort();
2798 }
2799 process_pending_signals(env);
2800 }
2801}
2802#endif /* TARGET_M68K */
2803
7a3148a9 2804#ifdef TARGET_ALPHA
6910b8f6
RH		 2805static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2806{
2807 target_ulong addr, val, tmp;
2808 target_siginfo_t info;
2809 int ret = 0;
2810
2811 addr = env->lock_addr;
2812 tmp = env->lock_st_addr;
2813 env->lock_addr = -1;
2814 env->lock_st_addr = 0;
2815
2816 start_exclusive();
2817 mmap_lock();
2818
2819 if (addr == tmp) {
2820 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2821 goto do_sigsegv;
2822 }
2823
2824 if (val == env->lock_value) {
2825 tmp = env->ir[reg];
2826 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2827 goto do_sigsegv;
2828 }
2829 ret = 1;
2830 }
2831 }
2832 env->ir[reg] = ret;
2833 env->pc += 4;
2834
2835 mmap_unlock();
2836 end_exclusive();
2837 return;
2838
2839 do_sigsegv:
2840 mmap_unlock();
2841 end_exclusive();
2842
2843 info.si_signo = TARGET_SIGSEGV;
2844 info.si_errno = 0;
2845 info.si_code = TARGET_SEGV_MAPERR;
2846 info._sifields._sigfault._addr = addr;
2847 queue_signal(env, TARGET_SIGSEGV, &info);
2848}
2849
05390248 2850void cpu_loop(CPUAlphaState *env)
7a3148a9 2851{
878096ee 2852 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 2853 int trapnr;
c227f099 2854 target_siginfo_t info;
6049f4f8 2855 abi_long sysret;
3b46e624 2856
7a3148a9
JM		 2857 while (1) {
2858 trapnr = cpu_alpha_exec (env);
3b46e624 2859
ac316ca4
RH		 2860 /* All of the traps imply a transition through PALcode, which
2861 implies an REI instruction has been executed. Which means
2862 that the intr_flag should be cleared. */
2863 env->intr_flag = 0;
2864
7a3148a9
JM		 2865 switch (trapnr) {
2866 case EXCP_RESET:
2867 fprintf(stderr, "Reset requested. Exit\n");
2868 exit(1);
2869 break;
2870 case EXCP_MCHK:
2871 fprintf(stderr, "Machine check exception. Exit\n");
2872 exit(1);
2873 break;
07b6c13b
RH		 2874 case EXCP_SMP_INTERRUPT:
2875 case EXCP_CLK_INTERRUPT:
2876 case EXCP_DEV_INTERRUPT:
5fafdf24 2877 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2878 exit(1);
2879 break;
07b6c13b 2880 case EXCP_MMFAULT:
6910b8f6 2881 env->lock_addr = -1;
6049f4f8
RH		 2882 info.si_signo = TARGET_SIGSEGV;
2883 info.si_errno = 0;
129d8aa5 2884 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2885 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2886 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2887 queue_signal(env, info.si_signo, &info);
7a3148a9 2888 break;
7a3148a9 2889 case EXCP_UNALIGN:
6910b8f6 2890 env->lock_addr = -1;
6049f4f8
RH		 2891 info.si_signo = TARGET_SIGBUS;
2892 info.si_errno = 0;
2893 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2894 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 2895 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2896 break;
2897 case EXCP_OPCDEC:
6049f4f8 2898 do_sigill:
6910b8f6 2899 env->lock_addr = -1;
6049f4f8
RH		 2900 info.si_signo = TARGET_SIGILL;
2901 info.si_errno = 0;
2902 info.si_code = TARGET_ILL_ILLOPC;
2903 info._sifields._sigfault._addr = env->pc;
2904 queue_signal(env, info.si_signo, &info);
7a3148a9 2905 break;
07b6c13b
RH		 2906 case EXCP_ARITH:
2907 env->lock_addr = -1;
2908 info.si_signo = TARGET_SIGFPE;
2909 info.si_errno = 0;
2910 info.si_code = TARGET_FPE_FLTINV;
2911 info._sifields._sigfault._addr = env->pc;
2912 queue_signal(env, info.si_signo, &info);
2913 break;
7a3148a9 2914 case EXCP_FEN:
6049f4f8 2915 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2916 break;
07b6c13b 2917 case EXCP_CALL_PAL:
6910b8f6 2918 env->lock_addr = -1;
07b6c13b 2919 switch (env->error_code) {
6049f4f8
RH		 2920 case 0x80:
2921 /* BPT */
2922 info.si_signo = TARGET_SIGTRAP;
2923 info.si_errno = 0;
2924 info.si_code = TARGET_TRAP_BRKPT;
2925 info._sifields._sigfault._addr = env->pc;
2926 queue_signal(env, info.si_signo, &info);
2927 break;
2928 case 0x81:
2929 /* BUGCHK */
2930 info.si_signo = TARGET_SIGTRAP;
2931 info.si_errno = 0;
2932 info.si_code = 0;
2933 info._sifields._sigfault._addr = env->pc;
2934 queue_signal(env, info.si_signo, &info);
2935 break;
2936 case 0x83:
2937 /* CALLSYS */
2938 trapnr = env->ir[IR_V0];
2939 sysret = do_syscall(env, trapnr,
2940 env->ir[IR_A0], env->ir[IR_A1],
2941 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 2942 env->ir[IR_A4], env->ir[IR_A5],
2943 0, 0);
a5b3b13b
RH		 2944 if (trapnr == TARGET_NR_sigreturn
2945 || trapnr == TARGET_NR_rt_sigreturn) {
2946 break;
2947 }
2948 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 2949 to how this is handled internal to Linux kernel.
2950 (Ab)use trapnr temporarily as boolean indicating error. */
2951 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2952 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2953 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 2954 break;
2955 case 0x86:
2956 /* IMB */
2957 /* ??? We can probably elide the code using page_unprotect
2958 that is checking for self-modifying code. Instead we
2959 could simply call tb_flush here. Until we work out the
2960 changes required to turn off the extra write protection,
2961 this can be a no-op. */
2962 break;
2963 case 0x9E:
2964 /* RDUNIQUE */
2965 /* Handled in the translator for usermode. */
2966 abort();
2967 case 0x9F:
2968 /* WRUNIQUE */
2969 /* Handled in the translator for usermode. */
2970 abort();
2971 case 0xAA:
2972 /* GENTRAP */
2973 info.si_signo = TARGET_SIGFPE;
2974 switch (env->ir[IR_A0]) {
2975 case TARGET_GEN_INTOVF:
2976 info.si_code = TARGET_FPE_INTOVF;
2977 break;
2978 case TARGET_GEN_INTDIV:
2979 info.si_code = TARGET_FPE_INTDIV;
2980 break;
2981 case TARGET_GEN_FLTOVF:
2982 info.si_code = TARGET_FPE_FLTOVF;
2983 break;
2984 case TARGET_GEN_FLTUND:
2985 info.si_code = TARGET_FPE_FLTUND;
2986 break;
2987 case TARGET_GEN_FLTINV:
2988 info.si_code = TARGET_FPE_FLTINV;
2989 break;
2990 case TARGET_GEN_FLTINE:
2991 info.si_code = TARGET_FPE_FLTRES;
2992 break;
2993 case TARGET_GEN_ROPRAND:
2994 info.si_code = 0;
2995 break;
2996 default:
2997 info.si_signo = TARGET_SIGTRAP;
2998 info.si_code = 0;
2999 break;
3000 }
3001 info.si_errno = 0;
3002 info._sifields._sigfault._addr = env->pc;
3003 queue_signal(env, info.si_signo, &info);
3004 break;
3005 default:
3006 goto do_sigill;
3007 }
7a3148a9 3008 break;
7a3148a9 3009 case EXCP_DEBUG:
6049f4f8
RH		 3010 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
3011 if (info.si_signo) {
6910b8f6 3012 env->lock_addr = -1;
6049f4f8
RH		 3013 info.si_errno = 0;
3014 info.si_code = TARGET_TRAP_BRKPT;
3015 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3016 }
3017 break;
6910b8f6
RH		 3018 case EXCP_STL_C:
3019 case EXCP_STQ_C:
3020 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3021 break;
d0f20495
RH		 3022 case EXCP_INTERRUPT:
3023 /* Just indicate that signals should be handled asap. */
3024 break;
7a3148a9
JM		 3025 default:
3026 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3027 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3028 exit (1);
3029 }
3030 process_pending_signals (env);
3031 }
3032}
3033#endif /* TARGET_ALPHA */
3034
a4c075f1
UH		 3035#ifdef TARGET_S390X
3036void cpu_loop(CPUS390XState *env)
3037{
878096ee 3038 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3039 int trapnr, n, sig;
a4c075f1 3040 target_siginfo_t info;
d5a103cd 3041 target_ulong addr;
a4c075f1
UH		 3042
3043 while (1) {
d5a103cd 3044 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3045 switch (trapnr) {
3046 case EXCP_INTERRUPT:
d5a103cd 3047 /* Just indicate that signals should be handled asap. */
a4c075f1 3048 break;
a4c075f1 3049
d5a103cd
RH		 3050 case EXCP_SVC:
3051 n = env->int_svc_code;
3052 if (!n) {
3053 /* syscalls > 255 */
3054 n = env->regs[1];
a4c075f1 3055 }
d5a103cd
RH		 3056 env->psw.addr += env->int_svc_ilen;
3057 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3058 env->regs[4], env->regs[5],
3059 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3060 break;
d5a103cd
RH		 3061
3062 case EXCP_DEBUG:
3063 sig = gdb_handlesig(env, TARGET_SIGTRAP);
3064 if (sig) {
3065 n = TARGET_TRAP_BRKPT;
3066 goto do_signal_pc;
a4c075f1
UH		 3067 }
3068 break;
d5a103cd
RH		 3069 case EXCP_PGM:
3070 n = env->int_pgm_code;
3071 switch (n) {
3072 case PGM_OPERATION:
3073 case PGM_PRIVILEGED:
3074 sig = SIGILL;
3075 n = TARGET_ILL_ILLOPC;
3076 goto do_signal_pc;
3077 case PGM_PROTECTION:
3078 case PGM_ADDRESSING:
3079 sig = SIGSEGV;
a4c075f1 3080 /* XXX: check env->error_code */
d5a103cd
RH		 3081 n = TARGET_SEGV_MAPERR;
3082 addr = env->__excp_addr;
3083 goto do_signal;
3084 case PGM_EXECUTE:
3085 case PGM_SPECIFICATION:
3086 case PGM_SPECIAL_OP:
3087 case PGM_OPERAND:
3088 do_sigill_opn:
3089 sig = SIGILL;
3090 n = TARGET_ILL_ILLOPN;
3091 goto do_signal_pc;
3092
3093 case PGM_FIXPT_OVERFLOW:
3094 sig = SIGFPE;
3095 n = TARGET_FPE_INTOVF;
3096 goto do_signal_pc;
3097 case PGM_FIXPT_DIVIDE:
3098 sig = SIGFPE;
3099 n = TARGET_FPE_INTDIV;
3100 goto do_signal_pc;
3101
3102 case PGM_DATA:
3103 n = (env->fpc >> 8) & 0xff;
3104 if (n == 0xff) {
3105 /* compare-and-trap */
3106 goto do_sigill_opn;
3107 } else {
3108 /* An IEEE exception, simulated or otherwise. */
3109 if (n & 0x80) {
3110 n = TARGET_FPE_FLTINV;
3111 } else if (n & 0x40) {
3112 n = TARGET_FPE_FLTDIV;
3113 } else if (n & 0x20) {
3114 n = TARGET_FPE_FLTOVF;
3115 } else if (n & 0x10) {
3116 n = TARGET_FPE_FLTUND;
3117 } else if (n & 0x08) {
3118 n = TARGET_FPE_FLTRES;
3119 } else {
3120 /* ??? Quantum exception; BFP, DFP error. */
3121 goto do_sigill_opn;
3122 }
3123 sig = SIGFPE;
3124 goto do_signal_pc;
3125 }
3126
3127 default:
3128 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3129 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3130 exit(1);
a4c075f1
UH		 3131 }
3132 break;
d5a103cd
RH		 3133
3134 do_signal_pc:
3135 addr = env->psw.addr;
3136 do_signal:
3137 info.si_signo = sig;
3138 info.si_errno = 0;
3139 info.si_code = n;
3140 info._sifields._sigfault._addr = addr;
3141 queue_signal(env, info.si_signo, &info);
a4c075f1 3142 break;
d5a103cd 3143
a4c075f1 3144 default:
d5a103cd 3145 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3146 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3147 exit(1);
a4c075f1
UH		 3148 }
3149 process_pending_signals (env);
3150 }
3151}
3152
3153#endif /* TARGET_S390X */
3154
9349b4f9 3155THREAD CPUArchState *thread_env;
59faf6d6 3156
edf8e2af
MW		 3157void task_settid(TaskState *ts)
3158{
3159 if (ts->ts_tid == 0) {
2f7bb878 3160#ifdef CONFIG_USE_NPTL
edf8e2af
MW		 3161 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3162#else
3163 /* when no threads are used, tid becomes pid */
3164 ts->ts_tid = getpid();
3165#endif
3166 }
3167}
3168
3169void stop_all_tasks(void)
3170{
3171 /*
3172 * We trust that when using NPTL, start_exclusive()
3173 * handles thread stopping correctly.
3174 */
3175 start_exclusive();
3176}
3177
c3a92833 3178/* Assumes contents are already zeroed. */
624f7979
PB		 3179void init_task_state(TaskState *ts)
3180{
3181 int i;
3182
624f7979
PB		 3183 ts->used = 1;
3184 ts->first_free = ts->sigqueue_table;
3185 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3186 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3187 }
3188 ts->sigqueue_table[i].next = NULL;
3189}
fc9c5412
JS		 3190
3191static void handle_arg_help(const char *arg)
3192{
3193 usage();
3194}
3195
3196static void handle_arg_log(const char *arg)
3197{
3198 int mask;
fc9c5412 3199
4fde1eba 3200 mask = qemu_str_to_log_mask(arg);
fc9c5412 3201 if (!mask) {
59a6fa6e 3202 qemu_print_log_usage(stdout);
fc9c5412
JS		 3203 exit(1);
3204 }
24537a01 3205 qemu_set_log(mask);
fc9c5412
JS		 3206}
3207
50171d42 3208static void handle_arg_log_filename(const char *arg)
3209{
9a7e5424 3210 qemu_set_log_filename(arg);
50171d42 3211}
3212
fc9c5412
JS		 3213static void handle_arg_set_env(const char *arg)
3214{
3215 char *r, *p, *token;
3216 r = p = strdup(arg);
3217 while ((token = strsep(&p, ",")) != NULL) {
3218 if (envlist_setenv(envlist, token) != 0) {
3219 usage();
3220 }
3221 }
3222 free(r);
3223}
3224
3225static void handle_arg_unset_env(const char *arg)
3226{
3227 char *r, *p, *token;
3228 r = p = strdup(arg);
3229 while ((token = strsep(&p, ",")) != NULL) {
3230 if (envlist_unsetenv(envlist, token) != 0) {
3231 usage();
3232 }
3233 }
3234 free(r);
3235}
3236
3237static void handle_arg_argv0(const char *arg)
3238{
3239 argv0 = strdup(arg);
3240}
3241
3242static void handle_arg_stack_size(const char *arg)
3243{
3244 char *p;
3245 guest_stack_size = strtoul(arg, &p, 0);
3246 if (guest_stack_size == 0) {
3247 usage();
3248 }
3249
3250 if (*p == 'M') {
3251 guest_stack_size *= 1024 * 1024;
3252 } else if (*p == 'k' || *p == 'K') {
3253 guest_stack_size *= 1024;
3254 }
3255}
3256
3257static void handle_arg_ld_prefix(const char *arg)
3258{
3259 interp_prefix = strdup(arg);
3260}
3261
3262static void handle_arg_pagesize(const char *arg)
3263{
3264 qemu_host_page_size = atoi(arg);
3265 if (qemu_host_page_size == 0 ||
3266 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3267 fprintf(stderr, "page size must be a power of two\n");
3268 exit(1);
3269 }
3270}
3271
3272static void handle_arg_gdb(const char *arg)
3273{
3274 gdbstub_port = atoi(arg);
3275}
3276
3277static void handle_arg_uname(const char *arg)
3278{
3279 qemu_uname_release = strdup(arg);
3280}
3281
3282static void handle_arg_cpu(const char *arg)
3283{
3284 cpu_model = strdup(arg);
c8057f95 3285 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3286 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3287#if defined(cpu_list)
3288 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3289#endif
3290 exit(1);
3291 }
3292}
3293
3294#if defined(CONFIG_USE_GUEST_BASE)
3295static void handle_arg_guest_base(const char *arg)
3296{
3297 guest_base = strtol(arg, NULL, 0);
3298 have_guest_base = 1;
3299}
3300
3301static void handle_arg_reserved_va(const char *arg)
3302{
3303 char *p;
3304 int shift = 0;
3305 reserved_va = strtoul(arg, &p, 0);
3306 switch (*p) {
3307 case 'k':
3308 case 'K':
3309 shift = 10;
3310 break;
3311 case 'M':
3312 shift = 20;
3313 break;
3314 case 'G':
3315 shift = 30;
3316 break;
3317 }
3318 if (shift) {
3319 unsigned long unshifted = reserved_va;
3320 p++;
3321 reserved_va <<= shift;
3322 if (((reserved_va >> shift) != unshifted)
3323#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3324 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3325#endif
3326 ) {
3327 fprintf(stderr, "Reserved virtual address too big\n");
3328 exit(1);
3329 }
3330 }
3331 if (*p) {
3332 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3333 exit(1);
3334 }
3335}
3336#endif
3337
3338static void handle_arg_singlestep(const char *arg)
3339{
3340 singlestep = 1;
3341}
3342
3343static void handle_arg_strace(const char *arg)
3344{
3345 do_strace = 1;
3346}
3347
3348static void handle_arg_version(const char *arg)
3349{
2e59915d 3350 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3351 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3352 exit(0);
fc9c5412
JS		 3353}
3354
3355struct qemu_argument {
3356 const char *argv;
3357 const char *env;
3358 bool has_arg;
3359 void (*handle_opt)(const char *arg);
3360 const char *example;
3361 const char *help;
3362};
3363
42644cee 3364static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3365 {"h", "", false, handle_arg_help,
3366 "", "print this help"},
3367 {"g", "QEMU_GDB", true, handle_arg_gdb,
3368 "port", "wait gdb connection to 'port'"},
3369 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3370 "path", "set the elf interpreter prefix to 'path'"},
3371 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3372 "size", "set the stack size to 'size' bytes"},
3373 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3374 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3375 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3376 "var=value", "sets targets environment variable (see below)"},
3377 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3378 "var", "unsets targets environment variable (see below)"},
3379 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3380 "argv0", "forces target process argv[0] to be 'argv0'"},
3381 {"r", "QEMU_UNAME", true, handle_arg_uname,
3382 "uname", "set qemu uname release string to 'uname'"},
3383#if defined(CONFIG_USE_GUEST_BASE)
3384 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3385 "address", "set guest_base address to 'address'"},
3386 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3387 "size", "reserve 'size' bytes for guest virtual address space"},
3388#endif
3389 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3390 "item[,...]", "enable logging of specified items "
3391 "(use '-d help' for a list of items)"},
50171d42 3392 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3393 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3394 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3395 "pagesize", "set the host page size to 'pagesize'"},
3396 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3397 "", "run in singlestep mode"},
3398 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3399 "", "log system calls"},
3400 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3401 "", "display version information and exit"},
fc9c5412
JS		 3402 {NULL, NULL, false, NULL, NULL, NULL}
3403};
3404
3405static void usage(void)
3406{
42644cee 3407 const struct qemu_argument *arginfo;
fc9c5412
JS		 3408 int maxarglen;
3409 int maxenvlen;
3410
2e59915d
PB		 3411 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3412 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3413 "\n"
3414 "Options and associated environment variables:\n"
3415 "\n");
3416
63ec54d7
PM		 3417 /* Calculate column widths. We must always have at least enough space
3418 * for the column header.
3419 */
3420 maxarglen = strlen("Argument");
3421 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3422
3423 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3424 int arglen = strlen(arginfo->argv);
3425 if (arginfo->has_arg) {
3426 arglen += strlen(arginfo->example) + 1;
3427 }
fc9c5412
JS		 3428 if (strlen(arginfo->env) > maxenvlen) {
3429 maxenvlen = strlen(arginfo->env);
3430 }
63ec54d7
PM		 3431 if (arglen > maxarglen) {
3432 maxarglen = arglen;
fc9c5412
JS		 3433 }
3434 }
3435
63ec54d7
PM		 3436 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3437 maxenvlen, "Env-variable");
fc9c5412
JS		 3438
3439 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3440 if (arginfo->has_arg) {
3441 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3442 (int)(maxarglen - strlen(arginfo->argv) - 1),
3443 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3444 } else {
63ec54d7 3445 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3446 maxenvlen, arginfo->env,
3447 arginfo->help);
3448 }
3449 }
3450
3451 printf("\n"
3452 "Defaults:\n"
3453 "QEMU_LD_PREFIX = %s\n"
989b697d 3454 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3455 interp_prefix,
989b697d 3456 guest_stack_size);
fc9c5412
JS		 3457
3458 printf("\n"
3459 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3460 "QEMU_UNSET_ENV environment variables to set and unset\n"
3461 "environment variables for the target process.\n"
3462 "It is possible to provide several variables by separating them\n"
3463 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3464 "provide the -E and -U options multiple times.\n"
3465 "The following lines are equivalent:\n"
3466 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3467 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3468 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3469 "Note that if you provide several changes to a single variable\n"
3470 "the last change will stay in effect.\n");
3471
3472 exit(1);
3473}
3474
3475static int parse_args(int argc, char **argv)
3476{
3477 const char *r;
3478 int optind;
42644cee 3479 const struct qemu_argument *arginfo;
fc9c5412
JS		 3480
3481 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3482 if (arginfo->env == NULL) {
3483 continue;
3484 }
3485
3486 r = getenv(arginfo->env);
3487 if (r != NULL) {
3488 arginfo->handle_opt(r);
3489 }
3490 }
3491
3492 optind = 1;
3493 for (;;) {
3494 if (optind >= argc) {
3495 break;
3496 }
3497 r = argv[optind];
3498 if (r[0] != '-') {
3499 break;
3500 }
3501 optind++;
3502 r++;
3503 if (!strcmp(r, "-")) {
3504 break;
3505 }
3506
3507 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3508 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3509 if (arginfo->has_arg) {
1386d4c0
PM		 3510 if (optind >= argc) {
3511 usage();
3512 }
3513 arginfo->handle_opt(argv[optind]);
fc9c5412 3514 optind++;
1386d4c0
PM		 3515 } else {
3516 arginfo->handle_opt(NULL);
fc9c5412 3517 }
fc9c5412
JS		 3518 break;
3519 }
3520 }
3521
3522 /* no option matched the current argv */
3523 if (arginfo->handle_opt == NULL) {
3524 usage();
3525 }
3526 }
3527
3528 if (optind >= argc) {
3529 usage();
3530 }
3531
3532 filename = argv[optind];
3533 exec_path = argv[optind];
3534
3535 return optind;
3536}
3537
902b3d5c 3538int main(int argc, char **argv, char **envp)
31e31b8a 3539{
01ffc75b 3540 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3541 struct image_info info1, *info = &info1;
edf8e2af 3542 struct linux_binprm bprm;
48e15fc2 3543 TaskState *ts;
9349b4f9 3544 CPUArchState *env;
586314f2 3545 int optind;
04a6dfeb 3546 char **target_environ, **wrk;
7d8cec95
AJ		 3547 char **target_argv;
3548 int target_argc;
7d8cec95 3549 int i;
fd4d81dd 3550 int ret;
b12b6a18 3551
ce008c1f
AF		 3552 module_call_init(MODULE_INIT_QOM);
3553
902b3d5c 3554 qemu_cache_utils_init(envp);
3555
04a6dfeb
AJ		 3556 if ((envlist = envlist_create()) == NULL) {
3557 (void) fprintf(stderr, "Unable to allocate envlist\n");
3558 exit(1);
3559 }
3560
3561 /* add current environment into the list */
3562 for (wrk = environ; *wrk != NULL; wrk++) {
3563 (void) envlist_setenv(envlist, *wrk);
3564 }
3565
703e0e89
RH		 3566 /* Read the stack limit from the kernel. If it's "unlimited",
3567 then we can do little else besides use the default. */
3568 {
3569 struct rlimit lim;
3570 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906 3571 && lim.rlim_cur != RLIM_INFINITY
3572 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3573 guest_stack_size = lim.rlim_cur;
3574 }
3575 }
3576
b1f9be31 3577 cpu_model = NULL;
b5ec5ce0 3578#if defined(cpudef_setup)
3579 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3580#endif
3581
fc9c5412 3582 optind = parse_args(argc, argv);
586314f2 3583
31e31b8a 3584 /* Zero out regs */
01ffc75b 3585 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3586
3587 /* Zero out image_info */
3588 memset(info, 0, sizeof(struct image_info));
3589
edf8e2af
MW		 3590 memset(&bprm, 0, sizeof (bprm));
3591
74cd30b8
FB		 3592 /* Scan interp_prefix dir for replacement files. */
3593 init_paths(interp_prefix);
3594
46027c07 3595 if (cpu_model == NULL) {
aaed909a 3596#if defined(TARGET_I386)
46027c07
FB		 3597#ifdef TARGET_X86_64
3598 cpu_model = "qemu64";
3599#else
3600 cpu_model = "qemu32";
3601#endif
aaed909a 3602#elif defined(TARGET_ARM)
088ab16c 3603 cpu_model = "any";
d2fbca94
GX		 3604#elif defined(TARGET_UNICORE32)
3605 cpu_model = "any";
aaed909a
FB		 3606#elif defined(TARGET_M68K)
3607 cpu_model = "any";
3608#elif defined(TARGET_SPARC)
3609#ifdef TARGET_SPARC64
3610 cpu_model = "TI UltraSparc II";
3611#else
3612 cpu_model = "Fujitsu MB86904";
46027c07 3613#endif
aaed909a
FB		 3614#elif defined(TARGET_MIPS)
3615#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3616 cpu_model = "20Kc";
3617#else
3618 cpu_model = "24Kf";
3619#endif
d962783e
JL		 3620#elif defined TARGET_OPENRISC
3621 cpu_model = "or1200";
aaed909a 3622#elif defined(TARGET_PPC)
7ded4f52 3623#ifdef TARGET_PPC64
f7177937 3624 cpu_model = "970fx";
7ded4f52 3625#else
aaed909a 3626 cpu_model = "750";
7ded4f52 3627#endif
aaed909a
FB		 3628#else
3629 cpu_model = "any";
3630#endif
3631 }
d5ab9713
JK		 3632 tcg_exec_init(0);
3633 cpu_exec_init_all();
83fb7adf
FB		 3634 /* NOTE: we need to init the CPU at this stage to get
3635 qemu_host_page_size */
aaed909a
FB		 3636 env = cpu_init(cpu_model);
3637 if (!env) {
3638 fprintf(stderr, "Unable to find CPU definition\n");
3639 exit(1);
3640 }
77868120 3641#if defined(TARGET_SPARC) || defined(TARGET_PPC)
ff18b762 3642 cpu_reset(ENV_GET_CPU(env));
b55a37c9
BS		 3643#endif
3644
d5975363 3645 thread_env = env;
3b46e624 3646
b6741956
FB		 3647 if (getenv("QEMU_STRACE")) {
3648 do_strace = 1;
b92c47c1
TS		 3649 }
3650
04a6dfeb
AJ		 3651 target_environ = envlist_to_environ(envlist, NULL);
3652 envlist_free(envlist);
b12b6a18 3653
379f6698
PB		 3654#if defined(CONFIG_USE_GUEST_BASE)
3655 /*
3656 * Now that page sizes are configured in cpu_init() we can do
3657 * proper page alignment for guest_base.
3658 */
3659 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3660
806d1021
MI		 3661 if (reserved_va || have_guest_base) {
3662 guest_base = init_guest_space(guest_base, reserved_va, 0,
3663 have_guest_base);
3664 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3665 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3666 "space for use as guest address space (check your virtual "
3667 "memory ulimit setting or reserve less using -R option)\n",
3668 reserved_va);
68a1c816
PB		 3669 exit(1);
3670 }
97cc7560 3671
806d1021
MI		 3672 if (reserved_va) {
3673 mmap_next_start = reserved_va;
97cc7560
DDAG		 3674 }
3675 }
14f24e14 3676#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3677
3678 /*
3679 * Read in mmap_min_addr kernel parameter. This value is used
3680 * When loading the ELF image to determine whether guest_base
14f24e14 3681 * is needed. It is also used in mmap_find_vma.
379f6698 3682 */
14f24e14 3683 {
379f6698
PB		 3684 FILE *fp;
3685
3686 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3687 unsigned long tmp;
3688 if (fscanf(fp, "%lu", &tmp) == 1) {
3689 mmap_min_addr = tmp;
3690 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3691 }
3692 fclose(fp);
3693 }
3694 }
379f6698 3695
7d8cec95
AJ		 3696 /*
3697 * Prepare copy of argv vector for target.
3698 */
3699 target_argc = argc - optind;
3700 target_argv = calloc(target_argc + 1, sizeof (char *));
3701 if (target_argv == NULL) {
3702 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3703 exit(1);
3704 }
3705
3706 /*
3707 * If argv0 is specified (using '-0' switch) we replace
3708 * argv[0] pointer with the given one.
3709 */
3710 i = 0;
3711 if (argv0 != NULL) {
3712 target_argv[i++] = strdup(argv0);
3713 }
3714 for (; i < target_argc; i++) {
3715 target_argv[i] = strdup(argv[optind + i]);
3716 }
3717 target_argv[target_argc] = NULL;
3718
7267c094 3719 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3720 init_task_state(ts);
3721 /* build Task State */
3722 ts->info = info;
3723 ts->bprm = &bprm;
3724 env->opaque = ts;
3725 task_settid(ts);
3726
fd4d81dd
AP		 3727 ret = loader_exec(filename, target_argv, target_environ, regs,
3728 info, &bprm);
3729 if (ret != 0) {
885c1d10 3730 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3731 _exit(1);
3732 }
3733
3734 for (wrk = target_environ; *wrk; wrk++) {
3735 free(*wrk);
31e31b8a 3736 }
3b46e624 3737
b12b6a18
TS		 3738 free(target_environ);
3739
2e77eac6 3740 if (qemu_log_enabled()) {
379f6698
PB		 3741#if defined(CONFIG_USE_GUEST_BASE)
3742 qemu_log("guest_base 0x%lx\n", guest_base);
3743#endif
2e77eac6
BS		 3744 log_page_dump();
3745
3746 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3747 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3748 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3749 info->start_code);
3750 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3751 info->start_data);
3752 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3753 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3754 info->start_stack);
3755 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3756 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3757 }
31e31b8a 3758
53a5960a 3759 target_set_brk(info->brk);
31e31b8a 3760 syscall_init();
66fb9763 3761 signal_init();
31e31b8a 3762
9002ec79
RH		 3763#if defined(CONFIG_USE_GUEST_BASE)
3764 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3765 generating the prologue until now so that the prologue can take
3766 the real value of GUEST_BASE into account. */
3767 tcg_prologue_init(&tcg_ctx);
3768#endif
3769
b346ff46 3770#if defined(TARGET_I386)
2e255c6b
FB		 3771 cpu_x86_set_cpl(env, 3);
3772
3802ce26 3773 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e 3774 env->hflags |= HF_PE_MASK;
0514ef2f 3775 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 3776 env->cr[4] |= CR4_OSFXSR_MASK;
3777 env->hflags |= HF_OSFXSR_MASK;
3778 }
d2fd1af7 3779#ifndef TARGET_ABI32
4dbc422b 3780 /* enable 64 bit mode if possible */
0514ef2f 3781 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 3782 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3783 exit(1);
3784 }
d2fd1af7 3785 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3786 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3787 env->hflags |= HF_LMA_MASK;
3788#endif
1bde465e 3789
415e561f
FB		 3790 /* flags setup : we activate the IRQs by default as in user mode */
3791 env->eflags |= IF_MASK;
3b46e624 3792
6dbad63e 3793 /* linux register setup */
d2fd1af7 3794#ifndef TARGET_ABI32
84409ddb
JM		 3795 env->regs[R_EAX] = regs->rax;
3796 env->regs[R_EBX] = regs->rbx;
3797 env->regs[R_ECX] = regs->rcx;
3798 env->regs[R_EDX] = regs->rdx;
3799 env->regs[R_ESI] = regs->rsi;
3800 env->regs[R_EDI] = regs->rdi;
3801 env->regs[R_EBP] = regs->rbp;
3802 env->regs[R_ESP] = regs->rsp;
3803 env->eip = regs->rip;
3804#else
0ecfa993
FB		 3805 env->regs[R_EAX] = regs->eax;
3806 env->regs[R_EBX] = regs->ebx;
3807 env->regs[R_ECX] = regs->ecx;
3808 env->regs[R_EDX] = regs->edx;
3809 env->regs[R_ESI] = regs->esi;
3810 env->regs[R_EDI] = regs->edi;
3811 env->regs[R_EBP] = regs->ebp;
3812 env->regs[R_ESP] = regs->esp;
dab2ed99 3813 env->eip = regs->eip;
84409ddb 3814#endif
31e31b8a 3815
f4beb510 3816 /* linux interrupt setup */
e441570f
AZ		 3817#ifndef TARGET_ABI32
3818 env->idt.limit = 511;
3819#else
3820 env->idt.limit = 255;
3821#endif
3822 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3823 PROT_READ|PROT_WRITE,
3824 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3825 idt_table = g2h(env->idt.base);
f4beb510
FB		 3826 set_idt(0, 0);
3827 set_idt(1, 0);
3828 set_idt(2, 0);
3829 set_idt(3, 3);
3830 set_idt(4, 3);
ec95da6c 3831 set_idt(5, 0);
f4beb510
FB		 3832 set_idt(6, 0);
3833 set_idt(7, 0);
3834 set_idt(8, 0);
3835 set_idt(9, 0);
3836 set_idt(10, 0);
3837 set_idt(11, 0);
3838 set_idt(12, 0);
3839 set_idt(13, 0);
3840 set_idt(14, 0);
3841 set_idt(15, 0);
3842 set_idt(16, 0);
3843 set_idt(17, 0);
3844 set_idt(18, 0);
3845 set_idt(19, 0);
3846 set_idt(0x80, 3);
3847
6dbad63e 3848 /* linux segment setup */
8d18e893
FB		 3849 {
3850 uint64_t *gdt_table;
e441570f
AZ		 3851 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3852 PROT_READ|PROT_WRITE,
3853 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3854 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3855 gdt_table = g2h(env->gdt.base);
d2fd1af7 3856#ifdef TARGET_ABI32
8d18e893
FB		 3857 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3858 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3859 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3860#else
3861 /* 64 bit code segment */
3862 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3863 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3864 DESC_L_MASK |
3865 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3866#endif
8d18e893
FB		 3867 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3868 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3869 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3870 }
6dbad63e 3871 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3872 cpu_x86_load_seg(env, R_SS, __USER_DS);
3873#ifdef TARGET_ABI32
6dbad63e
FB		 3874 cpu_x86_load_seg(env, R_DS, __USER_DS);
3875 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3876 cpu_x86_load_seg(env, R_FS, __USER_DS);
3877 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3878 /* This hack makes Wine work... */
3879 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3880#else
3881 cpu_x86_load_seg(env, R_DS, 0);
3882 cpu_x86_load_seg(env, R_ES, 0);
3883 cpu_x86_load_seg(env, R_FS, 0);
3884 cpu_x86_load_seg(env, R_GS, 0);
3885#endif
b346ff46
FB		 3886#elif defined(TARGET_ARM)
3887 {
3888 int i;
b5ff1b31 3889 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3890 for(i = 0; i < 16; i++) {
3891 env->regs[i] = regs->uregs[i];
3892 }
d8fd2954
PB		 3893 /* Enable BE8. */
3894 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3895 && (info->elf_flags & EF_ARM_BE8)) {
3896 env->bswap_code = 1;
3897 }
b346ff46 3898 }
d2fbca94
GX		 3899#elif defined(TARGET_UNICORE32)
3900 {
3901 int i;
3902 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3903 for (i = 0; i < 32; i++) {
3904 env->regs[i] = regs->uregs[i];
3905 }
3906 }
93ac68bc 3907#elif defined(TARGET_SPARC)
060366c5
FB		 3908 {
3909 int i;
3910 env->pc = regs->pc;
3911 env->npc = regs->npc;
3912 env->y = regs->y;
3913 for(i = 0; i < 8; i++)
3914 env->gregs[i] = regs->u_regs[i];
3915 for(i = 0; i < 8; i++)
3916 env->regwptr[i] = regs->u_regs[i + 8];
3917 }
67867308
FB		 3918#elif defined(TARGET_PPC)
3919 {
3920 int i;
3fc6c082 3921
0411a972
JM		 3922#if defined(TARGET_PPC64)
3923#if defined(TARGET_ABI32)
3924 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3925#else
0411a972
JM		 3926 env->msr |= (target_ulong)1 << MSR_SF;
3927#endif
84409ddb 3928#endif
67867308
FB		 3929 env->nip = regs->nip;
3930 for(i = 0; i < 32; i++) {
3931 env->gpr[i] = regs->gpr[i];
3932 }
3933 }
e6e5906b
PB		 3934#elif defined(TARGET_M68K)
3935 {
e6e5906b
PB		 3936 env->pc = regs->pc;
3937 env->dregs[0] = regs->d0;
3938 env->dregs[1] = regs->d1;
3939 env->dregs[2] = regs->d2;
3940 env->dregs[3] = regs->d3;
3941 env->dregs[4] = regs->d4;
3942 env->dregs[5] = regs->d5;
3943 env->dregs[6] = regs->d6;
3944 env->dregs[7] = regs->d7;
3945 env->aregs[0] = regs->a0;
3946 env->aregs[1] = regs->a1;
3947 env->aregs[2] = regs->a2;
3948 env->aregs[3] = regs->a3;
3949 env->aregs[4] = regs->a4;
3950 env->aregs[5] = regs->a5;
3951 env->aregs[6] = regs->a6;
3952 env->aregs[7] = regs->usp;
3953 env->sr = regs->sr;
3954 ts->sim_syscalls = 1;
3955 }
b779e29e
EI		 3956#elif defined(TARGET_MICROBLAZE)
3957 {
3958 env->regs[0] = regs->r0;
3959 env->regs[1] = regs->r1;
3960 env->regs[2] = regs->r2;
3961 env->regs[3] = regs->r3;
3962 env->regs[4] = regs->r4;
3963 env->regs[5] = regs->r5;
3964 env->regs[6] = regs->r6;
3965 env->regs[7] = regs->r7;
3966 env->regs[8] = regs->r8;
3967 env->regs[9] = regs->r9;
3968 env->regs[10] = regs->r10;
3969 env->regs[11] = regs->r11;
3970 env->regs[12] = regs->r12;
3971 env->regs[13] = regs->r13;
3972 env->regs[14] = regs->r14;
3973 env->regs[15] = regs->r15;
3974 env->regs[16] = regs->r16;
3975 env->regs[17] = regs->r17;
3976 env->regs[18] = regs->r18;
3977 env->regs[19] = regs->r19;
3978 env->regs[20] = regs->r20;
3979 env->regs[21] = regs->r21;
3980 env->regs[22] = regs->r22;
3981 env->regs[23] = regs->r23;
3982 env->regs[24] = regs->r24;
3983 env->regs[25] = regs->r25;
3984 env->regs[26] = regs->r26;
3985 env->regs[27] = regs->r27;
3986 env->regs[28] = regs->r28;
3987 env->regs[29] = regs->r29;
3988 env->regs[30] = regs->r30;
3989 env->regs[31] = regs->r31;
3990 env->sregs[SR_PC] = regs->pc;
3991 }
048f6b4d
FB		 3992#elif defined(TARGET_MIPS)
3993 {
3994 int i;
3995
3996 for(i = 0; i < 32; i++) {
b5dc7732 3997 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3998 }
0fddbbf2
NF		 3999 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4000 if (regs->cp0_epc & 1) {
4001 env->hflags |= MIPS_HFLAG_M16;
4002 }
048f6b4d 4003 }
d962783e
JL		 4004#elif defined(TARGET_OPENRISC)
4005 {
4006 int i;
4007
4008 for (i = 0; i < 32; i++) {
4009 env->gpr[i] = regs->gpr[i];
4010 }
4011
4012 env->sr = regs->sr;
4013 env->pc = regs->pc;
4014 }
fdf9b3e8
FB		 4015#elif defined(TARGET_SH4)
4016 {
4017 int i;
4018
4019 for(i = 0; i < 16; i++) {
4020 env->gregs[i] = regs->regs[i];
4021 }
4022 env->pc = regs->pc;
4023 }
7a3148a9
JM		 4024#elif defined(TARGET_ALPHA)
4025 {
4026 int i;
4027
4028 for(i = 0; i < 28; i++) {
992f48a0 4029 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4030 }
dad081ee 4031 env->ir[IR_SP] = regs->usp;
7a3148a9 4032 env->pc = regs->pc;
7a3148a9 4033 }
48733d19
TS		 4034#elif defined(TARGET_CRIS)
4035 {
4036 env->regs[0] = regs->r0;
4037 env->regs[1] = regs->r1;
4038 env->regs[2] = regs->r2;
4039 env->regs[3] = regs->r3;
4040 env->regs[4] = regs->r4;
4041 env->regs[5] = regs->r5;
4042 env->regs[6] = regs->r6;
4043 env->regs[7] = regs->r7;
4044 env->regs[8] = regs->r8;
4045 env->regs[9] = regs->r9;
4046 env->regs[10] = regs->r10;
4047 env->regs[11] = regs->r11;
4048 env->regs[12] = regs->r12;
4049 env->regs[13] = regs->r13;
4050 env->regs[14] = info->start_stack;
4051 env->regs[15] = regs->acr;
4052 env->pc = regs->erp;
4053 }
a4c075f1
UH		 4054#elif defined(TARGET_S390X)
4055 {
4056 int i;
4057 for (i = 0; i < 16; i++) {
4058 env->regs[i] = regs->gprs[i];
4059 }
4060 env->psw.mask = regs->psw.mask;
4061 env->psw.addr = regs->psw.addr;
4062 }
b346ff46
FB		 4063#else
4064#error unsupported target CPU
4065#endif
31e31b8a 4066
d2fbca94 4067#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4068 ts->stack_base = info->start_stack;
4069 ts->heap_base = info->brk;
4070 /* This will be filled in on the first SYS_HEAPINFO call. */
4071 ts->heap_limit = 0;
4072#endif
4073
74c33bed 4074 if (gdbstub_port) {
ff7a981a
PM		 4075 if (gdbserver_start(gdbstub_port) < 0) {
4076 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4077 gdbstub_port);
4078 exit(1);
4079 }
1fddef4b
FB		 4080 gdb_handlesig(env, 0);
4081 }
1b6b029e
FB		 4082 cpu_loop(env);
4083 /* never exits */
31e31b8a
FB		 4084 return 0;
4085}
Qemu copy for testing