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CommitLineData
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
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PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
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14 */
15
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PB
16#include "exec/memory.h"
17#include "exec/address-spaces.h"
18#include "exec/ioport.h"
1de7afc9 19#include "qemu/bitops.h"
2c9b15ca 20#include "qom/object.h"
55d5d048 21#include "trace.h"
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22#include <assert.h>
23
022c62cb 24#include "exec/memory-internal.h"
220c3ebd 25#include "exec/ram_addr.h"
e1c57ab8 26#include "sysemu/sysemu.h"
67d95c15 27
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PB
28//#define DEBUG_UNASSIGNED
29
22bde714
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30static unsigned memory_region_transaction_depth;
31static bool memory_region_update_pending;
4dc56152 32static bool ioeventfd_update_pending;
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33static bool global_dirty_log = false;
34
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PB
35/* flat_view_mutex is taken around reading as->current_map; the critical
36 * section is extremely short, so I'm using a single mutex for every AS.
37 * We could also RCU for the read-side.
38 *
39 * The BQL is taken around transaction commits, hence both locks are taken
40 * while writing to as->current_map (with the BQL taken outside).
41 */
42static QemuMutex flat_view_mutex;
43
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50static void memory_init(void)
51{
52 qemu_mutex_init(&flat_view_mutex);
53}
54
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55typedef struct AddrRange AddrRange;
56
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57/*
58 * Note using signed integers limits us to physical addresses at most
59 * 63 bits wide. They are needed for negative offsetting in aliases
60 * (large MemoryRegion::alias_offset).
61 */
093bc2cd 62struct AddrRange {
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63 Int128 start;
64 Int128 size;
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65};
66
08dafab4 67static AddrRange addrrange_make(Int128 start, Int128 size)
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68{
69 return (AddrRange) { start, size };
70}
71
72static bool addrrange_equal(AddrRange r1, AddrRange r2)
73{
08dafab4 74 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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75}
76
08dafab4 77static Int128 addrrange_end(AddrRange r)
093bc2cd 78{
08dafab4 79 return int128_add(r.start, r.size);
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80}
81
08dafab4 82static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 83{
08dafab4 84 int128_addto(&range.start, delta);
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85 return range;
86}
87
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88static bool addrrange_contains(AddrRange range, Int128 addr)
89{
90 return int128_ge(addr, range.start)
91 && int128_lt(addr, addrrange_end(range));
92}
93
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94static bool addrrange_intersects(AddrRange r1, AddrRange r2)
95{
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96 return addrrange_contains(r1, r2.start)
97 || addrrange_contains(r2, r1.start);
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98}
99
100static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
101{
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102 Int128 start = int128_max(r1.start, r2.start);
103 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
104 return addrrange_make(start, int128_sub(end, start));
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105}
106
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107enum ListenerDirection { Forward, Reverse };
108
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109static bool memory_listener_match(MemoryListener *listener,
110 MemoryRegionSection *section)
111{
112 return !listener->address_space_filter
113 || listener->address_space_filter == section->address_space;
114}
115
116#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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117 do { \
118 MemoryListener *_listener; \
119 \
120 switch (_direction) { \
121 case Forward: \
122 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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123 if (_listener->_callback) { \
124 _listener->_callback(_listener, ##_args); \
125 } \
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126 } \
127 break; \
128 case Reverse: \
129 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
130 memory_listeners, link) { \
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131 if (_listener->_callback) { \
132 _listener->_callback(_listener, ##_args); \
133 } \
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134 } \
135 break; \
136 default: \
137 abort(); \
138 } \
139 } while (0)
140
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141#define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \
142 do { \
143 MemoryListener *_listener; \
144 \
145 switch (_direction) { \
146 case Forward: \
147 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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148 if (_listener->_callback \
149 && memory_listener_match(_listener, _section)) { \
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150 _listener->_callback(_listener, _section, ##_args); \
151 } \
152 } \
153 break; \
154 case Reverse: \
155 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
156 memory_listeners, link) { \
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157 if (_listener->_callback \
158 && memory_listener_match(_listener, _section)) { \
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159 _listener->_callback(_listener, _section, ##_args); \
160 } \
161 } \
162 break; \
163 default: \
164 abort(); \
165 } \
166 } while (0)
167
dfde4e6e 168/* No need to ref/unref .mr, the FlatRange keeps it alive. */
0e0d36b4 169#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \
7376e582 170 MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
0e0d36b4 171 .mr = (fr)->mr, \
f6790af6 172 .address_space = (as), \
0e0d36b4 173 .offset_within_region = (fr)->offset_in_region, \
052e87b0 174 .size = (fr)->addr.size, \
0e0d36b4 175 .offset_within_address_space = int128_get64((fr)->addr.start), \
7a8499e8 176 .readonly = (fr)->readonly, \
7376e582 177 }))
0e0d36b4 178
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179struct CoalescedMemoryRange {
180 AddrRange addr;
181 QTAILQ_ENTRY(CoalescedMemoryRange) link;
182};
183
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184struct MemoryRegionIoeventfd {
185 AddrRange addr;
186 bool match_data;
187 uint64_t data;
753d5e14 188 EventNotifier *e;
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189};
190
191static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
192 MemoryRegionIoeventfd b)
193{
08dafab4 194 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 195 return true;
08dafab4 196 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 197 return false;
08dafab4 198 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 199 return true;
08dafab4 200 } else if (int128_gt(a.addr.size, b.addr.size)) {
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201 return false;
202 } else if (a.match_data < b.match_data) {
203 return true;
204 } else if (a.match_data > b.match_data) {
205 return false;
206 } else if (a.match_data) {
207 if (a.data < b.data) {
208 return true;
209 } else if (a.data > b.data) {
210 return false;
211 }
212 }
753d5e14 213 if (a.e < b.e) {
3e9d69e7 214 return true;
753d5e14 215 } else if (a.e > b.e) {
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216 return false;
217 }
218 return false;
219}
220
221static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
222 MemoryRegionIoeventfd b)
223{
224 return !memory_region_ioeventfd_before(a, b)
225 && !memory_region_ioeventfd_before(b, a);
226}
227
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228typedef struct FlatRange FlatRange;
229typedef struct FlatView FlatView;
230
231/* Range of memory in the global map. Addresses are absolute. */
232struct FlatRange {
233 MemoryRegion *mr;
a8170e5e 234 hwaddr offset_in_region;
093bc2cd 235 AddrRange addr;
5a583347 236 uint8_t dirty_log_mask;
5f9a5ea1 237 bool romd_mode;
fb1cd6f9 238 bool readonly;
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239};
240
241/* Flattened global view of current active memory hierarchy. Kept in sorted
242 * order.
243 */
244struct FlatView {
856d7245 245 unsigned ref;
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246 FlatRange *ranges;
247 unsigned nr;
248 unsigned nr_allocated;
249};
250
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251typedef struct AddressSpaceOps AddressSpaceOps;
252
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253#define FOR_EACH_FLAT_RANGE(var, view) \
254 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
255
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256static bool flatrange_equal(FlatRange *a, FlatRange *b)
257{
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 260 && a->offset_in_region == b->offset_in_region
5f9a5ea1 261 && a->romd_mode == b->romd_mode
fb1cd6f9 262 && a->readonly == b->readonly;
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263}
264
265static void flatview_init(FlatView *view)
266{
856d7245 267 view->ref = 1;
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268 view->ranges = NULL;
269 view->nr = 0;
270 view->nr_allocated = 0;
271}
272
273/* Insert a range into a given position. Caller is responsible for maintaining
274 * sorting order.
275 */
276static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
277{
278 if (view->nr == view->nr_allocated) {
279 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 280 view->ranges = g_realloc(view->ranges,
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281 view->nr_allocated * sizeof(*view->ranges));
282 }
283 memmove(view->ranges + pos + 1, view->ranges + pos,
284 (view->nr - pos) * sizeof(FlatRange));
285 view->ranges[pos] = *range;
dfde4e6e 286 memory_region_ref(range->mr);
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287 ++view->nr;
288}
289
290static void flatview_destroy(FlatView *view)
291{
dfde4e6e
PB
292 int i;
293
294 for (i = 0; i < view->nr; i++) {
295 memory_region_unref(view->ranges[i].mr);
296 }
7267c094 297 g_free(view->ranges);
a9a0c06d 298 g_free(view);
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299}
300
856d7245
PB
301static void flatview_ref(FlatView *view)
302{
303 atomic_inc(&view->ref);
304}
305
306static void flatview_unref(FlatView *view)
307{
308 if (atomic_fetch_dec(&view->ref) == 1) {
309 flatview_destroy(view);
310 }
311}
312
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313static bool can_merge(FlatRange *r1, FlatRange *r2)
314{
08dafab4 315 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 316 && r1->mr == r2->mr
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317 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
318 r1->addr.size),
319 int128_make64(r2->offset_in_region))
d0a9b5bc 320 && r1->dirty_log_mask == r2->dirty_log_mask
5f9a5ea1 321 && r1->romd_mode == r2->romd_mode
fb1cd6f9 322 && r1->readonly == r2->readonly;
3d8e6bf9
AK
323}
324
8508e024 325/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
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326static void flatview_simplify(FlatView *view)
327{
328 unsigned i, j;
329
330 i = 0;
331 while (i < view->nr) {
332 j = i + 1;
333 while (j < view->nr
334 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 335 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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336 ++j;
337 }
338 ++i;
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343}
344
e7342aa3
PB
345static bool memory_region_big_endian(MemoryRegion *mr)
346{
347#ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349#else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351#endif
352}
353
e11ef3d1
PB
354static bool memory_region_wrong_endianness(MemoryRegion *mr)
355{
356#ifdef TARGET_WORDS_BIGENDIAN
357 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
358#else
359 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
360#endif
361}
362
363static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
364{
365 if (memory_region_wrong_endianness(mr)) {
366 switch (size) {
367 case 1:
368 break;
369 case 2:
370 *data = bswap16(*data);
371 break;
372 case 4:
373 *data = bswap32(*data);
374 break;
375 case 8:
376 *data = bswap64(*data);
377 break;
378 default:
379 abort();
380 }
381 }
382}
383
547e9201 384static void memory_region_oldmmio_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
385 hwaddr addr,
386 uint64_t *value,
387 unsigned size,
388 unsigned shift,
389 uint64_t mask)
390{
ce5d2f33
PB
391 uint64_t tmp;
392
393 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
55d5d048 394 trace_memory_region_ops_read(mr, addr, tmp, size);
ce5d2f33
PB
395 *value |= (tmp & mask) << shift;
396}
397
547e9201 398static void memory_region_read_accessor(MemoryRegion *mr,
a8170e5e 399 hwaddr addr,
164a4dcd
AK
400 uint64_t *value,
401 unsigned size,
402 unsigned shift,
403 uint64_t mask)
404{
164a4dcd
AK
405 uint64_t tmp;
406
d410515e
JK
407 if (mr->flush_coalesced_mmio) {
408 qemu_flush_coalesced_mmio_buffer();
409 }
164a4dcd 410 tmp = mr->ops->read(mr->opaque, addr, size);
55d5d048 411 trace_memory_region_ops_read(mr, addr, tmp, size);
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412 *value |= (tmp & mask) << shift;
413}
414
547e9201 415static void memory_region_oldmmio_write_accessor(MemoryRegion *mr,
ce5d2f33
PB
416 hwaddr addr,
417 uint64_t *value,
418 unsigned size,
419 unsigned shift,
420 uint64_t mask)
421{
ce5d2f33
PB
422 uint64_t tmp;
423
424 tmp = (*value >> shift) & mask;
55d5d048 425 trace_memory_region_ops_write(mr, addr, tmp, size);
ce5d2f33
PB
426 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
427}
428
547e9201 429static void memory_region_write_accessor(MemoryRegion *mr,
a8170e5e 430 hwaddr addr,
164a4dcd
AK
431 uint64_t *value,
432 unsigned size,
433 unsigned shift,
434 uint64_t mask)
435{
164a4dcd
AK
436 uint64_t tmp;
437
d410515e
JK
438 if (mr->flush_coalesced_mmio) {
439 qemu_flush_coalesced_mmio_buffer();
440 }
164a4dcd 441 tmp = (*value >> shift) & mask;
55d5d048 442 trace_memory_region_ops_write(mr, addr, tmp, size);
164a4dcd
AK
443 mr->ops->write(mr->opaque, addr, tmp, size);
444}
445
a8170e5e 446static void access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
447 uint64_t *value,
448 unsigned size,
449 unsigned access_size_min,
450 unsigned access_size_max,
547e9201 451 void (*access)(MemoryRegion *mr,
a8170e5e 452 hwaddr addr,
164a4dcd
AK
453 uint64_t *value,
454 unsigned size,
455 unsigned shift,
456 uint64_t mask),
547e9201 457 MemoryRegion *mr)
164a4dcd
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458{
459 uint64_t access_mask;
460 unsigned access_size;
461 unsigned i;
462
463 if (!access_size_min) {
464 access_size_min = 1;
465 }
466 if (!access_size_max) {
467 access_size_max = 4;
468 }
ce5d2f33
PB
469
470 /* FIXME: support unaligned access? */
164a4dcd
AK
471 access_size = MAX(MIN(size, access_size_max), access_size_min);
472 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
473 if (memory_region_big_endian(mr)) {
474 for (i = 0; i < size; i += access_size) {
475 access(mr, addr + i, value, access_size,
476 (size - access_size - i) * 8, access_mask);
477 }
478 } else {
479 for (i = 0; i < size; i += access_size) {
480 access(mr, addr + i, value, access_size, i * 8, access_mask);
481 }
164a4dcd
AK
482 }
483}
484
e2177955
AK
485static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
486{
0d673e36
AK
487 AddressSpace *as;
488
feca4ac1
PB
489 while (mr->container) {
490 mr = mr->container;
e2177955 491 }
0d673e36
AK
492 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
493 if (mr == as->root) {
494 return as;
495 }
e2177955 496 }
eed2bacf 497 return NULL;
e2177955
AK
498}
499
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500/* Render a memory region into the global view. Ranges in @view obscure
501 * ranges in @mr.
502 */
503static void render_memory_region(FlatView *view,
504 MemoryRegion *mr,
08dafab4 505 Int128 base,
fb1cd6f9
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506 AddrRange clip,
507 bool readonly)
093bc2cd
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508{
509 MemoryRegion *subregion;
510 unsigned i;
a8170e5e 511 hwaddr offset_in_region;
08dafab4
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512 Int128 remain;
513 Int128 now;
093bc2cd
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514 FlatRange fr;
515 AddrRange tmp;
516
6bba19ba
AK
517 if (!mr->enabled) {
518 return;
519 }
520
08dafab4 521 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 522 readonly |= mr->readonly;
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523
524 tmp = addrrange_make(base, mr->size);
525
526 if (!addrrange_intersects(tmp, clip)) {
527 return;
528 }
529
530 clip = addrrange_intersection(tmp, clip);
531
532 if (mr->alias) {
08dafab4
AK
533 int128_subfrom(&base, int128_make64(mr->alias->addr));
534 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 535 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
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536 return;
537 }
538
539 /* Render subregions in priority order. */
540 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 541 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
542 }
543
14a3c10a 544 if (!mr->terminates) {
093bc2cd
AK
545 return;
546 }
547
08dafab4 548 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
549 base = clip.start;
550 remain = clip.size;
551
2eb74e1a
PC
552 fr.mr = mr;
553 fr.dirty_log_mask = mr->dirty_log_mask;
554 fr.romd_mode = mr->romd_mode;
555 fr.readonly = readonly;
556
093bc2cd 557 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
558 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
559 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
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560 continue;
561 }
08dafab4
AK
562 if (int128_lt(base, view->ranges[i].addr.start)) {
563 now = int128_min(remain,
564 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
565 fr.offset_in_region = offset_in_region;
566 fr.addr = addrrange_make(base, now);
567 flatview_insert(view, i, &fr);
568 ++i;
08dafab4
AK
569 int128_addto(&base, now);
570 offset_in_region += int128_get64(now);
571 int128_subfrom(&remain, now);
093bc2cd 572 }
d26a8cae
AK
573 now = int128_sub(int128_min(int128_add(base, remain),
574 addrrange_end(view->ranges[i].addr)),
575 base);
576 int128_addto(&base, now);
577 offset_in_region += int128_get64(now);
578 int128_subfrom(&remain, now);
093bc2cd 579 }
08dafab4 580 if (int128_nz(remain)) {
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AK
581 fr.offset_in_region = offset_in_region;
582 fr.addr = addrrange_make(base, remain);
583 flatview_insert(view, i, &fr);
584 }
585}
586
587/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 588static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 589{
a9a0c06d 590 FlatView *view;
093bc2cd 591
a9a0c06d
PB
592 view = g_new(FlatView, 1);
593 flatview_init(view);
093bc2cd 594
83f3c251 595 if (mr) {
a9a0c06d 596 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
597 addrrange_make(int128_zero(), int128_2_64()), false);
598 }
a9a0c06d 599 flatview_simplify(view);
093bc2cd
AK
600
601 return view;
602}
603
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604static void address_space_add_del_ioeventfds(AddressSpace *as,
605 MemoryRegionIoeventfd *fds_new,
606 unsigned fds_new_nb,
607 MemoryRegionIoeventfd *fds_old,
608 unsigned fds_old_nb)
609{
610 unsigned iold, inew;
80a1ea37
AK
611 MemoryRegionIoeventfd *fd;
612 MemoryRegionSection section;
3e9d69e7
AK
613
614 /* Generate a symmetric difference of the old and new fd sets, adding
615 * and deleting as necessary.
616 */
617
618 iold = inew = 0;
619 while (iold < fds_old_nb || inew < fds_new_nb) {
620 if (iold < fds_old_nb
621 && (inew == fds_new_nb
622 || memory_region_ioeventfd_before(fds_old[iold],
623 fds_new[inew]))) {
80a1ea37
AK
624 fd = &fds_old[iold];
625 section = (MemoryRegionSection) {
f6790af6 626 .address_space = as,
80a1ea37 627 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 628 .size = fd->addr.size,
80a1ea37
AK
629 };
630 MEMORY_LISTENER_CALL(eventfd_del, Forward, &section,
753d5e14 631 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
632 ++iold;
633 } else if (inew < fds_new_nb
634 && (iold == fds_old_nb
635 || memory_region_ioeventfd_before(fds_new[inew],
636 fds_old[iold]))) {
80a1ea37
AK
637 fd = &fds_new[inew];
638 section = (MemoryRegionSection) {
f6790af6 639 .address_space = as,
80a1ea37 640 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 641 .size = fd->addr.size,
80a1ea37
AK
642 };
643 MEMORY_LISTENER_CALL(eventfd_add, Reverse, &section,
753d5e14 644 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
645 ++inew;
646 } else {
647 ++iold;
648 ++inew;
649 }
650 }
651}
652
856d7245
PB
653static FlatView *address_space_get_flatview(AddressSpace *as)
654{
655 FlatView *view;
656
657 qemu_mutex_lock(&flat_view_mutex);
658 view = as->current_map;
659 flatview_ref(view);
660 qemu_mutex_unlock(&flat_view_mutex);
661 return view;
662}
663
3e9d69e7
AK
664static void address_space_update_ioeventfds(AddressSpace *as)
665{
99e86347 666 FlatView *view;
3e9d69e7
AK
667 FlatRange *fr;
668 unsigned ioeventfd_nb = 0;
669 MemoryRegionIoeventfd *ioeventfds = NULL;
670 AddrRange tmp;
671 unsigned i;
672
856d7245 673 view = address_space_get_flatview(as);
99e86347 674 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
675 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
676 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
677 int128_sub(fr->addr.start,
678 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
679 if (addrrange_intersects(fr->addr, tmp)) {
680 ++ioeventfd_nb;
7267c094 681 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
682 ioeventfd_nb * sizeof(*ioeventfds));
683 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
684 ioeventfds[ioeventfd_nb-1].addr = tmp;
685 }
686 }
687 }
688
689 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
690 as->ioeventfds, as->ioeventfd_nb);
691
7267c094 692 g_free(as->ioeventfds);
3e9d69e7
AK
693 as->ioeventfds = ioeventfds;
694 as->ioeventfd_nb = ioeventfd_nb;
856d7245 695 flatview_unref(view);
3e9d69e7
AK
696}
697
b8af1afb 698static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
699 const FlatView *old_view,
700 const FlatView *new_view,
b8af1afb 701 bool adding)
093bc2cd 702{
093bc2cd
AK
703 unsigned iold, inew;
704 FlatRange *frold, *frnew;
093bc2cd
AK
705
706 /* Generate a symmetric difference of the old and new memory maps.
707 * Kill ranges in the old map, and instantiate ranges in the new map.
708 */
709 iold = inew = 0;
a9a0c06d
PB
710 while (iold < old_view->nr || inew < new_view->nr) {
711 if (iold < old_view->nr) {
712 frold = &old_view->ranges[iold];
093bc2cd
AK
713 } else {
714 frold = NULL;
715 }
a9a0c06d
PB
716 if (inew < new_view->nr) {
717 frnew = &new_view->ranges[inew];
093bc2cd
AK
718 } else {
719 frnew = NULL;
720 }
721
722 if (frold
723 && (!frnew
08dafab4
AK
724 || int128_lt(frold->addr.start, frnew->addr.start)
725 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 726 && !flatrange_equal(frold, frnew)))) {
41a6e477 727 /* In old but not in new, or in both but attributes changed. */
093bc2cd 728
b8af1afb 729 if (!adding) {
72e22d2f 730 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
731 }
732
093bc2cd
AK
733 ++iold;
734 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 735 /* In both and unchanged (except logging may have changed) */
093bc2cd 736
b8af1afb 737 if (adding) {
50c1e149 738 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b8af1afb 739 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
72e22d2f 740 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop);
b8af1afb 741 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
72e22d2f 742 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start);
b8af1afb 743 }
5a583347
AK
744 }
745
093bc2cd
AK
746 ++iold;
747 ++inew;
093bc2cd
AK
748 } else {
749 /* In new */
750
b8af1afb 751 if (adding) {
72e22d2f 752 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
753 }
754
093bc2cd
AK
755 ++inew;
756 }
757 }
b8af1afb
AK
758}
759
760
761static void address_space_update_topology(AddressSpace *as)
762{
856d7245 763 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 764 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK
765
766 address_space_update_topology_pass(as, old_view, new_view, false);
767 address_space_update_topology_pass(as, old_view, new_view, true);
768
856d7245
PB
769 qemu_mutex_lock(&flat_view_mutex);
770 flatview_unref(as->current_map);
a9a0c06d 771 as->current_map = new_view;
856d7245
PB
772 qemu_mutex_unlock(&flat_view_mutex);
773
774 /* Note that all the old MemoryRegions are still alive up to this
775 * point. This relieves most MemoryListeners from the need to
776 * ref/unref the MemoryRegions they get---unless they use them
777 * outside the iothread mutex, in which case precise reference
778 * counting is necessary.
779 */
780 flatview_unref(old_view);
781
3e9d69e7 782 address_space_update_ioeventfds(as);
093bc2cd
AK
783}
784
4ef4db86
AK
785void memory_region_transaction_begin(void)
786{
bb880ded 787 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
788 ++memory_region_transaction_depth;
789}
790
4dc56152
GA
791static void memory_region_clear_pending(void)
792{
793 memory_region_update_pending = false;
794 ioeventfd_update_pending = false;
795}
796
4ef4db86
AK
797void memory_region_transaction_commit(void)
798{
0d673e36
AK
799 AddressSpace *as;
800
4ef4db86
AK
801 assert(memory_region_transaction_depth);
802 --memory_region_transaction_depth;
4dc56152
GA
803 if (!memory_region_transaction_depth) {
804 if (memory_region_update_pending) {
805 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 806
4dc56152
GA
807 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
808 address_space_update_topology(as);
809 }
02e2b95f 810
4dc56152
GA
811 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
812 } else if (ioeventfd_update_pending) {
813 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
814 address_space_update_ioeventfds(as);
815 }
816 }
817 memory_region_clear_pending();
818 }
4ef4db86
AK
819}
820
545e92e0
AK
821static void memory_region_destructor_none(MemoryRegion *mr)
822{
823}
824
825static void memory_region_destructor_ram(MemoryRegion *mr)
826{
827 qemu_ram_free(mr->ram_addr);
828}
829
dfde4e6e
PB
830static void memory_region_destructor_alias(MemoryRegion *mr)
831{
832 memory_region_unref(mr->alias);
833}
834
545e92e0
AK
835static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
836{
837 qemu_ram_free_from_ptr(mr->ram_addr);
838}
839
d0a9b5bc
AK
840static void memory_region_destructor_rom_device(MemoryRegion *mr)
841{
842 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
d0a9b5bc
AK
843}
844
093bc2cd 845void memory_region_init(MemoryRegion *mr,
2c9b15ca 846 Object *owner,
093bc2cd
AK
847 const char *name,
848 uint64_t size)
849{
2cdfcf27
PB
850 mr->ops = &unassigned_mem_ops;
851 mr->opaque = NULL;
2c9b15ca 852 mr->owner = owner;
30951157 853 mr->iommu_ops = NULL;
feca4ac1 854 mr->container = NULL;
08dafab4
AK
855 mr->size = int128_make64(size);
856 if (size == UINT64_MAX) {
857 mr->size = int128_2_64();
858 }
093bc2cd 859 mr->addr = 0;
b3b00c78 860 mr->subpage = false;
6bba19ba 861 mr->enabled = true;
14a3c10a 862 mr->terminates = false;
8ea9252a 863 mr->ram = false;
5f9a5ea1 864 mr->romd_mode = true;
fb1cd6f9 865 mr->readonly = false;
75c578dc 866 mr->rom_device = false;
545e92e0 867 mr->destructor = memory_region_destructor_none;
093bc2cd
AK
868 mr->priority = 0;
869 mr->may_overlap = false;
870 mr->alias = NULL;
871 QTAILQ_INIT(&mr->subregions);
872 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
873 QTAILQ_INIT(&mr->coalesced);
7267c094 874 mr->name = g_strdup(name);
5a583347 875 mr->dirty_log_mask = 0;
3e9d69e7
AK
876 mr->ioeventfd_nb = 0;
877 mr->ioeventfds = NULL;
d410515e 878 mr->flush_coalesced_mmio = false;
093bc2cd
AK
879}
880
b018ddf6
PB
881static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
882 unsigned size)
883{
884#ifdef DEBUG_UNASSIGNED
885 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
886#endif
4917cf44
AF
887 if (current_cpu != NULL) {
888 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 889 }
68a7439a 890 return 0;
b018ddf6
PB
891}
892
893static void unassigned_mem_write(void *opaque, hwaddr addr,
894 uint64_t val, unsigned size)
895{
896#ifdef DEBUG_UNASSIGNED
897 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
898#endif
4917cf44
AF
899 if (current_cpu != NULL) {
900 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 901 }
b018ddf6
PB
902}
903
d197063f
PB
904static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
905 unsigned size, bool is_write)
906{
907 return false;
908}
909
910const MemoryRegionOps unassigned_mem_ops = {
911 .valid.accepts = unassigned_mem_accepts,
912 .endianness = DEVICE_NATIVE_ENDIAN,
913};
914
d2702032
PB
915bool memory_region_access_valid(MemoryRegion *mr,
916 hwaddr addr,
917 unsigned size,
918 bool is_write)
093bc2cd 919{
a014ed07
PB
920 int access_size_min, access_size_max;
921 int access_size, i;
897fa7cf 922
093bc2cd
AK
923 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
924 return false;
925 }
926
a014ed07 927 if (!mr->ops->valid.accepts) {
093bc2cd
AK
928 return true;
929 }
930
a014ed07
PB
931 access_size_min = mr->ops->valid.min_access_size;
932 if (!mr->ops->valid.min_access_size) {
933 access_size_min = 1;
934 }
935
936 access_size_max = mr->ops->valid.max_access_size;
937 if (!mr->ops->valid.max_access_size) {
938 access_size_max = 4;
939 }
940
941 access_size = MAX(MIN(size, access_size_max), access_size_min);
942 for (i = 0; i < size; i += access_size) {
943 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
944 is_write)) {
945 return false;
946 }
093bc2cd 947 }
a014ed07 948
093bc2cd
AK
949 return true;
950}
951
a621f38d 952static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
a8170e5e 953 hwaddr addr,
a621f38d 954 unsigned size)
093bc2cd 955{
164a4dcd 956 uint64_t data = 0;
093bc2cd 957
ce5d2f33
PB
958 if (mr->ops->read) {
959 access_with_adjusted_size(addr, &data, size,
960 mr->ops->impl.min_access_size,
961 mr->ops->impl.max_access_size,
962 memory_region_read_accessor, mr);
963 } else {
964 access_with_adjusted_size(addr, &data, size, 1, 4,
965 memory_region_oldmmio_read_accessor, mr);
74901c3b
AK
966 }
967
093bc2cd
AK
968 return data;
969}
970
791af8c8
PB
971static bool memory_region_dispatch_read(MemoryRegion *mr,
972 hwaddr addr,
973 uint64_t *pval,
974 unsigned size)
a621f38d 975{
791af8c8
PB
976 if (!memory_region_access_valid(mr, addr, size, false)) {
977 *pval = unassigned_mem_read(mr, addr, size);
978 return true;
979 }
a621f38d 980
791af8c8
PB
981 *pval = memory_region_dispatch_read1(mr, addr, size);
982 adjust_endianness(mr, pval, size);
983 return false;
a621f38d 984}
093bc2cd 985
791af8c8 986static bool memory_region_dispatch_write(MemoryRegion *mr,
a8170e5e 987 hwaddr addr,
a621f38d
AK
988 uint64_t data,
989 unsigned size)
990{
897fa7cf 991 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 992 unassigned_mem_write(mr, addr, data, size);
791af8c8 993 return true;
093bc2cd
AK
994 }
995
a621f38d
AK
996 adjust_endianness(mr, &data, size);
997
ce5d2f33
PB
998 if (mr->ops->write) {
999 access_with_adjusted_size(addr, &data, size,
1000 mr->ops->impl.min_access_size,
1001 mr->ops->impl.max_access_size,
1002 memory_region_write_accessor, mr);
1003 } else {
1004 access_with_adjusted_size(addr, &data, size, 1, 4,
1005 memory_region_oldmmio_write_accessor, mr);
74901c3b 1006 }
791af8c8 1007 return false;
093bc2cd
AK
1008}
1009
093bc2cd 1010void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1011 Object *owner,
093bc2cd
AK
1012 const MemoryRegionOps *ops,
1013 void *opaque,
1014 const char *name,
1015 uint64_t size)
1016{
2c9b15ca 1017 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1018 mr->ops = ops;
1019 mr->opaque = opaque;
14a3c10a 1020 mr->terminates = true;
97161e17 1021 mr->ram_addr = ~(ram_addr_t)0;
093bc2cd
AK
1022}
1023
1024void memory_region_init_ram(MemoryRegion *mr,
2c9b15ca 1025 Object *owner,
093bc2cd
AK
1026 const char *name,
1027 uint64_t size)
1028{
2c9b15ca 1029 memory_region_init(mr, owner, name, size);
8ea9252a 1030 mr->ram = true;
14a3c10a 1031 mr->terminates = true;
545e92e0 1032 mr->destructor = memory_region_destructor_ram;
0b183fc8
PB
1033 mr->ram_addr = qemu_ram_alloc(size, mr);
1034}
1035
1036#ifdef __linux__
1037void memory_region_init_ram_from_file(MemoryRegion *mr,
1038 struct Object *owner,
1039 const char *name,
1040 uint64_t size,
dbcb8981 1041 bool share,
7f56e740
PB
1042 const char *path,
1043 Error **errp)
0b183fc8
PB
1044{
1045 memory_region_init(mr, owner, name, size);
1046 mr->ram = true;
1047 mr->terminates = true;
1048 mr->destructor = memory_region_destructor_ram;
dbcb8981 1049 mr->ram_addr = qemu_ram_alloc_from_file(size, mr, share, path, errp);
093bc2cd 1050}
0b183fc8 1051#endif
093bc2cd
AK
1052
1053void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1054 Object *owner,
093bc2cd
AK
1055 const char *name,
1056 uint64_t size,
1057 void *ptr)
1058{
2c9b15ca 1059 memory_region_init(mr, owner, name, size);
8ea9252a 1060 mr->ram = true;
14a3c10a 1061 mr->terminates = true;
545e92e0 1062 mr->destructor = memory_region_destructor_ram_from_ptr;
c5705a77 1063 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
093bc2cd
AK
1064}
1065
1066void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1067 Object *owner,
093bc2cd
AK
1068 const char *name,
1069 MemoryRegion *orig,
a8170e5e 1070 hwaddr offset,
093bc2cd
AK
1071 uint64_t size)
1072{
2c9b15ca 1073 memory_region_init(mr, owner, name, size);
dfde4e6e
PB
1074 memory_region_ref(orig);
1075 mr->destructor = memory_region_destructor_alias;
093bc2cd
AK
1076 mr->alias = orig;
1077 mr->alias_offset = offset;
1078}
1079
d0a9b5bc 1080void memory_region_init_rom_device(MemoryRegion *mr,
2c9b15ca 1081 Object *owner,
d0a9b5bc 1082 const MemoryRegionOps *ops,
75f5941c 1083 void *opaque,
d0a9b5bc
AK
1084 const char *name,
1085 uint64_t size)
1086{
2c9b15ca 1087 memory_region_init(mr, owner, name, size);
7bc2b9cd 1088 mr->ops = ops;
75f5941c 1089 mr->opaque = opaque;
d0a9b5bc 1090 mr->terminates = true;
75c578dc 1091 mr->rom_device = true;
d0a9b5bc 1092 mr->destructor = memory_region_destructor_rom_device;
c5705a77 1093 mr->ram_addr = qemu_ram_alloc(size, mr);
d0a9b5bc
AK
1094}
1095
30951157 1096void memory_region_init_iommu(MemoryRegion *mr,
2c9b15ca 1097 Object *owner,
30951157
AK
1098 const MemoryRegionIOMMUOps *ops,
1099 const char *name,
1100 uint64_t size)
1101{
2c9b15ca 1102 memory_region_init(mr, owner, name, size);
30951157
AK
1103 mr->iommu_ops = ops,
1104 mr->terminates = true; /* then re-forwards */
06866575 1105 notifier_list_init(&mr->iommu_notify);
30951157
AK
1106}
1107
1660e72d 1108void memory_region_init_reservation(MemoryRegion *mr,
2c9b15ca 1109 Object *owner,
1660e72d
JK
1110 const char *name,
1111 uint64_t size)
1112{
2c9b15ca 1113 memory_region_init_io(mr, owner, &unassigned_mem_ops, mr, name, size);
1660e72d
JK
1114}
1115
093bc2cd
AK
1116void memory_region_destroy(MemoryRegion *mr)
1117{
1118 assert(QTAILQ_EMPTY(&mr->subregions));
2be0e25f 1119 assert(memory_region_transaction_depth == 0);
545e92e0 1120 mr->destructor(mr);
093bc2cd 1121 memory_region_clear_coalescing(mr);
7267c094
AL
1122 g_free((char *)mr->name);
1123 g_free(mr->ioeventfds);
093bc2cd
AK
1124}
1125
803c0816
PB
1126Object *memory_region_owner(MemoryRegion *mr)
1127{
1128 return mr->owner;
1129}
1130
46637be2
PB
1131void memory_region_ref(MemoryRegion *mr)
1132{
1133 if (mr && mr->owner) {
1134 object_ref(mr->owner);
1135 }
1136}
1137
1138void memory_region_unref(MemoryRegion *mr)
1139{
1140 if (mr && mr->owner) {
1141 object_unref(mr->owner);
1142 }
1143}
1144
093bc2cd
AK
1145uint64_t memory_region_size(MemoryRegion *mr)
1146{
08dafab4
AK
1147 if (int128_eq(mr->size, int128_2_64())) {
1148 return UINT64_MAX;
1149 }
1150 return int128_get64(mr->size);
093bc2cd
AK
1151}
1152
8991c79b
AK
1153const char *memory_region_name(MemoryRegion *mr)
1154{
1155 return mr->name;
1156}
1157
8ea9252a
AK
1158bool memory_region_is_ram(MemoryRegion *mr)
1159{
1160 return mr->ram;
1161}
1162
55043ba3
AK
1163bool memory_region_is_logging(MemoryRegion *mr)
1164{
1165 return mr->dirty_log_mask;
1166}
1167
ce7923da
AK
1168bool memory_region_is_rom(MemoryRegion *mr)
1169{
1170 return mr->ram && mr->readonly;
1171}
1172
30951157
AK
1173bool memory_region_is_iommu(MemoryRegion *mr)
1174{
1175 return mr->iommu_ops;
1176}
1177
06866575
DG
1178void memory_region_register_iommu_notifier(MemoryRegion *mr, Notifier *n)
1179{
1180 notifier_list_add(&mr->iommu_notify, n);
1181}
1182
1183void memory_region_unregister_iommu_notifier(Notifier *n)
1184{
1185 notifier_remove(n);
1186}
1187
1188void memory_region_notify_iommu(MemoryRegion *mr,
1189 IOMMUTLBEntry entry)
1190{
1191 assert(memory_region_is_iommu(mr));
1192 notifier_list_notify(&mr->iommu_notify, &entry);
1193}
1194
093bc2cd
AK
1195void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1196{
5a583347
AK
1197 uint8_t mask = 1 << client;
1198
59023ef4 1199 memory_region_transaction_begin();
5a583347 1200 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1201 memory_region_update_pending |= mr->enabled;
59023ef4 1202 memory_region_transaction_commit();
093bc2cd
AK
1203}
1204
a8170e5e
AK
1205bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1206 hwaddr size, unsigned client)
093bc2cd 1207{
14a3c10a 1208 assert(mr->terminates);
52159192 1209 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
093bc2cd
AK
1210}
1211
a8170e5e
AK
1212void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1213 hwaddr size)
093bc2cd 1214{
14a3c10a 1215 assert(mr->terminates);
75218e7f 1216 cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size);
093bc2cd
AK
1217}
1218
6c279db8
JQ
1219bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1220 hwaddr size, unsigned client)
1221{
1222 bool ret;
1223 assert(mr->terminates);
52159192 1224 ret = cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
6c279db8 1225 if (ret) {
a2f4d5be 1226 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
6c279db8
JQ
1227 }
1228 return ret;
1229}
1230
1231
093bc2cd
AK
1232void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1233{
0d673e36 1234 AddressSpace *as;
5a583347
AK
1235 FlatRange *fr;
1236
0d673e36 1237 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
856d7245 1238 FlatView *view = address_space_get_flatview(as);
99e86347 1239 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36
AK
1240 if (fr->mr == mr) {
1241 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1242 }
5a583347 1243 }
856d7245 1244 flatview_unref(view);
5a583347 1245 }
093bc2cd
AK
1246}
1247
1248void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1249{
fb1cd6f9 1250 if (mr->readonly != readonly) {
59023ef4 1251 memory_region_transaction_begin();
fb1cd6f9 1252 mr->readonly = readonly;
22bde714 1253 memory_region_update_pending |= mr->enabled;
59023ef4 1254 memory_region_transaction_commit();
fb1cd6f9 1255 }
093bc2cd
AK
1256}
1257
5f9a5ea1 1258void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1259{
5f9a5ea1 1260 if (mr->romd_mode != romd_mode) {
59023ef4 1261 memory_region_transaction_begin();
5f9a5ea1 1262 mr->romd_mode = romd_mode;
22bde714 1263 memory_region_update_pending |= mr->enabled;
59023ef4 1264 memory_region_transaction_commit();
d0a9b5bc
AK
1265 }
1266}
1267
a8170e5e
AK
1268void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1269 hwaddr size, unsigned client)
093bc2cd 1270{
14a3c10a 1271 assert(mr->terminates);
a2f4d5be 1272 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
093bc2cd
AK
1273}
1274
a35ba7be
PB
1275int memory_region_get_fd(MemoryRegion *mr)
1276{
1277 if (mr->alias) {
1278 return memory_region_get_fd(mr->alias);
1279 }
1280
1281 assert(mr->terminates);
1282
1283 return qemu_get_ram_fd(mr->ram_addr & TARGET_PAGE_MASK);
1284}
1285
093bc2cd
AK
1286void *memory_region_get_ram_ptr(MemoryRegion *mr)
1287{
1288 if (mr->alias) {
1289 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1290 }
1291
14a3c10a 1292 assert(mr->terminates);
093bc2cd 1293
021d26d1 1294 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
093bc2cd
AK
1295}
1296
0d673e36 1297static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1298{
99e86347 1299 FlatView *view;
093bc2cd
AK
1300 FlatRange *fr;
1301 CoalescedMemoryRange *cmr;
1302 AddrRange tmp;
95d2994a 1303 MemoryRegionSection section;
093bc2cd 1304
856d7245 1305 view = address_space_get_flatview(as);
99e86347 1306 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1307 if (fr->mr == mr) {
95d2994a 1308 section = (MemoryRegionSection) {
f6790af6 1309 .address_space = as,
95d2994a 1310 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1311 .size = fr->addr.size,
95d2994a
AK
1312 };
1313
1314 MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, &section,
1315 int128_get64(fr->addr.start),
1316 int128_get64(fr->addr.size));
093bc2cd
AK
1317 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1318 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1319 int128_sub(fr->addr.start,
1320 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1321 if (!addrrange_intersects(tmp, fr->addr)) {
1322 continue;
1323 }
1324 tmp = addrrange_intersection(tmp, fr->addr);
95d2994a
AK
1325 MEMORY_LISTENER_CALL(coalesced_mmio_add, Forward, &section,
1326 int128_get64(tmp.start),
1327 int128_get64(tmp.size));
093bc2cd
AK
1328 }
1329 }
1330 }
856d7245 1331 flatview_unref(view);
093bc2cd
AK
1332}
1333
0d673e36
AK
1334static void memory_region_update_coalesced_range(MemoryRegion *mr)
1335{
1336 AddressSpace *as;
1337
1338 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1339 memory_region_update_coalesced_range_as(mr, as);
1340 }
1341}
1342
093bc2cd
AK
1343void memory_region_set_coalescing(MemoryRegion *mr)
1344{
1345 memory_region_clear_coalescing(mr);
08dafab4 1346 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1347}
1348
1349void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1350 hwaddr offset,
093bc2cd
AK
1351 uint64_t size)
1352{
7267c094 1353 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1354
08dafab4 1355 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
1356 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1357 memory_region_update_coalesced_range(mr);
d410515e 1358 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
1359}
1360
1361void memory_region_clear_coalescing(MemoryRegion *mr)
1362{
1363 CoalescedMemoryRange *cmr;
ab5b3db5 1364 bool updated = false;
093bc2cd 1365
d410515e
JK
1366 qemu_flush_coalesced_mmio_buffer();
1367 mr->flush_coalesced_mmio = false;
1368
093bc2cd
AK
1369 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1370 cmr = QTAILQ_FIRST(&mr->coalesced);
1371 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1372 g_free(cmr);
ab5b3db5
FZ
1373 updated = true;
1374 }
1375
1376 if (updated) {
1377 memory_region_update_coalesced_range(mr);
093bc2cd 1378 }
093bc2cd
AK
1379}
1380
d410515e
JK
1381void memory_region_set_flush_coalesced(MemoryRegion *mr)
1382{
1383 mr->flush_coalesced_mmio = true;
1384}
1385
1386void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1387{
1388 qemu_flush_coalesced_mmio_buffer();
1389 if (QTAILQ_EMPTY(&mr->coalesced)) {
1390 mr->flush_coalesced_mmio = false;
1391 }
1392}
1393
3e9d69e7 1394void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 1395 hwaddr addr,
3e9d69e7
AK
1396 unsigned size,
1397 bool match_data,
1398 uint64_t data,
753d5e14 1399 EventNotifier *e)
3e9d69e7
AK
1400{
1401 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1402 .addr.start = int128_make64(addr),
1403 .addr.size = int128_make64(size),
3e9d69e7
AK
1404 .match_data = match_data,
1405 .data = data,
753d5e14 1406 .e = e,
3e9d69e7
AK
1407 };
1408 unsigned i;
1409
28f362be 1410 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1411 memory_region_transaction_begin();
3e9d69e7
AK
1412 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1413 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1414 break;
1415 }
1416 }
1417 ++mr->ioeventfd_nb;
7267c094 1418 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
1419 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1420 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1421 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1422 mr->ioeventfds[i] = mrfd;
4dc56152 1423 ioeventfd_update_pending |= mr->enabled;
59023ef4 1424 memory_region_transaction_commit();
3e9d69e7
AK
1425}
1426
1427void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 1428 hwaddr addr,
3e9d69e7
AK
1429 unsigned size,
1430 bool match_data,
1431 uint64_t data,
753d5e14 1432 EventNotifier *e)
3e9d69e7
AK
1433{
1434 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1435 .addr.start = int128_make64(addr),
1436 .addr.size = int128_make64(size),
3e9d69e7
AK
1437 .match_data = match_data,
1438 .data = data,
753d5e14 1439 .e = e,
3e9d69e7
AK
1440 };
1441 unsigned i;
1442
28f362be 1443 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1444 memory_region_transaction_begin();
3e9d69e7
AK
1445 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1446 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1447 break;
1448 }
1449 }
1450 assert(i != mr->ioeventfd_nb);
1451 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1452 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1453 --mr->ioeventfd_nb;
7267c094 1454 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1455 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 1456 ioeventfd_update_pending |= mr->enabled;
59023ef4 1457 memory_region_transaction_commit();
3e9d69e7
AK
1458}
1459
feca4ac1 1460static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 1461{
0598701a 1462 hwaddr offset = subregion->addr;
feca4ac1 1463 MemoryRegion *mr = subregion->container;
093bc2cd
AK
1464 MemoryRegion *other;
1465
59023ef4
JK
1466 memory_region_transaction_begin();
1467
dfde4e6e 1468 memory_region_ref(subregion);
093bc2cd
AK
1469 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1470 if (subregion->may_overlap || other->may_overlap) {
1471 continue;
1472 }
2c7cfd65 1473 if (int128_ge(int128_make64(offset),
08dafab4
AK
1474 int128_add(int128_make64(other->addr), other->size))
1475 || int128_le(int128_add(int128_make64(offset), subregion->size),
1476 int128_make64(other->addr))) {
093bc2cd
AK
1477 continue;
1478 }
a5e1cbc8 1479#if 0
860329b2
MW
1480 printf("warning: subregion collision %llx/%llx (%s) "
1481 "vs %llx/%llx (%s)\n",
093bc2cd 1482 (unsigned long long)offset,
08dafab4 1483 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1484 subregion->name,
1485 (unsigned long long)other->addr,
08dafab4 1486 (unsigned long long)int128_get64(other->size),
860329b2 1487 other->name);
a5e1cbc8 1488#endif
093bc2cd
AK
1489 }
1490 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1491 if (subregion->priority >= other->priority) {
1492 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1493 goto done;
1494 }
1495 }
1496 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1497done:
22bde714 1498 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1499 memory_region_transaction_commit();
093bc2cd
AK
1500}
1501
0598701a
PC
1502static void memory_region_add_subregion_common(MemoryRegion *mr,
1503 hwaddr offset,
1504 MemoryRegion *subregion)
1505{
feca4ac1
PB
1506 assert(!subregion->container);
1507 subregion->container = mr;
0598701a 1508 subregion->addr = offset;
feca4ac1 1509 memory_region_update_container_subregions(subregion);
0598701a 1510}
093bc2cd
AK
1511
1512void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 1513 hwaddr offset,
093bc2cd
AK
1514 MemoryRegion *subregion)
1515{
1516 subregion->may_overlap = false;
1517 subregion->priority = 0;
1518 memory_region_add_subregion_common(mr, offset, subregion);
1519}
1520
1521void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 1522 hwaddr offset,
093bc2cd 1523 MemoryRegion *subregion,
a1ff8ae0 1524 int priority)
093bc2cd
AK
1525{
1526 subregion->may_overlap = true;
1527 subregion->priority = priority;
1528 memory_region_add_subregion_common(mr, offset, subregion);
1529}
1530
1531void memory_region_del_subregion(MemoryRegion *mr,
1532 MemoryRegion *subregion)
1533{
59023ef4 1534 memory_region_transaction_begin();
feca4ac1
PB
1535 assert(subregion->container == mr);
1536 subregion->container = NULL;
093bc2cd 1537 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 1538 memory_region_unref(subregion);
22bde714 1539 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1540 memory_region_transaction_commit();
6bba19ba
AK
1541}
1542
1543void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1544{
1545 if (enabled == mr->enabled) {
1546 return;
1547 }
59023ef4 1548 memory_region_transaction_begin();
6bba19ba 1549 mr->enabled = enabled;
22bde714 1550 memory_region_update_pending = true;
59023ef4 1551 memory_region_transaction_commit();
093bc2cd 1552}
1c0ffa58 1553
67891b8a 1554static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 1555{
feca4ac1 1556 MemoryRegion *container = mr->container;
2282e1af 1557
feca4ac1 1558 if (container) {
67891b8a
PC
1559 memory_region_transaction_begin();
1560 memory_region_ref(mr);
feca4ac1
PB
1561 memory_region_del_subregion(container, mr);
1562 mr->container = container;
1563 memory_region_update_container_subregions(mr);
67891b8a
PC
1564 memory_region_unref(mr);
1565 memory_region_transaction_commit();
2282e1af 1566 }
67891b8a 1567}
2282e1af 1568
67891b8a
PC
1569void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
1570{
1571 if (addr != mr->addr) {
1572 mr->addr = addr;
1573 memory_region_readd_subregion(mr);
1574 }
2282e1af
AK
1575}
1576
a8170e5e 1577void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 1578{
4703359e 1579 assert(mr->alias);
4703359e 1580
59023ef4 1581 if (offset == mr->alias_offset) {
4703359e
AK
1582 return;
1583 }
1584
59023ef4
JK
1585 memory_region_transaction_begin();
1586 mr->alias_offset = offset;
22bde714 1587 memory_region_update_pending |= mr->enabled;
59023ef4 1588 memory_region_transaction_commit();
4703359e
AK
1589}
1590
e34911c4
AK
1591ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1592{
e34911c4
AK
1593 return mr->ram_addr;
1594}
1595
e2177955
AK
1596static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1597{
1598 const AddrRange *addr = addr_;
1599 const FlatRange *fr = fr_;
1600
1601 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1602 return -1;
1603 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1604 return 1;
1605 }
1606 return 0;
1607}
1608
99e86347 1609static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 1610{
99e86347 1611 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
1612 sizeof(FlatRange), cmp_flatrange_addr);
1613}
1614
feca4ac1 1615bool memory_region_present(MemoryRegion *container, hwaddr addr)
3ce10901 1616{
feca4ac1
PB
1617 MemoryRegion *mr = memory_region_find(container, addr, 1).mr;
1618 if (!mr || (mr == container)) {
3ce10901
PB
1619 return false;
1620 }
dfde4e6e 1621 memory_region_unref(mr);
3ce10901
PB
1622 return true;
1623}
1624
eed2bacf
IM
1625bool memory_region_is_mapped(MemoryRegion *mr)
1626{
1627 return mr->container ? true : false;
1628}
1629
73034e9e 1630MemoryRegionSection memory_region_find(MemoryRegion *mr,
a8170e5e 1631 hwaddr addr, uint64_t size)
e2177955 1632{
052e87b0 1633 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
1634 MemoryRegion *root;
1635 AddressSpace *as;
1636 AddrRange range;
99e86347 1637 FlatView *view;
73034e9e
PB
1638 FlatRange *fr;
1639
1640 addr += mr->addr;
feca4ac1
PB
1641 for (root = mr; root->container; ) {
1642 root = root->container;
73034e9e
PB
1643 addr += root->addr;
1644 }
e2177955 1645
73034e9e 1646 as = memory_region_to_address_space(root);
eed2bacf
IM
1647 if (!as) {
1648 return ret;
1649 }
73034e9e 1650 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 1651
856d7245 1652 view = address_space_get_flatview(as);
99e86347 1653 fr = flatview_lookup(view, range);
e2177955 1654 if (!fr) {
6307d974 1655 flatview_unref(view);
e2177955
AK
1656 return ret;
1657 }
1658
99e86347 1659 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
1660 --fr;
1661 }
1662
1663 ret.mr = fr->mr;
73034e9e 1664 ret.address_space = as;
e2177955
AK
1665 range = addrrange_intersection(range, fr->addr);
1666 ret.offset_within_region = fr->offset_in_region;
1667 ret.offset_within_region += int128_get64(int128_sub(range.start,
1668 fr->addr.start));
052e87b0 1669 ret.size = range.size;
e2177955 1670 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 1671 ret.readonly = fr->readonly;
dfde4e6e
PB
1672 memory_region_ref(ret.mr);
1673
856d7245 1674 flatview_unref(view);
e2177955
AK
1675 return ret;
1676}
1677
1d671369 1678void address_space_sync_dirty_bitmap(AddressSpace *as)
86e775c6 1679{
99e86347 1680 FlatView *view;
7664e80c
AK
1681 FlatRange *fr;
1682
856d7245 1683 view = address_space_get_flatview(as);
99e86347 1684 FOR_EACH_FLAT_RANGE(fr, view) {
72e22d2f 1685 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
7664e80c 1686 }
856d7245 1687 flatview_unref(view);
7664e80c
AK
1688}
1689
1690void memory_global_dirty_log_start(void)
1691{
7664e80c 1692 global_dirty_log = true;
7376e582 1693 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
7664e80c
AK
1694}
1695
1696void memory_global_dirty_log_stop(void)
1697{
7664e80c 1698 global_dirty_log = false;
7376e582 1699 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
1700}
1701
1702static void listener_add_address_space(MemoryListener *listener,
1703 AddressSpace *as)
1704{
99e86347 1705 FlatView *view;
7664e80c
AK
1706 FlatRange *fr;
1707
221b3a3f 1708 if (listener->address_space_filter
f6790af6 1709 && listener->address_space_filter != as) {
221b3a3f
JG
1710 return;
1711 }
1712
7664e80c 1713 if (global_dirty_log) {
975aefe0
AK
1714 if (listener->log_global_start) {
1715 listener->log_global_start(listener);
1716 }
7664e80c 1717 }
975aefe0 1718
856d7245 1719 view = address_space_get_flatview(as);
99e86347 1720 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
1721 MemoryRegionSection section = {
1722 .mr = fr->mr,
f6790af6 1723 .address_space = as,
7664e80c 1724 .offset_within_region = fr->offset_in_region,
052e87b0 1725 .size = fr->addr.size,
7664e80c 1726 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 1727 .readonly = fr->readonly,
7664e80c 1728 };
975aefe0
AK
1729 if (listener->region_add) {
1730 listener->region_add(listener, &section);
1731 }
7664e80c 1732 }
856d7245 1733 flatview_unref(view);
7664e80c
AK
1734}
1735
f6790af6 1736void memory_listener_register(MemoryListener *listener, AddressSpace *filter)
7664e80c 1737{
72e22d2f 1738 MemoryListener *other = NULL;
0d673e36 1739 AddressSpace *as;
72e22d2f 1740
7376e582 1741 listener->address_space_filter = filter;
72e22d2f
AK
1742 if (QTAILQ_EMPTY(&memory_listeners)
1743 || listener->priority >= QTAILQ_LAST(&memory_listeners,
1744 memory_listeners)->priority) {
1745 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
1746 } else {
1747 QTAILQ_FOREACH(other, &memory_listeners, link) {
1748 if (listener->priority < other->priority) {
1749 break;
1750 }
1751 }
1752 QTAILQ_INSERT_BEFORE(other, listener, link);
1753 }
0d673e36
AK
1754
1755 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1756 listener_add_address_space(listener, as);
1757 }
7664e80c
AK
1758}
1759
1760void memory_listener_unregister(MemoryListener *listener)
1761{
72e22d2f 1762 QTAILQ_REMOVE(&memory_listeners, listener, link);
86e775c6 1763}
e2177955 1764
7dca8043 1765void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 1766{
856d7245
PB
1767 if (QTAILQ_EMPTY(&address_spaces)) {
1768 memory_init();
1769 }
1770
59023ef4 1771 memory_region_transaction_begin();
8786db7c
AK
1772 as->root = root;
1773 as->current_map = g_new(FlatView, 1);
1774 flatview_init(as->current_map);
4c19eb72
AK
1775 as->ioeventfd_nb = 0;
1776 as->ioeventfds = NULL;
0d673e36 1777 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 1778 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 1779 address_space_init_dispatch(as);
f43793c7
PB
1780 memory_region_update_pending |= root->enabled;
1781 memory_region_transaction_commit();
1c0ffa58 1782}
658b2224 1783
83f3c251
AK
1784void address_space_destroy(AddressSpace *as)
1785{
078c44f4
DG
1786 MemoryListener *listener;
1787
83f3c251
AK
1788 /* Flush out anything from MemoryListeners listening in on this */
1789 memory_region_transaction_begin();
1790 as->root = NULL;
1791 memory_region_transaction_commit();
1792 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
1793 address_space_destroy_dispatch(as);
078c44f4
DG
1794
1795 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1796 assert(listener->address_space_filter != as);
1797 }
1798
856d7245 1799 flatview_unref(as->current_map);
7dca8043 1800 g_free(as->name);
4c19eb72 1801 g_free(as->ioeventfds);
83f3c251
AK
1802}
1803
791af8c8 1804bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size)
acbbec5d 1805{
791af8c8 1806 return memory_region_dispatch_read(mr, addr, pval, size);
acbbec5d
AK
1807}
1808
791af8c8 1809bool io_mem_write(MemoryRegion *mr, hwaddr addr,
acbbec5d
AK
1810 uint64_t val, unsigned size)
1811{
791af8c8 1812 return memory_region_dispatch_write(mr, addr, val, size);
acbbec5d
AK
1813}
1814
314e2987
BS
1815typedef struct MemoryRegionList MemoryRegionList;
1816
1817struct MemoryRegionList {
1818 const MemoryRegion *mr;
1819 bool printed;
1820 QTAILQ_ENTRY(MemoryRegionList) queue;
1821};
1822
1823typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1824
1825static void mtree_print_mr(fprintf_function mon_printf, void *f,
1826 const MemoryRegion *mr, unsigned int level,
a8170e5e 1827 hwaddr base,
9479c57a 1828 MemoryRegionListHead *alias_print_queue)
314e2987 1829{
9479c57a
JK
1830 MemoryRegionList *new_ml, *ml, *next_ml;
1831 MemoryRegionListHead submr_print_queue;
314e2987
BS
1832 const MemoryRegion *submr;
1833 unsigned int i;
1834
7ea692b2 1835 if (!mr || !mr->enabled) {
314e2987
BS
1836 return;
1837 }
1838
1839 for (i = 0; i < level; i++) {
1840 mon_printf(f, " ");
1841 }
1842
1843 if (mr->alias) {
1844 MemoryRegionList *ml;
1845 bool found = false;
1846
1847 /* check if the alias is already in the queue */
9479c57a 1848 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
314e2987
BS
1849 if (ml->mr == mr->alias && !ml->printed) {
1850 found = true;
1851 }
1852 }
1853
1854 if (!found) {
1855 ml = g_new(MemoryRegionList, 1);
1856 ml->mr = mr->alias;
1857 ml->printed = false;
9479c57a 1858 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 1859 }
4896d74b
JK
1860 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
1861 " (prio %d, %c%c): alias %s @%s " TARGET_FMT_plx
1862 "-" TARGET_FMT_plx "\n",
314e2987 1863 base + mr->addr,
08dafab4 1864 base + mr->addr
fd1d9926
AW
1865 + (int128_nz(mr->size) ?
1866 (hwaddr)int128_get64(int128_sub(mr->size,
1867 int128_one())) : 0),
4b474ba7 1868 mr->priority,
5f9a5ea1
JK
1869 mr->romd_mode ? 'R' : '-',
1870 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1871 : '-',
314e2987
BS
1872 mr->name,
1873 mr->alias->name,
1874 mr->alias_offset,
08dafab4 1875 mr->alias_offset
a66670c7
AK
1876 + (int128_nz(mr->size) ?
1877 (hwaddr)int128_get64(int128_sub(mr->size,
1878 int128_one())) : 0));
314e2987 1879 } else {
4896d74b
JK
1880 mon_printf(f,
1881 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s\n",
314e2987 1882 base + mr->addr,
08dafab4 1883 base + mr->addr
fd1d9926
AW
1884 + (int128_nz(mr->size) ?
1885 (hwaddr)int128_get64(int128_sub(mr->size,
1886 int128_one())) : 0),
4b474ba7 1887 mr->priority,
5f9a5ea1
JK
1888 mr->romd_mode ? 'R' : '-',
1889 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1890 : '-',
314e2987
BS
1891 mr->name);
1892 }
9479c57a
JK
1893
1894 QTAILQ_INIT(&submr_print_queue);
1895
314e2987 1896 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
1897 new_ml = g_new(MemoryRegionList, 1);
1898 new_ml->mr = submr;
1899 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1900 if (new_ml->mr->addr < ml->mr->addr ||
1901 (new_ml->mr->addr == ml->mr->addr &&
1902 new_ml->mr->priority > ml->mr->priority)) {
1903 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1904 new_ml = NULL;
1905 break;
1906 }
1907 }
1908 if (new_ml) {
1909 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1910 }
1911 }
1912
1913 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1914 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1915 alias_print_queue);
1916 }
1917
88365e47 1918 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 1919 g_free(ml);
314e2987
BS
1920 }
1921}
1922
1923void mtree_info(fprintf_function mon_printf, void *f)
1924{
1925 MemoryRegionListHead ml_head;
1926 MemoryRegionList *ml, *ml2;
0d673e36 1927 AddressSpace *as;
314e2987
BS
1928
1929 QTAILQ_INIT(&ml_head);
1930
0d673e36 1931 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
0d673e36
AK
1932 mon_printf(f, "%s\n", as->name);
1933 mtree_print_mr(mon_printf, f, as->root, 0, 0, &ml_head);
b9f9be88
BS
1934 }
1935
1936 mon_printf(f, "aliases\n");
314e2987
BS
1937 /* print aliased regions */
1938 QTAILQ_FOREACH(ml, &ml_head, queue) {
1939 if (!ml->printed) {
1940 mon_printf(f, "%s\n", ml->mr->name);
1941 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1942 }
1943 }
1944
1945 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 1946 g_free(ml);
314e2987 1947 }
314e2987 1948}