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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
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PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
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14 */
15
022c62cb
PB
16#include "exec/memory.h"
17#include "exec/address-spaces.h"
18#include "exec/ioport.h"
1de7afc9 19#include "qemu/bitops.h"
2c9b15ca 20#include "qom/object.h"
55d5d048 21#include "trace.h"
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22#include <assert.h>
23
022c62cb 24#include "exec/memory-internal.h"
220c3ebd 25#include "exec/ram_addr.h"
67d95c15 26
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27//#define DEBUG_UNASSIGNED
28
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29static unsigned memory_region_transaction_depth;
30static bool memory_region_update_pending;
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31static bool global_dirty_log = false;
32
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PB
33/* flat_view_mutex is taken around reading as->current_map; the critical
34 * section is extremely short, so I'm using a single mutex for every AS.
35 * We could also RCU for the read-side.
36 *
37 * The BQL is taken around transaction commits, hence both locks are taken
38 * while writing to as->current_map (with the BQL taken outside).
39 */
40static QemuMutex flat_view_mutex;
41
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42static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 44
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45static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
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48static void memory_init(void)
49{
50 qemu_mutex_init(&flat_view_mutex);
51}
52
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53typedef struct AddrRange AddrRange;
54
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55/*
56 * Note using signed integers limits us to physical addresses at most
57 * 63 bits wide. They are needed for negative offsetting in aliases
58 * (large MemoryRegion::alias_offset).
59 */
093bc2cd 60struct AddrRange {
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61 Int128 start;
62 Int128 size;
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63};
64
08dafab4 65static AddrRange addrrange_make(Int128 start, Int128 size)
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66{
67 return (AddrRange) { start, size };
68}
69
70static bool addrrange_equal(AddrRange r1, AddrRange r2)
71{
08dafab4 72 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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73}
74
08dafab4 75static Int128 addrrange_end(AddrRange r)
093bc2cd 76{
08dafab4 77 return int128_add(r.start, r.size);
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78}
79
08dafab4 80static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 81{
08dafab4 82 int128_addto(&range.start, delta);
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83 return range;
84}
85
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86static bool addrrange_contains(AddrRange range, Int128 addr)
87{
88 return int128_ge(addr, range.start)
89 && int128_lt(addr, addrrange_end(range));
90}
91
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92static bool addrrange_intersects(AddrRange r1, AddrRange r2)
93{
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94 return addrrange_contains(r1, r2.start)
95 || addrrange_contains(r2, r1.start);
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96}
97
98static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
99{
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100 Int128 start = int128_max(r1.start, r2.start);
101 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
102 return addrrange_make(start, int128_sub(end, start));
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103}
104
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105enum ListenerDirection { Forward, Reverse };
106
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107static bool memory_listener_match(MemoryListener *listener,
108 MemoryRegionSection *section)
109{
110 return !listener->address_space_filter
111 || listener->address_space_filter == section->address_space;
112}
113
114#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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115 do { \
116 MemoryListener *_listener; \
117 \
118 switch (_direction) { \
119 case Forward: \
120 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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121 if (_listener->_callback) { \
122 _listener->_callback(_listener, ##_args); \
123 } \
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124 } \
125 break; \
126 case Reverse: \
127 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
128 memory_listeners, link) { \
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129 if (_listener->_callback) { \
130 _listener->_callback(_listener, ##_args); \
131 } \
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132 } \
133 break; \
134 default: \
135 abort(); \
136 } \
137 } while (0)
138
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139#define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \
140 do { \
141 MemoryListener *_listener; \
142 \
143 switch (_direction) { \
144 case Forward: \
145 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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146 if (_listener->_callback \
147 && memory_listener_match(_listener, _section)) { \
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148 _listener->_callback(_listener, _section, ##_args); \
149 } \
150 } \
151 break; \
152 case Reverse: \
153 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
154 memory_listeners, link) { \
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155 if (_listener->_callback \
156 && memory_listener_match(_listener, _section)) { \
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157 _listener->_callback(_listener, _section, ##_args); \
158 } \
159 } \
160 break; \
161 default: \
162 abort(); \
163 } \
164 } while (0)
165
dfde4e6e 166/* No need to ref/unref .mr, the FlatRange keeps it alive. */
0e0d36b4 167#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \
7376e582 168 MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
0e0d36b4 169 .mr = (fr)->mr, \
f6790af6 170 .address_space = (as), \
0e0d36b4 171 .offset_within_region = (fr)->offset_in_region, \
052e87b0 172 .size = (fr)->addr.size, \
0e0d36b4 173 .offset_within_address_space = int128_get64((fr)->addr.start), \
7a8499e8 174 .readonly = (fr)->readonly, \
7376e582 175 }))
0e0d36b4 176
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177struct CoalescedMemoryRange {
178 AddrRange addr;
179 QTAILQ_ENTRY(CoalescedMemoryRange) link;
180};
181
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182struct MemoryRegionIoeventfd {
183 AddrRange addr;
184 bool match_data;
185 uint64_t data;
753d5e14 186 EventNotifier *e;
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187};
188
189static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
190 MemoryRegionIoeventfd b)
191{
08dafab4 192 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 193 return true;
08dafab4 194 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 195 return false;
08dafab4 196 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 197 return true;
08dafab4 198 } else if (int128_gt(a.addr.size, b.addr.size)) {
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199 return false;
200 } else if (a.match_data < b.match_data) {
201 return true;
202 } else if (a.match_data > b.match_data) {
203 return false;
204 } else if (a.match_data) {
205 if (a.data < b.data) {
206 return true;
207 } else if (a.data > b.data) {
208 return false;
209 }
210 }
753d5e14 211 if (a.e < b.e) {
3e9d69e7 212 return true;
753d5e14 213 } else if (a.e > b.e) {
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214 return false;
215 }
216 return false;
217}
218
219static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
220 MemoryRegionIoeventfd b)
221{
222 return !memory_region_ioeventfd_before(a, b)
223 && !memory_region_ioeventfd_before(b, a);
224}
225
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226typedef struct FlatRange FlatRange;
227typedef struct FlatView FlatView;
228
229/* Range of memory in the global map. Addresses are absolute. */
230struct FlatRange {
231 MemoryRegion *mr;
a8170e5e 232 hwaddr offset_in_region;
093bc2cd 233 AddrRange addr;
5a583347 234 uint8_t dirty_log_mask;
5f9a5ea1 235 bool romd_mode;
fb1cd6f9 236 bool readonly;
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237};
238
239/* Flattened global view of current active memory hierarchy. Kept in sorted
240 * order.
241 */
242struct FlatView {
856d7245 243 unsigned ref;
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244 FlatRange *ranges;
245 unsigned nr;
246 unsigned nr_allocated;
247};
248
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249typedef struct AddressSpaceOps AddressSpaceOps;
250
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251#define FOR_EACH_FLAT_RANGE(var, view) \
252 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
253
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254static bool flatrange_equal(FlatRange *a, FlatRange *b)
255{
256 return a->mr == b->mr
257 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 258 && a->offset_in_region == b->offset_in_region
5f9a5ea1 259 && a->romd_mode == b->romd_mode
fb1cd6f9 260 && a->readonly == b->readonly;
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261}
262
263static void flatview_init(FlatView *view)
264{
856d7245 265 view->ref = 1;
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266 view->ranges = NULL;
267 view->nr = 0;
268 view->nr_allocated = 0;
269}
270
271/* Insert a range into a given position. Caller is responsible for maintaining
272 * sorting order.
273 */
274static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
275{
276 if (view->nr == view->nr_allocated) {
277 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 278 view->ranges = g_realloc(view->ranges,
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279 view->nr_allocated * sizeof(*view->ranges));
280 }
281 memmove(view->ranges + pos + 1, view->ranges + pos,
282 (view->nr - pos) * sizeof(FlatRange));
283 view->ranges[pos] = *range;
dfde4e6e 284 memory_region_ref(range->mr);
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285 ++view->nr;
286}
287
288static void flatview_destroy(FlatView *view)
289{
dfde4e6e
PB
290 int i;
291
292 for (i = 0; i < view->nr; i++) {
293 memory_region_unref(view->ranges[i].mr);
294 }
7267c094 295 g_free(view->ranges);
a9a0c06d 296 g_free(view);
093bc2cd
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297}
298
856d7245
PB
299static void flatview_ref(FlatView *view)
300{
301 atomic_inc(&view->ref);
302}
303
304static void flatview_unref(FlatView *view)
305{
306 if (atomic_fetch_dec(&view->ref) == 1) {
307 flatview_destroy(view);
308 }
309}
310
3d8e6bf9
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311static bool can_merge(FlatRange *r1, FlatRange *r2)
312{
08dafab4 313 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 314 && r1->mr == r2->mr
08dafab4
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315 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
316 r1->addr.size),
317 int128_make64(r2->offset_in_region))
d0a9b5bc 318 && r1->dirty_log_mask == r2->dirty_log_mask
5f9a5ea1 319 && r1->romd_mode == r2->romd_mode
fb1cd6f9 320 && r1->readonly == r2->readonly;
3d8e6bf9
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321}
322
8508e024 323/* Attempt to simplify a view by merging adjacent ranges */
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324static void flatview_simplify(FlatView *view)
325{
326 unsigned i, j;
327
328 i = 0;
329 while (i < view->nr) {
330 j = i + 1;
331 while (j < view->nr
332 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 333 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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334 ++j;
335 }
336 ++i;
337 memmove(&view->ranges[i], &view->ranges[j],
338 (view->nr - j) * sizeof(view->ranges[j]));
339 view->nr -= j - i;
340 }
341}
342
e7342aa3
PB
343static bool memory_region_big_endian(MemoryRegion *mr)
344{
345#ifdef TARGET_WORDS_BIGENDIAN
346 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
347#else
348 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
349#endif
350}
351
e11ef3d1
PB
352static bool memory_region_wrong_endianness(MemoryRegion *mr)
353{
354#ifdef TARGET_WORDS_BIGENDIAN
355 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
356#else
357 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
358#endif
359}
360
361static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
362{
363 if (memory_region_wrong_endianness(mr)) {
364 switch (size) {
365 case 1:
366 break;
367 case 2:
368 *data = bswap16(*data);
369 break;
370 case 4:
371 *data = bswap32(*data);
372 break;
373 case 8:
374 *data = bswap64(*data);
375 break;
376 default:
377 abort();
378 }
379 }
380}
381
547e9201 382static void memory_region_oldmmio_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
383 hwaddr addr,
384 uint64_t *value,
385 unsigned size,
386 unsigned shift,
387 uint64_t mask)
388{
ce5d2f33
PB
389 uint64_t tmp;
390
391 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
55d5d048 392 trace_memory_region_ops_read(mr, addr, tmp, size);
ce5d2f33
PB
393 *value |= (tmp & mask) << shift;
394}
395
547e9201 396static void memory_region_read_accessor(MemoryRegion *mr,
a8170e5e 397 hwaddr addr,
164a4dcd
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398 uint64_t *value,
399 unsigned size,
400 unsigned shift,
401 uint64_t mask)
402{
164a4dcd
AK
403 uint64_t tmp;
404
d410515e
JK
405 if (mr->flush_coalesced_mmio) {
406 qemu_flush_coalesced_mmio_buffer();
407 }
164a4dcd 408 tmp = mr->ops->read(mr->opaque, addr, size);
55d5d048 409 trace_memory_region_ops_read(mr, addr, tmp, size);
164a4dcd
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410 *value |= (tmp & mask) << shift;
411}
412
547e9201 413static void memory_region_oldmmio_write_accessor(MemoryRegion *mr,
ce5d2f33
PB
414 hwaddr addr,
415 uint64_t *value,
416 unsigned size,
417 unsigned shift,
418 uint64_t mask)
419{
ce5d2f33
PB
420 uint64_t tmp;
421
422 tmp = (*value >> shift) & mask;
55d5d048 423 trace_memory_region_ops_write(mr, addr, tmp, size);
ce5d2f33
PB
424 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
425}
426
547e9201 427static void memory_region_write_accessor(MemoryRegion *mr,
a8170e5e 428 hwaddr addr,
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AK
429 uint64_t *value,
430 unsigned size,
431 unsigned shift,
432 uint64_t mask)
433{
164a4dcd
AK
434 uint64_t tmp;
435
d410515e
JK
436 if (mr->flush_coalesced_mmio) {
437 qemu_flush_coalesced_mmio_buffer();
438 }
164a4dcd 439 tmp = (*value >> shift) & mask;
55d5d048 440 trace_memory_region_ops_write(mr, addr, tmp, size);
164a4dcd
AK
441 mr->ops->write(mr->opaque, addr, tmp, size);
442}
443
a8170e5e 444static void access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
445 uint64_t *value,
446 unsigned size,
447 unsigned access_size_min,
448 unsigned access_size_max,
547e9201 449 void (*access)(MemoryRegion *mr,
a8170e5e 450 hwaddr addr,
164a4dcd
AK
451 uint64_t *value,
452 unsigned size,
453 unsigned shift,
454 uint64_t mask),
547e9201 455 MemoryRegion *mr)
164a4dcd
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456{
457 uint64_t access_mask;
458 unsigned access_size;
459 unsigned i;
460
461 if (!access_size_min) {
462 access_size_min = 1;
463 }
464 if (!access_size_max) {
465 access_size_max = 4;
466 }
ce5d2f33
PB
467
468 /* FIXME: support unaligned access? */
164a4dcd
AK
469 access_size = MAX(MIN(size, access_size_max), access_size_min);
470 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
471 if (memory_region_big_endian(mr)) {
472 for (i = 0; i < size; i += access_size) {
473 access(mr, addr + i, value, access_size,
474 (size - access_size - i) * 8, access_mask);
475 }
476 } else {
477 for (i = 0; i < size; i += access_size) {
478 access(mr, addr + i, value, access_size, i * 8, access_mask);
479 }
164a4dcd
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480 }
481}
482
e2177955
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483static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
484{
0d673e36
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485 AddressSpace *as;
486
e2177955
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487 while (mr->parent) {
488 mr = mr->parent;
489 }
0d673e36
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490 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
491 if (mr == as->root) {
492 return as;
493 }
e2177955
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494 }
495 abort();
496}
497
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498/* Render a memory region into the global view. Ranges in @view obscure
499 * ranges in @mr.
500 */
501static void render_memory_region(FlatView *view,
502 MemoryRegion *mr,
08dafab4 503 Int128 base,
fb1cd6f9
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504 AddrRange clip,
505 bool readonly)
093bc2cd
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506{
507 MemoryRegion *subregion;
508 unsigned i;
a8170e5e 509 hwaddr offset_in_region;
08dafab4
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510 Int128 remain;
511 Int128 now;
093bc2cd
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512 FlatRange fr;
513 AddrRange tmp;
514
6bba19ba
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515 if (!mr->enabled) {
516 return;
517 }
518
08dafab4 519 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 520 readonly |= mr->readonly;
093bc2cd
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521
522 tmp = addrrange_make(base, mr->size);
523
524 if (!addrrange_intersects(tmp, clip)) {
525 return;
526 }
527
528 clip = addrrange_intersection(tmp, clip);
529
530 if (mr->alias) {
08dafab4
AK
531 int128_subfrom(&base, int128_make64(mr->alias->addr));
532 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 533 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
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534 return;
535 }
536
537 /* Render subregions in priority order. */
538 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 539 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
540 }
541
14a3c10a 542 if (!mr->terminates) {
093bc2cd
AK
543 return;
544 }
545
08dafab4 546 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
547 base = clip.start;
548 remain = clip.size;
549
2eb74e1a
PC
550 fr.mr = mr;
551 fr.dirty_log_mask = mr->dirty_log_mask;
552 fr.romd_mode = mr->romd_mode;
553 fr.readonly = readonly;
554
093bc2cd 555 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
556 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
557 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
558 continue;
559 }
08dafab4
AK
560 if (int128_lt(base, view->ranges[i].addr.start)) {
561 now = int128_min(remain,
562 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
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563 fr.offset_in_region = offset_in_region;
564 fr.addr = addrrange_make(base, now);
565 flatview_insert(view, i, &fr);
566 ++i;
08dafab4
AK
567 int128_addto(&base, now);
568 offset_in_region += int128_get64(now);
569 int128_subfrom(&remain, now);
093bc2cd 570 }
d26a8cae
AK
571 now = int128_sub(int128_min(int128_add(base, remain),
572 addrrange_end(view->ranges[i].addr)),
573 base);
574 int128_addto(&base, now);
575 offset_in_region += int128_get64(now);
576 int128_subfrom(&remain, now);
093bc2cd 577 }
08dafab4 578 if (int128_nz(remain)) {
093bc2cd
AK
579 fr.offset_in_region = offset_in_region;
580 fr.addr = addrrange_make(base, remain);
581 flatview_insert(view, i, &fr);
582 }
583}
584
585/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 586static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 587{
a9a0c06d 588 FlatView *view;
093bc2cd 589
a9a0c06d
PB
590 view = g_new(FlatView, 1);
591 flatview_init(view);
093bc2cd 592
83f3c251 593 if (mr) {
a9a0c06d 594 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
595 addrrange_make(int128_zero(), int128_2_64()), false);
596 }
a9a0c06d 597 flatview_simplify(view);
093bc2cd
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598
599 return view;
600}
601
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602static void address_space_add_del_ioeventfds(AddressSpace *as,
603 MemoryRegionIoeventfd *fds_new,
604 unsigned fds_new_nb,
605 MemoryRegionIoeventfd *fds_old,
606 unsigned fds_old_nb)
607{
608 unsigned iold, inew;
80a1ea37
AK
609 MemoryRegionIoeventfd *fd;
610 MemoryRegionSection section;
3e9d69e7
AK
611
612 /* Generate a symmetric difference of the old and new fd sets, adding
613 * and deleting as necessary.
614 */
615
616 iold = inew = 0;
617 while (iold < fds_old_nb || inew < fds_new_nb) {
618 if (iold < fds_old_nb
619 && (inew == fds_new_nb
620 || memory_region_ioeventfd_before(fds_old[iold],
621 fds_new[inew]))) {
80a1ea37
AK
622 fd = &fds_old[iold];
623 section = (MemoryRegionSection) {
f6790af6 624 .address_space = as,
80a1ea37 625 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 626 .size = fd->addr.size,
80a1ea37
AK
627 };
628 MEMORY_LISTENER_CALL(eventfd_del, Forward, &section,
753d5e14 629 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
630 ++iold;
631 } else if (inew < fds_new_nb
632 && (iold == fds_old_nb
633 || memory_region_ioeventfd_before(fds_new[inew],
634 fds_old[iold]))) {
80a1ea37
AK
635 fd = &fds_new[inew];
636 section = (MemoryRegionSection) {
f6790af6 637 .address_space = as,
80a1ea37 638 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 639 .size = fd->addr.size,
80a1ea37
AK
640 };
641 MEMORY_LISTENER_CALL(eventfd_add, Reverse, &section,
753d5e14 642 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
643 ++inew;
644 } else {
645 ++iold;
646 ++inew;
647 }
648 }
649}
650
856d7245
PB
651static FlatView *address_space_get_flatview(AddressSpace *as)
652{
653 FlatView *view;
654
655 qemu_mutex_lock(&flat_view_mutex);
656 view = as->current_map;
657 flatview_ref(view);
658 qemu_mutex_unlock(&flat_view_mutex);
659 return view;
660}
661
3e9d69e7
AK
662static void address_space_update_ioeventfds(AddressSpace *as)
663{
99e86347 664 FlatView *view;
3e9d69e7
AK
665 FlatRange *fr;
666 unsigned ioeventfd_nb = 0;
667 MemoryRegionIoeventfd *ioeventfds = NULL;
668 AddrRange tmp;
669 unsigned i;
670
856d7245 671 view = address_space_get_flatview(as);
99e86347 672 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
673 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
674 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
675 int128_sub(fr->addr.start,
676 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
677 if (addrrange_intersects(fr->addr, tmp)) {
678 ++ioeventfd_nb;
7267c094 679 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
680 ioeventfd_nb * sizeof(*ioeventfds));
681 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
682 ioeventfds[ioeventfd_nb-1].addr = tmp;
683 }
684 }
685 }
686
687 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
688 as->ioeventfds, as->ioeventfd_nb);
689
7267c094 690 g_free(as->ioeventfds);
3e9d69e7
AK
691 as->ioeventfds = ioeventfds;
692 as->ioeventfd_nb = ioeventfd_nb;
856d7245 693 flatview_unref(view);
3e9d69e7
AK
694}
695
b8af1afb 696static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
697 const FlatView *old_view,
698 const FlatView *new_view,
b8af1afb 699 bool adding)
093bc2cd 700{
093bc2cd
AK
701 unsigned iold, inew;
702 FlatRange *frold, *frnew;
093bc2cd
AK
703
704 /* Generate a symmetric difference of the old and new memory maps.
705 * Kill ranges in the old map, and instantiate ranges in the new map.
706 */
707 iold = inew = 0;
a9a0c06d
PB
708 while (iold < old_view->nr || inew < new_view->nr) {
709 if (iold < old_view->nr) {
710 frold = &old_view->ranges[iold];
093bc2cd
AK
711 } else {
712 frold = NULL;
713 }
a9a0c06d
PB
714 if (inew < new_view->nr) {
715 frnew = &new_view->ranges[inew];
093bc2cd
AK
716 } else {
717 frnew = NULL;
718 }
719
720 if (frold
721 && (!frnew
08dafab4
AK
722 || int128_lt(frold->addr.start, frnew->addr.start)
723 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 724 && !flatrange_equal(frold, frnew)))) {
41a6e477 725 /* In old but not in new, or in both but attributes changed. */
093bc2cd 726
b8af1afb 727 if (!adding) {
72e22d2f 728 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
729 }
730
093bc2cd
AK
731 ++iold;
732 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 733 /* In both and unchanged (except logging may have changed) */
093bc2cd 734
b8af1afb 735 if (adding) {
50c1e149 736 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b8af1afb 737 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
72e22d2f 738 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop);
b8af1afb 739 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
72e22d2f 740 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start);
b8af1afb 741 }
5a583347
AK
742 }
743
093bc2cd
AK
744 ++iold;
745 ++inew;
093bc2cd
AK
746 } else {
747 /* In new */
748
b8af1afb 749 if (adding) {
72e22d2f 750 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
751 }
752
093bc2cd
AK
753 ++inew;
754 }
755 }
b8af1afb
AK
756}
757
758
759static void address_space_update_topology(AddressSpace *as)
760{
856d7245 761 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 762 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK
763
764 address_space_update_topology_pass(as, old_view, new_view, false);
765 address_space_update_topology_pass(as, old_view, new_view, true);
766
856d7245
PB
767 qemu_mutex_lock(&flat_view_mutex);
768 flatview_unref(as->current_map);
a9a0c06d 769 as->current_map = new_view;
856d7245
PB
770 qemu_mutex_unlock(&flat_view_mutex);
771
772 /* Note that all the old MemoryRegions are still alive up to this
773 * point. This relieves most MemoryListeners from the need to
774 * ref/unref the MemoryRegions they get---unless they use them
775 * outside the iothread mutex, in which case precise reference
776 * counting is necessary.
777 */
778 flatview_unref(old_view);
779
3e9d69e7 780 address_space_update_ioeventfds(as);
093bc2cd
AK
781}
782
4ef4db86
AK
783void memory_region_transaction_begin(void)
784{
bb880ded 785 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
786 ++memory_region_transaction_depth;
787}
788
789void memory_region_transaction_commit(void)
790{
0d673e36
AK
791 AddressSpace *as;
792
4ef4db86
AK
793 assert(memory_region_transaction_depth);
794 --memory_region_transaction_depth;
22bde714
JK
795 if (!memory_region_transaction_depth && memory_region_update_pending) {
796 memory_region_update_pending = false;
02e2b95f
JK
797 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
798
0d673e36
AK
799 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
800 address_space_update_topology(as);
02e2b95f
JK
801 }
802
803 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
e87c099f 804 }
4ef4db86
AK
805}
806
545e92e0
AK
807static void memory_region_destructor_none(MemoryRegion *mr)
808{
809}
810
811static void memory_region_destructor_ram(MemoryRegion *mr)
812{
813 qemu_ram_free(mr->ram_addr);
814}
815
dfde4e6e
PB
816static void memory_region_destructor_alias(MemoryRegion *mr)
817{
818 memory_region_unref(mr->alias);
819}
820
545e92e0
AK
821static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
822{
823 qemu_ram_free_from_ptr(mr->ram_addr);
824}
825
d0a9b5bc
AK
826static void memory_region_destructor_rom_device(MemoryRegion *mr)
827{
828 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
d0a9b5bc
AK
829}
830
093bc2cd 831void memory_region_init(MemoryRegion *mr,
2c9b15ca 832 Object *owner,
093bc2cd
AK
833 const char *name,
834 uint64_t size)
835{
2cdfcf27
PB
836 mr->ops = &unassigned_mem_ops;
837 mr->opaque = NULL;
2c9b15ca 838 mr->owner = owner;
30951157 839 mr->iommu_ops = NULL;
093bc2cd 840 mr->parent = NULL;
08dafab4
AK
841 mr->size = int128_make64(size);
842 if (size == UINT64_MAX) {
843 mr->size = int128_2_64();
844 }
093bc2cd 845 mr->addr = 0;
b3b00c78 846 mr->subpage = false;
6bba19ba 847 mr->enabled = true;
14a3c10a 848 mr->terminates = false;
8ea9252a 849 mr->ram = false;
5f9a5ea1 850 mr->romd_mode = true;
fb1cd6f9 851 mr->readonly = false;
75c578dc 852 mr->rom_device = false;
545e92e0 853 mr->destructor = memory_region_destructor_none;
093bc2cd
AK
854 mr->priority = 0;
855 mr->may_overlap = false;
856 mr->alias = NULL;
857 QTAILQ_INIT(&mr->subregions);
858 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
859 QTAILQ_INIT(&mr->coalesced);
7267c094 860 mr->name = g_strdup(name);
5a583347 861 mr->dirty_log_mask = 0;
3e9d69e7
AK
862 mr->ioeventfd_nb = 0;
863 mr->ioeventfds = NULL;
d410515e 864 mr->flush_coalesced_mmio = false;
093bc2cd
AK
865}
866
b018ddf6
PB
867static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
868 unsigned size)
869{
870#ifdef DEBUG_UNASSIGNED
871 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
872#endif
4917cf44
AF
873 if (current_cpu != NULL) {
874 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 875 }
68a7439a 876 return 0;
b018ddf6
PB
877}
878
879static void unassigned_mem_write(void *opaque, hwaddr addr,
880 uint64_t val, unsigned size)
881{
882#ifdef DEBUG_UNASSIGNED
883 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
884#endif
4917cf44
AF
885 if (current_cpu != NULL) {
886 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 887 }
b018ddf6
PB
888}
889
d197063f
PB
890static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
891 unsigned size, bool is_write)
892{
893 return false;
894}
895
896const MemoryRegionOps unassigned_mem_ops = {
897 .valid.accepts = unassigned_mem_accepts,
898 .endianness = DEVICE_NATIVE_ENDIAN,
899};
900
d2702032
PB
901bool memory_region_access_valid(MemoryRegion *mr,
902 hwaddr addr,
903 unsigned size,
904 bool is_write)
093bc2cd 905{
a014ed07
PB
906 int access_size_min, access_size_max;
907 int access_size, i;
897fa7cf 908
093bc2cd
AK
909 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
910 return false;
911 }
912
a014ed07 913 if (!mr->ops->valid.accepts) {
093bc2cd
AK
914 return true;
915 }
916
a014ed07
PB
917 access_size_min = mr->ops->valid.min_access_size;
918 if (!mr->ops->valid.min_access_size) {
919 access_size_min = 1;
920 }
921
922 access_size_max = mr->ops->valid.max_access_size;
923 if (!mr->ops->valid.max_access_size) {
924 access_size_max = 4;
925 }
926
927 access_size = MAX(MIN(size, access_size_max), access_size_min);
928 for (i = 0; i < size; i += access_size) {
929 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
930 is_write)) {
931 return false;
932 }
093bc2cd 933 }
a014ed07 934
093bc2cd
AK
935 return true;
936}
937
a621f38d 938static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
a8170e5e 939 hwaddr addr,
a621f38d 940 unsigned size)
093bc2cd 941{
164a4dcd 942 uint64_t data = 0;
093bc2cd 943
ce5d2f33
PB
944 if (mr->ops->read) {
945 access_with_adjusted_size(addr, &data, size,
946 mr->ops->impl.min_access_size,
947 mr->ops->impl.max_access_size,
948 memory_region_read_accessor, mr);
949 } else {
950 access_with_adjusted_size(addr, &data, size, 1, 4,
951 memory_region_oldmmio_read_accessor, mr);
74901c3b
AK
952 }
953
093bc2cd
AK
954 return data;
955}
956
791af8c8
PB
957static bool memory_region_dispatch_read(MemoryRegion *mr,
958 hwaddr addr,
959 uint64_t *pval,
960 unsigned size)
a621f38d 961{
791af8c8
PB
962 if (!memory_region_access_valid(mr, addr, size, false)) {
963 *pval = unassigned_mem_read(mr, addr, size);
964 return true;
965 }
a621f38d 966
791af8c8
PB
967 *pval = memory_region_dispatch_read1(mr, addr, size);
968 adjust_endianness(mr, pval, size);
969 return false;
a621f38d 970}
093bc2cd 971
791af8c8 972static bool memory_region_dispatch_write(MemoryRegion *mr,
a8170e5e 973 hwaddr addr,
a621f38d
AK
974 uint64_t data,
975 unsigned size)
976{
897fa7cf 977 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 978 unassigned_mem_write(mr, addr, data, size);
791af8c8 979 return true;
093bc2cd
AK
980 }
981
a621f38d
AK
982 adjust_endianness(mr, &data, size);
983
ce5d2f33
PB
984 if (mr->ops->write) {
985 access_with_adjusted_size(addr, &data, size,
986 mr->ops->impl.min_access_size,
987 mr->ops->impl.max_access_size,
988 memory_region_write_accessor, mr);
989 } else {
990 access_with_adjusted_size(addr, &data, size, 1, 4,
991 memory_region_oldmmio_write_accessor, mr);
74901c3b 992 }
791af8c8 993 return false;
093bc2cd
AK
994}
995
093bc2cd 996void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 997 Object *owner,
093bc2cd
AK
998 const MemoryRegionOps *ops,
999 void *opaque,
1000 const char *name,
1001 uint64_t size)
1002{
2c9b15ca 1003 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1004 mr->ops = ops;
1005 mr->opaque = opaque;
14a3c10a 1006 mr->terminates = true;
97161e17 1007 mr->ram_addr = ~(ram_addr_t)0;
093bc2cd
AK
1008}
1009
1010void memory_region_init_ram(MemoryRegion *mr,
2c9b15ca 1011 Object *owner,
093bc2cd
AK
1012 const char *name,
1013 uint64_t size)
1014{
2c9b15ca 1015 memory_region_init(mr, owner, name, size);
8ea9252a 1016 mr->ram = true;
14a3c10a 1017 mr->terminates = true;
545e92e0 1018 mr->destructor = memory_region_destructor_ram;
c5705a77 1019 mr->ram_addr = qemu_ram_alloc(size, mr);
093bc2cd
AK
1020}
1021
1022void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1023 Object *owner,
093bc2cd
AK
1024 const char *name,
1025 uint64_t size,
1026 void *ptr)
1027{
2c9b15ca 1028 memory_region_init(mr, owner, name, size);
8ea9252a 1029 mr->ram = true;
14a3c10a 1030 mr->terminates = true;
545e92e0 1031 mr->destructor = memory_region_destructor_ram_from_ptr;
c5705a77 1032 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
093bc2cd
AK
1033}
1034
1035void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1036 Object *owner,
093bc2cd
AK
1037 const char *name,
1038 MemoryRegion *orig,
a8170e5e 1039 hwaddr offset,
093bc2cd
AK
1040 uint64_t size)
1041{
2c9b15ca 1042 memory_region_init(mr, owner, name, size);
dfde4e6e
PB
1043 memory_region_ref(orig);
1044 mr->destructor = memory_region_destructor_alias;
093bc2cd
AK
1045 mr->alias = orig;
1046 mr->alias_offset = offset;
1047}
1048
d0a9b5bc 1049void memory_region_init_rom_device(MemoryRegion *mr,
2c9b15ca 1050 Object *owner,
d0a9b5bc 1051 const MemoryRegionOps *ops,
75f5941c 1052 void *opaque,
d0a9b5bc
AK
1053 const char *name,
1054 uint64_t size)
1055{
2c9b15ca 1056 memory_region_init(mr, owner, name, size);
7bc2b9cd 1057 mr->ops = ops;
75f5941c 1058 mr->opaque = opaque;
d0a9b5bc 1059 mr->terminates = true;
75c578dc 1060 mr->rom_device = true;
d0a9b5bc 1061 mr->destructor = memory_region_destructor_rom_device;
c5705a77 1062 mr->ram_addr = qemu_ram_alloc(size, mr);
d0a9b5bc
AK
1063}
1064
30951157 1065void memory_region_init_iommu(MemoryRegion *mr,
2c9b15ca 1066 Object *owner,
30951157
AK
1067 const MemoryRegionIOMMUOps *ops,
1068 const char *name,
1069 uint64_t size)
1070{
2c9b15ca 1071 memory_region_init(mr, owner, name, size);
30951157
AK
1072 mr->iommu_ops = ops,
1073 mr->terminates = true; /* then re-forwards */
06866575 1074 notifier_list_init(&mr->iommu_notify);
30951157
AK
1075}
1076
1660e72d 1077void memory_region_init_reservation(MemoryRegion *mr,
2c9b15ca 1078 Object *owner,
1660e72d
JK
1079 const char *name,
1080 uint64_t size)
1081{
2c9b15ca 1082 memory_region_init_io(mr, owner, &unassigned_mem_ops, mr, name, size);
1660e72d
JK
1083}
1084
093bc2cd
AK
1085void memory_region_destroy(MemoryRegion *mr)
1086{
1087 assert(QTAILQ_EMPTY(&mr->subregions));
2be0e25f 1088 assert(memory_region_transaction_depth == 0);
545e92e0 1089 mr->destructor(mr);
093bc2cd 1090 memory_region_clear_coalescing(mr);
7267c094
AL
1091 g_free((char *)mr->name);
1092 g_free(mr->ioeventfds);
093bc2cd
AK
1093}
1094
803c0816
PB
1095Object *memory_region_owner(MemoryRegion *mr)
1096{
1097 return mr->owner;
1098}
1099
46637be2
PB
1100void memory_region_ref(MemoryRegion *mr)
1101{
1102 if (mr && mr->owner) {
1103 object_ref(mr->owner);
1104 }
1105}
1106
1107void memory_region_unref(MemoryRegion *mr)
1108{
1109 if (mr && mr->owner) {
1110 object_unref(mr->owner);
1111 }
1112}
1113
093bc2cd
AK
1114uint64_t memory_region_size(MemoryRegion *mr)
1115{
08dafab4
AK
1116 if (int128_eq(mr->size, int128_2_64())) {
1117 return UINT64_MAX;
1118 }
1119 return int128_get64(mr->size);
093bc2cd
AK
1120}
1121
8991c79b
AK
1122const char *memory_region_name(MemoryRegion *mr)
1123{
1124 return mr->name;
1125}
1126
8ea9252a
AK
1127bool memory_region_is_ram(MemoryRegion *mr)
1128{
1129 return mr->ram;
1130}
1131
55043ba3
AK
1132bool memory_region_is_logging(MemoryRegion *mr)
1133{
1134 return mr->dirty_log_mask;
1135}
1136
ce7923da
AK
1137bool memory_region_is_rom(MemoryRegion *mr)
1138{
1139 return mr->ram && mr->readonly;
1140}
1141
30951157
AK
1142bool memory_region_is_iommu(MemoryRegion *mr)
1143{
1144 return mr->iommu_ops;
1145}
1146
06866575
DG
1147void memory_region_register_iommu_notifier(MemoryRegion *mr, Notifier *n)
1148{
1149 notifier_list_add(&mr->iommu_notify, n);
1150}
1151
1152void memory_region_unregister_iommu_notifier(Notifier *n)
1153{
1154 notifier_remove(n);
1155}
1156
1157void memory_region_notify_iommu(MemoryRegion *mr,
1158 IOMMUTLBEntry entry)
1159{
1160 assert(memory_region_is_iommu(mr));
1161 notifier_list_notify(&mr->iommu_notify, &entry);
1162}
1163
093bc2cd
AK
1164void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1165{
5a583347
AK
1166 uint8_t mask = 1 << client;
1167
59023ef4 1168 memory_region_transaction_begin();
5a583347 1169 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1170 memory_region_update_pending |= mr->enabled;
59023ef4 1171 memory_region_transaction_commit();
093bc2cd
AK
1172}
1173
a8170e5e
AK
1174bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1175 hwaddr size, unsigned client)
093bc2cd 1176{
14a3c10a 1177 assert(mr->terminates);
52159192 1178 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
093bc2cd
AK
1179}
1180
a8170e5e
AK
1181void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1182 hwaddr size)
093bc2cd 1183{
14a3c10a 1184 assert(mr->terminates);
75218e7f 1185 cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size);
093bc2cd
AK
1186}
1187
6c279db8
JQ
1188bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1189 hwaddr size, unsigned client)
1190{
1191 bool ret;
1192 assert(mr->terminates);
52159192 1193 ret = cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
6c279db8 1194 if (ret) {
a2f4d5be 1195 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
6c279db8
JQ
1196 }
1197 return ret;
1198}
1199
1200
093bc2cd
AK
1201void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1202{
0d673e36 1203 AddressSpace *as;
5a583347
AK
1204 FlatRange *fr;
1205
0d673e36 1206 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
856d7245 1207 FlatView *view = address_space_get_flatview(as);
99e86347 1208 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36
AK
1209 if (fr->mr == mr) {
1210 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1211 }
5a583347 1212 }
856d7245 1213 flatview_unref(view);
5a583347 1214 }
093bc2cd
AK
1215}
1216
1217void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1218{
fb1cd6f9 1219 if (mr->readonly != readonly) {
59023ef4 1220 memory_region_transaction_begin();
fb1cd6f9 1221 mr->readonly = readonly;
22bde714 1222 memory_region_update_pending |= mr->enabled;
59023ef4 1223 memory_region_transaction_commit();
fb1cd6f9 1224 }
093bc2cd
AK
1225}
1226
5f9a5ea1 1227void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1228{
5f9a5ea1 1229 if (mr->romd_mode != romd_mode) {
59023ef4 1230 memory_region_transaction_begin();
5f9a5ea1 1231 mr->romd_mode = romd_mode;
22bde714 1232 memory_region_update_pending |= mr->enabled;
59023ef4 1233 memory_region_transaction_commit();
d0a9b5bc
AK
1234 }
1235}
1236
a8170e5e
AK
1237void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1238 hwaddr size, unsigned client)
093bc2cd 1239{
14a3c10a 1240 assert(mr->terminates);
a2f4d5be 1241 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
093bc2cd
AK
1242}
1243
1244void *memory_region_get_ram_ptr(MemoryRegion *mr)
1245{
1246 if (mr->alias) {
1247 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1248 }
1249
14a3c10a 1250 assert(mr->terminates);
093bc2cd 1251
021d26d1 1252 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
093bc2cd
AK
1253}
1254
0d673e36 1255static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1256{
99e86347 1257 FlatView *view;
093bc2cd
AK
1258 FlatRange *fr;
1259 CoalescedMemoryRange *cmr;
1260 AddrRange tmp;
95d2994a 1261 MemoryRegionSection section;
093bc2cd 1262
856d7245 1263 view = address_space_get_flatview(as);
99e86347 1264 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1265 if (fr->mr == mr) {
95d2994a 1266 section = (MemoryRegionSection) {
f6790af6 1267 .address_space = as,
95d2994a 1268 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1269 .size = fr->addr.size,
95d2994a
AK
1270 };
1271
1272 MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, &section,
1273 int128_get64(fr->addr.start),
1274 int128_get64(fr->addr.size));
093bc2cd
AK
1275 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1276 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1277 int128_sub(fr->addr.start,
1278 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1279 if (!addrrange_intersects(tmp, fr->addr)) {
1280 continue;
1281 }
1282 tmp = addrrange_intersection(tmp, fr->addr);
95d2994a
AK
1283 MEMORY_LISTENER_CALL(coalesced_mmio_add, Forward, &section,
1284 int128_get64(tmp.start),
1285 int128_get64(tmp.size));
093bc2cd
AK
1286 }
1287 }
1288 }
856d7245 1289 flatview_unref(view);
093bc2cd
AK
1290}
1291
0d673e36
AK
1292static void memory_region_update_coalesced_range(MemoryRegion *mr)
1293{
1294 AddressSpace *as;
1295
1296 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1297 memory_region_update_coalesced_range_as(mr, as);
1298 }
1299}
1300
093bc2cd
AK
1301void memory_region_set_coalescing(MemoryRegion *mr)
1302{
1303 memory_region_clear_coalescing(mr);
08dafab4 1304 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1305}
1306
1307void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1308 hwaddr offset,
093bc2cd
AK
1309 uint64_t size)
1310{
7267c094 1311 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1312
08dafab4 1313 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
1314 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1315 memory_region_update_coalesced_range(mr);
d410515e 1316 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
1317}
1318
1319void memory_region_clear_coalescing(MemoryRegion *mr)
1320{
1321 CoalescedMemoryRange *cmr;
1322
d410515e
JK
1323 qemu_flush_coalesced_mmio_buffer();
1324 mr->flush_coalesced_mmio = false;
1325
093bc2cd
AK
1326 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1327 cmr = QTAILQ_FIRST(&mr->coalesced);
1328 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1329 g_free(cmr);
093bc2cd
AK
1330 }
1331 memory_region_update_coalesced_range(mr);
1332}
1333
d410515e
JK
1334void memory_region_set_flush_coalesced(MemoryRegion *mr)
1335{
1336 mr->flush_coalesced_mmio = true;
1337}
1338
1339void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1340{
1341 qemu_flush_coalesced_mmio_buffer();
1342 if (QTAILQ_EMPTY(&mr->coalesced)) {
1343 mr->flush_coalesced_mmio = false;
1344 }
1345}
1346
3e9d69e7 1347void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 1348 hwaddr addr,
3e9d69e7
AK
1349 unsigned size,
1350 bool match_data,
1351 uint64_t data,
753d5e14 1352 EventNotifier *e)
3e9d69e7
AK
1353{
1354 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1355 .addr.start = int128_make64(addr),
1356 .addr.size = int128_make64(size),
3e9d69e7
AK
1357 .match_data = match_data,
1358 .data = data,
753d5e14 1359 .e = e,
3e9d69e7
AK
1360 };
1361 unsigned i;
1362
28f362be 1363 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1364 memory_region_transaction_begin();
3e9d69e7
AK
1365 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1366 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1367 break;
1368 }
1369 }
1370 ++mr->ioeventfd_nb;
7267c094 1371 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
1372 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1373 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1374 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1375 mr->ioeventfds[i] = mrfd;
22bde714 1376 memory_region_update_pending |= mr->enabled;
59023ef4 1377 memory_region_transaction_commit();
3e9d69e7
AK
1378}
1379
1380void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 1381 hwaddr addr,
3e9d69e7
AK
1382 unsigned size,
1383 bool match_data,
1384 uint64_t data,
753d5e14 1385 EventNotifier *e)
3e9d69e7
AK
1386{
1387 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1388 .addr.start = int128_make64(addr),
1389 .addr.size = int128_make64(size),
3e9d69e7
AK
1390 .match_data = match_data,
1391 .data = data,
753d5e14 1392 .e = e,
3e9d69e7
AK
1393 };
1394 unsigned i;
1395
28f362be 1396 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1397 memory_region_transaction_begin();
3e9d69e7
AK
1398 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1399 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1400 break;
1401 }
1402 }
1403 assert(i != mr->ioeventfd_nb);
1404 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1405 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1406 --mr->ioeventfd_nb;
7267c094 1407 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1408 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
22bde714 1409 memory_region_update_pending |= mr->enabled;
59023ef4 1410 memory_region_transaction_commit();
3e9d69e7
AK
1411}
1412
093bc2cd 1413static void memory_region_add_subregion_common(MemoryRegion *mr,
a8170e5e 1414 hwaddr offset,
093bc2cd
AK
1415 MemoryRegion *subregion)
1416{
1417 MemoryRegion *other;
1418
59023ef4
JK
1419 memory_region_transaction_begin();
1420
093bc2cd 1421 assert(!subregion->parent);
dfde4e6e 1422 memory_region_ref(subregion);
093bc2cd
AK
1423 subregion->parent = mr;
1424 subregion->addr = offset;
1425 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1426 if (subregion->may_overlap || other->may_overlap) {
1427 continue;
1428 }
2c7cfd65 1429 if (int128_ge(int128_make64(offset),
08dafab4
AK
1430 int128_add(int128_make64(other->addr), other->size))
1431 || int128_le(int128_add(int128_make64(offset), subregion->size),
1432 int128_make64(other->addr))) {
093bc2cd
AK
1433 continue;
1434 }
a5e1cbc8 1435#if 0
860329b2
MW
1436 printf("warning: subregion collision %llx/%llx (%s) "
1437 "vs %llx/%llx (%s)\n",
093bc2cd 1438 (unsigned long long)offset,
08dafab4 1439 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1440 subregion->name,
1441 (unsigned long long)other->addr,
08dafab4 1442 (unsigned long long)int128_get64(other->size),
860329b2 1443 other->name);
a5e1cbc8 1444#endif
093bc2cd
AK
1445 }
1446 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1447 if (subregion->priority >= other->priority) {
1448 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1449 goto done;
1450 }
1451 }
1452 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1453done:
22bde714 1454 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1455 memory_region_transaction_commit();
093bc2cd
AK
1456}
1457
1458
1459void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 1460 hwaddr offset,
093bc2cd
AK
1461 MemoryRegion *subregion)
1462{
1463 subregion->may_overlap = false;
1464 subregion->priority = 0;
1465 memory_region_add_subregion_common(mr, offset, subregion);
1466}
1467
1468void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 1469 hwaddr offset,
093bc2cd 1470 MemoryRegion *subregion,
a1ff8ae0 1471 int priority)
093bc2cd
AK
1472{
1473 subregion->may_overlap = true;
1474 subregion->priority = priority;
1475 memory_region_add_subregion_common(mr, offset, subregion);
1476}
1477
1478void memory_region_del_subregion(MemoryRegion *mr,
1479 MemoryRegion *subregion)
1480{
59023ef4 1481 memory_region_transaction_begin();
093bc2cd
AK
1482 assert(subregion->parent == mr);
1483 subregion->parent = NULL;
1484 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 1485 memory_region_unref(subregion);
22bde714 1486 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1487 memory_region_transaction_commit();
6bba19ba
AK
1488}
1489
1490void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1491{
1492 if (enabled == mr->enabled) {
1493 return;
1494 }
59023ef4 1495 memory_region_transaction_begin();
6bba19ba 1496 mr->enabled = enabled;
22bde714 1497 memory_region_update_pending = true;
59023ef4 1498 memory_region_transaction_commit();
093bc2cd 1499}
1c0ffa58 1500
a8170e5e 1501void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2282e1af
AK
1502{
1503 MemoryRegion *parent = mr->parent;
a1ff8ae0 1504 int priority = mr->priority;
2282e1af
AK
1505 bool may_overlap = mr->may_overlap;
1506
1507 if (addr == mr->addr || !parent) {
1508 mr->addr = addr;
1509 return;
1510 }
1511
1512 memory_region_transaction_begin();
dfde4e6e 1513 memory_region_ref(mr);
2282e1af
AK
1514 memory_region_del_subregion(parent, mr);
1515 if (may_overlap) {
1516 memory_region_add_subregion_overlap(parent, addr, mr, priority);
1517 } else {
1518 memory_region_add_subregion(parent, addr, mr);
1519 }
dfde4e6e 1520 memory_region_unref(mr);
2282e1af
AK
1521 memory_region_transaction_commit();
1522}
1523
a8170e5e 1524void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 1525{
4703359e 1526 assert(mr->alias);
4703359e 1527
59023ef4 1528 if (offset == mr->alias_offset) {
4703359e
AK
1529 return;
1530 }
1531
59023ef4
JK
1532 memory_region_transaction_begin();
1533 mr->alias_offset = offset;
22bde714 1534 memory_region_update_pending |= mr->enabled;
59023ef4 1535 memory_region_transaction_commit();
4703359e
AK
1536}
1537
e34911c4
AK
1538ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1539{
e34911c4
AK
1540 return mr->ram_addr;
1541}
1542
e2177955
AK
1543static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1544{
1545 const AddrRange *addr = addr_;
1546 const FlatRange *fr = fr_;
1547
1548 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1549 return -1;
1550 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1551 return 1;
1552 }
1553 return 0;
1554}
1555
99e86347 1556static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 1557{
99e86347 1558 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
1559 sizeof(FlatRange), cmp_flatrange_addr);
1560}
1561
3ce10901
PB
1562bool memory_region_present(MemoryRegion *parent, hwaddr addr)
1563{
1564 MemoryRegion *mr = memory_region_find(parent, addr, 1).mr;
8e46bbf3 1565 if (!mr || (mr == parent)) {
3ce10901
PB
1566 return false;
1567 }
dfde4e6e 1568 memory_region_unref(mr);
3ce10901
PB
1569 return true;
1570}
1571
73034e9e 1572MemoryRegionSection memory_region_find(MemoryRegion *mr,
a8170e5e 1573 hwaddr addr, uint64_t size)
e2177955 1574{
052e87b0 1575 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
1576 MemoryRegion *root;
1577 AddressSpace *as;
1578 AddrRange range;
99e86347 1579 FlatView *view;
73034e9e
PB
1580 FlatRange *fr;
1581
1582 addr += mr->addr;
1583 for (root = mr; root->parent; ) {
1584 root = root->parent;
1585 addr += root->addr;
1586 }
e2177955 1587
73034e9e
PB
1588 as = memory_region_to_address_space(root);
1589 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 1590
856d7245 1591 view = address_space_get_flatview(as);
99e86347 1592 fr = flatview_lookup(view, range);
e2177955 1593 if (!fr) {
6307d974 1594 flatview_unref(view);
e2177955
AK
1595 return ret;
1596 }
1597
99e86347 1598 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
1599 --fr;
1600 }
1601
1602 ret.mr = fr->mr;
73034e9e 1603 ret.address_space = as;
e2177955
AK
1604 range = addrrange_intersection(range, fr->addr);
1605 ret.offset_within_region = fr->offset_in_region;
1606 ret.offset_within_region += int128_get64(int128_sub(range.start,
1607 fr->addr.start));
052e87b0 1608 ret.size = range.size;
e2177955 1609 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 1610 ret.readonly = fr->readonly;
dfde4e6e
PB
1611 memory_region_ref(ret.mr);
1612
856d7245 1613 flatview_unref(view);
e2177955
AK
1614 return ret;
1615}
1616
1d671369 1617void address_space_sync_dirty_bitmap(AddressSpace *as)
86e775c6 1618{
99e86347 1619 FlatView *view;
7664e80c
AK
1620 FlatRange *fr;
1621
856d7245 1622 view = address_space_get_flatview(as);
99e86347 1623 FOR_EACH_FLAT_RANGE(fr, view) {
72e22d2f 1624 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
7664e80c 1625 }
856d7245 1626 flatview_unref(view);
7664e80c
AK
1627}
1628
1629void memory_global_dirty_log_start(void)
1630{
7664e80c 1631 global_dirty_log = true;
7376e582 1632 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
7664e80c
AK
1633}
1634
1635void memory_global_dirty_log_stop(void)
1636{
7664e80c 1637 global_dirty_log = false;
7376e582 1638 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
1639}
1640
1641static void listener_add_address_space(MemoryListener *listener,
1642 AddressSpace *as)
1643{
99e86347 1644 FlatView *view;
7664e80c
AK
1645 FlatRange *fr;
1646
221b3a3f 1647 if (listener->address_space_filter
f6790af6 1648 && listener->address_space_filter != as) {
221b3a3f
JG
1649 return;
1650 }
1651
7664e80c 1652 if (global_dirty_log) {
975aefe0
AK
1653 if (listener->log_global_start) {
1654 listener->log_global_start(listener);
1655 }
7664e80c 1656 }
975aefe0 1657
856d7245 1658 view = address_space_get_flatview(as);
99e86347 1659 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
1660 MemoryRegionSection section = {
1661 .mr = fr->mr,
f6790af6 1662 .address_space = as,
7664e80c 1663 .offset_within_region = fr->offset_in_region,
052e87b0 1664 .size = fr->addr.size,
7664e80c 1665 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 1666 .readonly = fr->readonly,
7664e80c 1667 };
975aefe0
AK
1668 if (listener->region_add) {
1669 listener->region_add(listener, &section);
1670 }
7664e80c 1671 }
856d7245 1672 flatview_unref(view);
7664e80c
AK
1673}
1674
f6790af6 1675void memory_listener_register(MemoryListener *listener, AddressSpace *filter)
7664e80c 1676{
72e22d2f 1677 MemoryListener *other = NULL;
0d673e36 1678 AddressSpace *as;
72e22d2f 1679
7376e582 1680 listener->address_space_filter = filter;
72e22d2f
AK
1681 if (QTAILQ_EMPTY(&memory_listeners)
1682 || listener->priority >= QTAILQ_LAST(&memory_listeners,
1683 memory_listeners)->priority) {
1684 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
1685 } else {
1686 QTAILQ_FOREACH(other, &memory_listeners, link) {
1687 if (listener->priority < other->priority) {
1688 break;
1689 }
1690 }
1691 QTAILQ_INSERT_BEFORE(other, listener, link);
1692 }
0d673e36
AK
1693
1694 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1695 listener_add_address_space(listener, as);
1696 }
7664e80c
AK
1697}
1698
1699void memory_listener_unregister(MemoryListener *listener)
1700{
72e22d2f 1701 QTAILQ_REMOVE(&memory_listeners, listener, link);
86e775c6 1702}
e2177955 1703
7dca8043 1704void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 1705{
856d7245
PB
1706 if (QTAILQ_EMPTY(&address_spaces)) {
1707 memory_init();
1708 }
1709
59023ef4 1710 memory_region_transaction_begin();
8786db7c
AK
1711 as->root = root;
1712 as->current_map = g_new(FlatView, 1);
1713 flatview_init(as->current_map);
4c19eb72
AK
1714 as->ioeventfd_nb = 0;
1715 as->ioeventfds = NULL;
0d673e36 1716 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 1717 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 1718 address_space_init_dispatch(as);
f43793c7
PB
1719 memory_region_update_pending |= root->enabled;
1720 memory_region_transaction_commit();
1c0ffa58 1721}
658b2224 1722
83f3c251
AK
1723void address_space_destroy(AddressSpace *as)
1724{
1725 /* Flush out anything from MemoryListeners listening in on this */
1726 memory_region_transaction_begin();
1727 as->root = NULL;
1728 memory_region_transaction_commit();
1729 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
1730 address_space_destroy_dispatch(as);
856d7245 1731 flatview_unref(as->current_map);
7dca8043 1732 g_free(as->name);
4c19eb72 1733 g_free(as->ioeventfds);
83f3c251
AK
1734}
1735
791af8c8 1736bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size)
acbbec5d 1737{
791af8c8 1738 return memory_region_dispatch_read(mr, addr, pval, size);
acbbec5d
AK
1739}
1740
791af8c8 1741bool io_mem_write(MemoryRegion *mr, hwaddr addr,
acbbec5d
AK
1742 uint64_t val, unsigned size)
1743{
791af8c8 1744 return memory_region_dispatch_write(mr, addr, val, size);
acbbec5d
AK
1745}
1746
314e2987
BS
1747typedef struct MemoryRegionList MemoryRegionList;
1748
1749struct MemoryRegionList {
1750 const MemoryRegion *mr;
1751 bool printed;
1752 QTAILQ_ENTRY(MemoryRegionList) queue;
1753};
1754
1755typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1756
1757static void mtree_print_mr(fprintf_function mon_printf, void *f,
1758 const MemoryRegion *mr, unsigned int level,
a8170e5e 1759 hwaddr base,
9479c57a 1760 MemoryRegionListHead *alias_print_queue)
314e2987 1761{
9479c57a
JK
1762 MemoryRegionList *new_ml, *ml, *next_ml;
1763 MemoryRegionListHead submr_print_queue;
314e2987
BS
1764 const MemoryRegion *submr;
1765 unsigned int i;
1766
7ea692b2 1767 if (!mr || !mr->enabled) {
314e2987
BS
1768 return;
1769 }
1770
1771 for (i = 0; i < level; i++) {
1772 mon_printf(f, " ");
1773 }
1774
1775 if (mr->alias) {
1776 MemoryRegionList *ml;
1777 bool found = false;
1778
1779 /* check if the alias is already in the queue */
9479c57a 1780 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
314e2987
BS
1781 if (ml->mr == mr->alias && !ml->printed) {
1782 found = true;
1783 }
1784 }
1785
1786 if (!found) {
1787 ml = g_new(MemoryRegionList, 1);
1788 ml->mr = mr->alias;
1789 ml->printed = false;
9479c57a 1790 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 1791 }
4896d74b
JK
1792 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
1793 " (prio %d, %c%c): alias %s @%s " TARGET_FMT_plx
1794 "-" TARGET_FMT_plx "\n",
314e2987 1795 base + mr->addr,
08dafab4 1796 base + mr->addr
fd1d9926
AW
1797 + (int128_nz(mr->size) ?
1798 (hwaddr)int128_get64(int128_sub(mr->size,
1799 int128_one())) : 0),
4b474ba7 1800 mr->priority,
5f9a5ea1
JK
1801 mr->romd_mode ? 'R' : '-',
1802 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1803 : '-',
314e2987
BS
1804 mr->name,
1805 mr->alias->name,
1806 mr->alias_offset,
08dafab4 1807 mr->alias_offset
a66670c7
AK
1808 + (int128_nz(mr->size) ?
1809 (hwaddr)int128_get64(int128_sub(mr->size,
1810 int128_one())) : 0));
314e2987 1811 } else {
4896d74b
JK
1812 mon_printf(f,
1813 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s\n",
314e2987 1814 base + mr->addr,
08dafab4 1815 base + mr->addr
fd1d9926
AW
1816 + (int128_nz(mr->size) ?
1817 (hwaddr)int128_get64(int128_sub(mr->size,
1818 int128_one())) : 0),
4b474ba7 1819 mr->priority,
5f9a5ea1
JK
1820 mr->romd_mode ? 'R' : '-',
1821 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1822 : '-',
314e2987
BS
1823 mr->name);
1824 }
9479c57a
JK
1825
1826 QTAILQ_INIT(&submr_print_queue);
1827
314e2987 1828 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
1829 new_ml = g_new(MemoryRegionList, 1);
1830 new_ml->mr = submr;
1831 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1832 if (new_ml->mr->addr < ml->mr->addr ||
1833 (new_ml->mr->addr == ml->mr->addr &&
1834 new_ml->mr->priority > ml->mr->priority)) {
1835 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1836 new_ml = NULL;
1837 break;
1838 }
1839 }
1840 if (new_ml) {
1841 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1842 }
1843 }
1844
1845 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1846 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1847 alias_print_queue);
1848 }
1849
88365e47 1850 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 1851 g_free(ml);
314e2987
BS
1852 }
1853}
1854
1855void mtree_info(fprintf_function mon_printf, void *f)
1856{
1857 MemoryRegionListHead ml_head;
1858 MemoryRegionList *ml, *ml2;
0d673e36 1859 AddressSpace *as;
314e2987
BS
1860
1861 QTAILQ_INIT(&ml_head);
1862
0d673e36 1863 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
0d673e36
AK
1864 mon_printf(f, "%s\n", as->name);
1865 mtree_print_mr(mon_printf, f, as->root, 0, 0, &ml_head);
b9f9be88
BS
1866 }
1867
1868 mon_printf(f, "aliases\n");
314e2987
BS
1869 /* print aliased regions */
1870 QTAILQ_FOREACH(ml, &ml_head, queue) {
1871 if (!ml->printed) {
1872 mon_printf(f, "%s\n", ml->mr->name);
1873 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1874 }
1875 }
1876
1877 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 1878 g_free(ml);
314e2987 1879 }
314e2987 1880}