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Commit | Line | Data |
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093bc2cd AK |
1 | /* |
2 | * Physical memory management | |
3 | * | |
4 | * Copyright 2011 Red Hat, Inc. and/or its affiliates | |
5 | * | |
6 | * Authors: | |
7 | * Avi Kivity <avi@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "memory.h" | |
1c0ffa58 | 15 | #include "exec-memory.h" |
658b2224 | 16 | #include "ioport.h" |
74901c3b | 17 | #include "bitops.h" |
3e9d69e7 | 18 | #include "kvm.h" |
093bc2cd AK |
19 | #include <assert.h> |
20 | ||
4ef4db86 | 21 | unsigned memory_region_transaction_depth = 0; |
e87c099f | 22 | static bool memory_region_update_pending = false; |
4ef4db86 | 23 | |
093bc2cd AK |
24 | typedef struct AddrRange AddrRange; |
25 | ||
8417cebf AK |
26 | /* |
27 | * Note using signed integers limits us to physical addresses at most | |
28 | * 63 bits wide. They are needed for negative offsetting in aliases | |
29 | * (large MemoryRegion::alias_offset). | |
30 | */ | |
093bc2cd | 31 | struct AddrRange { |
08dafab4 AK |
32 | Int128 start; |
33 | Int128 size; | |
093bc2cd AK |
34 | }; |
35 | ||
08dafab4 | 36 | static AddrRange addrrange_make(Int128 start, Int128 size) |
093bc2cd AK |
37 | { |
38 | return (AddrRange) { start, size }; | |
39 | } | |
40 | ||
41 | static bool addrrange_equal(AddrRange r1, AddrRange r2) | |
42 | { | |
08dafab4 | 43 | return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size); |
093bc2cd AK |
44 | } |
45 | ||
08dafab4 | 46 | static Int128 addrrange_end(AddrRange r) |
093bc2cd | 47 | { |
08dafab4 | 48 | return int128_add(r.start, r.size); |
093bc2cd AK |
49 | } |
50 | ||
08dafab4 | 51 | static AddrRange addrrange_shift(AddrRange range, Int128 delta) |
093bc2cd | 52 | { |
08dafab4 | 53 | int128_addto(&range.start, delta); |
093bc2cd AK |
54 | return range; |
55 | } | |
56 | ||
08dafab4 AK |
57 | static bool addrrange_contains(AddrRange range, Int128 addr) |
58 | { | |
59 | return int128_ge(addr, range.start) | |
60 | && int128_lt(addr, addrrange_end(range)); | |
61 | } | |
62 | ||
093bc2cd AK |
63 | static bool addrrange_intersects(AddrRange r1, AddrRange r2) |
64 | { | |
08dafab4 AK |
65 | return addrrange_contains(r1, r2.start) |
66 | || addrrange_contains(r2, r1.start); | |
093bc2cd AK |
67 | } |
68 | ||
69 | static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) | |
70 | { | |
08dafab4 AK |
71 | Int128 start = int128_max(r1.start, r2.start); |
72 | Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2)); | |
73 | return addrrange_make(start, int128_sub(end, start)); | |
093bc2cd AK |
74 | } |
75 | ||
76 | struct CoalescedMemoryRange { | |
77 | AddrRange addr; | |
78 | QTAILQ_ENTRY(CoalescedMemoryRange) link; | |
79 | }; | |
80 | ||
3e9d69e7 AK |
81 | struct MemoryRegionIoeventfd { |
82 | AddrRange addr; | |
83 | bool match_data; | |
84 | uint64_t data; | |
85 | int fd; | |
86 | }; | |
87 | ||
88 | static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, | |
89 | MemoryRegionIoeventfd b) | |
90 | { | |
08dafab4 | 91 | if (int128_lt(a.addr.start, b.addr.start)) { |
3e9d69e7 | 92 | return true; |
08dafab4 | 93 | } else if (int128_gt(a.addr.start, b.addr.start)) { |
3e9d69e7 | 94 | return false; |
08dafab4 | 95 | } else if (int128_lt(a.addr.size, b.addr.size)) { |
3e9d69e7 | 96 | return true; |
08dafab4 | 97 | } else if (int128_gt(a.addr.size, b.addr.size)) { |
3e9d69e7 AK |
98 | return false; |
99 | } else if (a.match_data < b.match_data) { | |
100 | return true; | |
101 | } else if (a.match_data > b.match_data) { | |
102 | return false; | |
103 | } else if (a.match_data) { | |
104 | if (a.data < b.data) { | |
105 | return true; | |
106 | } else if (a.data > b.data) { | |
107 | return false; | |
108 | } | |
109 | } | |
110 | if (a.fd < b.fd) { | |
111 | return true; | |
112 | } else if (a.fd > b.fd) { | |
113 | return false; | |
114 | } | |
115 | return false; | |
116 | } | |
117 | ||
118 | static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a, | |
119 | MemoryRegionIoeventfd b) | |
120 | { | |
121 | return !memory_region_ioeventfd_before(a, b) | |
122 | && !memory_region_ioeventfd_before(b, a); | |
123 | } | |
124 | ||
093bc2cd AK |
125 | typedef struct FlatRange FlatRange; |
126 | typedef struct FlatView FlatView; | |
127 | ||
128 | /* Range of memory in the global map. Addresses are absolute. */ | |
129 | struct FlatRange { | |
130 | MemoryRegion *mr; | |
131 | target_phys_addr_t offset_in_region; | |
132 | AddrRange addr; | |
5a583347 | 133 | uint8_t dirty_log_mask; |
d0a9b5bc | 134 | bool readable; |
fb1cd6f9 | 135 | bool readonly; |
093bc2cd AK |
136 | }; |
137 | ||
138 | /* Flattened global view of current active memory hierarchy. Kept in sorted | |
139 | * order. | |
140 | */ | |
141 | struct FlatView { | |
142 | FlatRange *ranges; | |
143 | unsigned nr; | |
144 | unsigned nr_allocated; | |
145 | }; | |
146 | ||
cc31e6e7 AK |
147 | typedef struct AddressSpace AddressSpace; |
148 | typedef struct AddressSpaceOps AddressSpaceOps; | |
149 | ||
150 | /* A system address space - I/O, memory, etc. */ | |
151 | struct AddressSpace { | |
152 | const AddressSpaceOps *ops; | |
153 | MemoryRegion *root; | |
154 | FlatView current_map; | |
3e9d69e7 AK |
155 | int ioeventfd_nb; |
156 | MemoryRegionIoeventfd *ioeventfds; | |
cc31e6e7 AK |
157 | }; |
158 | ||
159 | struct AddressSpaceOps { | |
160 | void (*range_add)(AddressSpace *as, FlatRange *fr); | |
161 | void (*range_del)(AddressSpace *as, FlatRange *fr); | |
162 | void (*log_start)(AddressSpace *as, FlatRange *fr); | |
163 | void (*log_stop)(AddressSpace *as, FlatRange *fr); | |
3e9d69e7 AK |
164 | void (*ioeventfd_add)(AddressSpace *as, MemoryRegionIoeventfd *fd); |
165 | void (*ioeventfd_del)(AddressSpace *as, MemoryRegionIoeventfd *fd); | |
cc31e6e7 AK |
166 | }; |
167 | ||
093bc2cd AK |
168 | #define FOR_EACH_FLAT_RANGE(var, view) \ |
169 | for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) | |
170 | ||
093bc2cd AK |
171 | static bool flatrange_equal(FlatRange *a, FlatRange *b) |
172 | { | |
173 | return a->mr == b->mr | |
174 | && addrrange_equal(a->addr, b->addr) | |
d0a9b5bc | 175 | && a->offset_in_region == b->offset_in_region |
fb1cd6f9 AK |
176 | && a->readable == b->readable |
177 | && a->readonly == b->readonly; | |
093bc2cd AK |
178 | } |
179 | ||
180 | static void flatview_init(FlatView *view) | |
181 | { | |
182 | view->ranges = NULL; | |
183 | view->nr = 0; | |
184 | view->nr_allocated = 0; | |
185 | } | |
186 | ||
187 | /* Insert a range into a given position. Caller is responsible for maintaining | |
188 | * sorting order. | |
189 | */ | |
190 | static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) | |
191 | { | |
192 | if (view->nr == view->nr_allocated) { | |
193 | view->nr_allocated = MAX(2 * view->nr, 10); | |
7267c094 | 194 | view->ranges = g_realloc(view->ranges, |
093bc2cd AK |
195 | view->nr_allocated * sizeof(*view->ranges)); |
196 | } | |
197 | memmove(view->ranges + pos + 1, view->ranges + pos, | |
198 | (view->nr - pos) * sizeof(FlatRange)); | |
199 | view->ranges[pos] = *range; | |
200 | ++view->nr; | |
201 | } | |
202 | ||
203 | static void flatview_destroy(FlatView *view) | |
204 | { | |
7267c094 | 205 | g_free(view->ranges); |
093bc2cd AK |
206 | } |
207 | ||
3d8e6bf9 AK |
208 | static bool can_merge(FlatRange *r1, FlatRange *r2) |
209 | { | |
08dafab4 | 210 | return int128_eq(addrrange_end(r1->addr), r2->addr.start) |
3d8e6bf9 | 211 | && r1->mr == r2->mr |
08dafab4 AK |
212 | && int128_eq(int128_add(int128_make64(r1->offset_in_region), |
213 | r1->addr.size), | |
214 | int128_make64(r2->offset_in_region)) | |
d0a9b5bc | 215 | && r1->dirty_log_mask == r2->dirty_log_mask |
fb1cd6f9 AK |
216 | && r1->readable == r2->readable |
217 | && r1->readonly == r2->readonly; | |
3d8e6bf9 AK |
218 | } |
219 | ||
220 | /* Attempt to simplify a view by merging ajacent ranges */ | |
221 | static void flatview_simplify(FlatView *view) | |
222 | { | |
223 | unsigned i, j; | |
224 | ||
225 | i = 0; | |
226 | while (i < view->nr) { | |
227 | j = i + 1; | |
228 | while (j < view->nr | |
229 | && can_merge(&view->ranges[j-1], &view->ranges[j])) { | |
08dafab4 | 230 | int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size); |
3d8e6bf9 AK |
231 | ++j; |
232 | } | |
233 | ++i; | |
234 | memmove(&view->ranges[i], &view->ranges[j], | |
235 | (view->nr - j) * sizeof(view->ranges[j])); | |
236 | view->nr -= j - i; | |
237 | } | |
238 | } | |
239 | ||
164a4dcd AK |
240 | static void memory_region_read_accessor(void *opaque, |
241 | target_phys_addr_t addr, | |
242 | uint64_t *value, | |
243 | unsigned size, | |
244 | unsigned shift, | |
245 | uint64_t mask) | |
246 | { | |
247 | MemoryRegion *mr = opaque; | |
248 | uint64_t tmp; | |
249 | ||
250 | tmp = mr->ops->read(mr->opaque, addr, size); | |
251 | *value |= (tmp & mask) << shift; | |
252 | } | |
253 | ||
254 | static void memory_region_write_accessor(void *opaque, | |
255 | target_phys_addr_t addr, | |
256 | uint64_t *value, | |
257 | unsigned size, | |
258 | unsigned shift, | |
259 | uint64_t mask) | |
260 | { | |
261 | MemoryRegion *mr = opaque; | |
262 | uint64_t tmp; | |
263 | ||
264 | tmp = (*value >> shift) & mask; | |
265 | mr->ops->write(mr->opaque, addr, tmp, size); | |
266 | } | |
267 | ||
268 | static void access_with_adjusted_size(target_phys_addr_t addr, | |
269 | uint64_t *value, | |
270 | unsigned size, | |
271 | unsigned access_size_min, | |
272 | unsigned access_size_max, | |
273 | void (*access)(void *opaque, | |
274 | target_phys_addr_t addr, | |
275 | uint64_t *value, | |
276 | unsigned size, | |
277 | unsigned shift, | |
278 | uint64_t mask), | |
279 | void *opaque) | |
280 | { | |
281 | uint64_t access_mask; | |
282 | unsigned access_size; | |
283 | unsigned i; | |
284 | ||
285 | if (!access_size_min) { | |
286 | access_size_min = 1; | |
287 | } | |
288 | if (!access_size_max) { | |
289 | access_size_max = 4; | |
290 | } | |
291 | access_size = MAX(MIN(size, access_size_max), access_size_min); | |
292 | access_mask = -1ULL >> (64 - access_size * 8); | |
293 | for (i = 0; i < size; i += access_size) { | |
294 | /* FIXME: big-endian support */ | |
295 | access(opaque, addr + i, value, access_size, i * 8, access_mask); | |
296 | } | |
297 | } | |
298 | ||
16ef61c9 AK |
299 | static void memory_region_prepare_ram_addr(MemoryRegion *mr); |
300 | ||
cc31e6e7 AK |
301 | static void as_memory_range_add(AddressSpace *as, FlatRange *fr) |
302 | { | |
303 | ram_addr_t phys_offset, region_offset; | |
304 | ||
16ef61c9 AK |
305 | memory_region_prepare_ram_addr(fr->mr); |
306 | ||
cc31e6e7 AK |
307 | phys_offset = fr->mr->ram_addr; |
308 | region_offset = fr->offset_in_region; | |
309 | /* cpu_register_physical_memory_log() wants region_offset for | |
310 | * mmio, but prefers offseting phys_offset for RAM. Humour it. | |
311 | */ | |
312 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { | |
313 | phys_offset += region_offset; | |
314 | region_offset = 0; | |
315 | } | |
316 | ||
d0a9b5bc | 317 | if (!fr->readable) { |
b5fe14cc | 318 | phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD; |
d0a9b5bc AK |
319 | } |
320 | ||
fb1cd6f9 AK |
321 | if (fr->readonly) { |
322 | phys_offset |= IO_MEM_ROM; | |
323 | } | |
324 | ||
08dafab4 AK |
325 | cpu_register_physical_memory_log(int128_get64(fr->addr.start), |
326 | int128_get64(fr->addr.size), | |
cc31e6e7 AK |
327 | phys_offset, |
328 | region_offset, | |
329 | fr->dirty_log_mask); | |
330 | } | |
331 | ||
332 | static void as_memory_range_del(AddressSpace *as, FlatRange *fr) | |
333 | { | |
39b796f2 | 334 | if (fr->dirty_log_mask) { |
08dafab4 AK |
335 | Int128 end = addrrange_end(fr->addr); |
336 | cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start), | |
337 | int128_get64(end)); | |
39b796f2 | 338 | } |
08dafab4 AK |
339 | cpu_register_physical_memory(int128_get64(fr->addr.start), |
340 | int128_get64(fr->addr.size), | |
cc31e6e7 AK |
341 | IO_MEM_UNASSIGNED); |
342 | } | |
343 | ||
344 | static void as_memory_log_start(AddressSpace *as, FlatRange *fr) | |
345 | { | |
08dafab4 AK |
346 | cpu_physical_log_start(int128_get64(fr->addr.start), |
347 | int128_get64(fr->addr.size)); | |
cc31e6e7 AK |
348 | } |
349 | ||
350 | static void as_memory_log_stop(AddressSpace *as, FlatRange *fr) | |
351 | { | |
08dafab4 AK |
352 | cpu_physical_log_stop(int128_get64(fr->addr.start), |
353 | int128_get64(fr->addr.size)); | |
cc31e6e7 AK |
354 | } |
355 | ||
3e9d69e7 AK |
356 | static void as_memory_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) |
357 | { | |
358 | int r; | |
359 | ||
08dafab4 | 360 | assert(fd->match_data && int128_get64(fd->addr.size) == 4); |
3e9d69e7 | 361 | |
08dafab4 AK |
362 | r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start), |
363 | fd->data, true); | |
3e9d69e7 AK |
364 | if (r < 0) { |
365 | abort(); | |
366 | } | |
367 | } | |
368 | ||
369 | static void as_memory_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) | |
370 | { | |
371 | int r; | |
372 | ||
08dafab4 AK |
373 | r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start), |
374 | fd->data, false); | |
3e9d69e7 AK |
375 | if (r < 0) { |
376 | abort(); | |
377 | } | |
378 | } | |
379 | ||
cc31e6e7 AK |
380 | static const AddressSpaceOps address_space_ops_memory = { |
381 | .range_add = as_memory_range_add, | |
382 | .range_del = as_memory_range_del, | |
383 | .log_start = as_memory_log_start, | |
384 | .log_stop = as_memory_log_stop, | |
3e9d69e7 AK |
385 | .ioeventfd_add = as_memory_ioeventfd_add, |
386 | .ioeventfd_del = as_memory_ioeventfd_del, | |
cc31e6e7 AK |
387 | }; |
388 | ||
389 | static AddressSpace address_space_memory = { | |
390 | .ops = &address_space_ops_memory, | |
391 | }; | |
392 | ||
627a0e90 AK |
393 | static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset, |
394 | unsigned width, bool write) | |
395 | { | |
396 | const MemoryRegionPortio *mrp; | |
397 | ||
398 | for (mrp = mr->ops->old_portio; mrp->size; ++mrp) { | |
399 | if (offset >= mrp->offset && offset < mrp->offset + mrp->len | |
400 | && width == mrp->size | |
401 | && (write ? (bool)mrp->write : (bool)mrp->read)) { | |
402 | return mrp; | |
403 | } | |
404 | } | |
405 | return NULL; | |
406 | } | |
407 | ||
658b2224 AK |
408 | static void memory_region_iorange_read(IORange *iorange, |
409 | uint64_t offset, | |
410 | unsigned width, | |
411 | uint64_t *data) | |
412 | { | |
413 | MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); | |
414 | ||
627a0e90 AK |
415 | if (mr->ops->old_portio) { |
416 | const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false); | |
417 | ||
418 | *data = ((uint64_t)1 << (width * 8)) - 1; | |
419 | if (mrp) { | |
6bf9fd43 | 420 | *data = mrp->read(mr->opaque, offset + mr->offset); |
03808f58 JK |
421 | } else if (width == 2) { |
422 | mrp = find_portio(mr, offset, 1, false); | |
423 | assert(mrp); | |
424 | *data = mrp->read(mr->opaque, offset + mr->offset) | | |
425 | (mrp->read(mr->opaque, offset + mr->offset + 1) << 8); | |
627a0e90 AK |
426 | } |
427 | return; | |
428 | } | |
3a130f4e | 429 | *data = 0; |
6bf9fd43 | 430 | access_with_adjusted_size(offset + mr->offset, data, width, |
3a130f4e AK |
431 | mr->ops->impl.min_access_size, |
432 | mr->ops->impl.max_access_size, | |
433 | memory_region_read_accessor, mr); | |
658b2224 AK |
434 | } |
435 | ||
436 | static void memory_region_iorange_write(IORange *iorange, | |
437 | uint64_t offset, | |
438 | unsigned width, | |
439 | uint64_t data) | |
440 | { | |
441 | MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); | |
442 | ||
627a0e90 AK |
443 | if (mr->ops->old_portio) { |
444 | const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true); | |
445 | ||
446 | if (mrp) { | |
6bf9fd43 | 447 | mrp->write(mr->opaque, offset + mr->offset, data); |
03808f58 JK |
448 | } else if (width == 2) { |
449 | mrp = find_portio(mr, offset, 1, false); | |
450 | assert(mrp); | |
451 | mrp->write(mr->opaque, offset + mr->offset, data & 0xff); | |
452 | mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8); | |
627a0e90 AK |
453 | } |
454 | return; | |
455 | } | |
6bf9fd43 | 456 | access_with_adjusted_size(offset + mr->offset, &data, width, |
3a130f4e AK |
457 | mr->ops->impl.min_access_size, |
458 | mr->ops->impl.max_access_size, | |
459 | memory_region_write_accessor, mr); | |
658b2224 AK |
460 | } |
461 | ||
462 | static const IORangeOps memory_region_iorange_ops = { | |
463 | .read = memory_region_iorange_read, | |
464 | .write = memory_region_iorange_write, | |
465 | }; | |
466 | ||
467 | static void as_io_range_add(AddressSpace *as, FlatRange *fr) | |
468 | { | |
469 | iorange_init(&fr->mr->iorange, &memory_region_iorange_ops, | |
08dafab4 | 470 | int128_get64(fr->addr.start), int128_get64(fr->addr.size)); |
658b2224 AK |
471 | ioport_register(&fr->mr->iorange); |
472 | } | |
473 | ||
474 | static void as_io_range_del(AddressSpace *as, FlatRange *fr) | |
475 | { | |
08dafab4 AK |
476 | isa_unassign_ioport(int128_get64(fr->addr.start), |
477 | int128_get64(fr->addr.size)); | |
658b2224 AK |
478 | } |
479 | ||
3e9d69e7 AK |
480 | static void as_io_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) |
481 | { | |
482 | int r; | |
483 | ||
08dafab4 | 484 | assert(fd->match_data && int128_get64(fd->addr.size) == 2); |
3e9d69e7 | 485 | |
08dafab4 AK |
486 | r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start), |
487 | fd->data, true); | |
3e9d69e7 AK |
488 | if (r < 0) { |
489 | abort(); | |
490 | } | |
491 | } | |
492 | ||
493 | static void as_io_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) | |
494 | { | |
495 | int r; | |
496 | ||
08dafab4 AK |
497 | r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start), |
498 | fd->data, false); | |
3e9d69e7 AK |
499 | if (r < 0) { |
500 | abort(); | |
501 | } | |
502 | } | |
503 | ||
658b2224 AK |
504 | static const AddressSpaceOps address_space_ops_io = { |
505 | .range_add = as_io_range_add, | |
506 | .range_del = as_io_range_del, | |
3e9d69e7 AK |
507 | .ioeventfd_add = as_io_ioeventfd_add, |
508 | .ioeventfd_del = as_io_ioeventfd_del, | |
658b2224 AK |
509 | }; |
510 | ||
511 | static AddressSpace address_space_io = { | |
512 | .ops = &address_space_ops_io, | |
513 | }; | |
514 | ||
093bc2cd AK |
515 | /* Render a memory region into the global view. Ranges in @view obscure |
516 | * ranges in @mr. | |
517 | */ | |
518 | static void render_memory_region(FlatView *view, | |
519 | MemoryRegion *mr, | |
08dafab4 | 520 | Int128 base, |
fb1cd6f9 AK |
521 | AddrRange clip, |
522 | bool readonly) | |
093bc2cd AK |
523 | { |
524 | MemoryRegion *subregion; | |
525 | unsigned i; | |
526 | target_phys_addr_t offset_in_region; | |
08dafab4 AK |
527 | Int128 remain; |
528 | Int128 now; | |
093bc2cd AK |
529 | FlatRange fr; |
530 | AddrRange tmp; | |
531 | ||
6bba19ba AK |
532 | if (!mr->enabled) { |
533 | return; | |
534 | } | |
535 | ||
08dafab4 | 536 | int128_addto(&base, int128_make64(mr->addr)); |
fb1cd6f9 | 537 | readonly |= mr->readonly; |
093bc2cd AK |
538 | |
539 | tmp = addrrange_make(base, mr->size); | |
540 | ||
541 | if (!addrrange_intersects(tmp, clip)) { | |
542 | return; | |
543 | } | |
544 | ||
545 | clip = addrrange_intersection(tmp, clip); | |
546 | ||
547 | if (mr->alias) { | |
08dafab4 AK |
548 | int128_subfrom(&base, int128_make64(mr->alias->addr)); |
549 | int128_subfrom(&base, int128_make64(mr->alias_offset)); | |
fb1cd6f9 | 550 | render_memory_region(view, mr->alias, base, clip, readonly); |
093bc2cd AK |
551 | return; |
552 | } | |
553 | ||
554 | /* Render subregions in priority order. */ | |
555 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
fb1cd6f9 | 556 | render_memory_region(view, subregion, base, clip, readonly); |
093bc2cd AK |
557 | } |
558 | ||
14a3c10a | 559 | if (!mr->terminates) { |
093bc2cd AK |
560 | return; |
561 | } | |
562 | ||
08dafab4 | 563 | offset_in_region = int128_get64(int128_sub(clip.start, base)); |
093bc2cd AK |
564 | base = clip.start; |
565 | remain = clip.size; | |
566 | ||
567 | /* Render the region itself into any gaps left by the current view. */ | |
08dafab4 AK |
568 | for (i = 0; i < view->nr && int128_nz(remain); ++i) { |
569 | if (int128_ge(base, addrrange_end(view->ranges[i].addr))) { | |
093bc2cd AK |
570 | continue; |
571 | } | |
08dafab4 AK |
572 | if (int128_lt(base, view->ranges[i].addr.start)) { |
573 | now = int128_min(remain, | |
574 | int128_sub(view->ranges[i].addr.start, base)); | |
093bc2cd AK |
575 | fr.mr = mr; |
576 | fr.offset_in_region = offset_in_region; | |
577 | fr.addr = addrrange_make(base, now); | |
5a583347 | 578 | fr.dirty_log_mask = mr->dirty_log_mask; |
d0a9b5bc | 579 | fr.readable = mr->readable; |
fb1cd6f9 | 580 | fr.readonly = readonly; |
093bc2cd AK |
581 | flatview_insert(view, i, &fr); |
582 | ++i; | |
08dafab4 AK |
583 | int128_addto(&base, now); |
584 | offset_in_region += int128_get64(now); | |
585 | int128_subfrom(&remain, now); | |
093bc2cd | 586 | } |
08dafab4 AK |
587 | if (int128_eq(base, view->ranges[i].addr.start)) { |
588 | now = int128_min(remain, view->ranges[i].addr.size); | |
589 | int128_addto(&base, now); | |
590 | offset_in_region += int128_get64(now); | |
591 | int128_subfrom(&remain, now); | |
093bc2cd AK |
592 | } |
593 | } | |
08dafab4 | 594 | if (int128_nz(remain)) { |
093bc2cd AK |
595 | fr.mr = mr; |
596 | fr.offset_in_region = offset_in_region; | |
597 | fr.addr = addrrange_make(base, remain); | |
5a583347 | 598 | fr.dirty_log_mask = mr->dirty_log_mask; |
d0a9b5bc | 599 | fr.readable = mr->readable; |
fb1cd6f9 | 600 | fr.readonly = readonly; |
093bc2cd AK |
601 | flatview_insert(view, i, &fr); |
602 | } | |
603 | } | |
604 | ||
605 | /* Render a memory topology into a list of disjoint absolute ranges. */ | |
606 | static FlatView generate_memory_topology(MemoryRegion *mr) | |
607 | { | |
608 | FlatView view; | |
609 | ||
610 | flatview_init(&view); | |
611 | ||
08dafab4 AK |
612 | render_memory_region(&view, mr, int128_zero(), |
613 | addrrange_make(int128_zero(), int128_2_64()), false); | |
3d8e6bf9 | 614 | flatview_simplify(&view); |
093bc2cd AK |
615 | |
616 | return view; | |
617 | } | |
618 | ||
3e9d69e7 AK |
619 | static void address_space_add_del_ioeventfds(AddressSpace *as, |
620 | MemoryRegionIoeventfd *fds_new, | |
621 | unsigned fds_new_nb, | |
622 | MemoryRegionIoeventfd *fds_old, | |
623 | unsigned fds_old_nb) | |
624 | { | |
625 | unsigned iold, inew; | |
626 | ||
627 | /* Generate a symmetric difference of the old and new fd sets, adding | |
628 | * and deleting as necessary. | |
629 | */ | |
630 | ||
631 | iold = inew = 0; | |
632 | while (iold < fds_old_nb || inew < fds_new_nb) { | |
633 | if (iold < fds_old_nb | |
634 | && (inew == fds_new_nb | |
635 | || memory_region_ioeventfd_before(fds_old[iold], | |
636 | fds_new[inew]))) { | |
637 | as->ops->ioeventfd_del(as, &fds_old[iold]); | |
638 | ++iold; | |
639 | } else if (inew < fds_new_nb | |
640 | && (iold == fds_old_nb | |
641 | || memory_region_ioeventfd_before(fds_new[inew], | |
642 | fds_old[iold]))) { | |
643 | as->ops->ioeventfd_add(as, &fds_new[inew]); | |
644 | ++inew; | |
645 | } else { | |
646 | ++iold; | |
647 | ++inew; | |
648 | } | |
649 | } | |
650 | } | |
651 | ||
652 | static void address_space_update_ioeventfds(AddressSpace *as) | |
653 | { | |
654 | FlatRange *fr; | |
655 | unsigned ioeventfd_nb = 0; | |
656 | MemoryRegionIoeventfd *ioeventfds = NULL; | |
657 | AddrRange tmp; | |
658 | unsigned i; | |
659 | ||
660 | FOR_EACH_FLAT_RANGE(fr, &as->current_map) { | |
661 | for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { | |
662 | tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, | |
08dafab4 AK |
663 | int128_sub(fr->addr.start, |
664 | int128_make64(fr->offset_in_region))); | |
3e9d69e7 AK |
665 | if (addrrange_intersects(fr->addr, tmp)) { |
666 | ++ioeventfd_nb; | |
7267c094 | 667 | ioeventfds = g_realloc(ioeventfds, |
3e9d69e7 AK |
668 | ioeventfd_nb * sizeof(*ioeventfds)); |
669 | ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; | |
670 | ioeventfds[ioeventfd_nb-1].addr = tmp; | |
671 | } | |
672 | } | |
673 | } | |
674 | ||
675 | address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, | |
676 | as->ioeventfds, as->ioeventfd_nb); | |
677 | ||
7267c094 | 678 | g_free(as->ioeventfds); |
3e9d69e7 AK |
679 | as->ioeventfds = ioeventfds; |
680 | as->ioeventfd_nb = ioeventfd_nb; | |
681 | } | |
682 | ||
b8af1afb AK |
683 | static void address_space_update_topology_pass(AddressSpace *as, |
684 | FlatView old_view, | |
685 | FlatView new_view, | |
686 | bool adding) | |
093bc2cd | 687 | { |
093bc2cd AK |
688 | unsigned iold, inew; |
689 | FlatRange *frold, *frnew; | |
093bc2cd AK |
690 | |
691 | /* Generate a symmetric difference of the old and new memory maps. | |
692 | * Kill ranges in the old map, and instantiate ranges in the new map. | |
693 | */ | |
694 | iold = inew = 0; | |
695 | while (iold < old_view.nr || inew < new_view.nr) { | |
696 | if (iold < old_view.nr) { | |
697 | frold = &old_view.ranges[iold]; | |
698 | } else { | |
699 | frold = NULL; | |
700 | } | |
701 | if (inew < new_view.nr) { | |
702 | frnew = &new_view.ranges[inew]; | |
703 | } else { | |
704 | frnew = NULL; | |
705 | } | |
706 | ||
707 | if (frold | |
708 | && (!frnew | |
08dafab4 AK |
709 | || int128_lt(frold->addr.start, frnew->addr.start) |
710 | || (int128_eq(frold->addr.start, frnew->addr.start) | |
093bc2cd AK |
711 | && !flatrange_equal(frold, frnew)))) { |
712 | /* In old, but (not in new, or in new but attributes changed). */ | |
713 | ||
b8af1afb AK |
714 | if (!adding) { |
715 | as->ops->range_del(as, frold); | |
716 | } | |
717 | ||
093bc2cd AK |
718 | ++iold; |
719 | } else if (frold && frnew && flatrange_equal(frold, frnew)) { | |
720 | /* In both (logging may have changed) */ | |
721 | ||
b8af1afb AK |
722 | if (adding) { |
723 | if (frold->dirty_log_mask && !frnew->dirty_log_mask) { | |
724 | as->ops->log_stop(as, frnew); | |
725 | } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) { | |
726 | as->ops->log_start(as, frnew); | |
727 | } | |
5a583347 AK |
728 | } |
729 | ||
093bc2cd AK |
730 | ++iold; |
731 | ++inew; | |
093bc2cd AK |
732 | } else { |
733 | /* In new */ | |
734 | ||
b8af1afb AK |
735 | if (adding) { |
736 | as->ops->range_add(as, frnew); | |
737 | } | |
738 | ||
093bc2cd AK |
739 | ++inew; |
740 | } | |
741 | } | |
b8af1afb AK |
742 | } |
743 | ||
744 | ||
745 | static void address_space_update_topology(AddressSpace *as) | |
746 | { | |
747 | FlatView old_view = as->current_map; | |
748 | FlatView new_view = generate_memory_topology(as->root); | |
749 | ||
750 | address_space_update_topology_pass(as, old_view, new_view, false); | |
751 | address_space_update_topology_pass(as, old_view, new_view, true); | |
752 | ||
cc31e6e7 | 753 | as->current_map = new_view; |
093bc2cd | 754 | flatview_destroy(&old_view); |
3e9d69e7 | 755 | address_space_update_ioeventfds(as); |
093bc2cd AK |
756 | } |
757 | ||
6bba19ba | 758 | static void memory_region_update_topology(MemoryRegion *mr) |
cc31e6e7 | 759 | { |
4ef4db86 | 760 | if (memory_region_transaction_depth) { |
e87c099f | 761 | memory_region_update_pending |= !mr || mr->enabled; |
4ef4db86 AK |
762 | return; |
763 | } | |
764 | ||
6bba19ba AK |
765 | if (mr && !mr->enabled) { |
766 | return; | |
767 | } | |
768 | ||
658b2224 AK |
769 | if (address_space_memory.root) { |
770 | address_space_update_topology(&address_space_memory); | |
771 | } | |
772 | if (address_space_io.root) { | |
773 | address_space_update_topology(&address_space_io); | |
774 | } | |
e87c099f AK |
775 | |
776 | memory_region_update_pending = false; | |
cc31e6e7 AK |
777 | } |
778 | ||
4ef4db86 AK |
779 | void memory_region_transaction_begin(void) |
780 | { | |
781 | ++memory_region_transaction_depth; | |
782 | } | |
783 | ||
784 | void memory_region_transaction_commit(void) | |
785 | { | |
786 | assert(memory_region_transaction_depth); | |
787 | --memory_region_transaction_depth; | |
e87c099f AK |
788 | if (!memory_region_transaction_depth && memory_region_update_pending) { |
789 | memory_region_update_topology(NULL); | |
790 | } | |
4ef4db86 AK |
791 | } |
792 | ||
545e92e0 AK |
793 | static void memory_region_destructor_none(MemoryRegion *mr) |
794 | { | |
795 | } | |
796 | ||
797 | static void memory_region_destructor_ram(MemoryRegion *mr) | |
798 | { | |
799 | qemu_ram_free(mr->ram_addr); | |
800 | } | |
801 | ||
802 | static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr) | |
803 | { | |
804 | qemu_ram_free_from_ptr(mr->ram_addr); | |
805 | } | |
806 | ||
807 | static void memory_region_destructor_iomem(MemoryRegion *mr) | |
808 | { | |
809 | cpu_unregister_io_memory(mr->ram_addr); | |
810 | } | |
811 | ||
d0a9b5bc AK |
812 | static void memory_region_destructor_rom_device(MemoryRegion *mr) |
813 | { | |
814 | qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK); | |
815 | cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD)); | |
816 | } | |
817 | ||
093bc2cd AK |
818 | void memory_region_init(MemoryRegion *mr, |
819 | const char *name, | |
820 | uint64_t size) | |
821 | { | |
822 | mr->ops = NULL; | |
823 | mr->parent = NULL; | |
08dafab4 AK |
824 | mr->size = int128_make64(size); |
825 | if (size == UINT64_MAX) { | |
826 | mr->size = int128_2_64(); | |
827 | } | |
093bc2cd AK |
828 | mr->addr = 0; |
829 | mr->offset = 0; | |
6bba19ba | 830 | mr->enabled = true; |
14a3c10a | 831 | mr->terminates = false; |
d0a9b5bc | 832 | mr->readable = true; |
fb1cd6f9 | 833 | mr->readonly = false; |
545e92e0 | 834 | mr->destructor = memory_region_destructor_none; |
093bc2cd AK |
835 | mr->priority = 0; |
836 | mr->may_overlap = false; | |
837 | mr->alias = NULL; | |
838 | QTAILQ_INIT(&mr->subregions); | |
839 | memset(&mr->subregions_link, 0, sizeof mr->subregions_link); | |
840 | QTAILQ_INIT(&mr->coalesced); | |
7267c094 | 841 | mr->name = g_strdup(name); |
5a583347 | 842 | mr->dirty_log_mask = 0; |
3e9d69e7 AK |
843 | mr->ioeventfd_nb = 0; |
844 | mr->ioeventfds = NULL; | |
093bc2cd AK |
845 | } |
846 | ||
847 | static bool memory_region_access_valid(MemoryRegion *mr, | |
848 | target_phys_addr_t addr, | |
897fa7cf AK |
849 | unsigned size, |
850 | bool is_write) | |
093bc2cd | 851 | { |
897fa7cf AK |
852 | if (mr->ops->valid.accepts |
853 | && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) { | |
854 | return false; | |
855 | } | |
856 | ||
093bc2cd AK |
857 | if (!mr->ops->valid.unaligned && (addr & (size - 1))) { |
858 | return false; | |
859 | } | |
860 | ||
861 | /* Treat zero as compatibility all valid */ | |
862 | if (!mr->ops->valid.max_access_size) { | |
863 | return true; | |
864 | } | |
865 | ||
866 | if (size > mr->ops->valid.max_access_size | |
867 | || size < mr->ops->valid.min_access_size) { | |
868 | return false; | |
869 | } | |
870 | return true; | |
871 | } | |
872 | ||
873 | static uint32_t memory_region_read_thunk_n(void *_mr, | |
874 | target_phys_addr_t addr, | |
875 | unsigned size) | |
876 | { | |
877 | MemoryRegion *mr = _mr; | |
164a4dcd | 878 | uint64_t data = 0; |
093bc2cd | 879 | |
897fa7cf | 880 | if (!memory_region_access_valid(mr, addr, size, false)) { |
093bc2cd AK |
881 | return -1U; /* FIXME: better signalling */ |
882 | } | |
883 | ||
74901c3b AK |
884 | if (!mr->ops->read) { |
885 | return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr); | |
886 | } | |
887 | ||
093bc2cd | 888 | /* FIXME: support unaligned access */ |
164a4dcd AK |
889 | access_with_adjusted_size(addr + mr->offset, &data, size, |
890 | mr->ops->impl.min_access_size, | |
891 | mr->ops->impl.max_access_size, | |
892 | memory_region_read_accessor, mr); | |
093bc2cd AK |
893 | |
894 | return data; | |
895 | } | |
896 | ||
897 | static void memory_region_write_thunk_n(void *_mr, | |
898 | target_phys_addr_t addr, | |
899 | unsigned size, | |
900 | uint64_t data) | |
901 | { | |
902 | MemoryRegion *mr = _mr; | |
093bc2cd | 903 | |
897fa7cf | 904 | if (!memory_region_access_valid(mr, addr, size, true)) { |
093bc2cd AK |
905 | return; /* FIXME: better signalling */ |
906 | } | |
907 | ||
74901c3b AK |
908 | if (!mr->ops->write) { |
909 | mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data); | |
910 | return; | |
911 | } | |
912 | ||
093bc2cd | 913 | /* FIXME: support unaligned access */ |
164a4dcd AK |
914 | access_with_adjusted_size(addr + mr->offset, &data, size, |
915 | mr->ops->impl.min_access_size, | |
916 | mr->ops->impl.max_access_size, | |
917 | memory_region_write_accessor, mr); | |
093bc2cd AK |
918 | } |
919 | ||
920 | static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr) | |
921 | { | |
922 | return memory_region_read_thunk_n(mr, addr, 1); | |
923 | } | |
924 | ||
925 | static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr) | |
926 | { | |
927 | return memory_region_read_thunk_n(mr, addr, 2); | |
928 | } | |
929 | ||
930 | static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr) | |
931 | { | |
932 | return memory_region_read_thunk_n(mr, addr, 4); | |
933 | } | |
934 | ||
935 | static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr, | |
936 | uint32_t data) | |
937 | { | |
938 | memory_region_write_thunk_n(mr, addr, 1, data); | |
939 | } | |
940 | ||
941 | static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr, | |
942 | uint32_t data) | |
943 | { | |
944 | memory_region_write_thunk_n(mr, addr, 2, data); | |
945 | } | |
946 | ||
947 | static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr, | |
948 | uint32_t data) | |
949 | { | |
950 | memory_region_write_thunk_n(mr, addr, 4, data); | |
951 | } | |
952 | ||
953 | static CPUReadMemoryFunc * const memory_region_read_thunk[] = { | |
954 | memory_region_read_thunk_b, | |
955 | memory_region_read_thunk_w, | |
956 | memory_region_read_thunk_l, | |
957 | }; | |
958 | ||
959 | static CPUWriteMemoryFunc * const memory_region_write_thunk[] = { | |
960 | memory_region_write_thunk_b, | |
961 | memory_region_write_thunk_w, | |
962 | memory_region_write_thunk_l, | |
963 | }; | |
964 | ||
16ef61c9 AK |
965 | static void memory_region_prepare_ram_addr(MemoryRegion *mr) |
966 | { | |
967 | if (mr->backend_registered) { | |
968 | return; | |
969 | } | |
970 | ||
545e92e0 | 971 | mr->destructor = memory_region_destructor_iomem; |
16ef61c9 AK |
972 | mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk, |
973 | memory_region_write_thunk, | |
974 | mr, | |
975 | mr->ops->endianness); | |
976 | mr->backend_registered = true; | |
977 | } | |
978 | ||
093bc2cd AK |
979 | void memory_region_init_io(MemoryRegion *mr, |
980 | const MemoryRegionOps *ops, | |
981 | void *opaque, | |
982 | const char *name, | |
983 | uint64_t size) | |
984 | { | |
985 | memory_region_init(mr, name, size); | |
986 | mr->ops = ops; | |
987 | mr->opaque = opaque; | |
14a3c10a | 988 | mr->terminates = true; |
16ef61c9 | 989 | mr->backend_registered = false; |
093bc2cd AK |
990 | } |
991 | ||
992 | void memory_region_init_ram(MemoryRegion *mr, | |
993 | DeviceState *dev, | |
994 | const char *name, | |
995 | uint64_t size) | |
996 | { | |
997 | memory_region_init(mr, name, size); | |
14a3c10a | 998 | mr->terminates = true; |
545e92e0 | 999 | mr->destructor = memory_region_destructor_ram; |
093bc2cd | 1000 | mr->ram_addr = qemu_ram_alloc(dev, name, size); |
16ef61c9 | 1001 | mr->backend_registered = true; |
093bc2cd AK |
1002 | } |
1003 | ||
1004 | void memory_region_init_ram_ptr(MemoryRegion *mr, | |
1005 | DeviceState *dev, | |
1006 | const char *name, | |
1007 | uint64_t size, | |
1008 | void *ptr) | |
1009 | { | |
1010 | memory_region_init(mr, name, size); | |
14a3c10a | 1011 | mr->terminates = true; |
545e92e0 | 1012 | mr->destructor = memory_region_destructor_ram_from_ptr; |
093bc2cd | 1013 | mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr); |
16ef61c9 | 1014 | mr->backend_registered = true; |
093bc2cd AK |
1015 | } |
1016 | ||
1017 | void memory_region_init_alias(MemoryRegion *mr, | |
1018 | const char *name, | |
1019 | MemoryRegion *orig, | |
1020 | target_phys_addr_t offset, | |
1021 | uint64_t size) | |
1022 | { | |
1023 | memory_region_init(mr, name, size); | |
1024 | mr->alias = orig; | |
1025 | mr->alias_offset = offset; | |
1026 | } | |
1027 | ||
d0a9b5bc AK |
1028 | void memory_region_init_rom_device(MemoryRegion *mr, |
1029 | const MemoryRegionOps *ops, | |
75f5941c | 1030 | void *opaque, |
d0a9b5bc AK |
1031 | DeviceState *dev, |
1032 | const char *name, | |
1033 | uint64_t size) | |
1034 | { | |
1035 | memory_region_init(mr, name, size); | |
7bc2b9cd | 1036 | mr->ops = ops; |
75f5941c | 1037 | mr->opaque = opaque; |
d0a9b5bc AK |
1038 | mr->terminates = true; |
1039 | mr->destructor = memory_region_destructor_rom_device; | |
1040 | mr->ram_addr = qemu_ram_alloc(dev, name, size); | |
1041 | mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk, | |
1042 | memory_region_write_thunk, | |
1043 | mr, | |
1044 | mr->ops->endianness); | |
1045 | mr->ram_addr |= IO_MEM_ROMD; | |
1046 | mr->backend_registered = true; | |
1047 | } | |
1048 | ||
093bc2cd AK |
1049 | void memory_region_destroy(MemoryRegion *mr) |
1050 | { | |
1051 | assert(QTAILQ_EMPTY(&mr->subregions)); | |
545e92e0 | 1052 | mr->destructor(mr); |
093bc2cd | 1053 | memory_region_clear_coalescing(mr); |
7267c094 AL |
1054 | g_free((char *)mr->name); |
1055 | g_free(mr->ioeventfds); | |
093bc2cd AK |
1056 | } |
1057 | ||
1058 | uint64_t memory_region_size(MemoryRegion *mr) | |
1059 | { | |
08dafab4 AK |
1060 | if (int128_eq(mr->size, int128_2_64())) { |
1061 | return UINT64_MAX; | |
1062 | } | |
1063 | return int128_get64(mr->size); | |
093bc2cd AK |
1064 | } |
1065 | ||
1066 | void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset) | |
1067 | { | |
1068 | mr->offset = offset; | |
1069 | } | |
1070 | ||
1071 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) | |
1072 | { | |
5a583347 AK |
1073 | uint8_t mask = 1 << client; |
1074 | ||
1075 | mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); | |
6bba19ba | 1076 | memory_region_update_topology(mr); |
093bc2cd AK |
1077 | } |
1078 | ||
1079 | bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr, | |
1080 | unsigned client) | |
1081 | { | |
14a3c10a | 1082 | assert(mr->terminates); |
5a583347 | 1083 | return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client); |
093bc2cd AK |
1084 | } |
1085 | ||
1086 | void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr) | |
1087 | { | |
14a3c10a | 1088 | assert(mr->terminates); |
5a583347 | 1089 | return cpu_physical_memory_set_dirty(mr->ram_addr + addr); |
093bc2cd AK |
1090 | } |
1091 | ||
1092 | void memory_region_sync_dirty_bitmap(MemoryRegion *mr) | |
1093 | { | |
5a583347 AK |
1094 | FlatRange *fr; |
1095 | ||
cc31e6e7 | 1096 | FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { |
5a583347 | 1097 | if (fr->mr == mr) { |
08dafab4 AK |
1098 | cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start), |
1099 | int128_get64(addrrange_end(fr->addr))); | |
5a583347 AK |
1100 | } |
1101 | } | |
093bc2cd AK |
1102 | } |
1103 | ||
1104 | void memory_region_set_readonly(MemoryRegion *mr, bool readonly) | |
1105 | { | |
fb1cd6f9 AK |
1106 | if (mr->readonly != readonly) { |
1107 | mr->readonly = readonly; | |
6bba19ba | 1108 | memory_region_update_topology(mr); |
fb1cd6f9 | 1109 | } |
093bc2cd AK |
1110 | } |
1111 | ||
d0a9b5bc AK |
1112 | void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable) |
1113 | { | |
1114 | if (mr->readable != readable) { | |
1115 | mr->readable = readable; | |
6bba19ba | 1116 | memory_region_update_topology(mr); |
d0a9b5bc AK |
1117 | } |
1118 | } | |
1119 | ||
093bc2cd AK |
1120 | void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr, |
1121 | target_phys_addr_t size, unsigned client) | |
1122 | { | |
14a3c10a | 1123 | assert(mr->terminates); |
5a583347 AK |
1124 | cpu_physical_memory_reset_dirty(mr->ram_addr + addr, |
1125 | mr->ram_addr + addr + size, | |
1126 | 1 << client); | |
093bc2cd AK |
1127 | } |
1128 | ||
1129 | void *memory_region_get_ram_ptr(MemoryRegion *mr) | |
1130 | { | |
1131 | if (mr->alias) { | |
1132 | return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset; | |
1133 | } | |
1134 | ||
14a3c10a | 1135 | assert(mr->terminates); |
093bc2cd | 1136 | |
021d26d1 | 1137 | return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK); |
093bc2cd AK |
1138 | } |
1139 | ||
1140 | static void memory_region_update_coalesced_range(MemoryRegion *mr) | |
1141 | { | |
1142 | FlatRange *fr; | |
1143 | CoalescedMemoryRange *cmr; | |
1144 | AddrRange tmp; | |
1145 | ||
cc31e6e7 | 1146 | FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { |
093bc2cd | 1147 | if (fr->mr == mr) { |
08dafab4 AK |
1148 | qemu_unregister_coalesced_mmio(int128_get64(fr->addr.start), |
1149 | int128_get64(fr->addr.size)); | |
093bc2cd AK |
1150 | QTAILQ_FOREACH(cmr, &mr->coalesced, link) { |
1151 | tmp = addrrange_shift(cmr->addr, | |
08dafab4 AK |
1152 | int128_sub(fr->addr.start, |
1153 | int128_make64(fr->offset_in_region))); | |
093bc2cd AK |
1154 | if (!addrrange_intersects(tmp, fr->addr)) { |
1155 | continue; | |
1156 | } | |
1157 | tmp = addrrange_intersection(tmp, fr->addr); | |
08dafab4 AK |
1158 | qemu_register_coalesced_mmio(int128_get64(tmp.start), |
1159 | int128_get64(tmp.size)); | |
093bc2cd AK |
1160 | } |
1161 | } | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | void memory_region_set_coalescing(MemoryRegion *mr) | |
1166 | { | |
1167 | memory_region_clear_coalescing(mr); | |
08dafab4 | 1168 | memory_region_add_coalescing(mr, 0, int128_get64(mr->size)); |
093bc2cd AK |
1169 | } |
1170 | ||
1171 | void memory_region_add_coalescing(MemoryRegion *mr, | |
1172 | target_phys_addr_t offset, | |
1173 | uint64_t size) | |
1174 | { | |
7267c094 | 1175 | CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr)); |
093bc2cd | 1176 | |
08dafab4 | 1177 | cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size)); |
093bc2cd AK |
1178 | QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); |
1179 | memory_region_update_coalesced_range(mr); | |
1180 | } | |
1181 | ||
1182 | void memory_region_clear_coalescing(MemoryRegion *mr) | |
1183 | { | |
1184 | CoalescedMemoryRange *cmr; | |
1185 | ||
1186 | while (!QTAILQ_EMPTY(&mr->coalesced)) { | |
1187 | cmr = QTAILQ_FIRST(&mr->coalesced); | |
1188 | QTAILQ_REMOVE(&mr->coalesced, cmr, link); | |
7267c094 | 1189 | g_free(cmr); |
093bc2cd AK |
1190 | } |
1191 | memory_region_update_coalesced_range(mr); | |
1192 | } | |
1193 | ||
3e9d69e7 AK |
1194 | void memory_region_add_eventfd(MemoryRegion *mr, |
1195 | target_phys_addr_t addr, | |
1196 | unsigned size, | |
1197 | bool match_data, | |
1198 | uint64_t data, | |
1199 | int fd) | |
1200 | { | |
1201 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
1202 | .addr.start = int128_make64(addr), |
1203 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
1204 | .match_data = match_data, |
1205 | .data = data, | |
1206 | .fd = fd, | |
1207 | }; | |
1208 | unsigned i; | |
1209 | ||
1210 | for (i = 0; i < mr->ioeventfd_nb; ++i) { | |
1211 | if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) { | |
1212 | break; | |
1213 | } | |
1214 | } | |
1215 | ++mr->ioeventfd_nb; | |
7267c094 | 1216 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 AK |
1217 | sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); |
1218 | memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], | |
1219 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); | |
1220 | mr->ioeventfds[i] = mrfd; | |
6bba19ba | 1221 | memory_region_update_topology(mr); |
3e9d69e7 AK |
1222 | } |
1223 | ||
1224 | void memory_region_del_eventfd(MemoryRegion *mr, | |
1225 | target_phys_addr_t addr, | |
1226 | unsigned size, | |
1227 | bool match_data, | |
1228 | uint64_t data, | |
1229 | int fd) | |
1230 | { | |
1231 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
1232 | .addr.start = int128_make64(addr), |
1233 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
1234 | .match_data = match_data, |
1235 | .data = data, | |
1236 | .fd = fd, | |
1237 | }; | |
1238 | unsigned i; | |
1239 | ||
1240 | for (i = 0; i < mr->ioeventfd_nb; ++i) { | |
1241 | if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) { | |
1242 | break; | |
1243 | } | |
1244 | } | |
1245 | assert(i != mr->ioeventfd_nb); | |
1246 | memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], | |
1247 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); | |
1248 | --mr->ioeventfd_nb; | |
7267c094 | 1249 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 | 1250 | sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); |
6bba19ba | 1251 | memory_region_update_topology(mr); |
3e9d69e7 AK |
1252 | } |
1253 | ||
093bc2cd AK |
1254 | static void memory_region_add_subregion_common(MemoryRegion *mr, |
1255 | target_phys_addr_t offset, | |
1256 | MemoryRegion *subregion) | |
1257 | { | |
1258 | MemoryRegion *other; | |
1259 | ||
1260 | assert(!subregion->parent); | |
1261 | subregion->parent = mr; | |
1262 | subregion->addr = offset; | |
1263 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { | |
1264 | if (subregion->may_overlap || other->may_overlap) { | |
1265 | continue; | |
1266 | } | |
08dafab4 AK |
1267 | if (int128_gt(int128_make64(offset), |
1268 | int128_add(int128_make64(other->addr), other->size)) | |
1269 | || int128_le(int128_add(int128_make64(offset), subregion->size), | |
1270 | int128_make64(other->addr))) { | |
093bc2cd AK |
1271 | continue; |
1272 | } | |
a5e1cbc8 | 1273 | #if 0 |
860329b2 MW |
1274 | printf("warning: subregion collision %llx/%llx (%s) " |
1275 | "vs %llx/%llx (%s)\n", | |
093bc2cd | 1276 | (unsigned long long)offset, |
08dafab4 | 1277 | (unsigned long long)int128_get64(subregion->size), |
860329b2 MW |
1278 | subregion->name, |
1279 | (unsigned long long)other->addr, | |
08dafab4 | 1280 | (unsigned long long)int128_get64(other->size), |
860329b2 | 1281 | other->name); |
a5e1cbc8 | 1282 | #endif |
093bc2cd AK |
1283 | } |
1284 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { | |
1285 | if (subregion->priority >= other->priority) { | |
1286 | QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); | |
1287 | goto done; | |
1288 | } | |
1289 | } | |
1290 | QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); | |
1291 | done: | |
6bba19ba | 1292 | memory_region_update_topology(mr); |
093bc2cd AK |
1293 | } |
1294 | ||
1295 | ||
1296 | void memory_region_add_subregion(MemoryRegion *mr, | |
1297 | target_phys_addr_t offset, | |
1298 | MemoryRegion *subregion) | |
1299 | { | |
1300 | subregion->may_overlap = false; | |
1301 | subregion->priority = 0; | |
1302 | memory_region_add_subregion_common(mr, offset, subregion); | |
1303 | } | |
1304 | ||
1305 | void memory_region_add_subregion_overlap(MemoryRegion *mr, | |
1306 | target_phys_addr_t offset, | |
1307 | MemoryRegion *subregion, | |
1308 | unsigned priority) | |
1309 | { | |
1310 | subregion->may_overlap = true; | |
1311 | subregion->priority = priority; | |
1312 | memory_region_add_subregion_common(mr, offset, subregion); | |
1313 | } | |
1314 | ||
1315 | void memory_region_del_subregion(MemoryRegion *mr, | |
1316 | MemoryRegion *subregion) | |
1317 | { | |
1318 | assert(subregion->parent == mr); | |
1319 | subregion->parent = NULL; | |
1320 | QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); | |
6bba19ba AK |
1321 | memory_region_update_topology(mr); |
1322 | } | |
1323 | ||
1324 | void memory_region_set_enabled(MemoryRegion *mr, bool enabled) | |
1325 | { | |
1326 | if (enabled == mr->enabled) { | |
1327 | return; | |
1328 | } | |
1329 | mr->enabled = enabled; | |
1330 | memory_region_update_topology(NULL); | |
093bc2cd | 1331 | } |
1c0ffa58 | 1332 | |
2282e1af AK |
1333 | void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr) |
1334 | { | |
1335 | MemoryRegion *parent = mr->parent; | |
1336 | unsigned priority = mr->priority; | |
1337 | bool may_overlap = mr->may_overlap; | |
1338 | ||
1339 | if (addr == mr->addr || !parent) { | |
1340 | mr->addr = addr; | |
1341 | return; | |
1342 | } | |
1343 | ||
1344 | memory_region_transaction_begin(); | |
1345 | memory_region_del_subregion(parent, mr); | |
1346 | if (may_overlap) { | |
1347 | memory_region_add_subregion_overlap(parent, addr, mr, priority); | |
1348 | } else { | |
1349 | memory_region_add_subregion(parent, addr, mr); | |
1350 | } | |
1351 | memory_region_transaction_commit(); | |
1352 | } | |
1353 | ||
4703359e AK |
1354 | void memory_region_set_alias_offset(MemoryRegion *mr, target_phys_addr_t offset) |
1355 | { | |
1356 | target_phys_addr_t old_offset = mr->alias_offset; | |
1357 | ||
1358 | assert(mr->alias); | |
1359 | mr->alias_offset = offset; | |
1360 | ||
1361 | if (offset == old_offset || !mr->parent) { | |
1362 | return; | |
1363 | } | |
1364 | ||
1365 | memory_region_update_topology(mr); | |
1366 | } | |
1367 | ||
1c0ffa58 AK |
1368 | void set_system_memory_map(MemoryRegion *mr) |
1369 | { | |
cc31e6e7 | 1370 | address_space_memory.root = mr; |
6bba19ba | 1371 | memory_region_update_topology(NULL); |
1c0ffa58 | 1372 | } |
658b2224 AK |
1373 | |
1374 | void set_system_io_map(MemoryRegion *mr) | |
1375 | { | |
1376 | address_space_io.root = mr; | |
6bba19ba | 1377 | memory_region_update_topology(NULL); |
658b2224 | 1378 | } |
314e2987 BS |
1379 | |
1380 | typedef struct MemoryRegionList MemoryRegionList; | |
1381 | ||
1382 | struct MemoryRegionList { | |
1383 | const MemoryRegion *mr; | |
1384 | bool printed; | |
1385 | QTAILQ_ENTRY(MemoryRegionList) queue; | |
1386 | }; | |
1387 | ||
1388 | typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead; | |
1389 | ||
1390 | static void mtree_print_mr(fprintf_function mon_printf, void *f, | |
1391 | const MemoryRegion *mr, unsigned int level, | |
1392 | target_phys_addr_t base, | |
9479c57a | 1393 | MemoryRegionListHead *alias_print_queue) |
314e2987 | 1394 | { |
9479c57a JK |
1395 | MemoryRegionList *new_ml, *ml, *next_ml; |
1396 | MemoryRegionListHead submr_print_queue; | |
314e2987 BS |
1397 | const MemoryRegion *submr; |
1398 | unsigned int i; | |
1399 | ||
314e2987 BS |
1400 | if (!mr) { |
1401 | return; | |
1402 | } | |
1403 | ||
1404 | for (i = 0; i < level; i++) { | |
1405 | mon_printf(f, " "); | |
1406 | } | |
1407 | ||
1408 | if (mr->alias) { | |
1409 | MemoryRegionList *ml; | |
1410 | bool found = false; | |
1411 | ||
1412 | /* check if the alias is already in the queue */ | |
9479c57a | 1413 | QTAILQ_FOREACH(ml, alias_print_queue, queue) { |
314e2987 BS |
1414 | if (ml->mr == mr->alias && !ml->printed) { |
1415 | found = true; | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | if (!found) { | |
1420 | ml = g_new(MemoryRegionList, 1); | |
1421 | ml->mr = mr->alias; | |
1422 | ml->printed = false; | |
9479c57a | 1423 | QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue); |
314e2987 | 1424 | } |
4b474ba7 | 1425 | mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): alias %s @%s " |
314e2987 BS |
1426 | TARGET_FMT_plx "-" TARGET_FMT_plx "\n", |
1427 | base + mr->addr, | |
08dafab4 AK |
1428 | base + mr->addr |
1429 | + (target_phys_addr_t)int128_get64(mr->size) - 1, | |
4b474ba7 | 1430 | mr->priority, |
314e2987 BS |
1431 | mr->name, |
1432 | mr->alias->name, | |
1433 | mr->alias_offset, | |
08dafab4 AK |
1434 | mr->alias_offset |
1435 | + (target_phys_addr_t)int128_get64(mr->size) - 1); | |
314e2987 | 1436 | } else { |
4b474ba7 | 1437 | mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n", |
314e2987 | 1438 | base + mr->addr, |
08dafab4 AK |
1439 | base + mr->addr |
1440 | + (target_phys_addr_t)int128_get64(mr->size) - 1, | |
4b474ba7 | 1441 | mr->priority, |
314e2987 BS |
1442 | mr->name); |
1443 | } | |
9479c57a JK |
1444 | |
1445 | QTAILQ_INIT(&submr_print_queue); | |
1446 | ||
314e2987 | 1447 | QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) { |
9479c57a JK |
1448 | new_ml = g_new(MemoryRegionList, 1); |
1449 | new_ml->mr = submr; | |
1450 | QTAILQ_FOREACH(ml, &submr_print_queue, queue) { | |
1451 | if (new_ml->mr->addr < ml->mr->addr || | |
1452 | (new_ml->mr->addr == ml->mr->addr && | |
1453 | new_ml->mr->priority > ml->mr->priority)) { | |
1454 | QTAILQ_INSERT_BEFORE(ml, new_ml, queue); | |
1455 | new_ml = NULL; | |
1456 | break; | |
1457 | } | |
1458 | } | |
1459 | if (new_ml) { | |
1460 | QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue); | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | QTAILQ_FOREACH(ml, &submr_print_queue, queue) { | |
1465 | mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr, | |
1466 | alias_print_queue); | |
1467 | } | |
1468 | ||
88365e47 | 1469 | QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) { |
9479c57a | 1470 | g_free(ml); |
314e2987 BS |
1471 | } |
1472 | } | |
1473 | ||
1474 | void mtree_info(fprintf_function mon_printf, void *f) | |
1475 | { | |
1476 | MemoryRegionListHead ml_head; | |
1477 | MemoryRegionList *ml, *ml2; | |
1478 | ||
1479 | QTAILQ_INIT(&ml_head); | |
1480 | ||
1481 | mon_printf(f, "memory\n"); | |
1482 | mtree_print_mr(mon_printf, f, address_space_memory.root, 0, 0, &ml_head); | |
1483 | ||
1484 | /* print aliased regions */ | |
1485 | QTAILQ_FOREACH(ml, &ml_head, queue) { | |
1486 | if (!ml->printed) { | |
1487 | mon_printf(f, "%s\n", ml->mr->name); | |
1488 | mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head); | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) { | |
88365e47 | 1493 | g_free(ml); |
314e2987 BS |
1494 | } |
1495 | ||
06631810 JK |
1496 | if (address_space_io.root && |
1497 | !QTAILQ_EMPTY(&address_space_io.root->subregions)) { | |
1498 | QTAILQ_INIT(&ml_head); | |
1499 | mon_printf(f, "I/O\n"); | |
1500 | mtree_print_mr(mon_printf, f, address_space_io.root, 0, 0, &ml_head); | |
1501 | } | |
314e2987 | 1502 | } |