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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 */
13
14#include "memory.h"
1c0ffa58 15#include "exec-memory.h"
658b2224 16#include "ioport.h"
74901c3b 17#include "bitops.h"
3e9d69e7 18#include "kvm.h"
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19#include <assert.h>
20
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21#define WANT_EXEC_OBSOLETE
22#include "exec-obsolete.h"
23
4ef4db86 24unsigned memory_region_transaction_depth = 0;
e87c099f 25static bool memory_region_update_pending = false;
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26static bool global_dirty_log = false;
27
28static QLIST_HEAD(, MemoryListener) memory_listeners
29 = QLIST_HEAD_INITIALIZER(memory_listeners);
4ef4db86 30
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31typedef struct AddrRange AddrRange;
32
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33/*
34 * Note using signed integers limits us to physical addresses at most
35 * 63 bits wide. They are needed for negative offsetting in aliases
36 * (large MemoryRegion::alias_offset).
37 */
093bc2cd 38struct AddrRange {
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39 Int128 start;
40 Int128 size;
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41};
42
08dafab4 43static AddrRange addrrange_make(Int128 start, Int128 size)
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44{
45 return (AddrRange) { start, size };
46}
47
48static bool addrrange_equal(AddrRange r1, AddrRange r2)
49{
08dafab4 50 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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51}
52
08dafab4 53static Int128 addrrange_end(AddrRange r)
093bc2cd 54{
08dafab4 55 return int128_add(r.start, r.size);
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56}
57
08dafab4 58static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 59{
08dafab4 60 int128_addto(&range.start, delta);
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61 return range;
62}
63
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64static bool addrrange_contains(AddrRange range, Int128 addr)
65{
66 return int128_ge(addr, range.start)
67 && int128_lt(addr, addrrange_end(range));
68}
69
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70static bool addrrange_intersects(AddrRange r1, AddrRange r2)
71{
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72 return addrrange_contains(r1, r2.start)
73 || addrrange_contains(r2, r1.start);
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74}
75
76static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
77{
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78 Int128 start = int128_max(r1.start, r2.start);
79 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
80 return addrrange_make(start, int128_sub(end, start));
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81}
82
83struct CoalescedMemoryRange {
84 AddrRange addr;
85 QTAILQ_ENTRY(CoalescedMemoryRange) link;
86};
87
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88struct MemoryRegionIoeventfd {
89 AddrRange addr;
90 bool match_data;
91 uint64_t data;
92 int fd;
93};
94
95static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
96 MemoryRegionIoeventfd b)
97{
08dafab4 98 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 99 return true;
08dafab4 100 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 101 return false;
08dafab4 102 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 103 return true;
08dafab4 104 } else if (int128_gt(a.addr.size, b.addr.size)) {
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105 return false;
106 } else if (a.match_data < b.match_data) {
107 return true;
108 } else if (a.match_data > b.match_data) {
109 return false;
110 } else if (a.match_data) {
111 if (a.data < b.data) {
112 return true;
113 } else if (a.data > b.data) {
114 return false;
115 }
116 }
117 if (a.fd < b.fd) {
118 return true;
119 } else if (a.fd > b.fd) {
120 return false;
121 }
122 return false;
123}
124
125static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
126 MemoryRegionIoeventfd b)
127{
128 return !memory_region_ioeventfd_before(a, b)
129 && !memory_region_ioeventfd_before(b, a);
130}
131
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132typedef struct FlatRange FlatRange;
133typedef struct FlatView FlatView;
134
135/* Range of memory in the global map. Addresses are absolute. */
136struct FlatRange {
137 MemoryRegion *mr;
138 target_phys_addr_t offset_in_region;
139 AddrRange addr;
5a583347 140 uint8_t dirty_log_mask;
d0a9b5bc 141 bool readable;
fb1cd6f9 142 bool readonly;
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143};
144
145/* Flattened global view of current active memory hierarchy. Kept in sorted
146 * order.
147 */
148struct FlatView {
149 FlatRange *ranges;
150 unsigned nr;
151 unsigned nr_allocated;
152};
153
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154typedef struct AddressSpace AddressSpace;
155typedef struct AddressSpaceOps AddressSpaceOps;
156
157/* A system address space - I/O, memory, etc. */
158struct AddressSpace {
159 const AddressSpaceOps *ops;
160 MemoryRegion *root;
161 FlatView current_map;
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162 int ioeventfd_nb;
163 MemoryRegionIoeventfd *ioeventfds;
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164};
165
166struct AddressSpaceOps {
167 void (*range_add)(AddressSpace *as, FlatRange *fr);
168 void (*range_del)(AddressSpace *as, FlatRange *fr);
169 void (*log_start)(AddressSpace *as, FlatRange *fr);
170 void (*log_stop)(AddressSpace *as, FlatRange *fr);
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171 void (*ioeventfd_add)(AddressSpace *as, MemoryRegionIoeventfd *fd);
172 void (*ioeventfd_del)(AddressSpace *as, MemoryRegionIoeventfd *fd);
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173};
174
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175#define FOR_EACH_FLAT_RANGE(var, view) \
176 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
177
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178static bool flatrange_equal(FlatRange *a, FlatRange *b)
179{
180 return a->mr == b->mr
181 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 182 && a->offset_in_region == b->offset_in_region
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183 && a->readable == b->readable
184 && a->readonly == b->readonly;
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185}
186
187static void flatview_init(FlatView *view)
188{
189 view->ranges = NULL;
190 view->nr = 0;
191 view->nr_allocated = 0;
192}
193
194/* Insert a range into a given position. Caller is responsible for maintaining
195 * sorting order.
196 */
197static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
198{
199 if (view->nr == view->nr_allocated) {
200 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 201 view->ranges = g_realloc(view->ranges,
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202 view->nr_allocated * sizeof(*view->ranges));
203 }
204 memmove(view->ranges + pos + 1, view->ranges + pos,
205 (view->nr - pos) * sizeof(FlatRange));
206 view->ranges[pos] = *range;
207 ++view->nr;
208}
209
210static void flatview_destroy(FlatView *view)
211{
7267c094 212 g_free(view->ranges);
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213}
214
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215static bool can_merge(FlatRange *r1, FlatRange *r2)
216{
08dafab4 217 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 218 && r1->mr == r2->mr
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219 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
220 r1->addr.size),
221 int128_make64(r2->offset_in_region))
d0a9b5bc 222 && r1->dirty_log_mask == r2->dirty_log_mask
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223 && r1->readable == r2->readable
224 && r1->readonly == r2->readonly;
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225}
226
227/* Attempt to simplify a view by merging ajacent ranges */
228static void flatview_simplify(FlatView *view)
229{
230 unsigned i, j;
231
232 i = 0;
233 while (i < view->nr) {
234 j = i + 1;
235 while (j < view->nr
236 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 237 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
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238 ++j;
239 }
240 ++i;
241 memmove(&view->ranges[i], &view->ranges[j],
242 (view->nr - j) * sizeof(view->ranges[j]));
243 view->nr -= j - i;
244 }
245}
246
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247static void memory_region_read_accessor(void *opaque,
248 target_phys_addr_t addr,
249 uint64_t *value,
250 unsigned size,
251 unsigned shift,
252 uint64_t mask)
253{
254 MemoryRegion *mr = opaque;
255 uint64_t tmp;
256
257 tmp = mr->ops->read(mr->opaque, addr, size);
258 *value |= (tmp & mask) << shift;
259}
260
261static void memory_region_write_accessor(void *opaque,
262 target_phys_addr_t addr,
263 uint64_t *value,
264 unsigned size,
265 unsigned shift,
266 uint64_t mask)
267{
268 MemoryRegion *mr = opaque;
269 uint64_t tmp;
270
271 tmp = (*value >> shift) & mask;
272 mr->ops->write(mr->opaque, addr, tmp, size);
273}
274
275static void access_with_adjusted_size(target_phys_addr_t addr,
276 uint64_t *value,
277 unsigned size,
278 unsigned access_size_min,
279 unsigned access_size_max,
280 void (*access)(void *opaque,
281 target_phys_addr_t addr,
282 uint64_t *value,
283 unsigned size,
284 unsigned shift,
285 uint64_t mask),
286 void *opaque)
287{
288 uint64_t access_mask;
289 unsigned access_size;
290 unsigned i;
291
292 if (!access_size_min) {
293 access_size_min = 1;
294 }
295 if (!access_size_max) {
296 access_size_max = 4;
297 }
298 access_size = MAX(MIN(size, access_size_max), access_size_min);
299 access_mask = -1ULL >> (64 - access_size * 8);
300 for (i = 0; i < size; i += access_size) {
301 /* FIXME: big-endian support */
302 access(opaque, addr + i, value, access_size, i * 8, access_mask);
303 }
304}
305
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306static void memory_region_prepare_ram_addr(MemoryRegion *mr);
307
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308static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
309{
310 ram_addr_t phys_offset, region_offset;
311
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312 memory_region_prepare_ram_addr(fr->mr);
313
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314 phys_offset = fr->mr->ram_addr;
315 region_offset = fr->offset_in_region;
316 /* cpu_register_physical_memory_log() wants region_offset for
317 * mmio, but prefers offseting phys_offset for RAM. Humour it.
318 */
319 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
320 phys_offset += region_offset;
321 region_offset = 0;
322 }
323
d0a9b5bc 324 if (!fr->readable) {
b5fe14cc 325 phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD;
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326 }
327
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328 if (fr->readonly) {
329 phys_offset |= IO_MEM_ROM;
330 }
331
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332 cpu_register_physical_memory_log(int128_get64(fr->addr.start),
333 int128_get64(fr->addr.size),
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334 phys_offset,
335 region_offset,
336 fr->dirty_log_mask);
337}
338
339static void as_memory_range_del(AddressSpace *as, FlatRange *fr)
340{
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341 cpu_register_physical_memory(int128_get64(fr->addr.start),
342 int128_get64(fr->addr.size),
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343 IO_MEM_UNASSIGNED);
344}
345
346static void as_memory_log_start(AddressSpace *as, FlatRange *fr)
347{
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348}
349
350static void as_memory_log_stop(AddressSpace *as, FlatRange *fr)
351{
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352}
353
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354static void as_memory_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd)
355{
356 int r;
357
08dafab4 358 assert(fd->match_data && int128_get64(fd->addr.size) == 4);
3e9d69e7 359
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360 r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start),
361 fd->data, true);
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362 if (r < 0) {
363 abort();
364 }
365}
366
367static void as_memory_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd)
368{
369 int r;
370
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371 r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start),
372 fd->data, false);
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373 if (r < 0) {
374 abort();
375 }
376}
377
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378static const AddressSpaceOps address_space_ops_memory = {
379 .range_add = as_memory_range_add,
380 .range_del = as_memory_range_del,
381 .log_start = as_memory_log_start,
382 .log_stop = as_memory_log_stop,
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383 .ioeventfd_add = as_memory_ioeventfd_add,
384 .ioeventfd_del = as_memory_ioeventfd_del,
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385};
386
387static AddressSpace address_space_memory = {
388 .ops = &address_space_ops_memory,
389};
390
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391static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset,
392 unsigned width, bool write)
393{
394 const MemoryRegionPortio *mrp;
395
396 for (mrp = mr->ops->old_portio; mrp->size; ++mrp) {
397 if (offset >= mrp->offset && offset < mrp->offset + mrp->len
398 && width == mrp->size
399 && (write ? (bool)mrp->write : (bool)mrp->read)) {
400 return mrp;
401 }
402 }
403 return NULL;
404}
405
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406static void memory_region_iorange_read(IORange *iorange,
407 uint64_t offset,
408 unsigned width,
409 uint64_t *data)
410{
411 MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
412
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413 if (mr->ops->old_portio) {
414 const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false);
415
416 *data = ((uint64_t)1 << (width * 8)) - 1;
417 if (mrp) {
6bf9fd43 418 *data = mrp->read(mr->opaque, offset + mr->offset);
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419 } else if (width == 2) {
420 mrp = find_portio(mr, offset, 1, false);
421 assert(mrp);
422 *data = mrp->read(mr->opaque, offset + mr->offset) |
423 (mrp->read(mr->opaque, offset + mr->offset + 1) << 8);
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424 }
425 return;
426 }
3a130f4e 427 *data = 0;
6bf9fd43 428 access_with_adjusted_size(offset + mr->offset, data, width,
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429 mr->ops->impl.min_access_size,
430 mr->ops->impl.max_access_size,
431 memory_region_read_accessor, mr);
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432}
433
434static void memory_region_iorange_write(IORange *iorange,
435 uint64_t offset,
436 unsigned width,
437 uint64_t data)
438{
439 MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
440
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441 if (mr->ops->old_portio) {
442 const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true);
443
444 if (mrp) {
6bf9fd43 445 mrp->write(mr->opaque, offset + mr->offset, data);
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446 } else if (width == 2) {
447 mrp = find_portio(mr, offset, 1, false);
448 assert(mrp);
449 mrp->write(mr->opaque, offset + mr->offset, data & 0xff);
450 mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8);
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451 }
452 return;
453 }
6bf9fd43 454 access_with_adjusted_size(offset + mr->offset, &data, width,
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455 mr->ops->impl.min_access_size,
456 mr->ops->impl.max_access_size,
457 memory_region_write_accessor, mr);
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458}
459
460static const IORangeOps memory_region_iorange_ops = {
461 .read = memory_region_iorange_read,
462 .write = memory_region_iorange_write,
463};
464
465static void as_io_range_add(AddressSpace *as, FlatRange *fr)
466{
467 iorange_init(&fr->mr->iorange, &memory_region_iorange_ops,
08dafab4 468 int128_get64(fr->addr.start), int128_get64(fr->addr.size));
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469 ioport_register(&fr->mr->iorange);
470}
471
472static void as_io_range_del(AddressSpace *as, FlatRange *fr)
473{
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474 isa_unassign_ioport(int128_get64(fr->addr.start),
475 int128_get64(fr->addr.size));
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476}
477
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478static void as_io_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd)
479{
480 int r;
481
08dafab4 482 assert(fd->match_data && int128_get64(fd->addr.size) == 2);
3e9d69e7 483
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484 r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start),
485 fd->data, true);
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486 if (r < 0) {
487 abort();
488 }
489}
490
491static void as_io_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd)
492{
493 int r;
494
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495 r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start),
496 fd->data, false);
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497 if (r < 0) {
498 abort();
499 }
500}
501
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502static const AddressSpaceOps address_space_ops_io = {
503 .range_add = as_io_range_add,
504 .range_del = as_io_range_del,
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505 .ioeventfd_add = as_io_ioeventfd_add,
506 .ioeventfd_del = as_io_ioeventfd_del,
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507};
508
509static AddressSpace address_space_io = {
510 .ops = &address_space_ops_io,
511};
512
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513static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
514{
515 while (mr->parent) {
516 mr = mr->parent;
517 }
518 if (mr == address_space_memory.root) {
519 return &address_space_memory;
520 }
521 if (mr == address_space_io.root) {
522 return &address_space_io;
523 }
524 abort();
525}
526
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527/* Render a memory region into the global view. Ranges in @view obscure
528 * ranges in @mr.
529 */
530static void render_memory_region(FlatView *view,
531 MemoryRegion *mr,
08dafab4 532 Int128 base,
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533 AddrRange clip,
534 bool readonly)
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535{
536 MemoryRegion *subregion;
537 unsigned i;
538 target_phys_addr_t offset_in_region;
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539 Int128 remain;
540 Int128 now;
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541 FlatRange fr;
542 AddrRange tmp;
543
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544 if (!mr->enabled) {
545 return;
546 }
547
08dafab4 548 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 549 readonly |= mr->readonly;
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550
551 tmp = addrrange_make(base, mr->size);
552
553 if (!addrrange_intersects(tmp, clip)) {
554 return;
555 }
556
557 clip = addrrange_intersection(tmp, clip);
558
559 if (mr->alias) {
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560 int128_subfrom(&base, int128_make64(mr->alias->addr));
561 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 562 render_memory_region(view, mr->alias, base, clip, readonly);
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563 return;
564 }
565
566 /* Render subregions in priority order. */
567 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 568 render_memory_region(view, subregion, base, clip, readonly);
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569 }
570
14a3c10a 571 if (!mr->terminates) {
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572 return;
573 }
574
08dafab4 575 offset_in_region = int128_get64(int128_sub(clip.start, base));
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576 base = clip.start;
577 remain = clip.size;
578
579 /* Render the region itself into any gaps left by the current view. */
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580 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
581 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
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582 continue;
583 }
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584 if (int128_lt(base, view->ranges[i].addr.start)) {
585 now = int128_min(remain,
586 int128_sub(view->ranges[i].addr.start, base));
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587 fr.mr = mr;
588 fr.offset_in_region = offset_in_region;
589 fr.addr = addrrange_make(base, now);
5a583347 590 fr.dirty_log_mask = mr->dirty_log_mask;
d0a9b5bc 591 fr.readable = mr->readable;
fb1cd6f9 592 fr.readonly = readonly;
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593 flatview_insert(view, i, &fr);
594 ++i;
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595 int128_addto(&base, now);
596 offset_in_region += int128_get64(now);
597 int128_subfrom(&remain, now);
093bc2cd 598 }
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599 if (int128_eq(base, view->ranges[i].addr.start)) {
600 now = int128_min(remain, view->ranges[i].addr.size);
601 int128_addto(&base, now);
602 offset_in_region += int128_get64(now);
603 int128_subfrom(&remain, now);
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604 }
605 }
08dafab4 606 if (int128_nz(remain)) {
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607 fr.mr = mr;
608 fr.offset_in_region = offset_in_region;
609 fr.addr = addrrange_make(base, remain);
5a583347 610 fr.dirty_log_mask = mr->dirty_log_mask;
d0a9b5bc 611 fr.readable = mr->readable;
fb1cd6f9 612 fr.readonly = readonly;
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613 flatview_insert(view, i, &fr);
614 }
615}
616
617/* Render a memory topology into a list of disjoint absolute ranges. */
618static FlatView generate_memory_topology(MemoryRegion *mr)
619{
620 FlatView view;
621
622 flatview_init(&view);
623
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624 render_memory_region(&view, mr, int128_zero(),
625 addrrange_make(int128_zero(), int128_2_64()), false);
3d8e6bf9 626 flatview_simplify(&view);
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627
628 return view;
629}
630
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631static void address_space_add_del_ioeventfds(AddressSpace *as,
632 MemoryRegionIoeventfd *fds_new,
633 unsigned fds_new_nb,
634 MemoryRegionIoeventfd *fds_old,
635 unsigned fds_old_nb)
636{
637 unsigned iold, inew;
638
639 /* Generate a symmetric difference of the old and new fd sets, adding
640 * and deleting as necessary.
641 */
642
643 iold = inew = 0;
644 while (iold < fds_old_nb || inew < fds_new_nb) {
645 if (iold < fds_old_nb
646 && (inew == fds_new_nb
647 || memory_region_ioeventfd_before(fds_old[iold],
648 fds_new[inew]))) {
649 as->ops->ioeventfd_del(as, &fds_old[iold]);
650 ++iold;
651 } else if (inew < fds_new_nb
652 && (iold == fds_old_nb
653 || memory_region_ioeventfd_before(fds_new[inew],
654 fds_old[iold]))) {
655 as->ops->ioeventfd_add(as, &fds_new[inew]);
656 ++inew;
657 } else {
658 ++iold;
659 ++inew;
660 }
661 }
662}
663
664static void address_space_update_ioeventfds(AddressSpace *as)
665{
666 FlatRange *fr;
667 unsigned ioeventfd_nb = 0;
668 MemoryRegionIoeventfd *ioeventfds = NULL;
669 AddrRange tmp;
670 unsigned i;
671
672 FOR_EACH_FLAT_RANGE(fr, &as->current_map) {
673 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
674 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
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675 int128_sub(fr->addr.start,
676 int128_make64(fr->offset_in_region)));
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677 if (addrrange_intersects(fr->addr, tmp)) {
678 ++ioeventfd_nb;
7267c094 679 ioeventfds = g_realloc(ioeventfds,
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680 ioeventfd_nb * sizeof(*ioeventfds));
681 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
682 ioeventfds[ioeventfd_nb-1].addr = tmp;
683 }
684 }
685 }
686
687 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
688 as->ioeventfds, as->ioeventfd_nb);
689
7267c094 690 g_free(as->ioeventfds);
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691 as->ioeventfds = ioeventfds;
692 as->ioeventfd_nb = ioeventfd_nb;
693}
694
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695typedef void ListenerCallback(MemoryListener *listener,
696 MemoryRegionSection *mrs);
697
698/* Want "void (&MemoryListener::*callback)(const MemoryRegionSection& s)" */
699static void memory_listener_update_region(FlatRange *fr, AddressSpace *as,
700 size_t callback_offset)
701{
702 MemoryRegionSection section = {
703 .mr = fr->mr,
704 .address_space = as->root,
705 .offset_within_region = fr->offset_in_region,
706 .size = int128_get64(fr->addr.size),
707 .offset_within_address_space = int128_get64(fr->addr.start),
708 };
709 MemoryListener *listener;
710
711 QLIST_FOREACH(listener, &memory_listeners, link) {
712 ListenerCallback *callback
713 = *(ListenerCallback **)((void *)listener + callback_offset);
714 callback(listener, &section);
715 }
716}
717
718#define MEMORY_LISTENER_UPDATE_REGION(fr, as, callback) \
719 memory_listener_update_region(fr, as, offsetof(MemoryListener, callback))
720
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721static void address_space_update_topology_pass(AddressSpace *as,
722 FlatView old_view,
723 FlatView new_view,
724 bool adding)
093bc2cd 725{
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726 unsigned iold, inew;
727 FlatRange *frold, *frnew;
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728
729 /* Generate a symmetric difference of the old and new memory maps.
730 * Kill ranges in the old map, and instantiate ranges in the new map.
731 */
732 iold = inew = 0;
733 while (iold < old_view.nr || inew < new_view.nr) {
734 if (iold < old_view.nr) {
735 frold = &old_view.ranges[iold];
736 } else {
737 frold = NULL;
738 }
739 if (inew < new_view.nr) {
740 frnew = &new_view.ranges[inew];
741 } else {
742 frnew = NULL;
743 }
744
745 if (frold
746 && (!frnew
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747 || int128_lt(frold->addr.start, frnew->addr.start)
748 || (int128_eq(frold->addr.start, frnew->addr.start)
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749 && !flatrange_equal(frold, frnew)))) {
750 /* In old, but (not in new, or in new but attributes changed). */
751
b8af1afb 752 if (!adding) {
7664e80c 753 MEMORY_LISTENER_UPDATE_REGION(frold, as, region_del);
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754 as->ops->range_del(as, frold);
755 }
756
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757 ++iold;
758 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
759 /* In both (logging may have changed) */
760
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761 if (adding) {
762 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
9f213ed9 763 MEMORY_LISTENER_UPDATE_REGION(frnew, as, log_stop);
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764 as->ops->log_stop(as, frnew);
765 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
766 as->ops->log_start(as, frnew);
9f213ed9 767 MEMORY_LISTENER_UPDATE_REGION(frnew, as, log_start);
b8af1afb 768 }
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769 }
770
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771 ++iold;
772 ++inew;
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773 } else {
774 /* In new */
775
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776 if (adding) {
777 as->ops->range_add(as, frnew);
9f213ed9 778 MEMORY_LISTENER_UPDATE_REGION(frnew, as, region_add);
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779 }
780
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781 ++inew;
782 }
783 }
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784}
785
786
787static void address_space_update_topology(AddressSpace *as)
788{
789 FlatView old_view = as->current_map;
790 FlatView new_view = generate_memory_topology(as->root);
791
792 address_space_update_topology_pass(as, old_view, new_view, false);
793 address_space_update_topology_pass(as, old_view, new_view, true);
794
cc31e6e7 795 as->current_map = new_view;
093bc2cd 796 flatview_destroy(&old_view);
3e9d69e7 797 address_space_update_ioeventfds(as);
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798}
799
6bba19ba 800static void memory_region_update_topology(MemoryRegion *mr)
cc31e6e7 801{
4ef4db86 802 if (memory_region_transaction_depth) {
e87c099f 803 memory_region_update_pending |= !mr || mr->enabled;
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804 return;
805 }
806
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807 if (mr && !mr->enabled) {
808 return;
809 }
810
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811 if (address_space_memory.root) {
812 address_space_update_topology(&address_space_memory);
813 }
814 if (address_space_io.root) {
815 address_space_update_topology(&address_space_io);
816 }
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817
818 memory_region_update_pending = false;
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819}
820
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821void memory_region_transaction_begin(void)
822{
823 ++memory_region_transaction_depth;
824}
825
826void memory_region_transaction_commit(void)
827{
828 assert(memory_region_transaction_depth);
829 --memory_region_transaction_depth;
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830 if (!memory_region_transaction_depth && memory_region_update_pending) {
831 memory_region_update_topology(NULL);
832 }
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833}
834
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835static void memory_region_destructor_none(MemoryRegion *mr)
836{
837}
838
839static void memory_region_destructor_ram(MemoryRegion *mr)
840{
841 qemu_ram_free(mr->ram_addr);
842}
843
844static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
845{
846 qemu_ram_free_from_ptr(mr->ram_addr);
847}
848
849static void memory_region_destructor_iomem(MemoryRegion *mr)
850{
851 cpu_unregister_io_memory(mr->ram_addr);
852}
853
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854static void memory_region_destructor_rom_device(MemoryRegion *mr)
855{
856 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
857 cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
858}
859
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860static bool memory_region_wrong_endianness(MemoryRegion *mr)
861{
862#ifdef TARGET_BIG_ENDIAN
863 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
864#else
865 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
866#endif
867}
868
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869void memory_region_init(MemoryRegion *mr,
870 const char *name,
871 uint64_t size)
872{
873 mr->ops = NULL;
874 mr->parent = NULL;
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875 mr->size = int128_make64(size);
876 if (size == UINT64_MAX) {
877 mr->size = int128_2_64();
878 }
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879 mr->addr = 0;
880 mr->offset = 0;
6bba19ba 881 mr->enabled = true;
14a3c10a 882 mr->terminates = false;
8ea9252a 883 mr->ram = false;
d0a9b5bc 884 mr->readable = true;
fb1cd6f9 885 mr->readonly = false;
545e92e0 886 mr->destructor = memory_region_destructor_none;
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887 mr->priority = 0;
888 mr->may_overlap = false;
889 mr->alias = NULL;
890 QTAILQ_INIT(&mr->subregions);
891 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
892 QTAILQ_INIT(&mr->coalesced);
7267c094 893 mr->name = g_strdup(name);
5a583347 894 mr->dirty_log_mask = 0;
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895 mr->ioeventfd_nb = 0;
896 mr->ioeventfds = NULL;
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897}
898
899static bool memory_region_access_valid(MemoryRegion *mr,
900 target_phys_addr_t addr,
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901 unsigned size,
902 bool is_write)
093bc2cd 903{
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904 if (mr->ops->valid.accepts
905 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) {
906 return false;
907 }
908
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909 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
910 return false;
911 }
912
913 /* Treat zero as compatibility all valid */
914 if (!mr->ops->valid.max_access_size) {
915 return true;
916 }
917
918 if (size > mr->ops->valid.max_access_size
919 || size < mr->ops->valid.min_access_size) {
920 return false;
921 }
922 return true;
923}
924
925static uint32_t memory_region_read_thunk_n(void *_mr,
926 target_phys_addr_t addr,
927 unsigned size)
928{
929 MemoryRegion *mr = _mr;
164a4dcd 930 uint64_t data = 0;
093bc2cd 931
897fa7cf 932 if (!memory_region_access_valid(mr, addr, size, false)) {
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933 return -1U; /* FIXME: better signalling */
934 }
935
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936 if (!mr->ops->read) {
937 return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr);
938 }
939
093bc2cd 940 /* FIXME: support unaligned access */
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941 access_with_adjusted_size(addr + mr->offset, &data, size,
942 mr->ops->impl.min_access_size,
943 mr->ops->impl.max_access_size,
944 memory_region_read_accessor, mr);
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945
946 return data;
947}
948
949static void memory_region_write_thunk_n(void *_mr,
950 target_phys_addr_t addr,
951 unsigned size,
952 uint64_t data)
953{
954 MemoryRegion *mr = _mr;
093bc2cd 955
897fa7cf 956 if (!memory_region_access_valid(mr, addr, size, true)) {
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957 return; /* FIXME: better signalling */
958 }
959
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960 if (!mr->ops->write) {
961 mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data);
962 return;
963 }
964
093bc2cd 965 /* FIXME: support unaligned access */
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966 access_with_adjusted_size(addr + mr->offset, &data, size,
967 mr->ops->impl.min_access_size,
968 mr->ops->impl.max_access_size,
969 memory_region_write_accessor, mr);
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970}
971
972static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
973{
974 return memory_region_read_thunk_n(mr, addr, 1);
975}
976
977static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr)
978{
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979 uint32_t data;
980
981 data = memory_region_read_thunk_n(mr, addr, 2);
982 if (memory_region_wrong_endianness(mr)) {
983 data = bswap16(data);
984 }
985 return data;
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986}
987
988static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr)
989{
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990 uint32_t data;
991
992 data = memory_region_read_thunk_n(mr, addr, 4);
993 if (memory_region_wrong_endianness(mr)) {
994 data = bswap32(data);
995 }
996 return data;
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997}
998
999static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
1000 uint32_t data)
1001{
1002 memory_region_write_thunk_n(mr, addr, 1, data);
1003}
1004
1005static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr,
1006 uint32_t data)
1007{
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1008 if (memory_region_wrong_endianness(mr)) {
1009 data = bswap16(data);
1010 }
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1011 memory_region_write_thunk_n(mr, addr, 2, data);
1012}
1013
1014static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr,
1015 uint32_t data)
1016{
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1017 if (memory_region_wrong_endianness(mr)) {
1018 data = bswap32(data);
1019 }
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1020 memory_region_write_thunk_n(mr, addr, 4, data);
1021}
1022
1023static CPUReadMemoryFunc * const memory_region_read_thunk[] = {
1024 memory_region_read_thunk_b,
1025 memory_region_read_thunk_w,
1026 memory_region_read_thunk_l,
1027};
1028
1029static CPUWriteMemoryFunc * const memory_region_write_thunk[] = {
1030 memory_region_write_thunk_b,
1031 memory_region_write_thunk_w,
1032 memory_region_write_thunk_l,
1033};
1034
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1035static void memory_region_prepare_ram_addr(MemoryRegion *mr)
1036{
1037 if (mr->backend_registered) {
1038 return;
1039 }
1040
545e92e0 1041 mr->destructor = memory_region_destructor_iomem;
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1042 mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk,
1043 memory_region_write_thunk,
be675c97 1044 mr);
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1045 mr->backend_registered = true;
1046}
1047
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1048void memory_region_init_io(MemoryRegion *mr,
1049 const MemoryRegionOps *ops,
1050 void *opaque,
1051 const char *name,
1052 uint64_t size)
1053{
1054 memory_region_init(mr, name, size);
1055 mr->ops = ops;
1056 mr->opaque = opaque;
14a3c10a 1057 mr->terminates = true;
16ef61c9 1058 mr->backend_registered = false;
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1059}
1060
1061void memory_region_init_ram(MemoryRegion *mr,
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1062 const char *name,
1063 uint64_t size)
1064{
1065 memory_region_init(mr, name, size);
8ea9252a 1066 mr->ram = true;
14a3c10a 1067 mr->terminates = true;
545e92e0 1068 mr->destructor = memory_region_destructor_ram;
c5705a77 1069 mr->ram_addr = qemu_ram_alloc(size, mr);
16ef61c9 1070 mr->backend_registered = true;
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1071}
1072
1073void memory_region_init_ram_ptr(MemoryRegion *mr,
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1074 const char *name,
1075 uint64_t size,
1076 void *ptr)
1077{
1078 memory_region_init(mr, name, size);
8ea9252a 1079 mr->ram = true;
14a3c10a 1080 mr->terminates = true;
545e92e0 1081 mr->destructor = memory_region_destructor_ram_from_ptr;
c5705a77 1082 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
16ef61c9 1083 mr->backend_registered = true;
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1084}
1085
1086void memory_region_init_alias(MemoryRegion *mr,
1087 const char *name,
1088 MemoryRegion *orig,
1089 target_phys_addr_t offset,
1090 uint64_t size)
1091{
1092 memory_region_init(mr, name, size);
1093 mr->alias = orig;
1094 mr->alias_offset = offset;
1095}
1096
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1097void memory_region_init_rom_device(MemoryRegion *mr,
1098 const MemoryRegionOps *ops,
75f5941c 1099 void *opaque,
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1100 const char *name,
1101 uint64_t size)
1102{
1103 memory_region_init(mr, name, size);
7bc2b9cd 1104 mr->ops = ops;
75f5941c 1105 mr->opaque = opaque;
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1106 mr->terminates = true;
1107 mr->destructor = memory_region_destructor_rom_device;
c5705a77 1108 mr->ram_addr = qemu_ram_alloc(size, mr);
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1109 mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk,
1110 memory_region_write_thunk,
be675c97 1111 mr);
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1112 mr->ram_addr |= IO_MEM_ROMD;
1113 mr->backend_registered = true;
1114}
1115
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1116void memory_region_destroy(MemoryRegion *mr)
1117{
1118 assert(QTAILQ_EMPTY(&mr->subregions));
545e92e0 1119 mr->destructor(mr);
093bc2cd 1120 memory_region_clear_coalescing(mr);
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1121 g_free((char *)mr->name);
1122 g_free(mr->ioeventfds);
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1123}
1124
1125uint64_t memory_region_size(MemoryRegion *mr)
1126{
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1127 if (int128_eq(mr->size, int128_2_64())) {
1128 return UINT64_MAX;
1129 }
1130 return int128_get64(mr->size);
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1131}
1132
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1133const char *memory_region_name(MemoryRegion *mr)
1134{
1135 return mr->name;
1136}
1137
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1138bool memory_region_is_ram(MemoryRegion *mr)
1139{
1140 return mr->ram;
1141}
1142
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1143bool memory_region_is_logging(MemoryRegion *mr)
1144{
1145 return mr->dirty_log_mask;
1146}
1147
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1148bool memory_region_is_rom(MemoryRegion *mr)
1149{
1150 return mr->ram && mr->readonly;
1151}
1152
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1153void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset)
1154{
1155 mr->offset = offset;
1156}
1157
1158void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1159{
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1160 uint8_t mask = 1 << client;
1161
1162 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
6bba19ba 1163 memory_region_update_topology(mr);
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1164}
1165
1166bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
1167 unsigned client)
1168{
14a3c10a 1169 assert(mr->terminates);
5a583347 1170 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client);
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1171}
1172
1173void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr)
1174{
14a3c10a 1175 assert(mr->terminates);
5a583347 1176 return cpu_physical_memory_set_dirty(mr->ram_addr + addr);
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1177}
1178
1179void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1180{
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1181 FlatRange *fr;
1182
cc31e6e7 1183 FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
5a583347 1184 if (fr->mr == mr) {
7664e80c 1185 MEMORY_LISTENER_UPDATE_REGION(fr, &address_space_memory, log_sync);
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1186 }
1187 }
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1188}
1189
1190void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1191{
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1192 if (mr->readonly != readonly) {
1193 mr->readonly = readonly;
6bba19ba 1194 memory_region_update_topology(mr);
fb1cd6f9 1195 }
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1196}
1197
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1198void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable)
1199{
1200 if (mr->readable != readable) {
1201 mr->readable = readable;
6bba19ba 1202 memory_region_update_topology(mr);
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1203 }
1204}
1205
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1206void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
1207 target_phys_addr_t size, unsigned client)
1208{
14a3c10a 1209 assert(mr->terminates);
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1210 cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
1211 mr->ram_addr + addr + size,
1212 1 << client);
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1213}
1214
1215void *memory_region_get_ram_ptr(MemoryRegion *mr)
1216{
1217 if (mr->alias) {
1218 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1219 }
1220
14a3c10a 1221 assert(mr->terminates);
093bc2cd 1222
021d26d1 1223 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
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AK
1224}
1225
1226static void memory_region_update_coalesced_range(MemoryRegion *mr)
1227{
1228 FlatRange *fr;
1229 CoalescedMemoryRange *cmr;
1230 AddrRange tmp;
1231
cc31e6e7 1232 FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
093bc2cd 1233 if (fr->mr == mr) {
08dafab4
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1234 qemu_unregister_coalesced_mmio(int128_get64(fr->addr.start),
1235 int128_get64(fr->addr.size));
093bc2cd
AK
1236 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1237 tmp = addrrange_shift(cmr->addr,
08dafab4
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1238 int128_sub(fr->addr.start,
1239 int128_make64(fr->offset_in_region)));
093bc2cd
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1240 if (!addrrange_intersects(tmp, fr->addr)) {
1241 continue;
1242 }
1243 tmp = addrrange_intersection(tmp, fr->addr);
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1244 qemu_register_coalesced_mmio(int128_get64(tmp.start),
1245 int128_get64(tmp.size));
093bc2cd
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1246 }
1247 }
1248 }
1249}
1250
1251void memory_region_set_coalescing(MemoryRegion *mr)
1252{
1253 memory_region_clear_coalescing(mr);
08dafab4 1254 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
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1255}
1256
1257void memory_region_add_coalescing(MemoryRegion *mr,
1258 target_phys_addr_t offset,
1259 uint64_t size)
1260{
7267c094 1261 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1262
08dafab4 1263 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
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1264 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1265 memory_region_update_coalesced_range(mr);
1266}
1267
1268void memory_region_clear_coalescing(MemoryRegion *mr)
1269{
1270 CoalescedMemoryRange *cmr;
1271
1272 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1273 cmr = QTAILQ_FIRST(&mr->coalesced);
1274 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1275 g_free(cmr);
093bc2cd
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1276 }
1277 memory_region_update_coalesced_range(mr);
1278}
1279
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1280void memory_region_add_eventfd(MemoryRegion *mr,
1281 target_phys_addr_t addr,
1282 unsigned size,
1283 bool match_data,
1284 uint64_t data,
1285 int fd)
1286{
1287 MemoryRegionIoeventfd mrfd = {
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1288 .addr.start = int128_make64(addr),
1289 .addr.size = int128_make64(size),
3e9d69e7
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1290 .match_data = match_data,
1291 .data = data,
1292 .fd = fd,
1293 };
1294 unsigned i;
1295
1296 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1297 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1298 break;
1299 }
1300 }
1301 ++mr->ioeventfd_nb;
7267c094 1302 mr->ioeventfds = g_realloc(mr->ioeventfds,
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1303 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1304 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1305 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1306 mr->ioeventfds[i] = mrfd;
6bba19ba 1307 memory_region_update_topology(mr);
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1308}
1309
1310void memory_region_del_eventfd(MemoryRegion *mr,
1311 target_phys_addr_t addr,
1312 unsigned size,
1313 bool match_data,
1314 uint64_t data,
1315 int fd)
1316{
1317 MemoryRegionIoeventfd mrfd = {
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1318 .addr.start = int128_make64(addr),
1319 .addr.size = int128_make64(size),
3e9d69e7
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1320 .match_data = match_data,
1321 .data = data,
1322 .fd = fd,
1323 };
1324 unsigned i;
1325
1326 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1327 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1328 break;
1329 }
1330 }
1331 assert(i != mr->ioeventfd_nb);
1332 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1333 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1334 --mr->ioeventfd_nb;
7267c094 1335 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1336 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
6bba19ba 1337 memory_region_update_topology(mr);
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1338}
1339
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1340static void memory_region_add_subregion_common(MemoryRegion *mr,
1341 target_phys_addr_t offset,
1342 MemoryRegion *subregion)
1343{
1344 MemoryRegion *other;
1345
1346 assert(!subregion->parent);
1347 subregion->parent = mr;
1348 subregion->addr = offset;
1349 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1350 if (subregion->may_overlap || other->may_overlap) {
1351 continue;
1352 }
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1353 if (int128_gt(int128_make64(offset),
1354 int128_add(int128_make64(other->addr), other->size))
1355 || int128_le(int128_add(int128_make64(offset), subregion->size),
1356 int128_make64(other->addr))) {
093bc2cd
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1357 continue;
1358 }
a5e1cbc8 1359#if 0
860329b2
MW
1360 printf("warning: subregion collision %llx/%llx (%s) "
1361 "vs %llx/%llx (%s)\n",
093bc2cd 1362 (unsigned long long)offset,
08dafab4 1363 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1364 subregion->name,
1365 (unsigned long long)other->addr,
08dafab4 1366 (unsigned long long)int128_get64(other->size),
860329b2 1367 other->name);
a5e1cbc8 1368#endif
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1369 }
1370 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1371 if (subregion->priority >= other->priority) {
1372 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1373 goto done;
1374 }
1375 }
1376 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1377done:
6bba19ba 1378 memory_region_update_topology(mr);
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1379}
1380
1381
1382void memory_region_add_subregion(MemoryRegion *mr,
1383 target_phys_addr_t offset,
1384 MemoryRegion *subregion)
1385{
1386 subregion->may_overlap = false;
1387 subregion->priority = 0;
1388 memory_region_add_subregion_common(mr, offset, subregion);
1389}
1390
1391void memory_region_add_subregion_overlap(MemoryRegion *mr,
1392 target_phys_addr_t offset,
1393 MemoryRegion *subregion,
1394 unsigned priority)
1395{
1396 subregion->may_overlap = true;
1397 subregion->priority = priority;
1398 memory_region_add_subregion_common(mr, offset, subregion);
1399}
1400
1401void memory_region_del_subregion(MemoryRegion *mr,
1402 MemoryRegion *subregion)
1403{
1404 assert(subregion->parent == mr);
1405 subregion->parent = NULL;
1406 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
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1407 memory_region_update_topology(mr);
1408}
1409
1410void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1411{
1412 if (enabled == mr->enabled) {
1413 return;
1414 }
1415 mr->enabled = enabled;
1416 memory_region_update_topology(NULL);
093bc2cd 1417}
1c0ffa58 1418
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1419void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr)
1420{
1421 MemoryRegion *parent = mr->parent;
1422 unsigned priority = mr->priority;
1423 bool may_overlap = mr->may_overlap;
1424
1425 if (addr == mr->addr || !parent) {
1426 mr->addr = addr;
1427 return;
1428 }
1429
1430 memory_region_transaction_begin();
1431 memory_region_del_subregion(parent, mr);
1432 if (may_overlap) {
1433 memory_region_add_subregion_overlap(parent, addr, mr, priority);
1434 } else {
1435 memory_region_add_subregion(parent, addr, mr);
1436 }
1437 memory_region_transaction_commit();
1438}
1439
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1440void memory_region_set_alias_offset(MemoryRegion *mr, target_phys_addr_t offset)
1441{
1442 target_phys_addr_t old_offset = mr->alias_offset;
1443
1444 assert(mr->alias);
1445 mr->alias_offset = offset;
1446
1447 if (offset == old_offset || !mr->parent) {
1448 return;
1449 }
1450
1451 memory_region_update_topology(mr);
1452}
1453
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1454ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1455{
1456 assert(mr->backend_registered);
1457 return mr->ram_addr;
1458}
1459
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1460static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1461{
1462 const AddrRange *addr = addr_;
1463 const FlatRange *fr = fr_;
1464
1465 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1466 return -1;
1467 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1468 return 1;
1469 }
1470 return 0;
1471}
1472
1473static FlatRange *address_space_lookup(AddressSpace *as, AddrRange addr)
1474{
1475 return bsearch(&addr, as->current_map.ranges, as->current_map.nr,
1476 sizeof(FlatRange), cmp_flatrange_addr);
1477}
1478
1479MemoryRegionSection memory_region_find(MemoryRegion *address_space,
1480 target_phys_addr_t addr, uint64_t size)
1481{
1482 AddressSpace *as = memory_region_to_address_space(address_space);
1483 AddrRange range = addrrange_make(int128_make64(addr),
1484 int128_make64(size));
1485 FlatRange *fr = address_space_lookup(as, range);
1486 MemoryRegionSection ret = { .mr = NULL, .size = 0 };
1487
1488 if (!fr) {
1489 return ret;
1490 }
1491
1492 while (fr > as->current_map.ranges
1493 && addrrange_intersects(fr[-1].addr, range)) {
1494 --fr;
1495 }
1496
1497 ret.mr = fr->mr;
1498 range = addrrange_intersection(range, fr->addr);
1499 ret.offset_within_region = fr->offset_in_region;
1500 ret.offset_within_region += int128_get64(int128_sub(range.start,
1501 fr->addr.start));
1502 ret.size = int128_get64(range.size);
1503 ret.offset_within_address_space = int128_get64(range.start);
1504 return ret;
1505}
1506
86e775c6
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1507void memory_global_sync_dirty_bitmap(MemoryRegion *address_space)
1508{
7664e80c
AK
1509 AddressSpace *as = memory_region_to_address_space(address_space);
1510 FlatRange *fr;
1511
7664e80c
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1512 FOR_EACH_FLAT_RANGE(fr, &as->current_map) {
1513 MEMORY_LISTENER_UPDATE_REGION(fr, as, log_sync);
1514 }
1515}
1516
1517void memory_global_dirty_log_start(void)
1518{
1519 MemoryListener *listener;
1520
8f77558f 1521 cpu_physical_memory_set_dirty_tracking(1);
7664e80c
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1522 global_dirty_log = true;
1523 QLIST_FOREACH(listener, &memory_listeners, link) {
1524 listener->log_global_start(listener);
1525 }
1526}
1527
1528void memory_global_dirty_log_stop(void)
1529{
1530 MemoryListener *listener;
1531
1532 global_dirty_log = false;
1533 QLIST_FOREACH(listener, &memory_listeners, link) {
1534 listener->log_global_stop(listener);
1535 }
8f77558f 1536 cpu_physical_memory_set_dirty_tracking(0);
7664e80c
AK
1537}
1538
1539static void listener_add_address_space(MemoryListener *listener,
1540 AddressSpace *as)
1541{
1542 FlatRange *fr;
1543
1544 if (global_dirty_log) {
1545 listener->log_global_start(listener);
1546 }
1547 FOR_EACH_FLAT_RANGE(fr, &as->current_map) {
1548 MemoryRegionSection section = {
1549 .mr = fr->mr,
1550 .address_space = as->root,
1551 .offset_within_region = fr->offset_in_region,
1552 .size = int128_get64(fr->addr.size),
1553 .offset_within_address_space = int128_get64(fr->addr.start),
1554 };
1555 listener->region_add(listener, &section);
1556 }
1557}
1558
1559void memory_listener_register(MemoryListener *listener)
1560{
1561 QLIST_INSERT_HEAD(&memory_listeners, listener, link);
1562 listener_add_address_space(listener, &address_space_memory);
1563 listener_add_address_space(listener, &address_space_io);
1564}
1565
1566void memory_listener_unregister(MemoryListener *listener)
1567{
1568 QLIST_REMOVE(listener, link);
86e775c6 1569}
e2177955 1570
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1571void set_system_memory_map(MemoryRegion *mr)
1572{
cc31e6e7 1573 address_space_memory.root = mr;
6bba19ba 1574 memory_region_update_topology(NULL);
1c0ffa58 1575}
658b2224
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1576
1577void set_system_io_map(MemoryRegion *mr)
1578{
1579 address_space_io.root = mr;
6bba19ba 1580 memory_region_update_topology(NULL);
658b2224 1581}
314e2987
BS
1582
1583typedef struct MemoryRegionList MemoryRegionList;
1584
1585struct MemoryRegionList {
1586 const MemoryRegion *mr;
1587 bool printed;
1588 QTAILQ_ENTRY(MemoryRegionList) queue;
1589};
1590
1591typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1592
1593static void mtree_print_mr(fprintf_function mon_printf, void *f,
1594 const MemoryRegion *mr, unsigned int level,
1595 target_phys_addr_t base,
9479c57a 1596 MemoryRegionListHead *alias_print_queue)
314e2987 1597{
9479c57a
JK
1598 MemoryRegionList *new_ml, *ml, *next_ml;
1599 MemoryRegionListHead submr_print_queue;
314e2987
BS
1600 const MemoryRegion *submr;
1601 unsigned int i;
1602
314e2987
BS
1603 if (!mr) {
1604 return;
1605 }
1606
1607 for (i = 0; i < level; i++) {
1608 mon_printf(f, " ");
1609 }
1610
1611 if (mr->alias) {
1612 MemoryRegionList *ml;
1613 bool found = false;
1614
1615 /* check if the alias is already in the queue */
9479c57a 1616 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
314e2987
BS
1617 if (ml->mr == mr->alias && !ml->printed) {
1618 found = true;
1619 }
1620 }
1621
1622 if (!found) {
1623 ml = g_new(MemoryRegionList, 1);
1624 ml->mr = mr->alias;
1625 ml->printed = false;
9479c57a 1626 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 1627 }
4b474ba7 1628 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): alias %s @%s "
314e2987
BS
1629 TARGET_FMT_plx "-" TARGET_FMT_plx "\n",
1630 base + mr->addr,
08dafab4
AK
1631 base + mr->addr
1632 + (target_phys_addr_t)int128_get64(mr->size) - 1,
4b474ba7 1633 mr->priority,
314e2987
BS
1634 mr->name,
1635 mr->alias->name,
1636 mr->alias_offset,
08dafab4
AK
1637 mr->alias_offset
1638 + (target_phys_addr_t)int128_get64(mr->size) - 1);
314e2987 1639 } else {
4b474ba7 1640 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n",
314e2987 1641 base + mr->addr,
08dafab4
AK
1642 base + mr->addr
1643 + (target_phys_addr_t)int128_get64(mr->size) - 1,
4b474ba7 1644 mr->priority,
314e2987
BS
1645 mr->name);
1646 }
9479c57a
JK
1647
1648 QTAILQ_INIT(&submr_print_queue);
1649
314e2987 1650 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
1651 new_ml = g_new(MemoryRegionList, 1);
1652 new_ml->mr = submr;
1653 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1654 if (new_ml->mr->addr < ml->mr->addr ||
1655 (new_ml->mr->addr == ml->mr->addr &&
1656 new_ml->mr->priority > ml->mr->priority)) {
1657 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1658 new_ml = NULL;
1659 break;
1660 }
1661 }
1662 if (new_ml) {
1663 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1664 }
1665 }
1666
1667 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1668 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1669 alias_print_queue);
1670 }
1671
88365e47 1672 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 1673 g_free(ml);
314e2987
BS
1674 }
1675}
1676
1677void mtree_info(fprintf_function mon_printf, void *f)
1678{
1679 MemoryRegionListHead ml_head;
1680 MemoryRegionList *ml, *ml2;
1681
1682 QTAILQ_INIT(&ml_head);
1683
1684 mon_printf(f, "memory\n");
1685 mtree_print_mr(mon_printf, f, address_space_memory.root, 0, 0, &ml_head);
1686
1687 /* print aliased regions */
1688 QTAILQ_FOREACH(ml, &ml_head, queue) {
1689 if (!ml->printed) {
1690 mon_printf(f, "%s\n", ml->mr->name);
1691 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1692 }
1693 }
1694
1695 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 1696 g_free(ml);
314e2987
BS
1697 }
1698
06631810
JK
1699 if (address_space_io.root &&
1700 !QTAILQ_EMPTY(&address_space_io.root->subregions)) {
1701 QTAILQ_INIT(&ml_head);
1702 mon_printf(f, "I/O\n");
1703 mtree_print_mr(mon_printf, f, address_space_io.root, 0, 0, &ml_head);
1704 }
314e2987 1705}