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This should have been added in Gerd's previous commit.
[qemu.git] / pc-bios / bios.diff
CommitLineData
43661a95
AJ		 1--- bochs-2.3.7.orig/bios/rombios.h
2+++ bochs-2.3.7/bios/rombios.h
3@@ -19,7 +19,7 @@
4 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
5
6 /* define it to include QEMU specific code */
7-//#define BX_QEMU
8+#define BX_QEMU
9
10 #ifndef LEGACY
11 # define BX_ROMBIOS32 1
12--- bochs-2.3.7.orig/bios/rombios.c
13+++ bochs-2.3.7/bios/rombios.c
14@@ -4404,22 +4404,25 @@
acb98efb 15 #endif // BX_USE_PS2_MOUSE
e6e514c5
AJ		 16
17
acb98efb
AJ		 18-void set_e820_range(ES, DI, start, end, type)
19+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
20 Bit16u ES;
21 Bit16u DI;
22 Bit32u start;
23 Bit32u end;
24+ Bit8u extra_start;
25+ Bit8u extra_end;
26 Bit16u type;
27 {
28 write_word(ES, DI, start);
29 write_word(ES, DI+2, start >> 16);
30- write_word(ES, DI+4, 0x00);
31+ write_word(ES, DI+4, extra_start);
32 write_word(ES, DI+6, 0x00);
e6e514c5 33
acb98efb
AJ		 34 end -= start;
35+ extra_end -= extra_start;
36 write_word(ES, DI+8, end);
37 write_word(ES, DI+10, end >> 16);
38- write_word(ES, DI+12, 0x0000);
39+ write_word(ES, DI+12, extra_end);
40 write_word(ES, DI+14, 0x0000);
e6e514c5 41
acb98efb 42 write_word(ES, DI+16, type);
43661a95 43@@ -4432,7 +4435,9 @@
acb98efb
AJ		 44 Bit16u ES, DS, FLAGS;
45 {
46 Bit32u extended_memory_size=0; // 64bits long
47+ Bit32u extra_lowbits_memory_size=0;
48 Bit16u CX,DX;
49+ Bit8u extra_highbits_memory_size=0;
e6e514c5 50
acb98efb 51 BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
e6e514c5 52
43661a95 53@@ -4506,11 +4511,18 @@
acb98efb
AJ		 54 extended_memory_size += (1L * 1024 * 1024);
55 }
e6e514c5 56
acb98efb
AJ		 57+ extra_lowbits_memory_size = inb_cmos(0x5c);
58+ extra_lowbits_memory_size <<= 8;
59+ extra_lowbits_memory_size |= inb_cmos(0x5b);
60+ extra_lowbits_memory_size *= 64;
61+ extra_lowbits_memory_size *= 1024;
62+ extra_highbits_memory_size = inb_cmos(0x5d);
63+
64 switch(regs.u.r16.bx)
65 {
66 case 0:
67 set_e820_range(ES, regs.u.r16.di,
68- 0x0000000L, 0x0009fc00L, 1);
69+ 0x0000000L, 0x0009fc00L, 0, 0, 1);
70 regs.u.r32.ebx = 1;
71 regs.u.r32.eax = 0x534D4150;
72 regs.u.r32.ecx = 0x14;
43661a95 73@@ -4519,7 +4531,7 @@
acb98efb
AJ		 74 break;
75 case 1:
76 set_e820_range(ES, regs.u.r16.di,
77- 0x0009fc00L, 0x000a0000L, 2);
78+ 0x0009fc00L, 0x000a0000L, 0, 0, 2);
79 regs.u.r32.ebx = 2;
80 regs.u.r32.eax = 0x534D4150;
81 regs.u.r32.ecx = 0x14;
43661a95 82@@ -4528,7 +4540,7 @@
acb98efb
AJ		 83 break;
84 case 2:
85 set_e820_range(ES, regs.u.r16.di,
86- 0x000e8000L, 0x00100000L, 2);
87+ 0x000e8000L, 0x00100000L, 0, 0, 2);
88 regs.u.r32.ebx = 3;
89 regs.u.r32.eax = 0x534D4150;
90 regs.u.r32.ecx = 0x14;
43661a95 91@@ -4539,7 +4551,7 @@
e6e514c5 92 #if BX_ROMBIOS32
acb98efb
AJ		 93 set_e820_range(ES, regs.u.r16.di,
94 0x00100000L,
95- extended_memory_size - ACPI_DATA_SIZE, 1);
96+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
97 regs.u.r32.ebx = 4;
e6e514c5
AJ		 98 #else
99 set_e820_range(ES, regs.u.r16.di,
43661a95 100@@ -4555,7 +4567,7 @@
acb98efb
AJ		 101 case 4:
102 set_e820_range(ES, regs.u.r16.di,
103 extended_memory_size - ACPI_DATA_SIZE,
104- extended_memory_size, 3); // ACPI RAM
105+ extended_memory_size ,0, 0, 3); // ACPI RAM
106 regs.u.r32.ebx = 5;
107 regs.u.r32.eax = 0x534D4150;
108 regs.u.r32.ecx = 0x14;
43661a95 109@@ -4565,7 +4577,20 @@
acb98efb
AJ		 110 case 5:
111 /* 256KB BIOS area at the end of 4 GB */
112 set_e820_range(ES, regs.u.r16.di,
113- 0xfffc0000L, 0x00000000L, 2);
114+ 0xfffc0000L, 0x00000000L ,0, 0, 2);
115+ if (extra_highbits_memory_size || extra_lowbits_memory_size)
116+ regs.u.r32.ebx = 6;
117+ else
118+ regs.u.r32.ebx = 0;
119+ regs.u.r32.eax = 0x534D4150;
120+ regs.u.r32.ecx = 0x14;
121+ CLEAR_CF();
122+ return;
123+ case 6:
124+ /* Maping of memory above 4 GB */
125+ set_e820_range(ES, regs.u.r16.di, 0x00000000L,
126+ extra_lowbits_memory_size, 1, extra_highbits_memory_size
127+ + 1, 1);
128 regs.u.r32.ebx = 0;
129 regs.u.r32.eax = 0x534D4150;
130 regs.u.r32.ecx = 0x14;
43661a95
AJ		 131--- bochs-2.3.7.orig/bios/rombios32.c
132+++ bochs-2.3.7/bios/rombios32.c
133@@ -479,7 +479,12 @@
6cc9215e
AJ		 134 sipi_vector = AP_BOOT_ADDR >> 12;
135 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
a7e6f8ba 136
6cc9215e
AJ		 137+#ifndef BX_QEMU
138 delay_ms(10);
139+#else
140+ while (cmos_readb(0x5f) + 1 != readw((void *)CPU_COUNT_ADDR))
141+ ;
e3e97e7c 142+#endif
6cc9215e
AJ		 143
144 smp_cpus = readw((void *)CPU_COUNT_ADDR);
145 }
Qemu copy for testing