]> git.proxmox.com Git - qemu.git/blame - qemu-char.h
Disable >4G ram support on 32-bit targets
[qemu.git] / qemu-char.h
CommitLineData
87ecb68b
PB
1#ifndef QEMU_CHAR_H
2#define QEMU_CHAR_H
3
376253ec 4#include "qemu-common.h"
5ccfae10 5#include "sys-queue.h"
376253ec 6
87ecb68b
PB
7/* character device */
8
2724b180
AL
9#define CHR_EVENT_BREAK 0 /* serial break char */
10#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
11#define CHR_EVENT_RESET 2 /* new connection established */
12#define CHR_EVENT_MUX_IN 3 /* mux-focus was set to this terminal */
13#define CHR_EVENT_MUX_OUT 4 /* mux-focus will move on */
87ecb68b
PB
14
15
16#define CHR_IOCTL_SERIAL_SET_PARAMS 1
17typedef struct {
18 int speed;
19 int parity;
20 int data_bits;
21 int stop_bits;
22} QEMUSerialSetParams;
23
24#define CHR_IOCTL_SERIAL_SET_BREAK 2
25
26#define CHR_IOCTL_PP_READ_DATA 3
27#define CHR_IOCTL_PP_WRITE_DATA 4
28#define CHR_IOCTL_PP_READ_CONTROL 5
29#define CHR_IOCTL_PP_WRITE_CONTROL 6
30#define CHR_IOCTL_PP_READ_STATUS 7
31#define CHR_IOCTL_PP_EPP_READ_ADDR 8
32#define CHR_IOCTL_PP_EPP_READ 9
33#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
34#define CHR_IOCTL_PP_EPP_WRITE 11
563e3c6e 35#define CHR_IOCTL_PP_DATA_DIR 12
87ecb68b 36
f0664048
AJ
37#define CHR_IOCTL_SERIAL_SET_TIOCM 13
38#define CHR_IOCTL_SERIAL_GET_TIOCM 14
81174dae
AL
39
40#define CHR_TIOCM_CTS 0x020
41#define CHR_TIOCM_CAR 0x040
42#define CHR_TIOCM_DSR 0x100
43#define CHR_TIOCM_RI 0x080
44#define CHR_TIOCM_DTR 0x002
45#define CHR_TIOCM_RTS 0x004
46
87ecb68b
PB
47typedef void IOEventHandler(void *opaque, int event);
48
49struct CharDriverState {
ceecf1d1 50 void (*init)(struct CharDriverState *s);
87ecb68b
PB
51 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
52 void (*chr_update_read_handler)(struct CharDriverState *s);
53 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
54 IOEventHandler *chr_event;
55 IOCanRWHandler *chr_can_read;
56 IOReadHandler *chr_read;
57 void *handler_opaque;
58 void (*chr_send_event)(struct CharDriverState *chr, int event);
59 void (*chr_close)(struct CharDriverState *chr);
bd9bdce6 60 void (*chr_accept_input)(struct CharDriverState *chr);
87ecb68b
PB
61 void *opaque;
62 int focus;
63 QEMUBH *bh;
5ccfae10
AL
64 char *label;
65 char *filename;
66 TAILQ_ENTRY(CharDriverState) next;
87ecb68b
PB
67};
68
ceecf1d1 69CharDriverState *qemu_chr_open(const char *label, const char *filename, void (*init)(struct CharDriverState *s));
9596ebb7 70void qemu_chr_close(CharDriverState *chr);
87ecb68b
PB
71void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
72int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
73void qemu_chr_send_event(CharDriverState *s, int event);
74void qemu_chr_add_handlers(CharDriverState *s,
75 IOCanRWHandler *fd_can_read,
76 IOReadHandler *fd_read,
77 IOEventHandler *fd_event,
78 void *opaque);
79int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
80void qemu_chr_reset(CharDriverState *s);
2970a6c9 81void qemu_chr_initial_reset(void);
87ecb68b
PB
82int qemu_chr_can_read(CharDriverState *s);
83void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
bd9bdce6 84void qemu_chr_accept_input(CharDriverState *s);
376253ec 85void qemu_chr_info(Monitor *mon);
87ecb68b 86
0e82f34d
AL
87extern int term_escape_char;
88
87ecb68b
PB
89/* async I/O support */
90
91int qemu_set_fd_handler2(int fd,
92 IOCanRWHandler *fd_read_poll,
93 IOHandler *fd_read,
94 IOHandler *fd_write,
95 void *opaque);
96int qemu_set_fd_handler(int fd,
97 IOHandler *fd_read,
98 IOHandler *fd_write,
99 void *opaque);
100
101#endif