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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
14cccb61 | 21 | #include "qom/cpu.h" |
dd83b06a AF |
22 | #include "qemu-common.h" |
23 | ||
24 | void cpu_reset(CPUState *cpu) | |
25 | { | |
26 | CPUClass *klass = CPU_GET_CLASS(cpu); | |
27 | ||
28 | if (klass->reset != NULL) { | |
29 | (*klass->reset)(cpu); | |
30 | } | |
31 | } | |
32 | ||
33 | static void cpu_common_reset(CPUState *cpu) | |
34 | { | |
fcd7d003 | 35 | cpu->exit_request = 0; |
d77953b9 | 36 | cpu->current_tb = NULL; |
dd83b06a AF |
37 | } |
38 | ||
2b8c2754 AF |
39 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
40 | { | |
41 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); | |
42 | ||
43 | return cc->class_by_name(cpu_model); | |
44 | } | |
45 | ||
46 | static ObjectClass *cpu_common_class_by_name(const char *cpu_model) | |
47 | { | |
48 | return NULL; | |
49 | } | |
50 | ||
4f658099 AF |
51 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
52 | { | |
53 | } | |
54 | ||
dd83b06a AF |
55 | static void cpu_class_init(ObjectClass *klass, void *data) |
56 | { | |
961f8395 | 57 | DeviceClass *dc = DEVICE_CLASS(klass); |
dd83b06a AF |
58 | CPUClass *k = CPU_CLASS(klass); |
59 | ||
2b8c2754 | 60 | k->class_by_name = cpu_common_class_by_name; |
dd83b06a | 61 | k->reset = cpu_common_reset; |
4f658099 | 62 | dc->realize = cpu_common_realizefn; |
961f8395 | 63 | dc->no_user = 1; |
dd83b06a AF |
64 | } |
65 | ||
961f8395 | 66 | static const TypeInfo cpu_type_info = { |
dd83b06a | 67 | .name = TYPE_CPU, |
961f8395 | 68 | .parent = TYPE_DEVICE, |
dd83b06a AF |
69 | .instance_size = sizeof(CPUState), |
70 | .abstract = true, | |
71 | .class_size = sizeof(CPUClass), | |
72 | .class_init = cpu_class_init, | |
73 | }; | |
74 | ||
75 | static void cpu_register_types(void) | |
76 | { | |
77 | type_register_static(&cpu_type_info); | |
78 | } | |
79 | ||
80 | type_init(cpu_register_types) |