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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
14cccb61 | 21 | #include "qom/cpu.h" |
dd83b06a | 22 | #include "qemu-common.h" |
13eed94e | 23 | #include "sysemu/kvm.h" |
dd83b06a | 24 | |
d8ed887b AF |
25 | void cpu_reset_interrupt(CPUState *cpu, int mask) |
26 | { | |
27 | cpu->interrupt_request &= ~mask; | |
28 | } | |
29 | ||
dd83b06a AF |
30 | void cpu_reset(CPUState *cpu) |
31 | { | |
32 | CPUClass *klass = CPU_GET_CLASS(cpu); | |
33 | ||
34 | if (klass->reset != NULL) { | |
35 | (*klass->reset)(cpu); | |
36 | } | |
37 | } | |
38 | ||
39 | static void cpu_common_reset(CPUState *cpu) | |
40 | { | |
fcd7d003 | 41 | cpu->exit_request = 0; |
259186a7 | 42 | cpu->interrupt_request = 0; |
d77953b9 | 43 | cpu->current_tb = NULL; |
259186a7 | 44 | cpu->halted = 0; |
dd83b06a AF |
45 | } |
46 | ||
2b8c2754 AF |
47 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
48 | { | |
49 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); | |
50 | ||
51 | return cc->class_by_name(cpu_model); | |
52 | } | |
53 | ||
54 | static ObjectClass *cpu_common_class_by_name(const char *cpu_model) | |
55 | { | |
56 | return NULL; | |
57 | } | |
58 | ||
4f658099 AF |
59 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
60 | { | |
13eed94e IM |
61 | CPUState *cpu = CPU(dev); |
62 | ||
63 | if (dev->hotplugged) { | |
64 | cpu_synchronize_post_init(cpu); | |
65 | } | |
4f658099 AF |
66 | } |
67 | ||
dd83b06a AF |
68 | static void cpu_class_init(ObjectClass *klass, void *data) |
69 | { | |
961f8395 | 70 | DeviceClass *dc = DEVICE_CLASS(klass); |
dd83b06a AF |
71 | CPUClass *k = CPU_CLASS(klass); |
72 | ||
2b8c2754 | 73 | k->class_by_name = cpu_common_class_by_name; |
dd83b06a | 74 | k->reset = cpu_common_reset; |
4f658099 | 75 | dc->realize = cpu_common_realizefn; |
961f8395 | 76 | dc->no_user = 1; |
dd83b06a AF |
77 | } |
78 | ||
961f8395 | 79 | static const TypeInfo cpu_type_info = { |
dd83b06a | 80 | .name = TYPE_CPU, |
961f8395 | 81 | .parent = TYPE_DEVICE, |
dd83b06a AF |
82 | .instance_size = sizeof(CPUState), |
83 | .abstract = true, | |
84 | .class_size = sizeof(CPUClass), | |
85 | .class_init = cpu_class_init, | |
86 | }; | |
87 | ||
88 | static void cpu_register_types(void) | |
89 | { | |
90 | type_register_static(&cpu_type_info); | |
91 | } | |
92 | ||
93 | type_init(cpu_register_types) |