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Commit | Line | Data |
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54936004 | 1 | /* |
d9f24bf5 | 2 | * RAM allocation and memory access |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
61f3c91a | 9 | * version 2.1 of the License, or (at your option) any later version. |
54936004 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
14a48c1d | 19 | |
7b31bbc2 | 20 | #include "qemu/osdep.h" |
ec5f7ca8 | 21 | #include "exec/page-vary.h" |
da34e65c | 22 | #include "qapi/error.h" |
54936004 | 23 | |
f348b6d1 | 24 | #include "qemu/cutils.h" |
084cfca1 | 25 | #include "qemu/cacheflush.h" |
e2c1c34f | 26 | #include "qemu/hbitmap.h" |
b85ea5fa | 27 | #include "qemu/madvise.h" |
78271684 CF |
28 | |
29 | #ifdef CONFIG_TCG | |
30 | #include "hw/core/tcg-cpu-ops.h" | |
31 | #endif /* CONFIG_TCG */ | |
32 | ||
63c91552 | 33 | #include "exec/exec-all.h" |
51180423 | 34 | #include "exec/target_page.h" |
741da0d3 | 35 | #include "hw/qdev-core.h" |
c7e002c5 | 36 | #include "hw/qdev-properties.h" |
47c8ca53 | 37 | #include "hw/boards.h" |
33c11879 | 38 | #include "hw/xen/xen.h" |
9c17d615 | 39 | #include "sysemu/kvm.h" |
14a48c1d | 40 | #include "sysemu/tcg.h" |
a028edea | 41 | #include "sysemu/qtest.h" |
1de7afc9 PB |
42 | #include "qemu/timer.h" |
43 | #include "qemu/config-file.h" | |
75a34036 | 44 | #include "qemu/error-report.h" |
b6b71cb5 | 45 | #include "qemu/qemu-print.h" |
3ab6fdc9 | 46 | #include "qemu/log.h" |
5df022cf | 47 | #include "qemu/memalign.h" |
741da0d3 | 48 | #include "exec/memory.h" |
df43d49c | 49 | #include "exec/ioport.h" |
741da0d3 | 50 | #include "sysemu/dma.h" |
b58c5c2d | 51 | #include "sysemu/hostmem.h" |
79ca7a1b | 52 | #include "sysemu/hw_accel.h" |
9c17d615 | 53 | #include "sysemu/xen-mapcache.h" |
243af022 | 54 | #include "trace/trace-root.h" |
d3a5038c | 55 | |
e2fa71f5 | 56 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
e2fa71f5 DDAG |
57 | #include <linux/falloc.h> |
58 | #endif | |
59 | ||
0dc3f44a | 60 | #include "qemu/rcu_queue.h" |
4840f10e | 61 | #include "qemu/main-loop.h" |
3b9bd3f4 | 62 | #include "exec/translate-all.h" |
7615936e | 63 | #include "sysemu/replay.h" |
0cac1b66 | 64 | |
022c62cb | 65 | #include "exec/memory-internal.h" |
220c3ebd | 66 | #include "exec/ram_addr.h" |
67d95c15 | 67 | |
61c490e2 BM |
68 | #include "qemu/pmem.h" |
69 | ||
9dfeca7c BR |
70 | #include "migration/vmstate.h" |
71 | ||
b35ba30f | 72 | #include "qemu/range.h" |
794e8f30 MT |
73 | #ifndef _WIN32 |
74 | #include "qemu/mmap-alloc.h" | |
75 | #endif | |
b35ba30f | 76 | |
be9b23c4 PX |
77 | #include "monitor/monitor.h" |
78 | ||
ce317be9 JL |
79 | #ifdef CONFIG_LIBDAXCTL |
80 | #include <daxctl/libdaxctl.h> | |
81 | #endif | |
82 | ||
db7b5426 | 83 | //#define DEBUG_SUBPAGE |
1196be37 | 84 | |
0dc3f44a MD |
85 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
86 | * are protected by the ramlist lock. | |
87 | */ | |
0d53d9fe | 88 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
89 | |
90 | static MemoryRegion *system_memory; | |
309cb471 | 91 | static MemoryRegion *system_io; |
62152b8a | 92 | |
f6790af6 AK |
93 | AddressSpace address_space_io; |
94 | AddressSpace address_space_memory; | |
2673a5da | 95 | |
acc9d80b | 96 | static MemoryRegion io_mem_unassigned; |
4346ae3e | 97 | |
1db8abb1 PB |
98 | typedef struct PhysPageEntry PhysPageEntry; |
99 | ||
100 | struct PhysPageEntry { | |
9736e55b | 101 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 102 | uint32_t skip : 6; |
9736e55b | 103 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 104 | uint32_t ptr : 26; |
1db8abb1 PB |
105 | }; |
106 | ||
8b795765 MT |
107 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
108 | ||
03f49957 | 109 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 110 | #define ADDR_SPACE_BITS 64 |
03f49957 | 111 | |
026736ce | 112 | #define P_L2_BITS 9 |
03f49957 PB |
113 | #define P_L2_SIZE (1 << P_L2_BITS) |
114 | ||
115 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
116 | ||
117 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 118 | |
53cb28cb | 119 | typedef struct PhysPageMap { |
79e2b9ae PB |
120 | struct rcu_head rcu; |
121 | ||
53cb28cb MA |
122 | unsigned sections_nb; |
123 | unsigned sections_nb_alloc; | |
124 | unsigned nodes_nb; | |
125 | unsigned nodes_nb_alloc; | |
126 | Node *nodes; | |
127 | MemoryRegionSection *sections; | |
128 | } PhysPageMap; | |
129 | ||
1db8abb1 | 130 | struct AddressSpaceDispatch { |
729633c2 | 131 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
132 | /* This is a multi-level map on the physical address space. |
133 | * The bottom level has pointers to MemoryRegionSections. | |
134 | */ | |
135 | PhysPageEntry phys_map; | |
53cb28cb | 136 | PhysPageMap map; |
1db8abb1 PB |
137 | }; |
138 | ||
90260c6c JK |
139 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
140 | typedef struct subpage_t { | |
141 | MemoryRegion iomem; | |
16620684 | 142 | FlatView *fv; |
90260c6c | 143 | hwaddr base; |
2615fabd | 144 | uint16_t sub_section[]; |
90260c6c JK |
145 | } subpage_t; |
146 | ||
b41aac4f | 147 | #define PHYS_SECTION_UNASSIGNED 0 |
5312bd8b | 148 | |
e2eef170 | 149 | static void io_mem_init(void); |
62152b8a | 150 | static void memory_map_init(void); |
9458a9a1 | 151 | static void tcg_log_global_after_sync(MemoryListener *listener); |
09daed84 | 152 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 153 | |
32857f4d PM |
154 | /** |
155 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
156 | * @cpu: the CPU whose AddressSpace this is | |
157 | * @as: the AddressSpace itself | |
158 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
159 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
160 | */ | |
161 | struct CPUAddressSpace { | |
162 | CPUState *cpu; | |
163 | AddressSpace *as; | |
164 | struct AddressSpaceDispatch *memory_dispatch; | |
165 | MemoryListener tcg_as_listener; | |
166 | }; | |
167 | ||
8deaf12c GH |
168 | struct DirtyBitmapSnapshot { |
169 | ram_addr_t start; | |
170 | ram_addr_t end; | |
171 | unsigned long dirty[]; | |
172 | }; | |
173 | ||
53cb28cb | 174 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 175 | { |
101420b8 | 176 | static unsigned alloc_hint = 16; |
53cb28cb | 177 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
c95cfd04 | 178 | map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes); |
53cb28cb | 179 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); |
101420b8 | 180 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 181 | } |
f7bf5461 AK |
182 | } |
183 | ||
db94604b | 184 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
185 | { |
186 | unsigned i; | |
8b795765 | 187 | uint32_t ret; |
db94604b PB |
188 | PhysPageEntry e; |
189 | PhysPageEntry *p; | |
f7bf5461 | 190 | |
53cb28cb | 191 | ret = map->nodes_nb++; |
db94604b | 192 | p = map->nodes[ret]; |
f7bf5461 | 193 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 194 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
195 | |
196 | e.skip = leaf ? 0 : 1; | |
197 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 198 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 199 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 200 | } |
f7bf5461 | 201 | return ret; |
d6f2ea22 AK |
202 | } |
203 | ||
53cb28cb | 204 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
56b15076 | 205 | hwaddr *index, uint64_t *nb, uint16_t leaf, |
2999097b | 206 | int level) |
f7bf5461 AK |
207 | { |
208 | PhysPageEntry *p; | |
03f49957 | 209 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 210 | |
9736e55b | 211 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 212 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 213 | } |
db94604b | 214 | p = map->nodes[lp->ptr]; |
03f49957 | 215 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 216 | |
03f49957 | 217 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 218 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 219 | lp->skip = 0; |
c19e8800 | 220 | lp->ptr = leaf; |
07f07b31 AK |
221 | *index += step; |
222 | *nb -= step; | |
2999097b | 223 | } else { |
53cb28cb | 224 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
225 | } |
226 | ++lp; | |
f7bf5461 AK |
227 | } |
228 | } | |
229 | ||
ac1970fb | 230 | static void phys_page_set(AddressSpaceDispatch *d, |
56b15076 | 231 | hwaddr index, uint64_t nb, |
2999097b | 232 | uint16_t leaf) |
f7bf5461 | 233 | { |
2999097b | 234 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 235 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 236 | |
53cb28cb | 237 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
238 | } |
239 | ||
b35ba30f MT |
240 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
241 | * and update our entry so we can skip it and go directly to the destination. | |
242 | */ | |
efee678d | 243 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
244 | { |
245 | unsigned valid_ptr = P_L2_SIZE; | |
246 | int valid = 0; | |
247 | PhysPageEntry *p; | |
248 | int i; | |
249 | ||
250 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
251 | return; | |
252 | } | |
253 | ||
254 | p = nodes[lp->ptr]; | |
255 | for (i = 0; i < P_L2_SIZE; i++) { | |
256 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
257 | continue; | |
258 | } | |
259 | ||
260 | valid_ptr = i; | |
261 | valid++; | |
262 | if (p[i].skip) { | |
efee678d | 263 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
264 | } |
265 | } | |
266 | ||
267 | /* We can only compress if there's only one child. */ | |
268 | if (valid != 1) { | |
269 | return; | |
270 | } | |
271 | ||
272 | assert(valid_ptr < P_L2_SIZE); | |
273 | ||
274 | /* Don't compress if it won't fit in the # of bits we have. */ | |
526ca236 WY |
275 | if (P_L2_LEVELS >= (1 << 6) && |
276 | lp->skip + p[valid_ptr].skip >= (1 << 6)) { | |
b35ba30f MT |
277 | return; |
278 | } | |
279 | ||
280 | lp->ptr = p[valid_ptr].ptr; | |
281 | if (!p[valid_ptr].skip) { | |
282 | /* If our only child is a leaf, make this a leaf. */ | |
283 | /* By design, we should have made this node a leaf to begin with so we | |
284 | * should never reach here. | |
285 | * But since it's so simple to handle this, let's do it just in case we | |
286 | * change this rule. | |
287 | */ | |
288 | lp->skip = 0; | |
289 | } else { | |
290 | lp->skip += p[valid_ptr].skip; | |
291 | } | |
292 | } | |
293 | ||
8629d3fc | 294 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 295 | { |
b35ba30f | 296 | if (d->phys_map.skip) { |
efee678d | 297 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
298 | } |
299 | } | |
300 | ||
29cb533d FZ |
301 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
302 | hwaddr addr) | |
303 | { | |
304 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
305 | * the section must cover the entire address space. | |
306 | */ | |
258dfaaa | 307 | return int128_gethi(section->size) || |
29cb533d | 308 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 309 | int128_getlo(section->size), addr); |
29cb533d FZ |
310 | } |
311 | ||
003a0cf2 | 312 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 313 | { |
003a0cf2 PX |
314 | PhysPageEntry lp = d->phys_map, *p; |
315 | Node *nodes = d->map.nodes; | |
316 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 317 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 318 | int i; |
f1f6e3b8 | 319 | |
9736e55b | 320 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 321 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 322 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 323 | } |
9affd6fc | 324 | p = nodes[lp.ptr]; |
03f49957 | 325 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 326 | } |
b35ba30f | 327 | |
29cb533d | 328 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
329 | return §ions[lp.ptr]; |
330 | } else { | |
331 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
332 | } | |
f3705d53 AK |
333 | } |
334 | ||
79e2b9ae | 335 | /* Called from RCU critical section */ |
c7086b4a | 336 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
337 | hwaddr addr, |
338 | bool resolve_subpage) | |
9f029603 | 339 | { |
d73415a3 | 340 | MemoryRegionSection *section = qatomic_read(&d->mru_section); |
90260c6c JK |
341 | subpage_t *subpage; |
342 | ||
07c114bb PB |
343 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || |
344 | !section_covers_addr(section, addr)) { | |
003a0cf2 | 345 | section = phys_page_find(d, addr); |
d73415a3 | 346 | qatomic_set(&d->mru_section, section); |
729633c2 | 347 | } |
90260c6c JK |
348 | if (resolve_subpage && section->mr->subpage) { |
349 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 350 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
351 | } |
352 | return section; | |
9f029603 JK |
353 | } |
354 | ||
79e2b9ae | 355 | /* Called from RCU critical section */ |
90260c6c | 356 | static MemoryRegionSection * |
c7086b4a | 357 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 358 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
359 | { |
360 | MemoryRegionSection *section; | |
965eb2fc | 361 | MemoryRegion *mr; |
a87f3954 | 362 | Int128 diff; |
149f54b5 | 363 | |
c7086b4a | 364 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
365 | /* Compute offset within MemoryRegionSection */ |
366 | addr -= section->offset_within_address_space; | |
367 | ||
368 | /* Compute offset within MemoryRegion */ | |
369 | *xlat = addr + section->offset_within_region; | |
370 | ||
965eb2fc | 371 | mr = section->mr; |
b242e0e0 PB |
372 | |
373 | /* MMIO registers can be expected to perform full-width accesses based only | |
374 | * on their address, without considering adjacent registers that could | |
375 | * decode to completely different MemoryRegions. When such registers | |
376 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
377 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
378 | * here. | |
379 | * | |
380 | * If the length is small (as is the case for address_space_ldl/stl), | |
381 | * everything works fine. If the incoming length is large, however, | |
382 | * the caller really has to do the clamping through memory_access_size. | |
383 | */ | |
965eb2fc | 384 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 385 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
386 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
387 | } | |
149f54b5 PB |
388 | return section; |
389 | } | |
90260c6c | 390 | |
a411c84b PB |
391 | /** |
392 | * address_space_translate_iommu - translate an address through an IOMMU | |
393 | * memory region and then through the target address space. | |
394 | * | |
395 | * @iommu_mr: the IOMMU memory region that we start the translation from | |
396 | * @addr: the address to be translated through the MMU | |
397 | * @xlat: the translated address offset within the destination memory region. | |
398 | * It cannot be %NULL. | |
399 | * @plen_out: valid read/write length of the translated address. It | |
400 | * cannot be %NULL. | |
401 | * @page_mask_out: page mask for the translated address. This | |
402 | * should only be meaningful for IOMMU translated | |
403 | * addresses, since there may be huge pages that this bit | |
404 | * would tell. It can be %NULL if we don't care about it. | |
405 | * @is_write: whether the translation operation is for write | |
406 | * @is_mmio: whether this can be MMIO, set true if it can | |
407 | * @target_as: the address space targeted by the IOMMU | |
2f7b009c | 408 | * @attrs: transaction attributes |
a411c84b PB |
409 | * |
410 | * This function is called from RCU critical section. It is the common | |
411 | * part of flatview_do_translate and address_space_translate_cached. | |
412 | */ | |
413 | static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr, | |
414 | hwaddr *xlat, | |
415 | hwaddr *plen_out, | |
416 | hwaddr *page_mask_out, | |
417 | bool is_write, | |
418 | bool is_mmio, | |
2f7b009c PM |
419 | AddressSpace **target_as, |
420 | MemTxAttrs attrs) | |
a411c84b PB |
421 | { |
422 | MemoryRegionSection *section; | |
423 | hwaddr page_mask = (hwaddr)-1; | |
424 | ||
425 | do { | |
426 | hwaddr addr = *xlat; | |
427 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
2c91bcf2 PM |
428 | int iommu_idx = 0; |
429 | IOMMUTLBEntry iotlb; | |
430 | ||
431 | if (imrc->attrs_to_index) { | |
432 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
433 | } | |
434 | ||
435 | iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
436 | IOMMU_WO : IOMMU_RO, iommu_idx); | |
a411c84b PB |
437 | |
438 | if (!(iotlb.perm & (1 << is_write))) { | |
439 | goto unassigned; | |
440 | } | |
441 | ||
442 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
443 | | (addr & iotlb.addr_mask)); | |
444 | page_mask &= iotlb.addr_mask; | |
445 | *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1); | |
446 | *target_as = iotlb.target_as; | |
447 | ||
448 | section = address_space_translate_internal( | |
449 | address_space_to_dispatch(iotlb.target_as), addr, xlat, | |
450 | plen_out, is_mmio); | |
451 | ||
452 | iommu_mr = memory_region_get_iommu(section->mr); | |
453 | } while (unlikely(iommu_mr)); | |
454 | ||
455 | if (page_mask_out) { | |
456 | *page_mask_out = page_mask; | |
457 | } | |
458 | return *section; | |
459 | ||
460 | unassigned: | |
461 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
462 | } | |
463 | ||
d5e5fafd PX |
464 | /** |
465 | * flatview_do_translate - translate an address in FlatView | |
466 | * | |
467 | * @fv: the flat view that we want to translate on | |
468 | * @addr: the address to be translated in above address space | |
469 | * @xlat: the translated address offset within memory region. It | |
470 | * cannot be @NULL. | |
471 | * @plen_out: valid read/write length of the translated address. It | |
472 | * can be @NULL when we don't care about it. | |
473 | * @page_mask_out: page mask for the translated address. This | |
474 | * should only be meaningful for IOMMU translated | |
475 | * addresses, since there may be huge pages that this bit | |
476 | * would tell. It can be @NULL if we don't care about it. | |
477 | * @is_write: whether the translation operation is for write | |
478 | * @is_mmio: whether this can be MMIO, set true if it can | |
ad2804d9 | 479 | * @target_as: the address space targeted by the IOMMU |
49e14aa8 | 480 | * @attrs: memory transaction attributes |
d5e5fafd PX |
481 | * |
482 | * This function is called from RCU critical section | |
483 | */ | |
16620684 AK |
484 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
485 | hwaddr addr, | |
486 | hwaddr *xlat, | |
d5e5fafd PX |
487 | hwaddr *plen_out, |
488 | hwaddr *page_mask_out, | |
16620684 AK |
489 | bool is_write, |
490 | bool is_mmio, | |
49e14aa8 PM |
491 | AddressSpace **target_as, |
492 | MemTxAttrs attrs) | |
052c8fa9 | 493 | { |
052c8fa9 | 494 | MemoryRegionSection *section; |
3df9d748 | 495 | IOMMUMemoryRegion *iommu_mr; |
d5e5fafd PX |
496 | hwaddr plen = (hwaddr)(-1); |
497 | ||
ad2804d9 PB |
498 | if (!plen_out) { |
499 | plen_out = &plen; | |
d5e5fafd | 500 | } |
052c8fa9 | 501 | |
a411c84b PB |
502 | section = address_space_translate_internal( |
503 | flatview_to_dispatch(fv), addr, xlat, | |
504 | plen_out, is_mmio); | |
052c8fa9 | 505 | |
a411c84b PB |
506 | iommu_mr = memory_region_get_iommu(section->mr); |
507 | if (unlikely(iommu_mr)) { | |
508 | return address_space_translate_iommu(iommu_mr, xlat, | |
509 | plen_out, page_mask_out, | |
510 | is_write, is_mmio, | |
2f7b009c | 511 | target_as, attrs); |
052c8fa9 | 512 | } |
d5e5fafd | 513 | if (page_mask_out) { |
a411c84b PB |
514 | /* Not behind an IOMMU, use default page size. */ |
515 | *page_mask_out = ~TARGET_PAGE_MASK; | |
d5e5fafd PX |
516 | } |
517 | ||
a764040c | 518 | return *section; |
052c8fa9 JW |
519 | } |
520 | ||
521 | /* Called from RCU critical section */ | |
a764040c | 522 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
7446eb07 | 523 | bool is_write, MemTxAttrs attrs) |
90260c6c | 524 | { |
a764040c | 525 | MemoryRegionSection section; |
076a93d7 | 526 | hwaddr xlat, page_mask; |
30951157 | 527 | |
076a93d7 PX |
528 | /* |
529 | * This can never be MMIO, and we don't really care about plen, | |
530 | * but page mask. | |
531 | */ | |
532 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
49e14aa8 PM |
533 | NULL, &page_mask, is_write, false, &as, |
534 | attrs); | |
30951157 | 535 | |
a764040c PX |
536 | /* Illegal translation */ |
537 | if (section.mr == &io_mem_unassigned) { | |
538 | goto iotlb_fail; | |
539 | } | |
30951157 | 540 | |
a764040c PX |
541 | /* Convert memory region offset into address space offset */ |
542 | xlat += section.offset_within_address_space - | |
543 | section.offset_within_region; | |
544 | ||
a764040c | 545 | return (IOMMUTLBEntry) { |
e76bb18f | 546 | .target_as = as, |
076a93d7 PX |
547 | .iova = addr & ~page_mask, |
548 | .translated_addr = xlat & ~page_mask, | |
549 | .addr_mask = page_mask, | |
a764040c PX |
550 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ |
551 | .perm = IOMMU_RW, | |
552 | }; | |
553 | ||
554 | iotlb_fail: | |
555 | return (IOMMUTLBEntry) {0}; | |
556 | } | |
557 | ||
558 | /* Called from RCU critical section */ | |
16620684 | 559 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
efa99a2f PM |
560 | hwaddr *plen, bool is_write, |
561 | MemTxAttrs attrs) | |
a764040c PX |
562 | { |
563 | MemoryRegion *mr; | |
564 | MemoryRegionSection section; | |
16620684 | 565 | AddressSpace *as = NULL; |
a764040c PX |
566 | |
567 | /* This can be MMIO, so setup MMIO bit. */ | |
d5e5fafd | 568 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, |
49e14aa8 | 569 | is_write, true, &as, attrs); |
a764040c PX |
570 | mr = section.mr; |
571 | ||
fe680d0d | 572 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 573 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 574 | *plen = MIN(page, *plen); |
a87f3954 PB |
575 | } |
576 | ||
30951157 | 577 | return mr; |
90260c6c JK |
578 | } |
579 | ||
1f871c5e PM |
580 | typedef struct TCGIOMMUNotifier { |
581 | IOMMUNotifier n; | |
582 | MemoryRegion *mr; | |
583 | CPUState *cpu; | |
584 | int iommu_idx; | |
585 | bool active; | |
586 | } TCGIOMMUNotifier; | |
587 | ||
588 | static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) | |
589 | { | |
590 | TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n); | |
591 | ||
592 | if (!notifier->active) { | |
593 | return; | |
594 | } | |
595 | tlb_flush(notifier->cpu); | |
596 | notifier->active = false; | |
597 | /* We leave the notifier struct on the list to avoid reallocating it later. | |
598 | * Generally the number of IOMMUs a CPU deals with will be small. | |
599 | * In any case we can't unregister the iommu notifier from a notify | |
600 | * callback. | |
601 | */ | |
602 | } | |
603 | ||
604 | static void tcg_register_iommu_notifier(CPUState *cpu, | |
605 | IOMMUMemoryRegion *iommu_mr, | |
606 | int iommu_idx) | |
607 | { | |
608 | /* Make sure this CPU has an IOMMU notifier registered for this | |
609 | * IOMMU/IOMMU index combination, so that we can flush its TLB | |
610 | * when the IOMMU tells us the mappings we've cached have changed. | |
611 | */ | |
612 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
bbf90191 | 613 | TCGIOMMUNotifier *notifier = NULL; |
805d4496 | 614 | int i; |
1f871c5e PM |
615 | |
616 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 617 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e PM |
618 | if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { |
619 | break; | |
620 | } | |
621 | } | |
622 | if (i == cpu->iommu_notifiers->len) { | |
623 | /* Not found, add a new entry at the end of the array */ | |
624 | cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); | |
5601be3b PM |
625 | notifier = g_new0(TCGIOMMUNotifier, 1); |
626 | g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier; | |
1f871c5e PM |
627 | |
628 | notifier->mr = mr; | |
629 | notifier->iommu_idx = iommu_idx; | |
630 | notifier->cpu = cpu; | |
631 | /* Rather than trying to register interest in the specific part | |
632 | * of the iommu's address space that we've accessed and then | |
633 | * expand it later as subsequent accesses touch more of it, we | |
634 | * just register interest in the whole thing, on the assumption | |
635 | * that iommu reconfiguration will be rare. | |
636 | */ | |
637 | iommu_notifier_init(¬ifier->n, | |
638 | tcg_iommu_unmap_notify, | |
639 | IOMMU_NOTIFIER_UNMAP, | |
640 | 0, | |
641 | HWADDR_MAX, | |
642 | iommu_idx); | |
805d4496 MA |
643 | memory_region_register_iommu_notifier(notifier->mr, ¬ifier->n, |
644 | &error_fatal); | |
1f871c5e PM |
645 | } |
646 | ||
647 | if (!notifier->active) { | |
648 | notifier->active = true; | |
649 | } | |
650 | } | |
651 | ||
d9f24bf5 | 652 | void tcg_iommu_free_notifier_list(CPUState *cpu) |
1f871c5e PM |
653 | { |
654 | /* Destroy the CPU's notifier list */ | |
655 | int i; | |
656 | TCGIOMMUNotifier *notifier; | |
657 | ||
658 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 659 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e | 660 | memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); |
5601be3b | 661 | g_free(notifier); |
1f871c5e PM |
662 | } |
663 | g_array_free(cpu->iommu_notifiers, true); | |
664 | } | |
665 | ||
d9f24bf5 PB |
666 | void tcg_iommu_init_notifier_list(CPUState *cpu) |
667 | { | |
668 | cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *)); | |
669 | } | |
670 | ||
79e2b9ae | 671 | /* Called from RCU critical section */ |
90260c6c | 672 | MemoryRegionSection * |
418ade78 | 673 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr, |
1f871c5e PM |
674 | hwaddr *xlat, hwaddr *plen, |
675 | MemTxAttrs attrs, int *prot) | |
90260c6c | 676 | { |
30951157 | 677 | MemoryRegionSection *section; |
1f871c5e PM |
678 | IOMMUMemoryRegion *iommu_mr; |
679 | IOMMUMemoryRegionClass *imrc; | |
680 | IOMMUTLBEntry iotlb; | |
681 | int iommu_idx; | |
418ade78 | 682 | hwaddr addr = orig_addr; |
d73415a3 SH |
683 | AddressSpaceDispatch *d = |
684 | qatomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); | |
d7898cda | 685 | |
1f871c5e PM |
686 | for (;;) { |
687 | section = address_space_translate_internal(d, addr, &addr, plen, false); | |
688 | ||
689 | iommu_mr = memory_region_get_iommu(section->mr); | |
690 | if (!iommu_mr) { | |
691 | break; | |
692 | } | |
693 | ||
694 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
695 | ||
696 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
697 | tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); | |
698 | /* We need all the permissions, so pass IOMMU_NONE so the IOMMU | |
699 | * doesn't short-cut its translation table walk. | |
700 | */ | |
701 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); | |
702 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
703 | | (addr & iotlb.addr_mask)); | |
704 | /* Update the caller's prot bits to remove permissions the IOMMU | |
705 | * is giving us a failure response for. If we get down to no | |
706 | * permissions left at all we can give up now. | |
707 | */ | |
708 | if (!(iotlb.perm & IOMMU_RO)) { | |
709 | *prot &= ~(PAGE_READ | PAGE_EXEC); | |
710 | } | |
711 | if (!(iotlb.perm & IOMMU_WO)) { | |
712 | *prot &= ~PAGE_WRITE; | |
713 | } | |
714 | ||
715 | if (!*prot) { | |
716 | goto translate_fail; | |
717 | } | |
718 | ||
719 | d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as)); | |
720 | } | |
30951157 | 721 | |
3df9d748 | 722 | assert(!memory_region_is_iommu(section->mr)); |
1f871c5e | 723 | *xlat = addr; |
30951157 | 724 | return section; |
1f871c5e PM |
725 | |
726 | translate_fail: | |
418ade78 RH |
727 | /* |
728 | * We should be given a page-aligned address -- certainly | |
729 | * tlb_set_page_with_attrs() does so. The page offset of xlat | |
730 | * is used to index sections[], and PHYS_SECTION_UNASSIGNED = 0. | |
731 | * The page portion of xlat will be logged by memory_region_access_valid() | |
732 | * when this memory access is rejected, so use the original untranslated | |
733 | * physical address. | |
734 | */ | |
735 | assert((orig_addr & ~TARGET_PAGE_MASK) == 0); | |
736 | *xlat = orig_addr; | |
1f871c5e | 737 | return &d->map.sections[PHYS_SECTION_UNASSIGNED]; |
90260c6c | 738 | } |
1a1562f5 | 739 | |
80ceb07a PX |
740 | void cpu_address_space_init(CPUState *cpu, int asidx, |
741 | const char *prefix, MemoryRegion *mr) | |
09daed84 | 742 | { |
12ebc9a7 | 743 | CPUAddressSpace *newas; |
80ceb07a | 744 | AddressSpace *as = g_new0(AddressSpace, 1); |
87a621d8 | 745 | char *as_name; |
80ceb07a PX |
746 | |
747 | assert(mr); | |
87a621d8 PX |
748 | as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index); |
749 | address_space_init(as, mr, as_name); | |
750 | g_free(as_name); | |
12ebc9a7 PM |
751 | |
752 | /* Target code should have set num_ases before calling us */ | |
753 | assert(asidx < cpu->num_ases); | |
754 | ||
56943e8c PM |
755 | if (asidx == 0) { |
756 | /* address space 0 gets the convenience alias */ | |
757 | cpu->as = as; | |
758 | } | |
759 | ||
12ebc9a7 PM |
760 | /* KVM cannot currently support multiple address spaces. */ |
761 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 762 | |
12ebc9a7 PM |
763 | if (!cpu->cpu_ases) { |
764 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 765 | } |
32857f4d | 766 | |
12ebc9a7 PM |
767 | newas = &cpu->cpu_ases[asidx]; |
768 | newas->cpu = cpu; | |
769 | newas->as = as; | |
56943e8c | 770 | if (tcg_enabled()) { |
9458a9a1 | 771 | newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync; |
12ebc9a7 | 772 | newas->tcg_as_listener.commit = tcg_commit; |
142518bd | 773 | newas->tcg_as_listener.name = "tcg"; |
12ebc9a7 | 774 | memory_listener_register(&newas->tcg_as_listener, as); |
56943e8c | 775 | } |
09daed84 | 776 | } |
651a5bc0 PM |
777 | |
778 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
779 | { | |
780 | /* Return the AddressSpace corresponding to the specified index */ | |
781 | return cpu->cpu_ases[asidx].as; | |
782 | } | |
8bca9a03 | 783 | |
0dc3f44a | 784 | /* Called from RCU critical section */ |
041603fe PB |
785 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
786 | { | |
787 | RAMBlock *block; | |
788 | ||
d73415a3 | 789 | block = qatomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 790 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 791 | return block; |
041603fe | 792 | } |
99e15582 | 793 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 794 | if (addr - block->offset < block->max_length) { |
041603fe PB |
795 | goto found; |
796 | } | |
797 | } | |
798 | ||
799 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
800 | abort(); | |
801 | ||
802 | found: | |
43771539 PB |
803 | /* It is safe to write mru_block outside the iothread lock. This |
804 | * is what happens: | |
805 | * | |
806 | * mru_block = xxx | |
807 | * rcu_read_unlock() | |
808 | * xxx removed from list | |
809 | * rcu_read_lock() | |
810 | * read mru_block | |
811 | * mru_block = NULL; | |
812 | * call_rcu(reclaim_ramblock, xxx); | |
813 | * rcu_read_unlock() | |
814 | * | |
d73415a3 | 815 | * qatomic_rcu_set is not needed here. The block was already published |
43771539 PB |
816 | * when it was placed into the list. Here we're just making an extra |
817 | * copy of the pointer. | |
818 | */ | |
041603fe PB |
819 | ram_list.mru_block = block; |
820 | return block; | |
821 | } | |
822 | ||
a2f4d5be | 823 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 824 | { |
9a13565d | 825 | CPUState *cpu; |
041603fe | 826 | ram_addr_t start1; |
a2f4d5be JQ |
827 | RAMBlock *block; |
828 | ram_addr_t end; | |
829 | ||
f28d0dfd | 830 | assert(tcg_enabled()); |
a2f4d5be JQ |
831 | end = TARGET_PAGE_ALIGN(start + length); |
832 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 833 | |
694ea274 | 834 | RCU_READ_LOCK_GUARD(); |
041603fe PB |
835 | block = qemu_get_ram_block(start); |
836 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 837 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
838 | CPU_FOREACH(cpu) { |
839 | tlb_reset_dirty(cpu, start1, length); | |
840 | } | |
d24981d3 JQ |
841 | } |
842 | ||
5579c7f3 | 843 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
844 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
845 | ram_addr_t length, | |
846 | unsigned client) | |
1ccde1cb | 847 | { |
5b82b703 | 848 | DirtyMemoryBlocks *blocks; |
25aa6b37 | 849 | unsigned long end, page, start_page; |
5b82b703 | 850 | bool dirty = false; |
077874e0 PX |
851 | RAMBlock *ramblock; |
852 | uint64_t mr_offset, mr_size; | |
03eebc9e SH |
853 | |
854 | if (length == 0) { | |
855 | return false; | |
856 | } | |
f23db169 | 857 | |
03eebc9e | 858 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
25aa6b37 MB |
859 | start_page = start >> TARGET_PAGE_BITS; |
860 | page = start_page; | |
5b82b703 | 861 | |
694ea274 | 862 | WITH_RCU_READ_LOCK_GUARD() { |
d73415a3 | 863 | blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); |
694ea274 DDAG |
864 | ramblock = qemu_get_ram_block(start); |
865 | /* Range sanity check on the ramblock */ | |
866 | assert(start >= ramblock->offset && | |
867 | start + length <= ramblock->offset + ramblock->used_length); | |
5b82b703 | 868 | |
694ea274 DDAG |
869 | while (page < end) { |
870 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
871 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
872 | unsigned long num = MIN(end - page, | |
873 | DIRTY_MEMORY_BLOCK_SIZE - offset); | |
5b82b703 | 874 | |
694ea274 DDAG |
875 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], |
876 | offset, num); | |
877 | page += num; | |
878 | } | |
5b82b703 | 879 | |
25aa6b37 MB |
880 | mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset; |
881 | mr_size = (end - start_page) << TARGET_PAGE_BITS; | |
694ea274 | 882 | memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size); |
5b82b703 SH |
883 | } |
884 | ||
03eebc9e | 885 | if (dirty && tcg_enabled()) { |
a2f4d5be | 886 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 887 | } |
03eebc9e SH |
888 | |
889 | return dirty; | |
1ccde1cb FB |
890 | } |
891 | ||
8deaf12c | 892 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
5dea4079 | 893 | (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client) |
8deaf12c GH |
894 | { |
895 | DirtyMemoryBlocks *blocks; | |
5dea4079 | 896 | ram_addr_t start = memory_region_get_ram_addr(mr) + offset; |
8deaf12c GH |
897 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); |
898 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
899 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
900 | DirtyBitmapSnapshot *snap; | |
901 | unsigned long page, end, dest; | |
902 | ||
903 | snap = g_malloc0(sizeof(*snap) + | |
904 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
905 | snap->start = first; | |
906 | snap->end = last; | |
907 | ||
908 | page = first >> TARGET_PAGE_BITS; | |
909 | end = last >> TARGET_PAGE_BITS; | |
910 | dest = 0; | |
911 | ||
694ea274 | 912 | WITH_RCU_READ_LOCK_GUARD() { |
d73415a3 | 913 | blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); |
8deaf12c | 914 | |
694ea274 DDAG |
915 | while (page < end) { |
916 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
917 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
918 | unsigned long num = MIN(end - page, | |
919 | DIRTY_MEMORY_BLOCK_SIZE - offset); | |
8deaf12c | 920 | |
694ea274 DDAG |
921 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); |
922 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
923 | offset >>= BITS_PER_LEVEL; | |
8deaf12c | 924 | |
694ea274 DDAG |
925 | bitmap_copy_and_clear_atomic(snap->dirty + dest, |
926 | blocks->blocks[idx] + offset, | |
927 | num); | |
928 | page += num; | |
929 | dest += num >> BITS_PER_LEVEL; | |
930 | } | |
8deaf12c GH |
931 | } |
932 | ||
8deaf12c GH |
933 | if (tcg_enabled()) { |
934 | tlb_reset_dirty_range_all(start, length); | |
935 | } | |
936 | ||
077874e0 PX |
937 | memory_region_clear_dirty_bitmap(mr, offset, length); |
938 | ||
8deaf12c GH |
939 | return snap; |
940 | } | |
941 | ||
942 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
943 | ram_addr_t start, | |
944 | ram_addr_t length) | |
945 | { | |
946 | unsigned long page, end; | |
947 | ||
948 | assert(start >= snap->start); | |
949 | assert(start + length <= snap->end); | |
950 | ||
951 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
952 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
953 | ||
954 | while (page < end) { | |
955 | if (test_bit(page, snap->dirty)) { | |
956 | return true; | |
957 | } | |
958 | page++; | |
959 | } | |
960 | return false; | |
961 | } | |
962 | ||
79e2b9ae | 963 | /* Called from RCU critical section */ |
bb0e627a | 964 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
8f5db641 | 965 | MemoryRegionSection *section) |
e5548617 | 966 | { |
8f5db641 RH |
967 | AddressSpaceDispatch *d = flatview_to_dispatch(section->fv); |
968 | return section - d->map.sections; | |
e5548617 | 969 | } |
8da3ff18 | 970 | |
b797ab1a WY |
971 | static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, |
972 | uint16_t section); | |
16620684 | 973 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 974 | |
53cb28cb MA |
975 | static uint16_t phys_section_add(PhysPageMap *map, |
976 | MemoryRegionSection *section) | |
5312bd8b | 977 | { |
68f3f65b PB |
978 | /* The physical section number is ORed with a page-aligned |
979 | * pointer to produce the iotlb entries. Thus it should | |
980 | * never overflow into the page-aligned value. | |
981 | */ | |
53cb28cb | 982 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 983 | |
53cb28cb MA |
984 | if (map->sections_nb == map->sections_nb_alloc) { |
985 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
986 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
987 | map->sections_nb_alloc); | |
5312bd8b | 988 | } |
53cb28cb | 989 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 990 | memory_region_ref(section->mr); |
53cb28cb | 991 | return map->sections_nb++; |
5312bd8b AK |
992 | } |
993 | ||
058bc4b5 PB |
994 | static void phys_section_destroy(MemoryRegion *mr) |
995 | { | |
55b4e80b DS |
996 | bool have_sub_page = mr->subpage; |
997 | ||
dfde4e6e PB |
998 | memory_region_unref(mr); |
999 | ||
55b4e80b | 1000 | if (have_sub_page) { |
058bc4b5 | 1001 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1002 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1003 | g_free(subpage); |
1004 | } | |
1005 | } | |
1006 | ||
6092666e | 1007 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1008 | { |
9affd6fc PB |
1009 | while (map->sections_nb > 0) { |
1010 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1011 | phys_section_destroy(section->mr); |
1012 | } | |
9affd6fc PB |
1013 | g_free(map->sections); |
1014 | g_free(map->nodes); | |
5312bd8b AK |
1015 | } |
1016 | ||
9950322a | 1017 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1018 | { |
9950322a | 1019 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1020 | subpage_t *subpage; |
a8170e5e | 1021 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1022 | & TARGET_PAGE_MASK; |
003a0cf2 | 1023 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1024 | MemoryRegionSection subsection = { |
1025 | .offset_within_address_space = base, | |
052e87b0 | 1026 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1027 | }; |
a8170e5e | 1028 | hwaddr start, end; |
0f0cb164 | 1029 | |
f3705d53 | 1030 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1031 | |
f3705d53 | 1032 | if (!(existing->mr->subpage)) { |
16620684 AK |
1033 | subpage = subpage_init(fv, base); |
1034 | subsection.fv = fv; | |
0f0cb164 | 1035 | subsection.mr = &subpage->iomem; |
ac1970fb | 1036 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1037 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1038 | } else { |
f3705d53 | 1039 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1040 | } |
1041 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1042 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1043 | subpage_register(subpage, start, end, |
1044 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1045 | } |
1046 | ||
1047 | ||
9950322a | 1048 | static void register_multipage(FlatView *fv, |
052e87b0 | 1049 | MemoryRegionSection *section) |
33417e70 | 1050 | { |
9950322a | 1051 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1052 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1053 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1054 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1055 | TARGET_PAGE_BITS)); | |
dd81124b | 1056 | |
733d5ef5 PB |
1057 | assert(num_pages); |
1058 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1059 | } |
1060 | ||
494d1997 WY |
1061 | /* |
1062 | * The range in *section* may look like this: | |
1063 | * | |
1064 | * |s|PPPPPPP|s| | |
1065 | * | |
1066 | * where s stands for subpage and P for page. | |
1067 | */ | |
8629d3fc | 1068 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1069 | { |
494d1997 | 1070 | MemoryRegionSection remain = *section; |
052e87b0 | 1071 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1072 | |
494d1997 WY |
1073 | /* register first subpage */ |
1074 | if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1075 | uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space) | |
1076 | - remain.offset_within_address_space; | |
733d5ef5 | 1077 | |
494d1997 | 1078 | MemoryRegionSection now = remain; |
052e87b0 | 1079 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1080 | register_subpage(fv, &now); |
494d1997 WY |
1081 | if (int128_eq(remain.size, now.size)) { |
1082 | return; | |
1083 | } | |
052e87b0 PB |
1084 | remain.size = int128_sub(remain.size, now.size); |
1085 | remain.offset_within_address_space += int128_get64(now.size); | |
1086 | remain.offset_within_region += int128_get64(now.size); | |
494d1997 WY |
1087 | } |
1088 | ||
1089 | /* register whole pages */ | |
1090 | if (int128_ge(remain.size, page_size)) { | |
1091 | MemoryRegionSection now = remain; | |
1092 | now.size = int128_and(now.size, int128_neg(page_size)); | |
1093 | register_multipage(fv, &now); | |
1094 | if (int128_eq(remain.size, now.size)) { | |
1095 | return; | |
69b67646 | 1096 | } |
494d1997 WY |
1097 | remain.size = int128_sub(remain.size, now.size); |
1098 | remain.offset_within_address_space += int128_get64(now.size); | |
1099 | remain.offset_within_region += int128_get64(now.size); | |
0f0cb164 | 1100 | } |
494d1997 WY |
1101 | |
1102 | /* register last subpage */ | |
1103 | register_subpage(fv, &remain); | |
0f0cb164 AK |
1104 | } |
1105 | ||
62a2744c SY |
1106 | void qemu_flush_coalesced_mmio_buffer(void) |
1107 | { | |
1108 | if (kvm_enabled()) | |
1109 | kvm_flush_coalesced_mmio_buffer(); | |
1110 | } | |
1111 | ||
b2a8658e UD |
1112 | void qemu_mutex_lock_ramlist(void) |
1113 | { | |
1114 | qemu_mutex_lock(&ram_list.mutex); | |
1115 | } | |
1116 | ||
1117 | void qemu_mutex_unlock_ramlist(void) | |
1118 | { | |
1119 | qemu_mutex_unlock(&ram_list.mutex); | |
1120 | } | |
1121 | ||
ca411b7c | 1122 | GString *ram_block_format(void) |
be9b23c4 PX |
1123 | { |
1124 | RAMBlock *block; | |
1125 | char *psize; | |
ca411b7c | 1126 | GString *buf = g_string_new(""); |
be9b23c4 | 1127 | |
694ea274 | 1128 | RCU_READ_LOCK_GUARD(); |
dbc6ae9c TC |
1129 | g_string_append_printf(buf, "%24s %8s %18s %18s %18s %18s %3s\n", |
1130 | "Block Name", "PSize", "Offset", "Used", "Total", | |
1131 | "HVA", "RO"); | |
1132 | ||
be9b23c4 PX |
1133 | RAMBLOCK_FOREACH(block) { |
1134 | psize = size_to_str(block->page_size); | |
ca411b7c | 1135 | g_string_append_printf(buf, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 |
dbc6ae9c TC |
1136 | " 0x%016" PRIx64 " 0x%016" PRIx64 " %3s\n", |
1137 | block->idstr, psize, | |
ca411b7c DB |
1138 | (uint64_t)block->offset, |
1139 | (uint64_t)block->used_length, | |
dbc6ae9c TC |
1140 | (uint64_t)block->max_length, |
1141 | (uint64_t)(uintptr_t)block->host, | |
1142 | block->mr->readonly ? "ro" : "rw"); | |
1143 | ||
be9b23c4 PX |
1144 | g_free(psize); |
1145 | } | |
ca411b7c DB |
1146 | |
1147 | return buf; | |
be9b23c4 PX |
1148 | } |
1149 | ||
905b7ee4 | 1150 | static int find_min_backend_pagesize(Object *obj, void *opaque) |
9c607668 | 1151 | { |
9c607668 AK |
1152 | long *hpsize_min = opaque; |
1153 | ||
1154 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
7d5489e6 DG |
1155 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); |
1156 | long hpsize = host_memory_backend_pagesize(backend); | |
2b108085 | 1157 | |
7d5489e6 | 1158 | if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) { |
0de6e2a3 | 1159 | *hpsize_min = hpsize; |
9c607668 AK |
1160 | } |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
905b7ee4 DH |
1166 | static int find_max_backend_pagesize(Object *obj, void *opaque) |
1167 | { | |
1168 | long *hpsize_max = opaque; | |
1169 | ||
1170 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1171 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); | |
1172 | long hpsize = host_memory_backend_pagesize(backend); | |
1173 | ||
1174 | if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) { | |
1175 | *hpsize_max = hpsize; | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* | |
1183 | * TODO: We assume right now that all mapped host memory backends are | |
1184 | * used as RAM, however some might be used for different purposes. | |
1185 | */ | |
1186 | long qemu_minrampagesize(void) | |
9c607668 AK |
1187 | { |
1188 | long hpsize = LONG_MAX; | |
ad1172d8 | 1189 | Object *memdev_root = object_resolve_path("/objects", NULL); |
9c607668 | 1190 | |
ad1172d8 | 1191 | object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); |
9c607668 AK |
1192 | return hpsize; |
1193 | } | |
905b7ee4 DH |
1194 | |
1195 | long qemu_maxrampagesize(void) | |
1196 | { | |
ad1172d8 | 1197 | long pagesize = 0; |
905b7ee4 DH |
1198 | Object *memdev_root = object_resolve_path("/objects", NULL); |
1199 | ||
ad1172d8 | 1200 | object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize); |
905b7ee4 DH |
1201 | return pagesize; |
1202 | } | |
9c607668 | 1203 | |
d5dbde46 | 1204 | #ifdef CONFIG_POSIX |
d6af99c9 HZ |
1205 | static int64_t get_file_size(int fd) |
1206 | { | |
72d41eb4 SH |
1207 | int64_t size; |
1208 | #if defined(__linux__) | |
1209 | struct stat st; | |
1210 | ||
1211 | if (fstat(fd, &st) < 0) { | |
1212 | return -errno; | |
1213 | } | |
1214 | ||
1215 | /* Special handling for devdax character devices */ | |
1216 | if (S_ISCHR(st.st_mode)) { | |
1217 | g_autofree char *subsystem_path = NULL; | |
1218 | g_autofree char *subsystem = NULL; | |
1219 | ||
1220 | subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem", | |
1221 | major(st.st_rdev), minor(st.st_rdev)); | |
1222 | subsystem = g_file_read_link(subsystem_path, NULL); | |
1223 | ||
1224 | if (subsystem && g_str_has_suffix(subsystem, "/dax")) { | |
1225 | g_autofree char *size_path = NULL; | |
1226 | g_autofree char *size_str = NULL; | |
1227 | ||
1228 | size_path = g_strdup_printf("/sys/dev/char/%d:%d/size", | |
1229 | major(st.st_rdev), minor(st.st_rdev)); | |
1230 | ||
1231 | if (g_file_get_contents(size_path, &size_str, NULL, NULL)) { | |
1232 | return g_ascii_strtoll(size_str, NULL, 0); | |
1233 | } | |
1234 | } | |
1235 | } | |
1236 | #endif /* defined(__linux__) */ | |
1237 | ||
1238 | /* st.st_size may be zero for special files yet lseek(2) works */ | |
1239 | size = lseek(fd, 0, SEEK_END); | |
d6af99c9 HZ |
1240 | if (size < 0) { |
1241 | return -errno; | |
1242 | } | |
1243 | return size; | |
1244 | } | |
1245 | ||
ce317be9 JL |
1246 | static int64_t get_file_align(int fd) |
1247 | { | |
1248 | int64_t align = -1; | |
1249 | #if defined(__linux__) && defined(CONFIG_LIBDAXCTL) | |
1250 | struct stat st; | |
1251 | ||
1252 | if (fstat(fd, &st) < 0) { | |
1253 | return -errno; | |
1254 | } | |
1255 | ||
1256 | /* Special handling for devdax character devices */ | |
1257 | if (S_ISCHR(st.st_mode)) { | |
1258 | g_autofree char *path = NULL; | |
1259 | g_autofree char *rpath = NULL; | |
1260 | struct daxctl_ctx *ctx; | |
1261 | struct daxctl_region *region; | |
1262 | int rc = 0; | |
1263 | ||
1264 | path = g_strdup_printf("/sys/dev/char/%d:%d", | |
1265 | major(st.st_rdev), minor(st.st_rdev)); | |
1266 | rpath = realpath(path, NULL); | |
8efdb7ba PM |
1267 | if (!rpath) { |
1268 | return -errno; | |
1269 | } | |
ce317be9 JL |
1270 | |
1271 | rc = daxctl_new(&ctx); | |
1272 | if (rc) { | |
1273 | return -1; | |
1274 | } | |
1275 | ||
1276 | daxctl_region_foreach(ctx, region) { | |
1277 | if (strstr(rpath, daxctl_region_get_path(region))) { | |
1278 | align = daxctl_region_get_align(region); | |
1279 | break; | |
1280 | } | |
1281 | } | |
1282 | daxctl_unref(ctx); | |
1283 | } | |
1284 | #endif /* defined(__linux__) && defined(CONFIG_LIBDAXCTL) */ | |
1285 | ||
1286 | return align; | |
1287 | } | |
1288 | ||
8d37b030 MAL |
1289 | static int file_ram_open(const char *path, |
1290 | const char *region_name, | |
369d6dc4 | 1291 | bool readonly, |
8d37b030 MAL |
1292 | bool *created, |
1293 | Error **errp) | |
c902760f MT |
1294 | { |
1295 | char *filename; | |
8ca761f6 PF |
1296 | char *sanitized_name; |
1297 | char *c; | |
5c3ece79 | 1298 | int fd = -1; |
c902760f | 1299 | |
8d37b030 | 1300 | *created = false; |
fd97fd44 | 1301 | for (;;) { |
369d6dc4 | 1302 | fd = open(path, readonly ? O_RDONLY : O_RDWR); |
fd97fd44 MA |
1303 | if (fd >= 0) { |
1304 | /* @path names an existing file, use it */ | |
1305 | break; | |
8d31d6b6 | 1306 | } |
fd97fd44 MA |
1307 | if (errno == ENOENT) { |
1308 | /* @path names a file that doesn't exist, create it */ | |
1309 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1310 | if (fd >= 0) { | |
8d37b030 | 1311 | *created = true; |
fd97fd44 MA |
1312 | break; |
1313 | } | |
1314 | } else if (errno == EISDIR) { | |
1315 | /* @path names a directory, create a file there */ | |
1316 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1317 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1318 | for (c = sanitized_name; *c != '\0'; c++) { |
1319 | if (*c == '/') { | |
1320 | *c = '_'; | |
1321 | } | |
1322 | } | |
8ca761f6 | 1323 | |
fd97fd44 MA |
1324 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1325 | sanitized_name); | |
1326 | g_free(sanitized_name); | |
8d31d6b6 | 1327 | |
fd97fd44 MA |
1328 | fd = mkstemp(filename); |
1329 | if (fd >= 0) { | |
1330 | unlink(filename); | |
1331 | g_free(filename); | |
1332 | break; | |
1333 | } | |
1334 | g_free(filename); | |
8d31d6b6 | 1335 | } |
fd97fd44 MA |
1336 | if (errno != EEXIST && errno != EINTR) { |
1337 | error_setg_errno(errp, errno, | |
1338 | "can't open backing store %s for guest RAM", | |
1339 | path); | |
8d37b030 | 1340 | return -1; |
fd97fd44 MA |
1341 | } |
1342 | /* | |
1343 | * Try again on EINTR and EEXIST. The latter happens when | |
1344 | * something else creates the file between our two open(). | |
1345 | */ | |
8d31d6b6 | 1346 | } |
c902760f | 1347 | |
8d37b030 MAL |
1348 | return fd; |
1349 | } | |
1350 | ||
1351 | static void *file_ram_alloc(RAMBlock *block, | |
1352 | ram_addr_t memory, | |
1353 | int fd, | |
369d6dc4 | 1354 | bool readonly, |
8d37b030 | 1355 | bool truncate, |
44a4ff31 | 1356 | off_t offset, |
8d37b030 MAL |
1357 | Error **errp) |
1358 | { | |
b444f5c0 | 1359 | uint32_t qemu_map_flags; |
8d37b030 MAL |
1360 | void *area; |
1361 | ||
863e9621 | 1362 | block->page_size = qemu_fd_getpagesize(fd); |
98376843 HZ |
1363 | if (block->mr->align % block->page_size) { |
1364 | error_setg(errp, "alignment 0x%" PRIx64 | |
1365 | " must be multiples of page size 0x%zx", | |
1366 | block->mr->align, block->page_size); | |
1367 | return NULL; | |
61362b71 DH |
1368 | } else if (block->mr->align && !is_power_of_2(block->mr->align)) { |
1369 | error_setg(errp, "alignment 0x%" PRIx64 | |
1370 | " must be a power of two", block->mr->align); | |
1371 | return NULL; | |
4b870dc4 AG |
1372 | } else if (offset % block->page_size) { |
1373 | error_setg(errp, "offset 0x%" PRIx64 | |
1374 | " must be multiples of page size 0x%zx", | |
1375 | offset, block->page_size); | |
1376 | return NULL; | |
98376843 HZ |
1377 | } |
1378 | block->mr->align = MAX(block->page_size, block->mr->align); | |
8360668e HZ |
1379 | #if defined(__s390x__) |
1380 | if (kvm_enabled()) { | |
1381 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1382 | } | |
1383 | #endif | |
fd97fd44 | 1384 | |
863e9621 | 1385 | if (memory < block->page_size) { |
fd97fd44 | 1386 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1387 | "or larger than page size 0x%zx", |
1388 | memory, block->page_size); | |
8d37b030 | 1389 | return NULL; |
1775f111 HZ |
1390 | } |
1391 | ||
863e9621 | 1392 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1393 | |
1394 | /* | |
1395 | * ftruncate is not supported by hugetlbfs in older | |
1396 | * hosts, so don't bother bailing out on errors. | |
1397 | * If anything goes wrong with it under other filesystems, | |
1398 | * mmap will fail. | |
d6af99c9 HZ |
1399 | * |
1400 | * Do not truncate the non-empty backend file to avoid corrupting | |
1401 | * the existing data in the file. Disabling shrinking is not | |
1402 | * enough. For example, the current vNVDIMM implementation stores | |
1403 | * the guest NVDIMM labels at the end of the backend file. If the | |
1404 | * backend file is later extended, QEMU will not be able to find | |
1405 | * those labels. Therefore, extending the non-empty backend file | |
1406 | * is disabled as well. | |
c902760f | 1407 | */ |
4b870dc4 | 1408 | if (truncate && ftruncate(fd, offset + memory)) { |
9742bf26 | 1409 | perror("ftruncate"); |
7f56e740 | 1410 | } |
c902760f | 1411 | |
b444f5c0 DH |
1412 | qemu_map_flags = readonly ? QEMU_MAP_READONLY : 0; |
1413 | qemu_map_flags |= (block->flags & RAM_SHARED) ? QEMU_MAP_SHARED : 0; | |
1414 | qemu_map_flags |= (block->flags & RAM_PMEM) ? QEMU_MAP_SYNC : 0; | |
8dbe22c6 | 1415 | qemu_map_flags |= (block->flags & RAM_NORESERVE) ? QEMU_MAP_NORESERVE : 0; |
b444f5c0 | 1416 | area = qemu_ram_mmap(fd, memory, block->mr->align, qemu_map_flags, offset); |
c902760f | 1417 | if (area == MAP_FAILED) { |
7f56e740 | 1418 | error_setg_errno(errp, errno, |
fd97fd44 | 1419 | "unable to map backing store for guest RAM"); |
8d37b030 | 1420 | return NULL; |
c902760f | 1421 | } |
ef36fa14 | 1422 | |
04b16653 | 1423 | block->fd = fd; |
4b870dc4 | 1424 | block->fd_offset = offset; |
c902760f MT |
1425 | return area; |
1426 | } | |
1427 | #endif | |
1428 | ||
154cc9ea DDAG |
1429 | /* Allocate space within the ram_addr_t space that governs the |
1430 | * dirty bitmaps. | |
1431 | * Called with the ramlist lock held. | |
1432 | */ | |
d17b5288 | 1433 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1434 | { |
1435 | RAMBlock *block, *next_block; | |
3e837b2c | 1436 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1437 | |
49cd9ac6 SH |
1438 | assert(size != 0); /* it would hand out same offset multiple times */ |
1439 | ||
0dc3f44a | 1440 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1441 | return 0; |
0d53d9fe | 1442 | } |
04b16653 | 1443 | |
99e15582 | 1444 | RAMBLOCK_FOREACH(block) { |
154cc9ea | 1445 | ram_addr_t candidate, next = RAM_ADDR_MAX; |
04b16653 | 1446 | |
801110ab DDAG |
1447 | /* Align blocks to start on a 'long' in the bitmap |
1448 | * which makes the bitmap sync'ing take the fast path. | |
1449 | */ | |
154cc9ea | 1450 | candidate = block->offset + block->max_length; |
801110ab | 1451 | candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS); |
04b16653 | 1452 | |
154cc9ea DDAG |
1453 | /* Search for the closest following block |
1454 | * and find the gap. | |
1455 | */ | |
99e15582 | 1456 | RAMBLOCK_FOREACH(next_block) { |
154cc9ea | 1457 | if (next_block->offset >= candidate) { |
04b16653 AW |
1458 | next = MIN(next, next_block->offset); |
1459 | } | |
1460 | } | |
154cc9ea DDAG |
1461 | |
1462 | /* If it fits remember our place and remember the size | |
1463 | * of gap, but keep going so that we might find a smaller | |
1464 | * gap to fill so avoiding fragmentation. | |
1465 | */ | |
1466 | if (next - candidate >= size && next - candidate < mingap) { | |
1467 | offset = candidate; | |
1468 | mingap = next - candidate; | |
04b16653 | 1469 | } |
154cc9ea DDAG |
1470 | |
1471 | trace_find_ram_offset_loop(size, candidate, offset, next, mingap); | |
04b16653 | 1472 | } |
3e837b2c AW |
1473 | |
1474 | if (offset == RAM_ADDR_MAX) { | |
1475 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1476 | (uint64_t)size); | |
1477 | abort(); | |
1478 | } | |
1479 | ||
154cc9ea DDAG |
1480 | trace_find_ram_offset(size, offset); |
1481 | ||
04b16653 AW |
1482 | return offset; |
1483 | } | |
1484 | ||
c136180c | 1485 | static unsigned long last_ram_page(void) |
d17b5288 AW |
1486 | { |
1487 | RAMBlock *block; | |
1488 | ram_addr_t last = 0; | |
1489 | ||
694ea274 | 1490 | RCU_READ_LOCK_GUARD(); |
99e15582 | 1491 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 1492 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1493 | } |
b8c48993 | 1494 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
1495 | } |
1496 | ||
ddb97f1d JB |
1497 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1498 | { | |
1499 | int ret; | |
ddb97f1d JB |
1500 | |
1501 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1502 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1503 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1504 | if (ret) { | |
1505 | perror("qemu_madvise"); | |
1506 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1507 | "but dump_guest_core=off specified\n"); | |
1508 | } | |
1509 | } | |
1510 | } | |
1511 | ||
422148d3 DDAG |
1512 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1513 | { | |
1514 | return rb->idstr; | |
1515 | } | |
1516 | ||
754cb9c0 YK |
1517 | void *qemu_ram_get_host_addr(RAMBlock *rb) |
1518 | { | |
1519 | return rb->host; | |
1520 | } | |
1521 | ||
1522 | ram_addr_t qemu_ram_get_offset(RAMBlock *rb) | |
1523 | { | |
1524 | return rb->offset; | |
1525 | } | |
1526 | ||
1527 | ram_addr_t qemu_ram_get_used_length(RAMBlock *rb) | |
1528 | { | |
1529 | return rb->used_length; | |
1530 | } | |
1531 | ||
082851a3 DH |
1532 | ram_addr_t qemu_ram_get_max_length(RAMBlock *rb) |
1533 | { | |
1534 | return rb->max_length; | |
1535 | } | |
1536 | ||
463a4ac2 DDAG |
1537 | bool qemu_ram_is_shared(RAMBlock *rb) |
1538 | { | |
1539 | return rb->flags & RAM_SHARED; | |
1540 | } | |
1541 | ||
8dbe22c6 DH |
1542 | bool qemu_ram_is_noreserve(RAMBlock *rb) |
1543 | { | |
1544 | return rb->flags & RAM_NORESERVE; | |
1545 | } | |
1546 | ||
2ce16640 DDAG |
1547 | /* Note: Only set at the start of postcopy */ |
1548 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb) | |
1549 | { | |
1550 | return rb->flags & RAM_UF_ZEROPAGE; | |
1551 | } | |
1552 | ||
1553 | void qemu_ram_set_uf_zeroable(RAMBlock *rb) | |
1554 | { | |
1555 | rb->flags |= RAM_UF_ZEROPAGE; | |
1556 | } | |
1557 | ||
b895de50 CLG |
1558 | bool qemu_ram_is_migratable(RAMBlock *rb) |
1559 | { | |
1560 | return rb->flags & RAM_MIGRATABLE; | |
1561 | } | |
1562 | ||
1563 | void qemu_ram_set_migratable(RAMBlock *rb) | |
1564 | { | |
1565 | rb->flags |= RAM_MIGRATABLE; | |
1566 | } | |
1567 | ||
1568 | void qemu_ram_unset_migratable(RAMBlock *rb) | |
1569 | { | |
1570 | rb->flags &= ~RAM_MIGRATABLE; | |
1571 | } | |
1572 | ||
6d998f3c SH |
1573 | int qemu_ram_get_fd(RAMBlock *rb) |
1574 | { | |
1575 | return rb->fd; | |
1576 | } | |
1577 | ||
ae3a7047 | 1578 | /* Called with iothread lock held. */ |
fa53a0e5 | 1579 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 1580 | { |
fa53a0e5 | 1581 | RAMBlock *block; |
20cfe881 | 1582 | |
c5705a77 AK |
1583 | assert(new_block); |
1584 | assert(!new_block->idstr[0]); | |
84b89d78 | 1585 | |
09e5ab63 AL |
1586 | if (dev) { |
1587 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1588 | if (id) { |
1589 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1590 | g_free(id); |
84b89d78 CM |
1591 | } |
1592 | } | |
1593 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1594 | ||
694ea274 | 1595 | RCU_READ_LOCK_GUARD(); |
99e15582 | 1596 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
1597 | if (block != new_block && |
1598 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
1599 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1600 | new_block->idstr); | |
1601 | abort(); | |
1602 | } | |
1603 | } | |
c5705a77 AK |
1604 | } |
1605 | ||
ae3a7047 | 1606 | /* Called with iothread lock held. */ |
fa53a0e5 | 1607 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 1608 | { |
ae3a7047 MD |
1609 | /* FIXME: arch_init.c assumes that this is not called throughout |
1610 | * migration. Ignore the problem since hot-unplug during migration | |
1611 | * does not work anyway. | |
1612 | */ | |
20cfe881 HT |
1613 | if (block) { |
1614 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1615 | } | |
1616 | } | |
1617 | ||
863e9621 DDAG |
1618 | size_t qemu_ram_pagesize(RAMBlock *rb) |
1619 | { | |
1620 | return rb->page_size; | |
1621 | } | |
1622 | ||
67f11b5c DDAG |
1623 | /* Returns the largest size of page in use */ |
1624 | size_t qemu_ram_pagesize_largest(void) | |
1625 | { | |
1626 | RAMBlock *block; | |
1627 | size_t largest = 0; | |
1628 | ||
99e15582 | 1629 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
1630 | largest = MAX(largest, qemu_ram_pagesize(block)); |
1631 | } | |
1632 | ||
1633 | return largest; | |
1634 | } | |
1635 | ||
8490fc78 LC |
1636 | static int memory_try_enable_merging(void *addr, size_t len) |
1637 | { | |
75cc7f01 | 1638 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1639 | /* disabled by the user */ |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1644 | } | |
1645 | ||
c7c0e724 DH |
1646 | /* |
1647 | * Resizing RAM while migrating can result in the migration being canceled. | |
1648 | * Care has to be taken if the guest might have already detected the memory. | |
62be4e3a MT |
1649 | * |
1650 | * As memory core doesn't know how is memory accessed, it is up to | |
1651 | * resize callback to update device state and/or add assertions to detect | |
1652 | * misuse, if necessary. | |
1653 | */ | |
fa53a0e5 | 1654 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 1655 | { |
8f44304c | 1656 | const ram_addr_t oldsize = block->used_length; |
ce4adc0b DH |
1657 | const ram_addr_t unaligned_size = newsize; |
1658 | ||
62be4e3a MT |
1659 | assert(block); |
1660 | ||
4ed023ce | 1661 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1662 | |
62be4e3a | 1663 | if (block->used_length == newsize) { |
ce4adc0b DH |
1664 | /* |
1665 | * We don't have to resize the ram block (which only knows aligned | |
1666 | * sizes), however, we have to notify if the unaligned size changed. | |
1667 | */ | |
1668 | if (unaligned_size != memory_region_size(block->mr)) { | |
1669 | memory_region_set_size(block->mr, unaligned_size); | |
1670 | if (block->resized) { | |
1671 | block->resized(block->idstr, unaligned_size, block->host); | |
1672 | } | |
1673 | } | |
62be4e3a MT |
1674 | return 0; |
1675 | } | |
1676 | ||
1677 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1678 | error_setg_errno(errp, EINVAL, | |
a3a92908 PG |
1679 | "Size mismatch: %s: 0x" RAM_ADDR_FMT |
1680 | " != 0x" RAM_ADDR_FMT, block->idstr, | |
62be4e3a MT |
1681 | newsize, block->used_length); |
1682 | return -EINVAL; | |
1683 | } | |
1684 | ||
1685 | if (block->max_length < newsize) { | |
1686 | error_setg_errno(errp, EINVAL, | |
a3a92908 | 1687 | "Size too large: %s: 0x" RAM_ADDR_FMT |
62be4e3a MT |
1688 | " > 0x" RAM_ADDR_FMT, block->idstr, |
1689 | newsize, block->max_length); | |
1690 | return -EINVAL; | |
1691 | } | |
1692 | ||
8f44304c DH |
1693 | /* Notify before modifying the ram block and touching the bitmaps. */ |
1694 | if (block->host) { | |
1695 | ram_block_notify_resize(block->host, oldsize, newsize); | |
1696 | } | |
1697 | ||
62be4e3a MT |
1698 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); |
1699 | block->used_length = newsize; | |
58d2707e PB |
1700 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1701 | DIRTY_CLIENTS_ALL); | |
ce4adc0b | 1702 | memory_region_set_size(block->mr, unaligned_size); |
62be4e3a | 1703 | if (block->resized) { |
ce4adc0b | 1704 | block->resized(block->idstr, unaligned_size, block->host); |
62be4e3a MT |
1705 | } |
1706 | return 0; | |
1707 | } | |
1708 | ||
61c490e2 BM |
1709 | /* |
1710 | * Trigger sync on the given ram block for range [start, start + length] | |
1711 | * with the backing store if one is available. | |
1712 | * Otherwise no-op. | |
1713 | * @Note: this is supposed to be a synchronous op. | |
1714 | */ | |
ab7e41e6 | 1715 | void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length) |
61c490e2 | 1716 | { |
61c490e2 BM |
1717 | /* The requested range should fit in within the block range */ |
1718 | g_assert((start + length) <= block->used_length); | |
1719 | ||
1720 | #ifdef CONFIG_LIBPMEM | |
1721 | /* The lack of support for pmem should not block the sync */ | |
1722 | if (ramblock_is_pmem(block)) { | |
5d4c9549 | 1723 | void *addr = ramblock_ptr(block, start); |
61c490e2 BM |
1724 | pmem_persist(addr, length); |
1725 | return; | |
1726 | } | |
1727 | #endif | |
1728 | if (block->fd >= 0) { | |
1729 | /** | |
1730 | * Case there is no support for PMEM or the memory has not been | |
1731 | * specified as persistent (or is not one) - use the msync. | |
1732 | * Less optimal but still achieves the same goal | |
1733 | */ | |
5d4c9549 | 1734 | void *addr = ramblock_ptr(block, start); |
61c490e2 BM |
1735 | if (qemu_msync(addr, length, block->fd)) { |
1736 | warn_report("%s: failed to sync memory range: start: " | |
1737 | RAM_ADDR_FMT " length: " RAM_ADDR_FMT, | |
1738 | __func__, start, length); | |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | ||
5b82b703 SH |
1743 | /* Called with ram_list.mutex held */ |
1744 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1745 | ram_addr_t new_ram_size) | |
1746 | { | |
1747 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1748 | DIRTY_MEMORY_BLOCK_SIZE); | |
1749 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1750 | DIRTY_MEMORY_BLOCK_SIZE); | |
1751 | int i; | |
1752 | ||
1753 | /* Only need to extend if block count increased */ | |
1754 | if (new_num_blocks <= old_num_blocks) { | |
1755 | return; | |
1756 | } | |
1757 | ||
1758 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1759 | DirtyMemoryBlocks *old_blocks; | |
1760 | DirtyMemoryBlocks *new_blocks; | |
1761 | int j; | |
1762 | ||
d73415a3 | 1763 | old_blocks = qatomic_rcu_read(&ram_list.dirty_memory[i]); |
5b82b703 SH |
1764 | new_blocks = g_malloc(sizeof(*new_blocks) + |
1765 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1766 | ||
1767 | if (old_num_blocks) { | |
1768 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1769 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1770 | } | |
1771 | ||
1772 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1773 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1774 | } | |
1775 | ||
d73415a3 | 1776 | qatomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); |
5b82b703 SH |
1777 | |
1778 | if (old_blocks) { | |
1779 | g_free_rcu(old_blocks, rcu); | |
1780 | } | |
1781 | } | |
1782 | } | |
1783 | ||
7ce18ca0 | 1784 | static void ram_block_add(RAMBlock *new_block, Error **errp) |
c5705a77 | 1785 | { |
8dbe22c6 | 1786 | const bool noreserve = qemu_ram_is_noreserve(new_block); |
7ce18ca0 | 1787 | const bool shared = qemu_ram_is_shared(new_block); |
e1c57ab8 | 1788 | RAMBlock *block; |
0d53d9fe | 1789 | RAMBlock *last_block = NULL; |
2152f5ca | 1790 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 1791 | Error *err = NULL; |
2152f5ca | 1792 | |
b8c48993 | 1793 | old_ram_size = last_ram_page(); |
c5705a77 | 1794 | |
b2a8658e | 1795 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 1796 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
1797 | |
1798 | if (!new_block->host) { | |
1799 | if (xen_enabled()) { | |
9b8424d5 | 1800 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
1801 | new_block->mr, &err); |
1802 | if (err) { | |
1803 | error_propagate(errp, err); | |
1804 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1805 | return; |
37aa7a0e | 1806 | } |
e1c57ab8 | 1807 | } else { |
25459eb7 DH |
1808 | new_block->host = qemu_anon_ram_alloc(new_block->max_length, |
1809 | &new_block->mr->align, | |
8dbe22c6 | 1810 | shared, noreserve); |
39228250 | 1811 | if (!new_block->host) { |
ef701d7b HT |
1812 | error_setg_errno(errp, errno, |
1813 | "cannot set up guest memory '%s'", | |
1814 | memory_region_name(new_block->mr)); | |
1815 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1816 | return; |
39228250 | 1817 | } |
9b8424d5 | 1818 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 1819 | } |
c902760f | 1820 | } |
94a6b54f | 1821 | |
dd631697 LZ |
1822 | new_ram_size = MAX(old_ram_size, |
1823 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1824 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 1825 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 1826 | } |
0d53d9fe MD |
1827 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
1828 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1829 | * tail, so save the last element in last_block. | |
1830 | */ | |
99e15582 | 1831 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 1832 | last_block = block; |
9b8424d5 | 1833 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
1834 | break; |
1835 | } | |
1836 | } | |
1837 | if (block) { | |
0dc3f44a | 1838 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 1839 | } else if (last_block) { |
0dc3f44a | 1840 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 1841 | } else { /* list is empty */ |
0dc3f44a | 1842 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 1843 | } |
0d6d3c87 | 1844 | ram_list.mru_block = NULL; |
94a6b54f | 1845 | |
0dc3f44a MD |
1846 | /* Write list before version */ |
1847 | smp_wmb(); | |
f798b07f | 1848 | ram_list.version++; |
b2a8658e | 1849 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1850 | |
9b8424d5 | 1851 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
1852 | new_block->used_length, |
1853 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 1854 | |
a904c911 PB |
1855 | if (new_block->host) { |
1856 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1857 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
a028edea AB |
1858 | /* |
1859 | * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU | |
1860 | * Configure it unless the machine is a qtest server, in which case | |
1861 | * KVM is not used and it may be forked (eg for fuzzing purposes). | |
1862 | */ | |
1863 | if (!qtest_enabled()) { | |
1864 | qemu_madvise(new_block->host, new_block->max_length, | |
1865 | QEMU_MADV_DONTFORK); | |
1866 | } | |
8f44304c DH |
1867 | ram_block_notify_add(new_block->host, new_block->used_length, |
1868 | new_block->max_length); | |
e1c57ab8 | 1869 | } |
94a6b54f | 1870 | } |
e9a1ab19 | 1871 | |
d5dbde46 | 1872 | #ifdef CONFIG_POSIX |
38b3362d | 1873 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
44a4ff31 JR |
1874 | uint32_t ram_flags, int fd, off_t offset, |
1875 | bool readonly, Error **errp) | |
e1c57ab8 PB |
1876 | { |
1877 | RAMBlock *new_block; | |
ef701d7b | 1878 | Error *local_err = NULL; |
ce317be9 | 1879 | int64_t file_size, file_align; |
e1c57ab8 | 1880 | |
a4de8552 | 1881 | /* Just support these ram flags by now. */ |
56918a12 SC |
1882 | assert((ram_flags & ~(RAM_SHARED | RAM_PMEM | RAM_NORESERVE | |
1883 | RAM_PROTECTED)) == 0); | |
a4de8552 | 1884 | |
e1c57ab8 | 1885 | if (xen_enabled()) { |
7f56e740 | 1886 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 1887 | return NULL; |
e1c57ab8 PB |
1888 | } |
1889 | ||
e45e7ae2 MAL |
1890 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
1891 | error_setg(errp, | |
1892 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
1893 | return NULL; | |
1894 | } | |
1895 | ||
4ed023ce | 1896 | size = HOST_PAGE_ALIGN(size); |
8d37b030 | 1897 | file_size = get_file_size(fd); |
4b870dc4 | 1898 | if (file_size > offset && file_size < (offset + size)) { |
c001c3b3 | 1899 | error_setg(errp, "backing store size 0x%" PRIx64 |
8d37b030 | 1900 | " does not match 'size' option 0x" RAM_ADDR_FMT, |
c001c3b3 | 1901 | file_size, size); |
8d37b030 MAL |
1902 | return NULL; |
1903 | } | |
1904 | ||
ce317be9 | 1905 | file_align = get_file_align(fd); |
8f1bdb0e | 1906 | if (file_align > 0 && file_align > mr->align) { |
ce317be9 | 1907 | error_setg(errp, "backing store align 0x%" PRIx64 |
5f509751 | 1908 | " is larger than 'align' option 0x%" PRIx64, |
ce317be9 JL |
1909 | file_align, mr->align); |
1910 | return NULL; | |
1911 | } | |
1912 | ||
e1c57ab8 PB |
1913 | new_block = g_malloc0(sizeof(*new_block)); |
1914 | new_block->mr = mr; | |
9b8424d5 MT |
1915 | new_block->used_length = size; |
1916 | new_block->max_length = size; | |
cbfc0171 | 1917 | new_block->flags = ram_flags; |
369d6dc4 | 1918 | new_block->host = file_ram_alloc(new_block, size, fd, readonly, |
44a4ff31 | 1919 | !file_size, offset, errp); |
7f56e740 PB |
1920 | if (!new_block->host) { |
1921 | g_free(new_block); | |
528f46af | 1922 | return NULL; |
7f56e740 PB |
1923 | } |
1924 | ||
7ce18ca0 | 1925 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
1926 | if (local_err) { |
1927 | g_free(new_block); | |
1928 | error_propagate(errp, local_err); | |
528f46af | 1929 | return NULL; |
ef701d7b | 1930 | } |
528f46af | 1931 | return new_block; |
38b3362d MAL |
1932 | |
1933 | } | |
1934 | ||
1935 | ||
1936 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
cbfc0171 | 1937 | uint32_t ram_flags, const char *mem_path, |
4b870dc4 | 1938 | off_t offset, bool readonly, Error **errp) |
38b3362d MAL |
1939 | { |
1940 | int fd; | |
1941 | bool created; | |
1942 | RAMBlock *block; | |
1943 | ||
369d6dc4 SH |
1944 | fd = file_ram_open(mem_path, memory_region_name(mr), readonly, &created, |
1945 | errp); | |
38b3362d MAL |
1946 | if (fd < 0) { |
1947 | return NULL; | |
1948 | } | |
1949 | ||
4b870dc4 AG |
1950 | block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, offset, readonly, |
1951 | errp); | |
38b3362d MAL |
1952 | if (!block) { |
1953 | if (created) { | |
1954 | unlink(mem_path); | |
1955 | } | |
1956 | close(fd); | |
1957 | return NULL; | |
1958 | } | |
1959 | ||
1960 | return block; | |
e1c57ab8 | 1961 | } |
0b183fc8 | 1962 | #endif |
e1c57ab8 | 1963 | |
62be4e3a | 1964 | static |
528f46af FZ |
1965 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
1966 | void (*resized)(const char*, | |
1967 | uint64_t length, | |
1968 | void *host), | |
ebef62d0 | 1969 | void *host, uint32_t ram_flags, |
528f46af | 1970 | MemoryRegion *mr, Error **errp) |
e1c57ab8 PB |
1971 | { |
1972 | RAMBlock *new_block; | |
ef701d7b | 1973 | Error *local_err = NULL; |
e1c57ab8 | 1974 | |
8dbe22c6 DH |
1975 | assert((ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC | |
1976 | RAM_NORESERVE)) == 0); | |
ebef62d0 DH |
1977 | assert(!host ^ (ram_flags & RAM_PREALLOC)); |
1978 | ||
4ed023ce DDAG |
1979 | size = HOST_PAGE_ALIGN(size); |
1980 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
1981 | new_block = g_malloc0(sizeof(*new_block)); |
1982 | new_block->mr = mr; | |
62be4e3a | 1983 | new_block->resized = resized; |
9b8424d5 MT |
1984 | new_block->used_length = size; |
1985 | new_block->max_length = max_size; | |
62be4e3a | 1986 | assert(max_size >= size); |
e1c57ab8 | 1987 | new_block->fd = -1; |
8e3b0cbb | 1988 | new_block->page_size = qemu_real_host_page_size(); |
e1c57ab8 | 1989 | new_block->host = host; |
ebef62d0 | 1990 | new_block->flags = ram_flags; |
7ce18ca0 | 1991 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
1992 | if (local_err) { |
1993 | g_free(new_block); | |
1994 | error_propagate(errp, local_err); | |
528f46af | 1995 | return NULL; |
ef701d7b | 1996 | } |
528f46af | 1997 | return new_block; |
e1c57ab8 PB |
1998 | } |
1999 | ||
528f46af | 2000 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2001 | MemoryRegion *mr, Error **errp) |
2002 | { | |
ebef62d0 DH |
2003 | return qemu_ram_alloc_internal(size, size, NULL, host, RAM_PREALLOC, mr, |
2004 | errp); | |
62be4e3a MT |
2005 | } |
2006 | ||
ebef62d0 | 2007 | RAMBlock *qemu_ram_alloc(ram_addr_t size, uint32_t ram_flags, |
06329cce | 2008 | MemoryRegion *mr, Error **errp) |
6977dfe6 | 2009 | { |
8dbe22c6 | 2010 | assert((ram_flags & ~(RAM_SHARED | RAM_NORESERVE)) == 0); |
ebef62d0 | 2011 | return qemu_ram_alloc_internal(size, size, NULL, NULL, ram_flags, mr, errp); |
62be4e3a MT |
2012 | } |
2013 | ||
528f46af | 2014 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2015 | void (*resized)(const char*, |
2016 | uint64_t length, | |
2017 | void *host), | |
2018 | MemoryRegion *mr, Error **errp) | |
2019 | { | |
ebef62d0 DH |
2020 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, |
2021 | RAM_RESIZEABLE, mr, errp); | |
6977dfe6 YT |
2022 | } |
2023 | ||
43771539 PB |
2024 | static void reclaim_ramblock(RAMBlock *block) |
2025 | { | |
2026 | if (block->flags & RAM_PREALLOC) { | |
2027 | ; | |
2028 | } else if (xen_enabled()) { | |
2029 | xen_invalidate_map_cache_entry(block->host); | |
2030 | #ifndef _WIN32 | |
2031 | } else if (block->fd >= 0) { | |
53adb9d4 | 2032 | qemu_ram_munmap(block->fd, block->host, block->max_length); |
43771539 PB |
2033 | close(block->fd); |
2034 | #endif | |
2035 | } else { | |
2036 | qemu_anon_ram_free(block->host, block->max_length); | |
2037 | } | |
2038 | g_free(block); | |
2039 | } | |
2040 | ||
f1060c55 | 2041 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2042 | { |
85bc2a15 MAL |
2043 | if (!block) { |
2044 | return; | |
2045 | } | |
2046 | ||
0987d735 | 2047 | if (block->host) { |
8f44304c DH |
2048 | ram_block_notify_remove(block->host, block->used_length, |
2049 | block->max_length); | |
0987d735 PB |
2050 | } |
2051 | ||
b2a8658e | 2052 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2053 | QLIST_REMOVE_RCU(block, next); |
2054 | ram_list.mru_block = NULL; | |
2055 | /* Write list before version */ | |
2056 | smp_wmb(); | |
2057 | ram_list.version++; | |
2058 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2059 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2060 | } |
2061 | ||
cd19cfa2 HY |
2062 | #ifndef _WIN32 |
2063 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2064 | { | |
2065 | RAMBlock *block; | |
2066 | ram_addr_t offset; | |
2067 | int flags; | |
2068 | void *area, *vaddr; | |
2069 | ||
99e15582 | 2070 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2071 | offset = addr - block->offset; |
9b8424d5 | 2072 | if (offset < block->max_length) { |
1240be24 | 2073 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2074 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2075 | ; |
dfeaf2ab MA |
2076 | } else if (xen_enabled()) { |
2077 | abort(); | |
cd19cfa2 HY |
2078 | } else { |
2079 | flags = MAP_FIXED; | |
dbb92eea DH |
2080 | flags |= block->flags & RAM_SHARED ? |
2081 | MAP_SHARED : MAP_PRIVATE; | |
d94e0bc9 | 2082 | flags |= block->flags & RAM_NORESERVE ? MAP_NORESERVE : 0; |
3435f395 | 2083 | if (block->fd >= 0) { |
3435f395 | 2084 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
4b870dc4 | 2085 | flags, block->fd, offset + block->fd_offset); |
cd19cfa2 | 2086 | } else { |
dbb92eea | 2087 | flags |= MAP_ANONYMOUS; |
cd19cfa2 HY |
2088 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2089 | flags, -1, 0); | |
cd19cfa2 HY |
2090 | } |
2091 | if (area != vaddr) { | |
493d89bf AF |
2092 | error_report("Could not remap addr: " |
2093 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "", | |
2094 | length, addr); | |
cd19cfa2 HY |
2095 | exit(1); |
2096 | } | |
8490fc78 | 2097 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2098 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2099 | } |
cd19cfa2 HY |
2100 | } |
2101 | } | |
2102 | } | |
2103 | #endif /* !_WIN32 */ | |
2104 | ||
1b5ec234 | 2105 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2106 | * This should not be used for general purpose DMA. Use address_space_map |
2107 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2108 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2109 | * |
49b24afc | 2110 | * Called within RCU critical section. |
1b5ec234 | 2111 | */ |
0878d0e1 | 2112 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2113 | { |
3655cb9c GA |
2114 | RAMBlock *block = ram_block; |
2115 | ||
2116 | if (block == NULL) { | |
2117 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2118 | addr -= block->offset; |
3655cb9c | 2119 | } |
ae3a7047 MD |
2120 | |
2121 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2122 | /* We need to check if the requested address is in the RAM |
2123 | * because we don't want to map the entire memory in QEMU. | |
2124 | * In that case just map until the end of the page. | |
2125 | */ | |
2126 | if (block->offset == 0) { | |
1ff7c598 | 2127 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2128 | } |
ae3a7047 | 2129 | |
1ff7c598 | 2130 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2131 | } |
0878d0e1 | 2132 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2133 | } |
2134 | ||
0878d0e1 | 2135 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2136 | * but takes a size argument. |
0dc3f44a | 2137 | * |
e81bcda5 | 2138 | * Called within RCU critical section. |
ae3a7047 | 2139 | */ |
3655cb9c | 2140 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2141 | hwaddr *size, bool lock) |
38bee5dc | 2142 | { |
3655cb9c | 2143 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2144 | if (*size == 0) { |
2145 | return NULL; | |
2146 | } | |
e81bcda5 | 2147 | |
3655cb9c GA |
2148 | if (block == NULL) { |
2149 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2150 | addr -= block->offset; |
3655cb9c | 2151 | } |
0878d0e1 | 2152 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2153 | |
2154 | if (xen_enabled() && block->host == NULL) { | |
2155 | /* We need to check if the requested address is in the RAM | |
2156 | * because we don't want to map the entire memory in QEMU. | |
2157 | * In that case just map the requested area. | |
2158 | */ | |
2159 | if (block->offset == 0) { | |
f5aa69bd | 2160 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2161 | } |
2162 | ||
f5aa69bd | 2163 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2164 | } |
e81bcda5 | 2165 | |
0878d0e1 | 2166 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2167 | } |
2168 | ||
f90bb71b DDAG |
2169 | /* Return the offset of a hostpointer within a ramblock */ |
2170 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) | |
2171 | { | |
2172 | ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host; | |
2173 | assert((uintptr_t)host >= (uintptr_t)rb->host); | |
2174 | assert(res < rb->max_length); | |
2175 | ||
2176 | return res; | |
2177 | } | |
2178 | ||
422148d3 DDAG |
2179 | /* |
2180 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2181 | * in that RAMBlock. | |
2182 | * | |
2183 | * ptr: Host pointer to look up | |
2184 | * round_offset: If true round the result offset down to a page boundary | |
2185 | * *ram_addr: set to result ram_addr | |
2186 | * *offset: set to result offset within the RAMBlock | |
2187 | * | |
2188 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2189 | * |
2190 | * By the time this function returns, the returned pointer is not protected | |
2191 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2192 | * does not hold the iothread lock, it must have other means of protecting the | |
2193 | * pointer, such as a reference to the region that includes the incoming | |
2194 | * ram_addr_t. | |
2195 | */ | |
422148d3 | 2196 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2197 | ram_addr_t *offset) |
5579c7f3 | 2198 | { |
94a6b54f PB |
2199 | RAMBlock *block; |
2200 | uint8_t *host = ptr; | |
2201 | ||
868bb33f | 2202 | if (xen_enabled()) { |
f615f396 | 2203 | ram_addr_t ram_addr; |
694ea274 | 2204 | RCU_READ_LOCK_GUARD(); |
f615f396 PB |
2205 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2206 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2207 | if (block) { |
d6b6aec4 | 2208 | *offset = ram_addr - block->offset; |
422148d3 | 2209 | } |
422148d3 | 2210 | return block; |
712c2b41 SS |
2211 | } |
2212 | ||
694ea274 | 2213 | RCU_READ_LOCK_GUARD(); |
d73415a3 | 2214 | block = qatomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 2215 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2216 | goto found; |
2217 | } | |
2218 | ||
99e15582 | 2219 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2220 | /* This case append when the block is not mapped. */ |
2221 | if (block->host == NULL) { | |
2222 | continue; | |
2223 | } | |
9b8424d5 | 2224 | if (host - block->host < block->max_length) { |
23887b79 | 2225 | goto found; |
f471a17e | 2226 | } |
94a6b54f | 2227 | } |
432d268c | 2228 | |
1b5ec234 | 2229 | return NULL; |
23887b79 PB |
2230 | |
2231 | found: | |
422148d3 DDAG |
2232 | *offset = (host - block->host); |
2233 | if (round_offset) { | |
2234 | *offset &= TARGET_PAGE_MASK; | |
2235 | } | |
422148d3 DDAG |
2236 | return block; |
2237 | } | |
2238 | ||
e3dd7493 DDAG |
2239 | /* |
2240 | * Finds the named RAMBlock | |
2241 | * | |
2242 | * name: The name of RAMBlock to find | |
2243 | * | |
2244 | * Returns: RAMBlock (or NULL if not found) | |
2245 | */ | |
2246 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2247 | { | |
2248 | RAMBlock *block; | |
2249 | ||
99e15582 | 2250 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2251 | if (!strcmp(name, block->idstr)) { |
2252 | return block; | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | return NULL; | |
2257 | } | |
2258 | ||
422148d3 DDAG |
2259 | /* Some of the softmmu routines need to translate from a host pointer |
2260 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2261 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2262 | { |
2263 | RAMBlock *block; | |
f615f396 | 2264 | ram_addr_t offset; |
422148d3 | 2265 | |
f615f396 | 2266 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2267 | if (!block) { |
07bdaa41 | 2268 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2269 | } |
2270 | ||
07bdaa41 | 2271 | return block->offset + offset; |
e890261f | 2272 | } |
f471a17e | 2273 | |
97e03465 RH |
2274 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) |
2275 | { | |
2276 | ram_addr_t ram_addr; | |
2277 | ||
2278 | ram_addr = qemu_ram_addr_from_host(ptr); | |
2279 | if (ram_addr == RAM_ADDR_INVALID) { | |
2280 | error_report("Bad ram pointer %p", ptr); | |
2281 | abort(); | |
2282 | } | |
2283 | return ram_addr; | |
2284 | } | |
2285 | ||
b2a44fca | 2286 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, |
a152be43 | 2287 | MemTxAttrs attrs, void *buf, hwaddr len); |
16620684 | 2288 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
a152be43 | 2289 | const void *buf, hwaddr len); |
0c249ff7 | 2290 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, |
eace72b7 | 2291 | bool is_write, MemTxAttrs attrs); |
16620684 | 2292 | |
f25a49e0 PM |
2293 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2294 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2295 | { |
acc9d80b | 2296 | subpage_t *subpage = opaque; |
ff6cff75 | 2297 | uint8_t buf[8]; |
5c9eb028 | 2298 | MemTxResult res; |
791af8c8 | 2299 | |
db7b5426 | 2300 | #if defined(DEBUG_SUBPAGE) |
883f2c59 | 2301 | printf("%s: subpage %p len %u addr " HWADDR_FMT_plx "\n", __func__, |
acc9d80b | 2302 | subpage, len, addr); |
db7b5426 | 2303 | #endif |
16620684 | 2304 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2305 | if (res) { |
2306 | return res; | |
f25a49e0 | 2307 | } |
6d3ede54 PM |
2308 | *data = ldn_p(buf, len); |
2309 | return MEMTX_OK; | |
db7b5426 BS |
2310 | } |
2311 | ||
f25a49e0 PM |
2312 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2313 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2314 | { |
acc9d80b | 2315 | subpage_t *subpage = opaque; |
ff6cff75 | 2316 | uint8_t buf[8]; |
acc9d80b | 2317 | |
db7b5426 | 2318 | #if defined(DEBUG_SUBPAGE) |
883f2c59 | 2319 | printf("%s: subpage %p len %u addr " HWADDR_FMT_plx |
acc9d80b JK |
2320 | " value %"PRIx64"\n", |
2321 | __func__, subpage, len, addr, value); | |
db7b5426 | 2322 | #endif |
6d3ede54 | 2323 | stn_p(buf, len, value); |
16620684 | 2324 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2325 | } |
2326 | ||
c353e4cc | 2327 | static bool subpage_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2328 | unsigned len, bool is_write, |
2329 | MemTxAttrs attrs) | |
c353e4cc | 2330 | { |
acc9d80b | 2331 | subpage_t *subpage = opaque; |
c353e4cc | 2332 | #if defined(DEBUG_SUBPAGE) |
883f2c59 | 2333 | printf("%s: subpage %p %c len %u addr " HWADDR_FMT_plx "\n", |
acc9d80b | 2334 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2335 | #endif |
2336 | ||
16620684 | 2337 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
eace72b7 | 2338 | len, is_write, attrs); |
c353e4cc PB |
2339 | } |
2340 | ||
70c68e44 | 2341 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2342 | .read_with_attrs = subpage_read, |
2343 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2344 | .impl.min_access_size = 1, |
2345 | .impl.max_access_size = 8, | |
2346 | .valid.min_access_size = 1, | |
2347 | .valid.max_access_size = 8, | |
c353e4cc | 2348 | .valid.accepts = subpage_accepts, |
70c68e44 | 2349 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2350 | }; |
2351 | ||
b797ab1a WY |
2352 | static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, |
2353 | uint16_t section) | |
db7b5426 BS |
2354 | { |
2355 | int idx, eidx; | |
2356 | ||
2357 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2358 | return -1; | |
2359 | idx = SUBPAGE_IDX(start); | |
2360 | eidx = SUBPAGE_IDX(end); | |
2361 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2362 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2363 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2364 | #endif |
db7b5426 | 2365 | for (; idx <= eidx; idx++) { |
5312bd8b | 2366 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2367 | } |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
16620684 | 2372 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 2373 | { |
c227f099 | 2374 | subpage_t *mmio; |
db7b5426 | 2375 | |
b797ab1a | 2376 | /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */ |
2615fabd | 2377 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 2378 | mmio->fv = fv; |
1eec614b | 2379 | mmio->base = base; |
2c9b15ca | 2380 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2381 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2382 | mmio->iomem.subpage = true; |
db7b5426 | 2383 | #if defined(DEBUG_SUBPAGE) |
883f2c59 | 2384 | printf("%s: %p base " HWADDR_FMT_plx " len %08x\n", __func__, |
016e9d62 | 2385 | mmio, base, TARGET_PAGE_SIZE); |
db7b5426 | 2386 | #endif |
db7b5426 BS |
2387 | |
2388 | return mmio; | |
2389 | } | |
2390 | ||
16620684 | 2391 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 2392 | { |
16620684 | 2393 | assert(fv); |
5312bd8b | 2394 | MemoryRegionSection section = { |
16620684 | 2395 | .fv = fv, |
5312bd8b AK |
2396 | .mr = mr, |
2397 | .offset_within_address_space = 0, | |
2398 | .offset_within_region = 0, | |
052e87b0 | 2399 | .size = int128_2_64(), |
5312bd8b AK |
2400 | }; |
2401 | ||
53cb28cb | 2402 | return phys_section_add(map, §ion); |
5312bd8b AK |
2403 | } |
2404 | ||
2d54f194 PM |
2405 | MemoryRegionSection *iotlb_to_section(CPUState *cpu, |
2406 | hwaddr index, MemTxAttrs attrs) | |
aa102231 | 2407 | { |
a54c87b6 PM |
2408 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2409 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
d73415a3 | 2410 | AddressSpaceDispatch *d = qatomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2411 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 | 2412 | |
2d54f194 | 2413 | return §ions[index & ~TARGET_PAGE_MASK]; |
aa102231 AK |
2414 | } |
2415 | ||
e9179ce1 AK |
2416 | static void io_mem_init(void) |
2417 | { | |
2c9b15ca | 2418 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2419 | NULL, UINT64_MAX); |
e9179ce1 AK |
2420 | } |
2421 | ||
8629d3fc | 2422 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 2423 | { |
53cb28cb MA |
2424 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2425 | uint16_t n; | |
2426 | ||
16620684 | 2427 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 2428 | assert(n == PHYS_SECTION_UNASSIGNED); |
00752703 | 2429 | |
9736e55b | 2430 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
2431 | |
2432 | return d; | |
00752703 PB |
2433 | } |
2434 | ||
66a6df1d | 2435 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
2436 | { |
2437 | phys_sections_free(&d->map); | |
2438 | g_free(d); | |
2439 | } | |
2440 | ||
9458a9a1 PB |
2441 | static void do_nothing(CPUState *cpu, run_on_cpu_data d) |
2442 | { | |
2443 | } | |
2444 | ||
2445 | static void tcg_log_global_after_sync(MemoryListener *listener) | |
2446 | { | |
2447 | CPUAddressSpace *cpuas; | |
2448 | ||
2449 | /* Wait for the CPU to end the current TB. This avoids the following | |
2450 | * incorrect race: | |
2451 | * | |
2452 | * vCPU migration | |
2453 | * ---------------------- ------------------------- | |
2454 | * TLB check -> slow path | |
2455 | * notdirty_mem_write | |
2456 | * write to RAM | |
2457 | * mark dirty | |
2458 | * clear dirty flag | |
2459 | * TLB check -> fast path | |
2460 | * read memory | |
2461 | * write to RAM | |
2462 | * | |
2463 | * by pushing the migration thread's memory read after the vCPU thread has | |
2464 | * written the memory. | |
2465 | */ | |
86cf9e15 PD |
2466 | if (replay_mode == REPLAY_MODE_NONE) { |
2467 | /* | |
2468 | * VGA can make calls to this function while updating the screen. | |
2469 | * In record/replay mode this causes a deadlock, because | |
2470 | * run_on_cpu waits for rr mutex. Therefore no races are possible | |
2471 | * in this case and no need for making run_on_cpu when | |
f18d403f | 2472 | * record/replay is enabled. |
86cf9e15 PD |
2473 | */ |
2474 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); | |
2475 | run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL); | |
2476 | } | |
9458a9a1 PB |
2477 | } |
2478 | ||
1d71148e | 2479 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2480 | { |
32857f4d PM |
2481 | CPUAddressSpace *cpuas; |
2482 | AddressSpaceDispatch *d; | |
117712c3 | 2483 | |
f28d0dfd | 2484 | assert(tcg_enabled()); |
117712c3 AK |
2485 | /* since each CPU stores ram addresses in its TLB cache, we must |
2486 | reset the modified entries */ | |
32857f4d PM |
2487 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2488 | cpu_reloading_memory_map(); | |
2489 | /* The CPU and TLB are protected by the iothread lock. | |
2490 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2491 | * may have split the RCU critical section. | |
2492 | */ | |
66a6df1d | 2493 | d = address_space_to_dispatch(cpuas->as); |
d73415a3 | 2494 | qatomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 2495 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
2496 | } |
2497 | ||
62152b8a AK |
2498 | static void memory_map_init(void) |
2499 | { | |
7267c094 | 2500 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2501 | |
57271d63 | 2502 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2503 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2504 | |
7267c094 | 2505 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2506 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2507 | 65536); | |
7dca8043 | 2508 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2509 | } |
2510 | ||
2511 | MemoryRegion *get_system_memory(void) | |
2512 | { | |
2513 | return system_memory; | |
2514 | } | |
2515 | ||
309cb471 AK |
2516 | MemoryRegion *get_system_io(void) |
2517 | { | |
2518 | return system_io; | |
2519 | } | |
2520 | ||
845b6214 | 2521 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 2522 | hwaddr length) |
51d7a9eb | 2523 | { |
e87f7778 | 2524 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
2525 | addr += memory_region_get_ram_addr(mr); |
2526 | ||
e87f7778 PB |
2527 | /* No early return if dirty_log_mask is or becomes 0, because |
2528 | * cpu_physical_memory_set_dirty_range will still call | |
2529 | * xen_modified_memory. | |
2530 | */ | |
2531 | if (dirty_log_mask) { | |
2532 | dirty_log_mask = | |
2533 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2534 | } | |
2535 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 2536 | assert(tcg_enabled()); |
e506ad6a | 2537 | tb_invalidate_phys_range(addr, addr + length - 1); |
e87f7778 | 2538 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); |
51d7a9eb | 2539 | } |
e87f7778 | 2540 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
2541 | } |
2542 | ||
047be4ed SH |
2543 | void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size) |
2544 | { | |
2545 | /* | |
2546 | * In principle this function would work on other memory region types too, | |
2547 | * but the ROM device use case is the only one where this operation is | |
2548 | * necessary. Other memory regions should use the | |
2549 | * address_space_read/write() APIs. | |
2550 | */ | |
2551 | assert(memory_region_is_romd(mr)); | |
2552 | ||
2553 | invalidate_and_set_dirty(mr, addr, size); | |
2554 | } | |
2555 | ||
3123f93d | 2556 | int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 2557 | { |
e1622f4b | 2558 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
2559 | |
2560 | /* Regions are assumed to support 1-4 byte accesses unless | |
2561 | otherwise specified. */ | |
23326164 RH |
2562 | if (access_size_max == 0) { |
2563 | access_size_max = 4; | |
2564 | } | |
2565 | ||
2566 | /* Bound the maximum access by the alignment of the address. */ | |
2567 | if (!mr->ops->impl.unaligned) { | |
2568 | unsigned align_size_max = addr & -addr; | |
2569 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2570 | access_size_max = align_size_max; | |
2571 | } | |
82f2563f | 2572 | } |
23326164 RH |
2573 | |
2574 | /* Don't attempt accesses larger than the maximum. */ | |
2575 | if (l > access_size_max) { | |
2576 | l = access_size_max; | |
82f2563f | 2577 | } |
6554f5c0 | 2578 | l = pow2floor(l); |
23326164 RH |
2579 | |
2580 | return l; | |
82f2563f PB |
2581 | } |
2582 | ||
3123f93d | 2583 | bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 2584 | { |
4840f10e JK |
2585 | bool release_lock = false; |
2586 | ||
37921851 | 2587 | if (!qemu_mutex_iothread_locked()) { |
4840f10e | 2588 | qemu_mutex_lock_iothread(); |
4840f10e JK |
2589 | release_lock = true; |
2590 | } | |
125b3806 PB |
2591 | if (mr->flush_coalesced_mmio) { |
2592 | qemu_flush_coalesced_mmio_buffer(); | |
2593 | } | |
4840f10e JK |
2594 | |
2595 | return release_lock; | |
125b3806 PB |
2596 | } |
2597 | ||
3ab6fdc9 PMD |
2598 | /** |
2599 | * flatview_access_allowed | |
2600 | * @mr: #MemoryRegion to be accessed | |
2601 | * @attrs: memory transaction attributes | |
2602 | * @addr: address within that memory region | |
2603 | * @len: the number of bytes to access | |
2604 | * | |
2605 | * Check if a memory transaction is allowed. | |
2606 | * | |
2607 | * Returns: true if transaction is allowed, false if denied. | |
2608 | */ | |
2609 | static bool flatview_access_allowed(MemoryRegion *mr, MemTxAttrs attrs, | |
2610 | hwaddr addr, hwaddr len) | |
2611 | { | |
2612 | if (likely(!attrs.memory)) { | |
2613 | return true; | |
2614 | } | |
2615 | if (memory_region_is_ram(mr)) { | |
2616 | return true; | |
2617 | } | |
2618 | qemu_log_mask(LOG_GUEST_ERROR, | |
2619 | "Invalid access to non-RAM device at " | |
2620 | "addr 0x%" HWADDR_PRIX ", size %" HWADDR_PRIu ", " | |
2621 | "region '%s'\n", addr, len, memory_region_name(mr)); | |
2622 | return false; | |
2623 | } | |
2624 | ||
a203ac70 | 2625 | /* Called within RCU critical section. */ |
16620684 AK |
2626 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
2627 | MemTxAttrs attrs, | |
a152be43 | 2628 | const void *ptr, |
0c249ff7 | 2629 | hwaddr len, hwaddr addr1, |
16620684 | 2630 | hwaddr l, MemoryRegion *mr) |
13eb76e0 | 2631 | { |
20804676 | 2632 | uint8_t *ram_ptr; |
791af8c8 | 2633 | uint64_t val; |
3b643495 | 2634 | MemTxResult result = MEMTX_OK; |
4840f10e | 2635 | bool release_lock = false; |
a152be43 | 2636 | const uint8_t *buf = ptr; |
3b46e624 | 2637 | |
a203ac70 | 2638 | for (;;) { |
3ab6fdc9 PMD |
2639 | if (!flatview_access_allowed(mr, attrs, addr1, l)) { |
2640 | result |= MEMTX_ACCESS_ERROR; | |
2641 | /* Keep going. */ | |
2642 | } else if (!memory_access_is_direct(mr, true)) { | |
eb7eeb88 PB |
2643 | release_lock |= prepare_mmio_access(mr); |
2644 | l = memory_access_size(mr, l, addr1); | |
2645 | /* XXX: could force current_cpu to NULL to avoid | |
2646 | potential bugs */ | |
9bf825bf | 2647 | val = ldn_he_p(buf, l); |
3d9e7c3e | 2648 | result |= memory_region_dispatch_write(mr, addr1, val, |
9bf825bf | 2649 | size_memop(l), attrs); |
13eb76e0 | 2650 | } else { |
eb7eeb88 | 2651 | /* RAM case */ |
20804676 | 2652 | ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
4a73aee8 | 2653 | memmove(ram_ptr, buf, l); |
eb7eeb88 | 2654 | invalidate_and_set_dirty(mr, addr1, l); |
13eb76e0 | 2655 | } |
4840f10e JK |
2656 | |
2657 | if (release_lock) { | |
2658 | qemu_mutex_unlock_iothread(); | |
2659 | release_lock = false; | |
2660 | } | |
2661 | ||
13eb76e0 FB |
2662 | len -= l; |
2663 | buf += l; | |
2664 | addr += l; | |
a203ac70 PB |
2665 | |
2666 | if (!len) { | |
2667 | break; | |
2668 | } | |
2669 | ||
2670 | l = len; | |
efa99a2f | 2671 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
13eb76e0 | 2672 | } |
fd8aaa76 | 2673 | |
3b643495 | 2674 | return result; |
13eb76e0 | 2675 | } |
8df1cd07 | 2676 | |
4c6ebbb3 | 2677 | /* Called from RCU critical section. */ |
16620684 | 2678 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
a152be43 | 2679 | const void *buf, hwaddr len) |
ac1970fb | 2680 | { |
eb7eeb88 | 2681 | hwaddr l; |
eb7eeb88 PB |
2682 | hwaddr addr1; |
2683 | MemoryRegion *mr; | |
eb7eeb88 | 2684 | |
4c6ebbb3 | 2685 | l = len; |
efa99a2f | 2686 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
3ab6fdc9 PMD |
2687 | if (!flatview_access_allowed(mr, attrs, addr, len)) { |
2688 | return MEMTX_ACCESS_ERROR; | |
2689 | } | |
58e74682 PMD |
2690 | return flatview_write_continue(fv, addr, attrs, buf, len, |
2691 | addr1, l, mr); | |
a203ac70 PB |
2692 | } |
2693 | ||
2694 | /* Called within RCU critical section. */ | |
16620684 | 2695 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
a152be43 | 2696 | MemTxAttrs attrs, void *ptr, |
0c249ff7 | 2697 | hwaddr len, hwaddr addr1, hwaddr l, |
16620684 | 2698 | MemoryRegion *mr) |
a203ac70 | 2699 | { |
20804676 | 2700 | uint8_t *ram_ptr; |
a203ac70 PB |
2701 | uint64_t val; |
2702 | MemTxResult result = MEMTX_OK; | |
2703 | bool release_lock = false; | |
a152be43 | 2704 | uint8_t *buf = ptr; |
eb7eeb88 | 2705 | |
7cac7fea | 2706 | fuzz_dma_read_cb(addr, len, mr); |
a203ac70 | 2707 | for (;;) { |
3ab6fdc9 PMD |
2708 | if (!flatview_access_allowed(mr, attrs, addr1, l)) { |
2709 | result |= MEMTX_ACCESS_ERROR; | |
2710 | /* Keep going. */ | |
2711 | } else if (!memory_access_is_direct(mr, false)) { | |
eb7eeb88 PB |
2712 | /* I/O case */ |
2713 | release_lock |= prepare_mmio_access(mr); | |
2714 | l = memory_access_size(mr, l, addr1); | |
3d9e7c3e | 2715 | result |= memory_region_dispatch_read(mr, addr1, &val, |
9bf825bf TN |
2716 | size_memop(l), attrs); |
2717 | stn_he_p(buf, l, val); | |
eb7eeb88 PB |
2718 | } else { |
2719 | /* RAM case */ | |
20804676 PMD |
2720 | ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
2721 | memcpy(buf, ram_ptr, l); | |
eb7eeb88 PB |
2722 | } |
2723 | ||
2724 | if (release_lock) { | |
2725 | qemu_mutex_unlock_iothread(); | |
2726 | release_lock = false; | |
2727 | } | |
2728 | ||
2729 | len -= l; | |
2730 | buf += l; | |
2731 | addr += l; | |
a203ac70 PB |
2732 | |
2733 | if (!len) { | |
2734 | break; | |
2735 | } | |
2736 | ||
2737 | l = len; | |
efa99a2f | 2738 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
a203ac70 PB |
2739 | } |
2740 | ||
2741 | return result; | |
2742 | } | |
2743 | ||
b2a44fca PB |
2744 | /* Called from RCU critical section. */ |
2745 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
a152be43 | 2746 | MemTxAttrs attrs, void *buf, hwaddr len) |
a203ac70 PB |
2747 | { |
2748 | hwaddr l; | |
2749 | hwaddr addr1; | |
2750 | MemoryRegion *mr; | |
eb7eeb88 | 2751 | |
b2a44fca | 2752 | l = len; |
efa99a2f | 2753 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
3ab6fdc9 PMD |
2754 | if (!flatview_access_allowed(mr, attrs, addr, len)) { |
2755 | return MEMTX_ACCESS_ERROR; | |
2756 | } | |
b2a44fca PB |
2757 | return flatview_read_continue(fv, addr, attrs, buf, len, |
2758 | addr1, l, mr); | |
ac1970fb AK |
2759 | } |
2760 | ||
b2a44fca | 2761 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, |
daa3dda4 | 2762 | MemTxAttrs attrs, void *buf, hwaddr len) |
b2a44fca PB |
2763 | { |
2764 | MemTxResult result = MEMTX_OK; | |
2765 | FlatView *fv; | |
2766 | ||
2767 | if (len > 0) { | |
694ea274 | 2768 | RCU_READ_LOCK_GUARD(); |
b2a44fca PB |
2769 | fv = address_space_to_flatview(as); |
2770 | result = flatview_read(fv, addr, attrs, buf, len); | |
b2a44fca PB |
2771 | } |
2772 | ||
2773 | return result; | |
2774 | } | |
2775 | ||
4c6ebbb3 PB |
2776 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
2777 | MemTxAttrs attrs, | |
daa3dda4 | 2778 | const void *buf, hwaddr len) |
4c6ebbb3 PB |
2779 | { |
2780 | MemTxResult result = MEMTX_OK; | |
2781 | FlatView *fv; | |
2782 | ||
2783 | if (len > 0) { | |
694ea274 | 2784 | RCU_READ_LOCK_GUARD(); |
4c6ebbb3 PB |
2785 | fv = address_space_to_flatview(as); |
2786 | result = flatview_write(fv, addr, attrs, buf, len); | |
4c6ebbb3 PB |
2787 | } |
2788 | ||
2789 | return result; | |
2790 | } | |
2791 | ||
db84fd97 | 2792 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
daa3dda4 | 2793 | void *buf, hwaddr len, bool is_write) |
db84fd97 PB |
2794 | { |
2795 | if (is_write) { | |
2796 | return address_space_write(as, addr, attrs, buf, len); | |
2797 | } else { | |
2798 | return address_space_read_full(as, addr, attrs, buf, len); | |
2799 | } | |
2800 | } | |
2801 | ||
75f01c68 PMD |
2802 | MemTxResult address_space_set(AddressSpace *as, hwaddr addr, |
2803 | uint8_t c, hwaddr len, MemTxAttrs attrs) | |
2804 | { | |
2805 | #define FILLBUF_SIZE 512 | |
2806 | uint8_t fillbuf[FILLBUF_SIZE]; | |
2807 | int l; | |
2808 | MemTxResult error = MEMTX_OK; | |
2809 | ||
2810 | memset(fillbuf, c, FILLBUF_SIZE); | |
2811 | while (len > 0) { | |
2812 | l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; | |
2813 | error |= address_space_write(as, addr, attrs, fillbuf, l); | |
2814 | len -= l; | |
2815 | addr += l; | |
2816 | } | |
2817 | ||
2818 | return error; | |
2819 | } | |
2820 | ||
d7ef71ef | 2821 | void cpu_physical_memory_rw(hwaddr addr, void *buf, |
28c80bfe | 2822 | hwaddr len, bool is_write) |
ac1970fb | 2823 | { |
5c9eb028 PM |
2824 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
2825 | buf, len, is_write); | |
ac1970fb AK |
2826 | } |
2827 | ||
582b55a9 AG |
2828 | enum write_rom_type { |
2829 | WRITE_DATA, | |
2830 | FLUSH_CACHE, | |
2831 | }; | |
2832 | ||
75693e14 PM |
2833 | static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, |
2834 | hwaddr addr, | |
2835 | MemTxAttrs attrs, | |
daa3dda4 | 2836 | const void *ptr, |
0c249ff7 | 2837 | hwaddr len, |
75693e14 | 2838 | enum write_rom_type type) |
d0ecd2aa | 2839 | { |
149f54b5 | 2840 | hwaddr l; |
20804676 | 2841 | uint8_t *ram_ptr; |
149f54b5 | 2842 | hwaddr addr1; |
5c8a00ce | 2843 | MemoryRegion *mr; |
daa3dda4 | 2844 | const uint8_t *buf = ptr; |
3b46e624 | 2845 | |
694ea274 | 2846 | RCU_READ_LOCK_GUARD(); |
d0ecd2aa | 2847 | while (len > 0) { |
149f54b5 | 2848 | l = len; |
75693e14 | 2849 | mr = address_space_translate(as, addr, &addr1, &l, true, attrs); |
3b46e624 | 2850 | |
5c8a00ce PB |
2851 | if (!(memory_region_is_ram(mr) || |
2852 | memory_region_is_romd(mr))) { | |
b242e0e0 | 2853 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 2854 | } else { |
d0ecd2aa | 2855 | /* ROM/RAM case */ |
20804676 | 2856 | ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
2857 | switch (type) { |
2858 | case WRITE_DATA: | |
20804676 | 2859 | memcpy(ram_ptr, buf, l); |
845b6214 | 2860 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
2861 | break; |
2862 | case FLUSH_CACHE: | |
1da8de39 | 2863 | flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); |
582b55a9 AG |
2864 | break; |
2865 | } | |
d0ecd2aa FB |
2866 | } |
2867 | len -= l; | |
2868 | buf += l; | |
2869 | addr += l; | |
2870 | } | |
75693e14 | 2871 | return MEMTX_OK; |
d0ecd2aa FB |
2872 | } |
2873 | ||
582b55a9 | 2874 | /* used for ROM loading : can write in RAM and ROM */ |
3c8133f9 PM |
2875 | MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, |
2876 | MemTxAttrs attrs, | |
daa3dda4 | 2877 | const void *buf, hwaddr len) |
582b55a9 | 2878 | { |
3c8133f9 PM |
2879 | return address_space_write_rom_internal(as, addr, attrs, |
2880 | buf, len, WRITE_DATA); | |
582b55a9 AG |
2881 | } |
2882 | ||
0c249ff7 | 2883 | void cpu_flush_icache_range(hwaddr start, hwaddr len) |
582b55a9 AG |
2884 | { |
2885 | /* | |
2886 | * This function should do the same thing as an icache flush that was | |
2887 | * triggered from within the guest. For TCG we are always cache coherent, | |
2888 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
2889 | * the host's instruction cache at least. | |
2890 | */ | |
2891 | if (tcg_enabled()) { | |
2892 | return; | |
2893 | } | |
2894 | ||
75693e14 PM |
2895 | address_space_write_rom_internal(&address_space_memory, |
2896 | start, MEMTXATTRS_UNSPECIFIED, | |
2897 | NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
2898 | } |
2899 | ||
6d16c2f8 | 2900 | typedef struct { |
d3e71559 | 2901 | MemoryRegion *mr; |
6d16c2f8 | 2902 | void *buffer; |
a8170e5e AK |
2903 | hwaddr addr; |
2904 | hwaddr len; | |
c2cba0ff | 2905 | bool in_use; |
6d16c2f8 AL |
2906 | } BounceBuffer; |
2907 | ||
2908 | static BounceBuffer bounce; | |
2909 | ||
ba223c29 | 2910 | typedef struct MapClient { |
e95205e1 | 2911 | QEMUBH *bh; |
72cf2d4f | 2912 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
2913 | } MapClient; |
2914 | ||
38e047b5 | 2915 | QemuMutex map_client_list_lock; |
b58deb34 | 2916 | static QLIST_HEAD(, MapClient) map_client_list |
72cf2d4f | 2917 | = QLIST_HEAD_INITIALIZER(map_client_list); |
ba223c29 | 2918 | |
e95205e1 FZ |
2919 | static void cpu_unregister_map_client_do(MapClient *client) |
2920 | { | |
2921 | QLIST_REMOVE(client, link); | |
2922 | g_free(client); | |
2923 | } | |
2924 | ||
33b6c2ed FZ |
2925 | static void cpu_notify_map_clients_locked(void) |
2926 | { | |
2927 | MapClient *client; | |
2928 | ||
2929 | while (!QLIST_EMPTY(&map_client_list)) { | |
2930 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
2931 | qemu_bh_schedule(client->bh); |
2932 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
2933 | } |
2934 | } | |
2935 | ||
e95205e1 | 2936 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 2937 | { |
7267c094 | 2938 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 2939 | |
38e047b5 | 2940 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 2941 | client->bh = bh; |
72cf2d4f | 2942 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33828ca1 PB |
2943 | /* Write map_client_list before reading in_use. */ |
2944 | smp_mb(); | |
d73415a3 | 2945 | if (!qatomic_read(&bounce.in_use)) { |
33b6c2ed FZ |
2946 | cpu_notify_map_clients_locked(); |
2947 | } | |
38e047b5 | 2948 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2949 | } |
2950 | ||
38e047b5 | 2951 | void cpu_exec_init_all(void) |
ba223c29 | 2952 | { |
38e047b5 | 2953 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
2954 | /* The data structures we set up here depend on knowing the page size, |
2955 | * so no more changes can be made after this point. | |
2956 | * In an ideal world, nothing we did before we had finished the | |
2957 | * machine setup would care about the target page size, and we could | |
2958 | * do this much later, rather than requiring board models to state | |
2959 | * up front what their requirements are. | |
2960 | */ | |
2961 | finalize_target_page_bits(); | |
38e047b5 | 2962 | io_mem_init(); |
680a4783 | 2963 | memory_map_init(); |
38e047b5 | 2964 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
2965 | } |
2966 | ||
e95205e1 | 2967 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
2968 | { |
2969 | MapClient *client; | |
2970 | ||
e95205e1 FZ |
2971 | qemu_mutex_lock(&map_client_list_lock); |
2972 | QLIST_FOREACH(client, &map_client_list, link) { | |
2973 | if (client->bh == bh) { | |
2974 | cpu_unregister_map_client_do(client); | |
2975 | break; | |
2976 | } | |
ba223c29 | 2977 | } |
e95205e1 | 2978 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2979 | } |
2980 | ||
2981 | static void cpu_notify_map_clients(void) | |
2982 | { | |
38e047b5 | 2983 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 2984 | cpu_notify_map_clients_locked(); |
38e047b5 | 2985 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2986 | } |
2987 | ||
0c249ff7 | 2988 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, |
eace72b7 | 2989 | bool is_write, MemTxAttrs attrs) |
51644ab7 | 2990 | { |
5c8a00ce | 2991 | MemoryRegion *mr; |
51644ab7 PB |
2992 | hwaddr l, xlat; |
2993 | ||
2994 | while (len > 0) { | |
2995 | l = len; | |
efa99a2f | 2996 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
5c8a00ce PB |
2997 | if (!memory_access_is_direct(mr, is_write)) { |
2998 | l = memory_access_size(mr, l, addr); | |
eace72b7 | 2999 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { |
51644ab7 PB |
3000 | return false; |
3001 | } | |
3002 | } | |
3003 | ||
3004 | len -= l; | |
3005 | addr += l; | |
3006 | } | |
3007 | return true; | |
3008 | } | |
3009 | ||
16620684 | 3010 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
0c249ff7 | 3011 | hwaddr len, bool is_write, |
fddffa42 | 3012 | MemTxAttrs attrs) |
16620684 | 3013 | { |
11e732a5 | 3014 | FlatView *fv; |
11e732a5 | 3015 | |
694ea274 | 3016 | RCU_READ_LOCK_GUARD(); |
11e732a5 | 3017 | fv = address_space_to_flatview(as); |
58e74682 | 3018 | return flatview_access_valid(fv, addr, len, is_write, attrs); |
16620684 AK |
3019 | } |
3020 | ||
715c31ec | 3021 | static hwaddr |
16620684 | 3022 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
53d0790d PM |
3023 | hwaddr target_len, |
3024 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3025 | bool is_write, MemTxAttrs attrs) | |
715c31ec PB |
3026 | { |
3027 | hwaddr done = 0; | |
3028 | hwaddr xlat; | |
3029 | MemoryRegion *this_mr; | |
3030 | ||
3031 | for (;;) { | |
3032 | target_len -= len; | |
3033 | addr += len; | |
3034 | done += len; | |
3035 | if (target_len == 0) { | |
3036 | return done; | |
3037 | } | |
3038 | ||
3039 | len = target_len; | |
16620684 | 3040 | this_mr = flatview_translate(fv, addr, &xlat, |
efa99a2f | 3041 | &len, is_write, attrs); |
715c31ec PB |
3042 | if (this_mr != mr || xlat != base + done) { |
3043 | return done; | |
3044 | } | |
3045 | } | |
3046 | } | |
3047 | ||
6d16c2f8 AL |
3048 | /* Map a physical memory region into a host virtual address. |
3049 | * May map a subset of the requested range, given by and returned in *plen. | |
3050 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3051 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3052 | * Use cpu_register_map_client() to know when retrying the map operation is |
3053 | * likely to succeed. | |
6d16c2f8 | 3054 | */ |
ac1970fb | 3055 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3056 | hwaddr addr, |
3057 | hwaddr *plen, | |
f26404fb PM |
3058 | bool is_write, |
3059 | MemTxAttrs attrs) | |
6d16c2f8 | 3060 | { |
a8170e5e | 3061 | hwaddr len = *plen; |
715c31ec PB |
3062 | hwaddr l, xlat; |
3063 | MemoryRegion *mr; | |
ad0c60fa | 3064 | FlatView *fv; |
6d16c2f8 | 3065 | |
e3127ae0 PB |
3066 | if (len == 0) { |
3067 | return NULL; | |
3068 | } | |
38bee5dc | 3069 | |
e3127ae0 | 3070 | l = len; |
694ea274 | 3071 | RCU_READ_LOCK_GUARD(); |
ad0c60fa | 3072 | fv = address_space_to_flatview(as); |
efa99a2f | 3073 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
41063e1e | 3074 | |
e3127ae0 | 3075 | if (!memory_access_is_direct(mr, is_write)) { |
d73415a3 | 3076 | if (qatomic_xchg(&bounce.in_use, true)) { |
77f55eac | 3077 | *plen = 0; |
e3127ae0 | 3078 | return NULL; |
6d16c2f8 | 3079 | } |
e85d9db5 KW |
3080 | /* Avoid unbounded allocations */ |
3081 | l = MIN(l, TARGET_PAGE_SIZE); | |
3082 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3083 | bounce.addr = addr; |
3084 | bounce.len = l; | |
d3e71559 PB |
3085 | |
3086 | memory_region_ref(mr); | |
3087 | bounce.mr = mr; | |
e3127ae0 | 3088 | if (!is_write) { |
16620684 | 3089 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3090 | bounce.buffer, l); |
8ab934f9 | 3091 | } |
6d16c2f8 | 3092 | |
e3127ae0 PB |
3093 | *plen = l; |
3094 | return bounce.buffer; | |
3095 | } | |
3096 | ||
e3127ae0 | 3097 | |
d3e71559 | 3098 | memory_region_ref(mr); |
16620684 | 3099 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
53d0790d | 3100 | l, is_write, attrs); |
fc1c8344 | 3101 | fuzz_dma_read_cb(addr, *plen, mr); |
66997c42 | 3102 | return qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
6d16c2f8 AL |
3103 | } |
3104 | ||
ac1970fb | 3105 | /* Unmaps a memory region previously mapped by address_space_map(). |
ae5883ab | 3106 | * Will also mark the memory as dirty if is_write is true. access_len gives |
6d16c2f8 AL |
3107 | * the amount of memory that was actually read or written by the caller. |
3108 | */ | |
a8170e5e | 3109 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
ae5883ab | 3110 | bool is_write, hwaddr access_len) |
6d16c2f8 AL |
3111 | { |
3112 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3113 | MemoryRegion *mr; |
3114 | ram_addr_t addr1; | |
3115 | ||
07bdaa41 | 3116 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3117 | assert(mr != NULL); |
6d16c2f8 | 3118 | if (is_write) { |
845b6214 | 3119 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3120 | } |
868bb33f | 3121 | if (xen_enabled()) { |
e41d7c69 | 3122 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3123 | } |
d3e71559 | 3124 | memory_region_unref(mr); |
6d16c2f8 AL |
3125 | return; |
3126 | } | |
3127 | if (is_write) { | |
5c9eb028 PM |
3128 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3129 | bounce.buffer, access_len); | |
6d16c2f8 | 3130 | } |
f8a83245 | 3131 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3132 | bounce.buffer = NULL; |
d3e71559 | 3133 | memory_region_unref(bounce.mr); |
33828ca1 | 3134 | /* Clear in_use before reading map_client_list. */ |
06831001 | 3135 | qatomic_set_mb(&bounce.in_use, false); |
ba223c29 | 3136 | cpu_notify_map_clients(); |
6d16c2f8 | 3137 | } |
d0ecd2aa | 3138 | |
a8170e5e AK |
3139 | void *cpu_physical_memory_map(hwaddr addr, |
3140 | hwaddr *plen, | |
28c80bfe | 3141 | bool is_write) |
ac1970fb | 3142 | { |
f26404fb PM |
3143 | return address_space_map(&address_space_memory, addr, plen, is_write, |
3144 | MEMTXATTRS_UNSPECIFIED); | |
ac1970fb AK |
3145 | } |
3146 | ||
a8170e5e | 3147 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
28c80bfe | 3148 | bool is_write, hwaddr access_len) |
ac1970fb AK |
3149 | { |
3150 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3151 | } | |
3152 | ||
0ce265ff PB |
3153 | #define ARG1_DECL AddressSpace *as |
3154 | #define ARG1 as | |
3155 | #define SUFFIX | |
3156 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
0ce265ff PB |
3157 | #define RCU_READ_LOCK(...) rcu_read_lock() |
3158 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
139c1837 | 3159 | #include "memory_ldst.c.inc" |
1e78bcc1 | 3160 | |
1f4e496e PB |
3161 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3162 | AddressSpace *as, | |
3163 | hwaddr addr, | |
3164 | hwaddr len, | |
3165 | bool is_write) | |
3166 | { | |
48564041 PB |
3167 | AddressSpaceDispatch *d; |
3168 | hwaddr l; | |
3169 | MemoryRegion *mr; | |
4bfb024b | 3170 | Int128 diff; |
48564041 PB |
3171 | |
3172 | assert(len > 0); | |
3173 | ||
3174 | l = len; | |
3175 | cache->fv = address_space_get_flatview(as); | |
3176 | d = flatview_to_dispatch(cache->fv); | |
3177 | cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true); | |
3178 | ||
4bfb024b PB |
3179 | /* |
3180 | * cache->xlat is now relative to cache->mrs.mr, not to the section itself. | |
3181 | * Take that into account to compute how many bytes are there between | |
3182 | * cache->xlat and the end of the section. | |
3183 | */ | |
3184 | diff = int128_sub(cache->mrs.size, | |
48805df9 | 3185 | int128_make64(cache->xlat - cache->mrs.offset_within_region)); |
4bfb024b PB |
3186 | l = int128_get64(int128_min(diff, int128_make64(l))); |
3187 | ||
48564041 PB |
3188 | mr = cache->mrs.mr; |
3189 | memory_region_ref(mr); | |
3190 | if (memory_access_is_direct(mr, is_write)) { | |
53d0790d PM |
3191 | /* We don't care about the memory attributes here as we're only |
3192 | * doing this if we found actual RAM, which behaves the same | |
3193 | * regardless of attributes; so UNSPECIFIED is fine. | |
3194 | */ | |
48564041 | 3195 | l = flatview_extend_translation(cache->fv, addr, len, mr, |
53d0790d PM |
3196 | cache->xlat, l, is_write, |
3197 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3198 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); |
3199 | } else { | |
3200 | cache->ptr = NULL; | |
3201 | } | |
3202 | ||
3203 | cache->len = l; | |
3204 | cache->is_write = is_write; | |
3205 | return l; | |
1f4e496e PB |
3206 | } |
3207 | ||
3208 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3209 | hwaddr addr, | |
3210 | hwaddr access_len) | |
3211 | { | |
48564041 PB |
3212 | assert(cache->is_write); |
3213 | if (likely(cache->ptr)) { | |
3214 | invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len); | |
3215 | } | |
1f4e496e PB |
3216 | } |
3217 | ||
3218 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3219 | { | |
48564041 PB |
3220 | if (!cache->mrs.mr) { |
3221 | return; | |
3222 | } | |
3223 | ||
3224 | if (xen_enabled()) { | |
3225 | xen_invalidate_map_cache_entry(cache->ptr); | |
3226 | } | |
3227 | memory_region_unref(cache->mrs.mr); | |
3228 | flatview_unref(cache->fv); | |
3229 | cache->mrs.mr = NULL; | |
3230 | cache->fv = NULL; | |
3231 | } | |
3232 | ||
3233 | /* Called from RCU critical section. This function has the same | |
3234 | * semantics as address_space_translate, but it only works on a | |
3235 | * predefined range of a MemoryRegion that was mapped with | |
3236 | * address_space_cache_init. | |
3237 | */ | |
3238 | static inline MemoryRegion *address_space_translate_cached( | |
3239 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | |
bc6b1cec | 3240 | hwaddr *plen, bool is_write, MemTxAttrs attrs) |
48564041 PB |
3241 | { |
3242 | MemoryRegionSection section; | |
3243 | MemoryRegion *mr; | |
3244 | IOMMUMemoryRegion *iommu_mr; | |
3245 | AddressSpace *target_as; | |
3246 | ||
3247 | assert(!cache->ptr); | |
3248 | *xlat = addr + cache->xlat; | |
3249 | ||
3250 | mr = cache->mrs.mr; | |
3251 | iommu_mr = memory_region_get_iommu(mr); | |
3252 | if (!iommu_mr) { | |
3253 | /* MMIO region. */ | |
3254 | return mr; | |
3255 | } | |
3256 | ||
3257 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | |
3258 | NULL, is_write, true, | |
2f7b009c | 3259 | &target_as, attrs); |
48564041 PB |
3260 | return section.mr; |
3261 | } | |
3262 | ||
3263 | /* Called from RCU critical section. address_space_read_cached uses this | |
3264 | * out of line function when the target is an MMIO or IOMMU region. | |
3265 | */ | |
38df19fa | 3266 | MemTxResult |
48564041 | 3267 | address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, |
0c249ff7 | 3268 | void *buf, hwaddr len) |
48564041 PB |
3269 | { |
3270 | hwaddr addr1, l; | |
3271 | MemoryRegion *mr; | |
3272 | ||
3273 | l = len; | |
bc6b1cec PM |
3274 | mr = address_space_translate_cached(cache, addr, &addr1, &l, false, |
3275 | MEMTXATTRS_UNSPECIFIED); | |
38df19fa PMD |
3276 | return flatview_read_continue(cache->fv, |
3277 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3278 | addr1, l, mr); | |
48564041 PB |
3279 | } |
3280 | ||
3281 | /* Called from RCU critical section. address_space_write_cached uses this | |
3282 | * out of line function when the target is an MMIO or IOMMU region. | |
3283 | */ | |
38df19fa | 3284 | MemTxResult |
48564041 | 3285 | address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, |
0c249ff7 | 3286 | const void *buf, hwaddr len) |
48564041 PB |
3287 | { |
3288 | hwaddr addr1, l; | |
3289 | MemoryRegion *mr; | |
3290 | ||
3291 | l = len; | |
bc6b1cec PM |
3292 | mr = address_space_translate_cached(cache, addr, &addr1, &l, true, |
3293 | MEMTXATTRS_UNSPECIFIED); | |
38df19fa PMD |
3294 | return flatview_write_continue(cache->fv, |
3295 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3296 | addr1, l, mr); | |
1f4e496e PB |
3297 | } |
3298 | ||
3299 | #define ARG1_DECL MemoryRegionCache *cache | |
3300 | #define ARG1 cache | |
48564041 PB |
3301 | #define SUFFIX _cached_slow |
3302 | #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) | |
48564041 PB |
3303 | #define RCU_READ_LOCK() ((void)0) |
3304 | #define RCU_READ_UNLOCK() ((void)0) | |
139c1837 | 3305 | #include "memory_ldst.c.inc" |
1f4e496e | 3306 | |
5e2972fd | 3307 | /* virtual memory access for debug (includes writing to ROM) */ |
73842ef0 PMD |
3308 | int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, |
3309 | void *ptr, size_t len, bool is_write) | |
13eb76e0 | 3310 | { |
a8170e5e | 3311 | hwaddr phys_addr; |
73842ef0 | 3312 | vaddr l, page; |
d7ef71ef | 3313 | uint8_t *buf = ptr; |
13eb76e0 | 3314 | |
79ca7a1b | 3315 | cpu_synchronize_state(cpu); |
13eb76e0 | 3316 | while (len > 0) { |
5232e4c7 PM |
3317 | int asidx; |
3318 | MemTxAttrs attrs; | |
ddfc8b96 | 3319 | MemTxResult res; |
5232e4c7 | 3320 | |
13eb76e0 | 3321 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3322 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3323 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3324 | /* if no physical page mapped, return an error */ |
3325 | if (phys_addr == -1) | |
3326 | return -1; | |
3327 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3328 | if (l > len) | |
3329 | l = len; | |
5e2972fd | 3330 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3331 | if (is_write) { |
ddfc8b96 PMD |
3332 | res = address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, |
3333 | attrs, buf, l); | |
2e38847b | 3334 | } else { |
ddfc8b96 PMD |
3335 | res = address_space_read(cpu->cpu_ases[asidx].as, phys_addr, |
3336 | attrs, buf, l); | |
3337 | } | |
3338 | if (res != MEMTX_OK) { | |
3339 | return -1; | |
2e38847b | 3340 | } |
13eb76e0 FB |
3341 | len -= l; |
3342 | buf += l; | |
3343 | addr += l; | |
3344 | } | |
3345 | return 0; | |
3346 | } | |
038629a6 DDAG |
3347 | |
3348 | /* | |
3349 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3350 | * target independent. | |
3351 | */ | |
20afaed9 | 3352 | size_t qemu_target_page_size(void) |
038629a6 | 3353 | { |
20afaed9 | 3354 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
3355 | } |
3356 | ||
46d702b1 JQ |
3357 | int qemu_target_page_bits(void) |
3358 | { | |
3359 | return TARGET_PAGE_BITS; | |
3360 | } | |
3361 | ||
3362 | int qemu_target_page_bits_min(void) | |
3363 | { | |
3364 | return TARGET_PAGE_BITS_MIN; | |
3365 | } | |
8e4a424b | 3366 | |
62c5e181 JQ |
3367 | /* Convert target pages to MiB (2**20). */ |
3368 | size_t qemu_target_pages_to_MiB(size_t pages) | |
3369 | { | |
3370 | int page_bits = TARGET_PAGE_BITS; | |
3371 | ||
3372 | /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ | |
3373 | g_assert(page_bits < 20); | |
3374 | ||
3375 | return pages >> (20 - page_bits); | |
3376 | } | |
3377 | ||
a8170e5e | 3378 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3379 | { |
5c8a00ce | 3380 | MemoryRegion*mr; |
149f54b5 | 3381 | hwaddr l = 1; |
76f35538 | 3382 | |
694ea274 | 3383 | RCU_READ_LOCK_GUARD(); |
5c8a00ce | 3384 | mr = address_space_translate(&address_space_memory, |
bc6b1cec PM |
3385 | phys_addr, &phys_addr, &l, false, |
3386 | MEMTXATTRS_UNSPECIFIED); | |
76f35538 | 3387 | |
66997c42 | 3388 | return !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
76f35538 | 3389 | } |
bd2fa51f | 3390 | |
e3807054 | 3391 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3392 | { |
3393 | RAMBlock *block; | |
e3807054 | 3394 | int ret = 0; |
bd2fa51f | 3395 | |
694ea274 | 3396 | RCU_READ_LOCK_GUARD(); |
99e15582 | 3397 | RAMBLOCK_FOREACH(block) { |
754cb9c0 | 3398 | ret = func(block, opaque); |
e3807054 DDAG |
3399 | if (ret) { |
3400 | break; | |
3401 | } | |
bd2fa51f | 3402 | } |
e3807054 | 3403 | return ret; |
bd2fa51f | 3404 | } |
d3a5038c DDAG |
3405 | |
3406 | /* | |
3407 | * Unmap pages of memory from start to start+length such that | |
3408 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3409 | * the OS provides for postcopy. | |
3410 | * The pages must be unmapped by the end of the function. | |
3411 | * Returns: 0 on success, none-0 on failure | |
3412 | * | |
3413 | */ | |
3414 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3415 | { | |
3416 | int ret = -1; | |
3417 | ||
3418 | uint8_t *host_startaddr = rb->host + start; | |
3419 | ||
619bd31d | 3420 | if (!QEMU_PTR_IS_ALIGNED(host_startaddr, rb->page_size)) { |
d3a5038c DDAG |
3421 | error_report("ram_block_discard_range: Unaligned start address: %p", |
3422 | host_startaddr); | |
3423 | goto err; | |
3424 | } | |
3425 | ||
dcdc4607 | 3426 | if ((start + length) <= rb->max_length) { |
db144f70 | 3427 | bool need_madvise, need_fallocate; |
619bd31d | 3428 | if (!QEMU_IS_ALIGNED(length, rb->page_size)) { |
72821d93 WY |
3429 | error_report("ram_block_discard_range: Unaligned length: %zx", |
3430 | length); | |
d3a5038c DDAG |
3431 | goto err; |
3432 | } | |
3433 | ||
3434 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3435 | ||
db144f70 DDAG |
3436 | /* The logic here is messy; |
3437 | * madvise DONTNEED fails for hugepages | |
3438 | * fallocate works on hugepages and shmem | |
cdfa56c5 | 3439 | * shared anonymous memory requires madvise REMOVE |
db144f70 DDAG |
3440 | */ |
3441 | need_madvise = (rb->page_size == qemu_host_page_size); | |
3442 | need_fallocate = rb->fd != -1; | |
3443 | if (need_fallocate) { | |
3444 | /* For a file, this causes the area of the file to be zero'd | |
3445 | * if read, and for hugetlbfs also causes it to be unmapped | |
3446 | * so a userfault will trigger. | |
e2fa71f5 DDAG |
3447 | */ |
3448 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3449 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3450 | start, length); | |
db144f70 DDAG |
3451 | if (ret) { |
3452 | ret = -errno; | |
3453 | error_report("ram_block_discard_range: Failed to fallocate " | |
3454 | "%s:%" PRIx64 " +%zx (%d)", | |
3455 | rb->idstr, start, length, ret); | |
3456 | goto err; | |
3457 | } | |
3458 | #else | |
3459 | ret = -ENOSYS; | |
3460 | error_report("ram_block_discard_range: fallocate not available/file" | |
3461 | "%s:%" PRIx64 " +%zx (%d)", | |
3462 | rb->idstr, start, length, ret); | |
3463 | goto err; | |
e2fa71f5 DDAG |
3464 | #endif |
3465 | } | |
db144f70 DDAG |
3466 | if (need_madvise) { |
3467 | /* For normal RAM this causes it to be unmapped, | |
3468 | * for shared memory it causes the local mapping to disappear | |
3469 | * and to fall back on the file contents (which we just | |
3470 | * fallocate'd away). | |
3471 | */ | |
3472 | #if defined(CONFIG_MADVISE) | |
cdfa56c5 DH |
3473 | if (qemu_ram_is_shared(rb) && rb->fd < 0) { |
3474 | ret = madvise(host_startaddr, length, QEMU_MADV_REMOVE); | |
3475 | } else { | |
3476 | ret = madvise(host_startaddr, length, QEMU_MADV_DONTNEED); | |
3477 | } | |
db144f70 DDAG |
3478 | if (ret) { |
3479 | ret = -errno; | |
3480 | error_report("ram_block_discard_range: Failed to discard range " | |
3481 | "%s:%" PRIx64 " +%zx (%d)", | |
3482 | rb->idstr, start, length, ret); | |
3483 | goto err; | |
3484 | } | |
3485 | #else | |
3486 | ret = -ENOSYS; | |
3487 | error_report("ram_block_discard_range: MADVISE not available" | |
d3a5038c DDAG |
3488 | "%s:%" PRIx64 " +%zx (%d)", |
3489 | rb->idstr, start, length, ret); | |
db144f70 DDAG |
3490 | goto err; |
3491 | #endif | |
d3a5038c | 3492 | } |
db144f70 DDAG |
3493 | trace_ram_block_discard_range(rb->idstr, host_startaddr, length, |
3494 | need_madvise, need_fallocate, ret); | |
d3a5038c DDAG |
3495 | } else { |
3496 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3497 | "/%zx/" RAM_ADDR_FMT")", | |
dcdc4607 | 3498 | rb->idstr, start, length, rb->max_length); |
d3a5038c DDAG |
3499 | } |
3500 | ||
3501 | err: | |
3502 | return ret; | |
3503 | } | |
3504 | ||
a4de8552 JH |
3505 | bool ramblock_is_pmem(RAMBlock *rb) |
3506 | { | |
3507 | return rb->flags & RAM_PMEM; | |
3508 | } | |
3509 | ||
b6b71cb5 | 3510 | static void mtree_print_phys_entries(int start, int end, int skip, int ptr) |
5e8fd947 AK |
3511 | { |
3512 | if (start == end - 1) { | |
b6b71cb5 | 3513 | qemu_printf("\t%3d ", start); |
5e8fd947 | 3514 | } else { |
b6b71cb5 | 3515 | qemu_printf("\t%3d..%-3d ", start, end - 1); |
5e8fd947 | 3516 | } |
b6b71cb5 | 3517 | qemu_printf(" skip=%d ", skip); |
5e8fd947 | 3518 | if (ptr == PHYS_MAP_NODE_NIL) { |
b6b71cb5 | 3519 | qemu_printf(" ptr=NIL"); |
5e8fd947 | 3520 | } else if (!skip) { |
b6b71cb5 | 3521 | qemu_printf(" ptr=#%d", ptr); |
5e8fd947 | 3522 | } else { |
b6b71cb5 | 3523 | qemu_printf(" ptr=[%d]", ptr); |
5e8fd947 | 3524 | } |
b6b71cb5 | 3525 | qemu_printf("\n"); |
5e8fd947 AK |
3526 | } |
3527 | ||
3528 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
3529 | int128_sub((size), int128_one())) : 0) | |
3530 | ||
b6b71cb5 | 3531 | void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) |
5e8fd947 AK |
3532 | { |
3533 | int i; | |
3534 | ||
b6b71cb5 MA |
3535 | qemu_printf(" Dispatch\n"); |
3536 | qemu_printf(" Physical sections\n"); | |
5e8fd947 AK |
3537 | |
3538 | for (i = 0; i < d->map.sections_nb; ++i) { | |
3539 | MemoryRegionSection *s = d->map.sections + i; | |
3540 | const char *names[] = { " [unassigned]", " [not dirty]", | |
3541 | " [ROM]", " [watch]" }; | |
3542 | ||
883f2c59 | 3543 | qemu_printf(" #%d @" HWADDR_FMT_plx ".." HWADDR_FMT_plx |
b6b71cb5 | 3544 | " %s%s%s%s%s", |
5e8fd947 AK |
3545 | i, |
3546 | s->offset_within_address_space, | |
f9c307c3 | 3547 | s->offset_within_address_space + MR_SIZE(s->size), |
5e8fd947 AK |
3548 | s->mr->name ? s->mr->name : "(noname)", |
3549 | i < ARRAY_SIZE(names) ? names[i] : "", | |
3550 | s->mr == root ? " [ROOT]" : "", | |
3551 | s == d->mru_section ? " [MRU]" : "", | |
3552 | s->mr->is_iommu ? " [iommu]" : ""); | |
3553 | ||
3554 | if (s->mr->alias) { | |
b6b71cb5 | 3555 | qemu_printf(" alias=%s", s->mr->alias->name ? |
5e8fd947 AK |
3556 | s->mr->alias->name : "noname"); |
3557 | } | |
b6b71cb5 | 3558 | qemu_printf("\n"); |
5e8fd947 AK |
3559 | } |
3560 | ||
b6b71cb5 | 3561 | qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", |
5e8fd947 AK |
3562 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); |
3563 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
3564 | int j, jprev; | |
3565 | PhysPageEntry prev; | |
3566 | Node *n = d->map.nodes + i; | |
3567 | ||
b6b71cb5 | 3568 | qemu_printf(" [%d]\n", i); |
5e8fd947 AK |
3569 | |
3570 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
3571 | PhysPageEntry *pe = *n + j; | |
3572 | ||
3573 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
3574 | continue; | |
3575 | } | |
3576 | ||
b6b71cb5 | 3577 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
3578 | |
3579 | jprev = j; | |
3580 | prev = *pe; | |
3581 | } | |
3582 | ||
3583 | if (jprev != ARRAY_SIZE(*n)) { | |
b6b71cb5 | 3584 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
3585 | } |
3586 | } | |
3587 | } | |
3588 | ||
7e6d32eb | 3589 | /* Require any discards to work. */ |
98da491d | 3590 | static unsigned int ram_block_discard_required_cnt; |
7e6d32eb DH |
3591 | /* Require only coordinated discards to work. */ |
3592 | static unsigned int ram_block_coordinated_discard_required_cnt; | |
3593 | /* Disable any discards. */ | |
98da491d | 3594 | static unsigned int ram_block_discard_disabled_cnt; |
7e6d32eb DH |
3595 | /* Disable only uncoordinated discards. */ |
3596 | static unsigned int ram_block_uncoordinated_discard_disabled_cnt; | |
98da491d DH |
3597 | static QemuMutex ram_block_discard_disable_mutex; |
3598 | ||
3599 | static void ram_block_discard_disable_mutex_lock(void) | |
3600 | { | |
3601 | static gsize initialized; | |
3602 | ||
3603 | if (g_once_init_enter(&initialized)) { | |
3604 | qemu_mutex_init(&ram_block_discard_disable_mutex); | |
3605 | g_once_init_leave(&initialized, 1); | |
3606 | } | |
3607 | qemu_mutex_lock(&ram_block_discard_disable_mutex); | |
3608 | } | |
3609 | ||
3610 | static void ram_block_discard_disable_mutex_unlock(void) | |
3611 | { | |
3612 | qemu_mutex_unlock(&ram_block_discard_disable_mutex); | |
3613 | } | |
d24f31db DH |
3614 | |
3615 | int ram_block_discard_disable(bool state) | |
3616 | { | |
98da491d | 3617 | int ret = 0; |
d24f31db | 3618 | |
98da491d | 3619 | ram_block_discard_disable_mutex_lock(); |
d24f31db | 3620 | if (!state) { |
98da491d | 3621 | ram_block_discard_disabled_cnt--; |
7e6d32eb DH |
3622 | } else if (ram_block_discard_required_cnt || |
3623 | ram_block_coordinated_discard_required_cnt) { | |
3624 | ret = -EBUSY; | |
98da491d | 3625 | } else { |
7e6d32eb DH |
3626 | ram_block_discard_disabled_cnt++; |
3627 | } | |
3628 | ram_block_discard_disable_mutex_unlock(); | |
3629 | return ret; | |
3630 | } | |
3631 | ||
3632 | int ram_block_uncoordinated_discard_disable(bool state) | |
3633 | { | |
3634 | int ret = 0; | |
3635 | ||
3636 | ram_block_discard_disable_mutex_lock(); | |
3637 | if (!state) { | |
3638 | ram_block_uncoordinated_discard_disabled_cnt--; | |
3639 | } else if (ram_block_discard_required_cnt) { | |
98da491d | 3640 | ret = -EBUSY; |
7e6d32eb DH |
3641 | } else { |
3642 | ram_block_uncoordinated_discard_disabled_cnt++; | |
d24f31db | 3643 | } |
98da491d DH |
3644 | ram_block_discard_disable_mutex_unlock(); |
3645 | return ret; | |
d24f31db DH |
3646 | } |
3647 | ||
3648 | int ram_block_discard_require(bool state) | |
3649 | { | |
98da491d | 3650 | int ret = 0; |
d24f31db | 3651 | |
98da491d | 3652 | ram_block_discard_disable_mutex_lock(); |
d24f31db | 3653 | if (!state) { |
98da491d | 3654 | ram_block_discard_required_cnt--; |
7e6d32eb DH |
3655 | } else if (ram_block_discard_disabled_cnt || |
3656 | ram_block_uncoordinated_discard_disabled_cnt) { | |
3657 | ret = -EBUSY; | |
98da491d | 3658 | } else { |
7e6d32eb DH |
3659 | ram_block_discard_required_cnt++; |
3660 | } | |
3661 | ram_block_discard_disable_mutex_unlock(); | |
3662 | return ret; | |
3663 | } | |
3664 | ||
3665 | int ram_block_coordinated_discard_require(bool state) | |
3666 | { | |
3667 | int ret = 0; | |
3668 | ||
3669 | ram_block_discard_disable_mutex_lock(); | |
3670 | if (!state) { | |
3671 | ram_block_coordinated_discard_required_cnt--; | |
3672 | } else if (ram_block_discard_disabled_cnt) { | |
98da491d | 3673 | ret = -EBUSY; |
7e6d32eb DH |
3674 | } else { |
3675 | ram_block_coordinated_discard_required_cnt++; | |
d24f31db | 3676 | } |
98da491d DH |
3677 | ram_block_discard_disable_mutex_unlock(); |
3678 | return ret; | |
d24f31db DH |
3679 | } |
3680 | ||
3681 | bool ram_block_discard_is_disabled(void) | |
3682 | { | |
7e6d32eb DH |
3683 | return qatomic_read(&ram_block_discard_disabled_cnt) || |
3684 | qatomic_read(&ram_block_uncoordinated_discard_disabled_cnt); | |
d24f31db DH |
3685 | } |
3686 | ||
3687 | bool ram_block_discard_is_required(void) | |
3688 | { | |
7e6d32eb DH |
3689 | return qatomic_read(&ram_block_discard_required_cnt) || |
3690 | qatomic_read(&ram_block_coordinated_discard_required_cnt); | |
d24f31db | 3691 | } |