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b92e5a22 FB |
1 | /* |
2 | * Software MMU support | |
5fafdf24 | 3 | * |
b92e5a22 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
b92e5a22 | 18 | */ |
29e922b6 BS |
19 | #include "qemu-timer.h" |
20 | ||
b92e5a22 FB |
21 | #define DATA_SIZE (1 << SHIFT) |
22 | ||
23 | #if DATA_SIZE == 8 | |
24 | #define SUFFIX q | |
61382a50 | 25 | #define USUFFIX q |
b92e5a22 FB |
26 | #define DATA_TYPE uint64_t |
27 | #elif DATA_SIZE == 4 | |
28 | #define SUFFIX l | |
61382a50 | 29 | #define USUFFIX l |
b92e5a22 FB |
30 | #define DATA_TYPE uint32_t |
31 | #elif DATA_SIZE == 2 | |
32 | #define SUFFIX w | |
61382a50 | 33 | #define USUFFIX uw |
b92e5a22 FB |
34 | #define DATA_TYPE uint16_t |
35 | #elif DATA_SIZE == 1 | |
36 | #define SUFFIX b | |
61382a50 | 37 | #define USUFFIX ub |
b92e5a22 FB |
38 | #define DATA_TYPE uint8_t |
39 | #else | |
40 | #error unsupported data size | |
41 | #endif | |
42 | ||
b769d8fe FB |
43 | #ifdef SOFTMMU_CODE_ACCESS |
44 | #define READ_ACCESS_TYPE 2 | |
84b7b8e7 | 45 | #define ADDR_READ addr_code |
b769d8fe FB |
46 | #else |
47 | #define READ_ACCESS_TYPE 0 | |
84b7b8e7 | 48 | #define ADDR_READ addr_read |
b769d8fe FB |
49 | #endif |
50 | ||
5fafdf24 | 51 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
6ebbf390 | 52 | int mmu_idx, |
61382a50 | 53 | void *retaddr); |
c227f099 | 54 | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
2e70f6ef PB |
55 | target_ulong addr, |
56 | void *retaddr) | |
b92e5a22 FB |
57 | { |
58 | DATA_TYPE res; | |
59 | int index; | |
0f459d16 PB |
60 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
61 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; | |
2e70f6ef PB |
62 | env->mem_io_pc = (unsigned long)retaddr; |
63 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT) | |
64 | && !can_do_io(env)) { | |
65 | cpu_io_recompile(env, retaddr); | |
66 | } | |
b92e5a22 | 67 | |
db8886d3 | 68 | env->mem_io_vaddr = addr; |
b92e5a22 | 69 | #if SHIFT <= 2 |
a4193c8a | 70 | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
b92e5a22 FB |
71 | #else |
72 | #ifdef TARGET_WORDS_BIGENDIAN | |
a4193c8a FB |
73 | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
74 | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); | |
b92e5a22 | 75 | #else |
a4193c8a FB |
76 | res = io_mem_read[index][2](io_mem_opaque[index], physaddr); |
77 | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; | |
b92e5a22 FB |
78 | #endif |
79 | #endif /* SHIFT > 2 */ | |
80 | return res; | |
81 | } | |
82 | ||
b92e5a22 | 83 | /* handle all cases except unaligned access which span two pages */ |
d656469f FB |
84 | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
85 | int mmu_idx) | |
b92e5a22 FB |
86 | { |
87 | DATA_TYPE res; | |
61382a50 | 88 | int index; |
c27004ec | 89 | target_ulong tlb_addr; |
c227f099 | 90 | target_phys_addr_t addend; |
b92e5a22 | 91 | void *retaddr; |
3b46e624 | 92 | |
b92e5a22 FB |
93 | /* test if there is match for unaligned or IO access */ |
94 | /* XXX: could done more in memory macro in a non portable way */ | |
b92e5a22 FB |
95 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
96 | redo: | |
6ebbf390 | 97 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
b92e5a22 | 98 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
b92e5a22 FB |
99 | if (tlb_addr & ~TARGET_PAGE_MASK) { |
100 | /* IO access */ | |
101 | if ((addr & (DATA_SIZE - 1)) != 0) | |
102 | goto do_unaligned_access; | |
2e70f6ef | 103 | retaddr = GETPC(); |
0f459d16 | 104 | addend = env->iotlb[mmu_idx][index]; |
2e70f6ef | 105 | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
98699967 | 106 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
b92e5a22 FB |
107 | /* slow unaligned access (it spans two pages or IO) */ |
108 | do_unaligned_access: | |
61382a50 | 109 | retaddr = GETPC(); |
a64d4718 | 110 | #ifdef ALIGNED_ONLY |
6ebbf390 | 111 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
a64d4718 | 112 | #endif |
5fafdf24 | 113 | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
6ebbf390 | 114 | mmu_idx, retaddr); |
b92e5a22 | 115 | } else { |
a64d4718 FB |
116 | /* unaligned/aligned access in the same page */ |
117 | #ifdef ALIGNED_ONLY | |
118 | if ((addr & (DATA_SIZE - 1)) != 0) { | |
119 | retaddr = GETPC(); | |
6ebbf390 | 120 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
a64d4718 FB |
121 | } |
122 | #endif | |
0f459d16 PB |
123 | addend = env->tlb_table[mmu_idx][index].addend; |
124 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend)); | |
b92e5a22 FB |
125 | } |
126 | } else { | |
127 | /* the page is not in the TLB : fill it */ | |
61382a50 | 128 | retaddr = GETPC(); |
a64d4718 FB |
129 | #ifdef ALIGNED_ONLY |
130 | if ((addr & (DATA_SIZE - 1)) != 0) | |
6ebbf390 | 131 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
a64d4718 | 132 | #endif |
6ebbf390 | 133 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
b92e5a22 FB |
134 | goto redo; |
135 | } | |
136 | return res; | |
137 | } | |
138 | ||
139 | /* handle all unaligned cases */ | |
5fafdf24 | 140 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
6ebbf390 | 141 | int mmu_idx, |
61382a50 | 142 | void *retaddr) |
b92e5a22 FB |
143 | { |
144 | DATA_TYPE res, res1, res2; | |
61382a50 | 145 | int index, shift; |
c227f099 | 146 | target_phys_addr_t addend; |
c27004ec | 147 | target_ulong tlb_addr, addr1, addr2; |
b92e5a22 | 148 | |
b92e5a22 FB |
149 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
150 | redo: | |
6ebbf390 | 151 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
b92e5a22 | 152 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
b92e5a22 FB |
153 | if (tlb_addr & ~TARGET_PAGE_MASK) { |
154 | /* IO access */ | |
155 | if ((addr & (DATA_SIZE - 1)) != 0) | |
156 | goto do_unaligned_access; | |
0f459d16 | 157 | addend = env->iotlb[mmu_idx][index]; |
2e70f6ef | 158 | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
98699967 | 159 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
b92e5a22 FB |
160 | do_unaligned_access: |
161 | /* slow unaligned access (it spans two pages) */ | |
162 | addr1 = addr & ~(DATA_SIZE - 1); | |
163 | addr2 = addr1 + DATA_SIZE; | |
5fafdf24 | 164 | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
6ebbf390 | 165 | mmu_idx, retaddr); |
5fafdf24 | 166 | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
6ebbf390 | 167 | mmu_idx, retaddr); |
b92e5a22 FB |
168 | shift = (addr & (DATA_SIZE - 1)) * 8; |
169 | #ifdef TARGET_WORDS_BIGENDIAN | |
170 | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); | |
171 | #else | |
172 | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); | |
173 | #endif | |
6986f88c | 174 | res = (DATA_TYPE)res; |
b92e5a22 FB |
175 | } else { |
176 | /* unaligned/aligned access in the same page */ | |
0f459d16 PB |
177 | addend = env->tlb_table[mmu_idx][index].addend; |
178 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend)); | |
b92e5a22 FB |
179 | } |
180 | } else { | |
181 | /* the page is not in the TLB : fill it */ | |
6ebbf390 | 182 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
b92e5a22 FB |
183 | goto redo; |
184 | } | |
185 | return res; | |
186 | } | |
187 | ||
b769d8fe FB |
188 | #ifndef SOFTMMU_CODE_ACCESS |
189 | ||
5fafdf24 TS |
190 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
191 | DATA_TYPE val, | |
6ebbf390 | 192 | int mmu_idx, |
b769d8fe FB |
193 | void *retaddr); |
194 | ||
c227f099 | 195 | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
b769d8fe | 196 | DATA_TYPE val, |
0f459d16 | 197 | target_ulong addr, |
b769d8fe FB |
198 | void *retaddr) |
199 | { | |
200 | int index; | |
0f459d16 PB |
201 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
202 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; | |
2e70f6ef PB |
203 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT) |
204 | && !can_do_io(env)) { | |
205 | cpu_io_recompile(env, retaddr); | |
206 | } | |
b769d8fe | 207 | |
2e70f6ef PB |
208 | env->mem_io_vaddr = addr; |
209 | env->mem_io_pc = (unsigned long)retaddr; | |
b769d8fe FB |
210 | #if SHIFT <= 2 |
211 | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); | |
212 | #else | |
213 | #ifdef TARGET_WORDS_BIGENDIAN | |
214 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); | |
215 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); | |
216 | #else | |
217 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val); | |
218 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); | |
219 | #endif | |
220 | #endif /* SHIFT > 2 */ | |
221 | } | |
b92e5a22 | 222 | |
d656469f FB |
223 | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
224 | DATA_TYPE val, | |
225 | int mmu_idx) | |
b92e5a22 | 226 | { |
c227f099 | 227 | target_phys_addr_t addend; |
c27004ec | 228 | target_ulong tlb_addr; |
b92e5a22 | 229 | void *retaddr; |
61382a50 | 230 | int index; |
3b46e624 | 231 | |
b92e5a22 FB |
232 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
233 | redo: | |
6ebbf390 | 234 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
b92e5a22 | 235 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
b92e5a22 FB |
236 | if (tlb_addr & ~TARGET_PAGE_MASK) { |
237 | /* IO access */ | |
238 | if ((addr & (DATA_SIZE - 1)) != 0) | |
239 | goto do_unaligned_access; | |
d720b93d | 240 | retaddr = GETPC(); |
0f459d16 PB |
241 | addend = env->iotlb[mmu_idx][index]; |
242 | glue(io_write, SUFFIX)(addend, val, addr, retaddr); | |
98699967 | 243 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
b92e5a22 | 244 | do_unaligned_access: |
61382a50 | 245 | retaddr = GETPC(); |
a64d4718 | 246 | #ifdef ALIGNED_ONLY |
6ebbf390 | 247 | do_unaligned_access(addr, 1, mmu_idx, retaddr); |
a64d4718 | 248 | #endif |
5fafdf24 | 249 | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
6ebbf390 | 250 | mmu_idx, retaddr); |
b92e5a22 FB |
251 | } else { |
252 | /* aligned/unaligned access in the same page */ | |
a64d4718 FB |
253 | #ifdef ALIGNED_ONLY |
254 | if ((addr & (DATA_SIZE - 1)) != 0) { | |
255 | retaddr = GETPC(); | |
6ebbf390 | 256 | do_unaligned_access(addr, 1, mmu_idx, retaddr); |
a64d4718 FB |
257 | } |
258 | #endif | |
0f459d16 PB |
259 | addend = env->tlb_table[mmu_idx][index].addend; |
260 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val); | |
b92e5a22 FB |
261 | } |
262 | } else { | |
263 | /* the page is not in the TLB : fill it */ | |
61382a50 | 264 | retaddr = GETPC(); |
a64d4718 FB |
265 | #ifdef ALIGNED_ONLY |
266 | if ((addr & (DATA_SIZE - 1)) != 0) | |
6ebbf390 | 267 | do_unaligned_access(addr, 1, mmu_idx, retaddr); |
a64d4718 | 268 | #endif |
6ebbf390 | 269 | tlb_fill(addr, 1, mmu_idx, retaddr); |
b92e5a22 FB |
270 | goto redo; |
271 | } | |
272 | } | |
273 | ||
274 | /* handles all unaligned cases */ | |
5fafdf24 | 275 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
61382a50 | 276 | DATA_TYPE val, |
6ebbf390 | 277 | int mmu_idx, |
61382a50 | 278 | void *retaddr) |
b92e5a22 | 279 | { |
c227f099 | 280 | target_phys_addr_t addend; |
c27004ec | 281 | target_ulong tlb_addr; |
61382a50 | 282 | int index, i; |
b92e5a22 | 283 | |
b92e5a22 FB |
284 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
285 | redo: | |
6ebbf390 | 286 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
b92e5a22 | 287 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
b92e5a22 FB |
288 | if (tlb_addr & ~TARGET_PAGE_MASK) { |
289 | /* IO access */ | |
290 | if ((addr & (DATA_SIZE - 1)) != 0) | |
291 | goto do_unaligned_access; | |
0f459d16 PB |
292 | addend = env->iotlb[mmu_idx][index]; |
293 | glue(io_write, SUFFIX)(addend, val, addr, retaddr); | |
98699967 | 294 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
b92e5a22 FB |
295 | do_unaligned_access: |
296 | /* XXX: not efficient, but simple */ | |
6c41b272 AZ |
297 | /* Note: relies on the fact that tlb_fill() does not remove the |
298 | * previous page from the TLB cache. */ | |
7221fa98 | 299 | for(i = DATA_SIZE - 1; i >= 0; i--) { |
b92e5a22 | 300 | #ifdef TARGET_WORDS_BIGENDIAN |
5fafdf24 | 301 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
6ebbf390 | 302 | mmu_idx, retaddr); |
b92e5a22 | 303 | #else |
5fafdf24 | 304 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8), |
6ebbf390 | 305 | mmu_idx, retaddr); |
b92e5a22 FB |
306 | #endif |
307 | } | |
308 | } else { | |
309 | /* aligned/unaligned access in the same page */ | |
0f459d16 PB |
310 | addend = env->tlb_table[mmu_idx][index].addend; |
311 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val); | |
b92e5a22 FB |
312 | } |
313 | } else { | |
314 | /* the page is not in the TLB : fill it */ | |
6ebbf390 | 315 | tlb_fill(addr, 1, mmu_idx, retaddr); |
b92e5a22 FB |
316 | goto redo; |
317 | } | |
318 | } | |
319 | ||
b769d8fe FB |
320 | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
321 | ||
322 | #undef READ_ACCESS_TYPE | |
b92e5a22 FB |
323 | #undef SHIFT |
324 | #undef DATA_TYPE | |
325 | #undef SUFFIX | |
61382a50 | 326 | #undef USUFFIX |
b92e5a22 | 327 | #undef DATA_SIZE |
84b7b8e7 | 328 | #undef ADDR_READ |