[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong addr)
{
    DATA_TYPE res;
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                      int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

    env->mem_write_vaddr = addr;
    env->mem_write_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
}

void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                 DATA_TYPE val,
                                                 int mmu_idx)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#define DATA_SIZE (1 << SHIFT)
	21
	22	#if DATA_SIZE == 8
	23	#define SUFFIX q
61382a50	24	#define USUFFIX q
b92e5a22 FB	25	#define DATA_TYPE uint64_t
	26	#elif DATA_SIZE == 4
	27	#define SUFFIX l
61382a50	28	#define USUFFIX l
b92e5a22 FB	29	#define DATA_TYPE uint32_t
	30	#elif DATA_SIZE == 2
	31	#define SUFFIX w
61382a50	32	#define USUFFIX uw
b92e5a22 FB	33	#define DATA_TYPE uint16_t
	34	#elif DATA_SIZE == 1
	35	#define SUFFIX b
61382a50	36	#define USUFFIX ub
b92e5a22 FB	37	#define DATA_TYPE uint8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
b769d8fe FB	42	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	43	#define READ_ACCESS_TYPE 2
84b7b8e7	44	#define ADDR_READ addr_code
b769d8fe FB	45	#else
b769d8fe FB	46	#define READ_ACCESS_TYPE 0
84b7b8e7	47	#define ADDR_READ addr_read
b769d8fe FB	48	#endif
b769d8fe FB	49
5fafdf24	50	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	51	int mmu_idx,
61382a50	52	void *retaddr);
5fafdf24	53	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
0f459d16	54	target_ulong addr)
b92e5a22 FB	55	{
	56	DATA_TYPE res;
	57	int index;
0f459d16 PB	58	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	59	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
b92e5a22	60
b92e5a22	61	#if SHIFT <= 2
a4193c8a	62	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	63	#else
b92e5a22 FB	64	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	65	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	66	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	67	#else
a4193c8a FB	68	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	69	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	70	#endif
b92e5a22 FB	71	#endif /* SHIFT > 2 */
f1c85677 FB	72	#ifdef USE_KQEMU
	73	env->last_io_time = cpu_get_time_fast();
	74	#endif
b92e5a22 FB	75	return res;
	76	}
	77
b92e5a22	78	/* handle all cases except unaligned access which span two pages */
d656469f FB	79	DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
d656469f FB	80	int mmu_idx)
b92e5a22 FB	81	{
b92e5a22 FB	82	DATA_TYPE res;
61382a50	83	int index;
c27004ec	84	target_ulong tlb_addr;
0f459d16	85	target_phys_addr_t addend;
b92e5a22	86	void *retaddr;
3b46e624	87
b92e5a22 FB	88	/* test if there is match for unaligned or IO access */
b92e5a22 FB	89	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	90	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	91	redo:
6ebbf390	92	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	93	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	94	if (tlb_addr & ~TARGET_PAGE_MASK) {
	95	/* IO access */
	96	if ((addr & (DATA_SIZE - 1)) != 0)
	97	goto do_unaligned_access;
0f459d16 PB	98	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	99	res = glue(io_read, SUFFIX)(addend, addr);
98699967	100	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	101	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	102	do_unaligned_access:
61382a50	103	retaddr = GETPC();
a64d4718	104	#ifdef ALIGNED_ONLY
6ebbf390	105	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	106	#endif
5fafdf24	107	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390	108	mmu_idx, retaddr);
b92e5a22	109	} else {
a64d4718 FB	110	/* unaligned/aligned access in the same page */
	111	#ifdef ALIGNED_ONLY
	112	if ((addr & (DATA_SIZE - 1)) != 0) {
	113	retaddr = GETPC();
6ebbf390	114	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	115	}
a64d4718 FB	116	#endif
0f459d16 PB	117	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	118	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	119	}
	120	} else {
	121	/* the page is not in the TLB : fill it */
61382a50	122	retaddr = GETPC();
a64d4718 FB	123	#ifdef ALIGNED_ONLY
a64d4718 FB	124	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	125	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	126	#endif
6ebbf390	127	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	128	goto redo;
	129	}
	130	return res;
	131	}
	132
	133	/* handle all unaligned cases */
5fafdf24	134	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	135	int mmu_idx,
61382a50	136	void *retaddr)
b92e5a22 FB	137	{
b92e5a22 FB	138	DATA_TYPE res, res1, res2;
61382a50	139	int index, shift;
0f459d16	140	target_phys_addr_t addend;
c27004ec	141	target_ulong tlb_addr, addr1, addr2;
b92e5a22	142
b92e5a22 FB	143	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	144	redo:
6ebbf390	145	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	146	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	147	if (tlb_addr & ~TARGET_PAGE_MASK) {
	148	/* IO access */
	149	if ((addr & (DATA_SIZE - 1)) != 0)
	150	goto do_unaligned_access;
0f459d16 PB	151	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	152	res = glue(io_read, SUFFIX)(addend, addr);
98699967	153	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	154	do_unaligned_access:
	155	/* slow unaligned access (it spans two pages) */
	156	addr1 = addr & ~(DATA_SIZE - 1);
	157	addr2 = addr1 + DATA_SIZE;
5fafdf24	158	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390	159	mmu_idx, retaddr);
5fafdf24	160	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390	161	mmu_idx, retaddr);
b92e5a22 FB	162	shift = (addr & (DATA_SIZE - 1)) * 8;
	163	#ifdef TARGET_WORDS_BIGENDIAN
	164	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	165	#else
	166	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	167	#endif
6986f88c	168	res = (DATA_TYPE)res;
b92e5a22 FB	169	} else {
b92e5a22 FB	170	/* unaligned/aligned access in the same page */
0f459d16 PB	171	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	172	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	173	}
	174	} else {
	175	/* the page is not in the TLB : fill it */
6ebbf390	176	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	177	goto redo;
	178	}
	179	return res;
	180	}
	181
b769d8fe FB	182	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	183
5fafdf24 TS	184	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
5fafdf24 TS	185	DATA_TYPE val,
6ebbf390	186	int mmu_idx,
b769d8fe FB	187	void *retaddr);
b769d8fe FB	188
5fafdf24	189	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	190	DATA_TYPE val,
0f459d16	191	target_ulong addr,
b769d8fe FB	192	void *retaddr)
	193	{
	194	int index;
0f459d16 PB	195	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	196	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
b769d8fe	197
0f459d16	198	env->mem_write_vaddr = addr;
b769d8fe FB	199	env->mem_write_pc = (unsigned long)retaddr;
	200	#if SHIFT <= 2
	201	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	202	#else
	203	#ifdef TARGET_WORDS_BIGENDIAN
	204	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	205	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	206	#else
	207	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	208	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	209	#endif
	210	#endif /* SHIFT > 2 */
f1c85677 FB	211	#ifdef USE_KQEMU
	212	env->last_io_time = cpu_get_time_fast();
	213	#endif
b769d8fe	214	}
b92e5a22	215
d656469f FB	216	void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	217	DATA_TYPE val,
	218	int mmu_idx)
b92e5a22	219	{
0f459d16	220	target_phys_addr_t addend;
c27004ec	221	target_ulong tlb_addr;
b92e5a22	222	void *retaddr;
61382a50	223	int index;
3b46e624	224
b92e5a22 FB	225	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	226	redo:
6ebbf390	227	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	228	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	229	if (tlb_addr & ~TARGET_PAGE_MASK) {
	230	/* IO access */
	231	if ((addr & (DATA_SIZE - 1)) != 0)
	232	goto do_unaligned_access;
d720b93d	233	retaddr = GETPC();
0f459d16 PB	234	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	235	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	236	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	237	do_unaligned_access:
61382a50	238	retaddr = GETPC();
a64d4718	239	#ifdef ALIGNED_ONLY
6ebbf390	240	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	241	#endif
5fafdf24	242	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390	243	mmu_idx, retaddr);
b92e5a22 FB	244	} else {
b92e5a22 FB	245	/* aligned/unaligned access in the same page */
a64d4718 FB	246	#ifdef ALIGNED_ONLY
	247	if ((addr & (DATA_SIZE - 1)) != 0) {
	248	retaddr = GETPC();
6ebbf390	249	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 FB	250	}
a64d4718 FB	251	#endif
0f459d16 PB	252	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	253	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	254	}
	255	} else {
	256	/* the page is not in the TLB : fill it */
61382a50	257	retaddr = GETPC();
a64d4718 FB	258	#ifdef ALIGNED_ONLY
a64d4718 FB	259	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	260	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	261	#endif
6ebbf390	262	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	263	goto redo;
	264	}
	265	}
	266
	267	/* handles all unaligned cases */
5fafdf24	268	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	269	DATA_TYPE val,
6ebbf390	270	int mmu_idx,
61382a50	271	void *retaddr)
b92e5a22	272	{
0f459d16	273	target_phys_addr_t addend;
c27004ec	274	target_ulong tlb_addr;
61382a50	275	int index, i;
b92e5a22	276
b92e5a22 FB	277	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	278	redo:
6ebbf390	279	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	280	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	281	if (tlb_addr & ~TARGET_PAGE_MASK) {
	282	/* IO access */
	283	if ((addr & (DATA_SIZE - 1)) != 0)
	284	goto do_unaligned_access;
0f459d16 PB	285	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	286	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	287	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	288	do_unaligned_access:
b92e5a22 FB	289	/* XXX: not efficient, but simple */
6c41b272 AZ	290	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	291	* previous page from the TLB cache. */
7221fa98	292	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	293	#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24	294	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	295	mmu_idx, retaddr);
b92e5a22	296	#else
5fafdf24	297	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390	298	mmu_idx, retaddr);
b92e5a22 FB	299	#endif
	300	}
	301	} else {
	302	/* aligned/unaligned access in the same page */
0f459d16 PB	303	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	304	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	305	}
	306	} else {
	307	/* the page is not in the TLB : fill it */
6ebbf390	308	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	309	goto redo;
	310	}
	311	}
	312
b769d8fe FB	313	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	314
	315	#undef READ_ACCESS_TYPE
b92e5a22 FB	316	#undef SHIFT
	317	#undef DATA_TYPE
	318	#undef SUFFIX
61382a50	319	#undef USUFFIX
b92e5a22	320	#undef DATA_SIZE
84b7b8e7	321	#undef ADDR_READ