[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong tlb_addr)
{
    DATA_TYPE res;
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t physaddr;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t physaddr;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong tlb_addr,
                                          void *retaddr)
{
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    env->mem_write_vaddr = tlb_addr;
    env->mem_write_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
}

void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                    DATA_TYPE val,
                                                    int mmu_idx)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#define DATA_SIZE (1 << SHIFT)
	21
	22	#if DATA_SIZE == 8
	23	#define SUFFIX q
61382a50	24	#define USUFFIX q
b92e5a22 FB	25	#define DATA_TYPE uint64_t
	26	#elif DATA_SIZE == 4
	27	#define SUFFIX l
61382a50	28	#define USUFFIX l
b92e5a22 FB	29	#define DATA_TYPE uint32_t
	30	#elif DATA_SIZE == 2
	31	#define SUFFIX w
61382a50	32	#define USUFFIX uw
b92e5a22 FB	33	#define DATA_TYPE uint16_t
	34	#elif DATA_SIZE == 1
	35	#define SUFFIX b
61382a50	36	#define USUFFIX ub
b92e5a22 FB	37	#define DATA_TYPE uint8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
b769d8fe FB	42	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	43	#define READ_ACCESS_TYPE 2
84b7b8e7	44	#define ADDR_READ addr_code
b769d8fe FB	45	#else
b769d8fe FB	46	#define READ_ACCESS_TYPE 0
84b7b8e7	47	#define ADDR_READ addr_read
b769d8fe FB	48	#endif
b769d8fe FB	49
5fafdf24	50	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	51	int mmu_idx,
61382a50	52	void *retaddr);
5fafdf24	53	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
c27004ec	54	target_ulong tlb_addr)
b92e5a22 FB	55	{
	56	DATA_TYPE res;
	57	int index;
	58
	59	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	60	#if SHIFT <= 2
a4193c8a	61	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	62	#else
b92e5a22 FB	63	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	64	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	65	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	66	#else
a4193c8a FB	67	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	68	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	69	#endif
b92e5a22 FB	70	#endif /* SHIFT > 2 */
f1c85677 FB	71	#ifdef USE_KQEMU
	72	env->last_io_time = cpu_get_time_fast();
	73	#endif
b92e5a22 FB	74	return res;
	75	}
	76
b92e5a22	77	/* handle all cases except unaligned access which span two pages */
c27004ec	78	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	79	int mmu_idx)
b92e5a22 FB	80	{
b92e5a22 FB	81	DATA_TYPE res;
61382a50	82	int index;
c27004ec	83	target_ulong tlb_addr;
108c49b8	84	target_phys_addr_t physaddr;
b92e5a22	85	void *retaddr;
3b46e624	86
b92e5a22 FB	87	/* test if there is match for unaligned or IO access */
b92e5a22 FB	88	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	89	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	90	redo:
6ebbf390	91	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	92	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
6ebbf390	93	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	94	if (tlb_addr & ~TARGET_PAGE_MASK) {
	95	/* IO access */
	96	if ((addr & (DATA_SIZE - 1)) != 0)
	97	goto do_unaligned_access;
	98	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	99	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	100	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	101	do_unaligned_access:
61382a50	102	retaddr = GETPC();
a64d4718	103	#ifdef ALIGNED_ONLY
6ebbf390	104	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	105	#endif
5fafdf24	106	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390	107	mmu_idx, retaddr);
b92e5a22	108	} else {
a64d4718 FB	109	/* unaligned/aligned access in the same page */
	110	#ifdef ALIGNED_ONLY
	111	if ((addr & (DATA_SIZE - 1)) != 0) {
	112	retaddr = GETPC();
6ebbf390	113	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	114	}
a64d4718 FB	115	#endif
108c49b8	116	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	117	}
	118	} else {
	119	/* the page is not in the TLB : fill it */
61382a50	120	retaddr = GETPC();
a64d4718 FB	121	#ifdef ALIGNED_ONLY
a64d4718 FB	122	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	123	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	124	#endif
6ebbf390	125	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	126	goto redo;
	127	}
	128	return res;
	129	}
	130
	131	/* handle all unaligned cases */
5fafdf24	132	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	133	int mmu_idx,
61382a50	134	void *retaddr)
b92e5a22 FB	135	{
b92e5a22 FB	136	DATA_TYPE res, res1, res2;
61382a50	137	int index, shift;
108c49b8	138	target_phys_addr_t physaddr;
c27004ec	139	target_ulong tlb_addr, addr1, addr2;
b92e5a22	140
b92e5a22 FB	141	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	142	redo:
6ebbf390	143	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	144	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
6ebbf390	145	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	146	if (tlb_addr & ~TARGET_PAGE_MASK) {
	147	/* IO access */
	148	if ((addr & (DATA_SIZE - 1)) != 0)
	149	goto do_unaligned_access;
	150	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	151	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	152	do_unaligned_access:
	153	/* slow unaligned access (it spans two pages) */
	154	addr1 = addr & ~(DATA_SIZE - 1);
	155	addr2 = addr1 + DATA_SIZE;
5fafdf24	156	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390	157	mmu_idx, retaddr);
5fafdf24	158	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390	159	mmu_idx, retaddr);
b92e5a22 FB	160	shift = (addr & (DATA_SIZE - 1)) * 8;
	161	#ifdef TARGET_WORDS_BIGENDIAN
	162	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	163	#else
	164	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	165	#endif
6986f88c	166	res = (DATA_TYPE)res;
b92e5a22 FB	167	} else {
b92e5a22 FB	168	/* unaligned/aligned access in the same page */
108c49b8	169	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	170	}
	171	} else {
	172	/* the page is not in the TLB : fill it */
6ebbf390	173	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	174	goto redo;
	175	}
	176	return res;
	177	}
	178
b769d8fe FB	179	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	180
5fafdf24 TS	181	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
5fafdf24 TS	182	DATA_TYPE val,
6ebbf390	183	int mmu_idx,
b769d8fe FB	184	void *retaddr);
b769d8fe FB	185
5fafdf24	186	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	187	DATA_TYPE val,
c27004ec	188	target_ulong tlb_addr,
b769d8fe FB	189	void *retaddr)
	190	{
	191	int index;
	192
	193	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	194	env->mem_write_vaddr = tlb_addr;
	195	env->mem_write_pc = (unsigned long)retaddr;
	196	#if SHIFT <= 2
	197	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	198	#else
	199	#ifdef TARGET_WORDS_BIGENDIAN
	200	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	201	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	202	#else
	203	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	204	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	205	#endif
	206	#endif /* SHIFT > 2 */
f1c85677 FB	207	#ifdef USE_KQEMU
	208	env->last_io_time = cpu_get_time_fast();
	209	#endif
b769d8fe	210	}
b92e5a22	211
5fafdf24	212	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	213	DATA_TYPE val,
6ebbf390	214	int mmu_idx)
b92e5a22	215	{
108c49b8	216	target_phys_addr_t physaddr;
c27004ec	217	target_ulong tlb_addr;
b92e5a22	218	void *retaddr;
61382a50	219	int index;
3b46e624	220
b92e5a22 FB	221	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	222	redo:
6ebbf390	223	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	224	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
6ebbf390	225	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	226	if (tlb_addr & ~TARGET_PAGE_MASK) {
	227	/* IO access */
	228	if ((addr & (DATA_SIZE - 1)) != 0)
	229	goto do_unaligned_access;
d720b93d FB	230	retaddr = GETPC();
d720b93d FB	231	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	232	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	233	do_unaligned_access:
61382a50	234	retaddr = GETPC();
a64d4718	235	#ifdef ALIGNED_ONLY
6ebbf390	236	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	237	#endif
5fafdf24	238	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390	239	mmu_idx, retaddr);
b92e5a22 FB	240	} else {
b92e5a22 FB	241	/* aligned/unaligned access in the same page */
a64d4718 FB	242	#ifdef ALIGNED_ONLY
	243	if ((addr & (DATA_SIZE - 1)) != 0) {
	244	retaddr = GETPC();
6ebbf390	245	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 FB	246	}
a64d4718 FB	247	#endif
108c49b8	248	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	249	}
	250	} else {
	251	/* the page is not in the TLB : fill it */
61382a50	252	retaddr = GETPC();
a64d4718 FB	253	#ifdef ALIGNED_ONLY
a64d4718 FB	254	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	255	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	256	#endif
6ebbf390	257	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	258	goto redo;
	259	}
	260	}
	261
	262	/* handles all unaligned cases */
5fafdf24	263	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	264	DATA_TYPE val,
6ebbf390	265	int mmu_idx,
61382a50	266	void *retaddr)
b92e5a22	267	{
108c49b8	268	target_phys_addr_t physaddr;
c27004ec	269	target_ulong tlb_addr;
61382a50	270	int index, i;
b92e5a22	271
b92e5a22 FB	272	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	273	redo:
6ebbf390	274	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	275	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
6ebbf390	276	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	277	if (tlb_addr & ~TARGET_PAGE_MASK) {
	278	/* IO access */
	279	if ((addr & (DATA_SIZE - 1)) != 0)
	280	goto do_unaligned_access;
d720b93d	281	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	282	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	283	do_unaligned_access:
b92e5a22 FB	284	/* XXX: not efficient, but simple */
6c41b272 AZ	285	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	286	* previous page from the TLB cache. */
7221fa98	287	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	288	#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24	289	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	290	mmu_idx, retaddr);
b92e5a22	291	#else
5fafdf24	292	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390	293	mmu_idx, retaddr);
b92e5a22 FB	294	#endif
	295	}
	296	} else {
	297	/* aligned/unaligned access in the same page */
108c49b8	298	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	299	}
	300	} else {
	301	/* the page is not in the TLB : fill it */
6ebbf390	302	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	303	goto redo;
	304	}
	305	}
	306
b769d8fe FB	307	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	308
	309	#undef READ_ACCESS_TYPE
b92e5a22 FB	310	#undef SHIFT
	311	#undef DATA_TYPE
	312	#undef SUFFIX
61382a50	313	#undef USUFFIX
b92e5a22	314	#undef DATA_SIZE
84b7b8e7	315	#undef ADDR_READ