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ASoC: AMD: Manage ACP 2.x SRAM banks power
[mirror_ubuntu-disco-kernel.git] / sound / soc / amd / acp-pcm-dma.c
CommitLineData
7c31335a
MSB		 1/*
2 * AMD ALSA SoC PCM Driver for ACP 2.x
3 *
4 * Copyright 2014-2015 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/sizes.h>
1927da93 19#include <linux/pm_runtime.h>
7c31335a
MSB		 20
21#include <sound/soc.h>
22
23#include "acp.h"
24
25#define PLAYBACK_MIN_NUM_PERIODS 2
26#define PLAYBACK_MAX_NUM_PERIODS 2
27#define PLAYBACK_MAX_PERIOD_SIZE 16384
28#define PLAYBACK_MIN_PERIOD_SIZE 1024
29#define CAPTURE_MIN_NUM_PERIODS 2
30#define CAPTURE_MAX_NUM_PERIODS 2
31#define CAPTURE_MAX_PERIOD_SIZE 16384
32#define CAPTURE_MIN_PERIOD_SIZE 1024
33
34#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
35#define MIN_BUFFER MAX_BUFFER
36
37static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
38 .info = SNDRV_PCM_INFO_INTERLEAVED |
39 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
40 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
41 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
42 .formats = SNDRV_PCM_FMTBIT_S16_LE |
43 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
44 .channels_min = 1,
45 .channels_max = 8,
46 .rates = SNDRV_PCM_RATE_8000_96000,
47 .rate_min = 8000,
48 .rate_max = 96000,
49 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
50 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
51 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
52 .periods_min = PLAYBACK_MIN_NUM_PERIODS,
53 .periods_max = PLAYBACK_MAX_NUM_PERIODS,
54};
55
56static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
57 .info = SNDRV_PCM_INFO_INTERLEAVED |
58 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
59 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
60 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
61 .formats = SNDRV_PCM_FMTBIT_S16_LE |
62 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
63 .channels_min = 1,
64 .channels_max = 2,
65 .rates = SNDRV_PCM_RATE_8000_48000,
66 .rate_min = 8000,
67 .rate_max = 48000,
68 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
69 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
70 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
71 .periods_min = CAPTURE_MIN_NUM_PERIODS,
72 .periods_max = CAPTURE_MAX_NUM_PERIODS,
73};
74
75struct audio_drv_data {
76 struct snd_pcm_substream *play_stream;
77 struct snd_pcm_substream *capture_stream;
78 void __iomem *acp_mmio;
79};
80
81static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
82{
83 return readl(acp_mmio + (reg * 4));
84}
85
86static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
87{
88 writel(val, acp_mmio + (reg * 4));
89}
90
91/* Configure a given dma channel parameters - enable/disble,
92 * number of descriptors, priority
93 */
94static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
95 u16 dscr_strt_idx, u16 num_dscrs,
96 enum acp_dma_priority_level priority_level)
97{
98 u32 dma_ctrl;
99
100 /* disable the channel run field */
101 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
102 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
103 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
104
105 /* program a DMA channel with first descriptor to be processed. */
106 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
107 & dscr_strt_idx),
108 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
109
110 /* program a DMA channel with the number of descriptors to be
111 * processed in the transfer
112 */
113 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
114 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
115
116 /* set DMA channel priority */
117 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
118}
119
120/* Initialize a dma descriptor in SRAM based on descritor information passed */
121static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
122 u16 descr_idx,
123 acp_dma_dscr_transfer_t *descr_info)
124{
125 u32 sram_offset;
126
127 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
128
129 /* program the source base address. */
130 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
131 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
132 /* program the destination base address. */
133 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
134 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
135
136 /* program the number of bytes to be transferred for this descriptor. */
137 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
138 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
139}
140
141/* Initialize the DMA descriptor information for transfer between
142 * system memory <-> ACP SRAM
143 */
144static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
145 u32 size, int direction,
146 u32 pte_offset)
147{
148 u16 i;
149 u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
150 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
151
152 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
153 dmadscr[i].xfer_val = 0;
154 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
155 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i;
156 dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS +
157 (size / 2) - (i * (size/2));
158 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
159 + (pte_offset * SZ_4K) + (i * (size/2));
160 dmadscr[i].xfer_val |=
161 (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
162 (size / 2);
163 } else {
164 dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
165 dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
166 (i * (size/2));
167 dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
168 + (pte_offset * SZ_4K) +
169 (i * (size/2));
170 dmadscr[i].xfer_val |=
171 BIT(22) |
172 (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
173 (size / 2);
174 }
175 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
176 &dmadscr[i]);
177 }
178 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
179 config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM,
180 PLAYBACK_START_DMA_DESCR_CH12,
181 NUM_DSCRS_PER_CHANNEL,
182 ACP_DMA_PRIORITY_LEVEL_NORMAL);
183 else
184 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM,
185 CAPTURE_START_DMA_DESCR_CH14,
186 NUM_DSCRS_PER_CHANNEL,
187 ACP_DMA_PRIORITY_LEVEL_NORMAL);
188}
189
190/* Initialize the DMA descriptor information for transfer between
191 * ACP SRAM <-> I2S
192 */
193static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
194 u32 size, int direction)
195{
196
197 u16 i;
198 u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
199 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
200
201 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
202 dmadscr[i].xfer_val = 0;
203 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
204 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i;
205 dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS +
206 (i * (size/2));
207 /* dmadscr[i].dest is unused by hardware. */
208 dmadscr[i].dest = 0;
209 dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) |
210 (size / 2);
211 } else {
212 dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i;
213 /* dmadscr[i].src is unused by hardware. */
214 dmadscr[i].src = 0;
215 dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS +
216 (i * (size / 2));
217 dmadscr[i].xfer_val |= BIT(22) |
218 (FROM_ACP_I2S_1 << 16) | (size / 2);
219 }
220 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
221 &dmadscr[i]);
222 }
223 /* Configure the DMA channel with the above descriptore */
224 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
225 config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
226 PLAYBACK_START_DMA_DESCR_CH13,
227 NUM_DSCRS_PER_CHANNEL,
228 ACP_DMA_PRIORITY_LEVEL_NORMAL);
229 else
230 config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
231 CAPTURE_START_DMA_DESCR_CH15,
232 NUM_DSCRS_PER_CHANNEL,
233 ACP_DMA_PRIORITY_LEVEL_NORMAL);
234}
235
236/* Create page table entries in ACP SRAM for the allocated memory */
237static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
238 u16 num_of_pages, u32 pte_offset)
239{
240 u16 page_idx;
241 u64 addr;
242 u32 low;
243 u32 high;
244 u32 offset;
245
246 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
247 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
248 /* Load the low address of page int ACP SRAM through SRBM */
249 acp_reg_write((offset + (page_idx * 8)),
250 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
251 addr = page_to_phys(pg);
252
253 low = lower_32_bits(addr);
254 high = upper_32_bits(addr);
255
256 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
257
258 /* Load the High address of page int ACP SRAM through SRBM */
259 acp_reg_write((offset + (page_idx * 8) + 4),
260 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
261
262 /* page enable in ACP */
263 high |= BIT(31);
264 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
265
266 /* Move to next physically contiguos page */
267 pg++;
268 }
269}
270
271static void config_acp_dma(void __iomem *acp_mmio,
272 struct audio_substream_data *audio_config)
273{
274 u32 pte_offset;
275
276 if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
277 pte_offset = ACP_PLAYBACK_PTE_OFFSET;
278 else
279 pte_offset = ACP_CAPTURE_PTE_OFFSET;
280
281 acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages,
282 pte_offset);
283
284 /* Configure System memory <-> ACP SRAM DMA descriptors */
285 set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
286 audio_config->direction, pte_offset);
287
288 /* Configure ACP SRAM <-> I2S DMA descriptors */
289 set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
290 audio_config->direction);
291}
292
293/* Start a given DMA channel transfer */
294static void acp_dma_start(void __iomem *acp_mmio,
295 u16 ch_num, bool is_circular)
296{
297 u32 dma_ctrl;
298
299 /* read the dma control register and disable the channel run field */
300 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
301
302 /* Invalidating the DAGB cache */
303 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
304
305 /* configure the DMA channel and start the DMA transfer
306 * set dmachrun bit to start the transfer and enable the
307 * interrupt on completion of the dma transfer
308 */
309 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
310
311 switch (ch_num) {
312 case ACP_TO_I2S_DMA_CH_NUM:
313 case ACP_TO_SYSRAM_CH_NUM:
314 case I2S_TO_ACP_DMA_CH_NUM:
315 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
316 break;
317 default:
318 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
319 break;
320 }
321
322 /* enable for ACP SRAM to/from I2S DMA channel */
323 if (is_circular == true)
324 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
325 else
326 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
327
328 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
329}
330
331/* Stop a given DMA channel transfer */
332static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
333{
334 u32 dma_ctrl;
335 u32 dma_ch_sts;
336 u32 count = ACP_DMA_RESET_TIME;
337
338 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
339
340 /* clear the dma control register fields before writing zero
341 * in reset bit
342 */
343 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
344 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
345
346 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
347 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
348
349 if (dma_ch_sts & BIT(ch_num)) {
350 /* set the reset bit for this channel to stop the dma
351 * transfer
352 */
353 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
354 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
355 }
356
357 /* check the channel status bit for some time and return the status */
358 while (true) {
359 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
360 if (!(dma_ch_sts & BIT(ch_num))) {
361 /* clear the reset flag after successfully stopping
362 * the dma transfer and break from the loop
363 */
364 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
365
366 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
367 + ch_num);
368 break;
369 }
370 if (--count == 0) {
371 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
372 return -ETIMEDOUT;
373 }
374 udelay(100);
375 }
376 return 0;
377}
378
c36d9b3f
MSB		 379static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
380 bool power_on)
381{
382 u32 val, req_reg, sts_reg, sts_reg_mask;
383 u32 loops = 1000;
384
385 if (bank < 32) {
386 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
387 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
388 sts_reg_mask = 0xFFFFFFFF;
389
390 } else {
391 bank -= 32;
392 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
393 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
394 sts_reg_mask = 0x0000FFFF;
395 }
396
397 val = acp_reg_read(acp_mmio, req_reg);
398 if (val & (1 << bank)) {
399 /* bank is in off state */
400 if (power_on == true)
401 /* request to on */
402 val &= ~(1 << bank);
403 else
404 /* request to off */
405 return;
406 } else {
407 /* bank is in on state */
408 if (power_on == false)
409 /* request to off */
410 val |= 1 << bank;
411 else
412 /* request to on */
413 return;
414 }
415 acp_reg_write(val, acp_mmio, req_reg);
416
417 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
418 if (!loops--) {
419 pr_err("ACP SRAM bank %d state change failed\n", bank);
420 break;
421 }
422 cpu_relax();
423 }
424}
425
7c31335a
MSB		 426/* Initialize and bring ACP hardware to default state. */
427static int acp_init(void __iomem *acp_mmio)
428{
c36d9b3f 429 u16 bank;
7c31335a
MSB		 430 u32 val, count, sram_pte_offset;
431
432 /* Assert Soft reset of ACP */
433 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
434
435 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
436 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
437
438 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
439 while (true) {
440 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
441 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
442 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
443 break;
444 if (--count == 0) {
445 pr_err("Failed to reset ACP\n");
446 return -ETIMEDOUT;
447 }
448 udelay(100);
449 }
450
451 /* Enable clock to ACP and wait until the clock is enabled */
452 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
453 val = val | ACP_CONTROL__ClkEn_MASK;
454 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
455
456 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
457
458 while (true) {
459 val = acp_reg_read(acp_mmio, mmACP_STATUS);
460 if (val & (u32) 0x1)
461 break;
462 if (--count == 0) {
463 pr_err("Failed to reset ACP\n");
464 return -ETIMEDOUT;
465 }
466 udelay(100);
467 }
468
469 /* Deassert the SOFT RESET flags */
470 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
471 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
472 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
473
474 /* initiailize Onion control DAGB register */
475 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
476 mmACP_AXI2DAGB_ONION_CNTL);
477
478 /* initiailize Garlic control DAGB registers */
479 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
480 mmACP_AXI2DAGB_GARLIC_CNTL);
481
482 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
483 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
484 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
485 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
486 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
487 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
488 mmACP_DAGB_PAGE_SIZE_GRP_1);
489
490 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
491 mmACP_DMA_DESC_BASE_ADDR);
492
493 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
494 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
495 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
496 acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
497
c36d9b3f
MSB		 498 /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
499 * Now, turn off all of them. This can't be done in 'poweron' of
500 * ACP pm domain, as this requires ACP to be initialized.
501 */
502 for (bank = 1; bank < 48; bank++)
503 acp_set_sram_bank_state(acp_mmio, bank, false);
504
7c31335a
MSB		 505 return 0;
506}
507
508/* Deintialize ACP */
509static int acp_deinit(void __iomem *acp_mmio)
510{
511 u32 val;
512 u32 count;
513
514 /* Assert Soft reset of ACP */
515 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
516
517 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
518 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
519
520 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
521 while (true) {
522 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
523 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
524 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
525 break;
526 if (--count == 0) {
527 pr_err("Failed to reset ACP\n");
528 return -ETIMEDOUT;
529 }
530 udelay(100);
531 }
532 /** Disable ACP clock */
533 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
534 val &= ~ACP_CONTROL__ClkEn_MASK;
535 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
536
537 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
538
539 while (true) {
540 val = acp_reg_read(acp_mmio, mmACP_STATUS);
541 if (!(val & (u32) 0x1))
542 break;
543 if (--count == 0) {
544 pr_err("Failed to reset ACP\n");
545 return -ETIMEDOUT;
546 }
547 udelay(100);
548 }
549 return 0;
550}
551
552/* ACP DMA irq handler routine for playback, capture usecases */
553static irqreturn_t dma_irq_handler(int irq, void *arg)
554{
555 u16 dscr_idx;
556 u32 intr_flag, ext_intr_status;
557 struct audio_drv_data *irq_data;
558 void __iomem *acp_mmio;
559 struct device *dev = arg;
560 bool valid_irq = false;
561
562 irq_data = dev_get_drvdata(dev);
563 acp_mmio = irq_data->acp_mmio;
564
565 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
566 intr_flag = (((ext_intr_status &
567 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
568 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
569
570 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
571 valid_irq = true;
572 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) ==
573 PLAYBACK_START_DMA_DESCR_CH13)
574 dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
575 else
576 dscr_idx = PLAYBACK_END_DMA_DESCR_CH12;
577 config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx,
578 1, 0);
579 acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
580
581 snd_pcm_period_elapsed(irq_data->play_stream);
582
583 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
584 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
585 }
586
587 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
588 valid_irq = true;
589 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) ==
590 CAPTURE_START_DMA_DESCR_CH15)
591 dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
592 else
593 dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
594 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
595 1, 0);
596 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
597
598 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
599 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
600 }
601
602 if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
603 valid_irq = true;
604 snd_pcm_period_elapsed(irq_data->capture_stream);
605 acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
606 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
607 }
608
609 if (valid_irq)
610 return IRQ_HANDLED;
611 else
612 return IRQ_NONE;
613}
614
615static int acp_dma_open(struct snd_pcm_substream *substream)
616{
c36d9b3f 617 u16 bank;
7c31335a
MSB		 618 int ret = 0;
619 struct snd_pcm_runtime *runtime = substream->runtime;
620 struct snd_soc_pcm_runtime *prtd = substream->private_data;
621 struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev);
622
623 struct audio_substream_data *adata =
624 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
625 if (adata == NULL)
626 return -ENOMEM;
627
628 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
629 runtime->hw = acp_pcm_hardware_playback;
630 else
631 runtime->hw = acp_pcm_hardware_capture;
632
633 ret = snd_pcm_hw_constraint_integer(runtime,
634 SNDRV_PCM_HW_PARAM_PERIODS);
635 if (ret < 0) {
636 dev_err(prtd->platform->dev, "set integer constraint failed\n");
637 return ret;
638 }
639
640 adata->acp_mmio = intr_data->acp_mmio;
641 runtime->private_data = adata;
642
643 /* Enable ACP irq, when neither playback or capture streams are
644 * active by the time when a new stream is being opened.
645 * This enablement is not required for another stream, if current
646 * stream is not closed
647 */
648 if (!intr_data->play_stream && !intr_data->capture_stream)
649 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
650
c36d9b3f 651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
7c31335a 652 intr_data->play_stream = substream;
c36d9b3f
MSB		 653 for (bank = 1; bank <= 4; bank++)
654 acp_set_sram_bank_state(intr_data->acp_mmio, bank,
655 true);
656 } else {
7c31335a 657 intr_data->capture_stream = substream;
c36d9b3f
MSB		 658 for (bank = 5; bank <= 8; bank++)
659 acp_set_sram_bank_state(intr_data->acp_mmio, bank,
660 true);
661 }
7c31335a
MSB		 662
663 return 0;
664}
665
666static int acp_dma_hw_params(struct snd_pcm_substream *substream,
667 struct snd_pcm_hw_params *params)
668{
669 int status;
670 uint64_t size;
671 struct snd_dma_buffer *dma_buffer;
672 struct page *pg;
673 struct snd_pcm_runtime *runtime;
674 struct audio_substream_data *rtd;
675
676 dma_buffer = &substream->dma_buffer;
677
678 runtime = substream->runtime;
679 rtd = runtime->private_data;
680
681 if (WARN_ON(!rtd))
682 return -EINVAL;
683
684 size = params_buffer_bytes(params);
685 status = snd_pcm_lib_malloc_pages(substream, size);
686 if (status < 0)
687 return status;
688
689 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
690 pg = virt_to_page(substream->dma_buffer.area);
691
692 if (pg != NULL) {
c36d9b3f 693 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
7c31335a
MSB		 694 /* Save for runtime private data */
695 rtd->pg = pg;
696 rtd->order = get_order(size);
697
698 /* Fill the page table entries in ACP SRAM */
699 rtd->pg = pg;
700 rtd->size = size;
701 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
702 rtd->direction = substream->stream;
703
704 config_acp_dma(rtd->acp_mmio, rtd);
705 status = 0;
706 } else {
707 status = -ENOMEM;
708 }
709 return status;
710}
711
712static int acp_dma_hw_free(struct snd_pcm_substream *substream)
713{
714 return snd_pcm_lib_free_pages(substream);
715}
716
717static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
718{
719 u16 dscr;
720 u32 mul, dma_config, period_bytes;
721 u32 pos = 0;
722
723 struct snd_pcm_runtime *runtime = substream->runtime;
724 struct audio_substream_data *rtd = runtime->private_data;
725
726 period_bytes = frames_to_bytes(runtime, runtime->period_size);
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
728 dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13);
729
730 if (dscr == PLAYBACK_START_DMA_DESCR_CH13)
731 mul = 0;
732 else
733 mul = 1;
734 pos = (mul * period_bytes);
735 } else {
736 dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14);
737 if (dma_config != 0) {
738 dscr = acp_reg_read(rtd->acp_mmio,
739 mmACP_DMA_CUR_DSCR_14);
740 if (dscr == CAPTURE_START_DMA_DESCR_CH14)
741 mul = 1;
742 else
743 mul = 2;
744 pos = (mul * period_bytes);
745 }
746
747 if (pos >= (2 * period_bytes))
748 pos = 0;
749
750 }
751 return bytes_to_frames(runtime, pos);
752}
753
754static int acp_dma_mmap(struct snd_pcm_substream *substream,
755 struct vm_area_struct *vma)
756{
757 return snd_pcm_lib_default_mmap(substream, vma);
758}
759
760static int acp_dma_prepare(struct snd_pcm_substream *substream)
761{
762 struct snd_pcm_runtime *runtime = substream->runtime;
763 struct audio_substream_data *rtd = runtime->private_data;
764
765 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
766 config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
767 PLAYBACK_START_DMA_DESCR_CH12,
768 NUM_DSCRS_PER_CHANNEL, 0);
769 config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
770 PLAYBACK_START_DMA_DESCR_CH13,
771 NUM_DSCRS_PER_CHANNEL, 0);
772 /* Fill ACP SRAM (2 periods) with zeros from System RAM
773 * which is zero-ed in hw_params
774 */
775 acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
776
777 /* ACP SRAM (2 periods of buffer size) is intially filled with
778 * zeros. Before rendering starts, 2nd half of SRAM will be
779 * filled with valid audio data DMA'ed from first half of system
780 * RAM and 1st half of SRAM will be filled with Zeros. This is
781 * the initial scenario when redering starts from SRAM. Later
782 * on, 2nd half of system memory will be DMA'ed to 1st half of
783 * SRAM, 1st half of system memory will be DMA'ed to 2nd half of
784 * SRAM in ping-pong way till rendering stops.
785 */
786 config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
787 PLAYBACK_START_DMA_DESCR_CH12,
788 1, 0);
789 } else {
790 config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
791 CAPTURE_START_DMA_DESCR_CH14,
792 NUM_DSCRS_PER_CHANNEL, 0);
793 config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
794 CAPTURE_START_DMA_DESCR_CH15,
795 NUM_DSCRS_PER_CHANNEL, 0);
796 }
797 return 0;
798}
799
800static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
801{
802 int ret;
803 u32 loops = 1000;
804
805 struct snd_pcm_runtime *runtime = substream->runtime;
806 struct snd_soc_pcm_runtime *prtd = substream->private_data;
807 struct audio_substream_data *rtd = runtime->private_data;
808
809 if (!rtd)
810 return -EINVAL;
811 switch (cmd) {
812 case SNDRV_PCM_TRIGGER_START:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 case SNDRV_PCM_TRIGGER_RESUME:
815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
816 acp_dma_start(rtd->acp_mmio,
817 SYSRAM_TO_ACP_CH_NUM, false);
818 while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
819 BIT(SYSRAM_TO_ACP_CH_NUM)) {
820 if (!loops--) {
821 dev_err(prtd->platform->dev,
822 "acp dma start timeout\n");
823 return -ETIMEDOUT;
824 }
825 cpu_relax();
826 }
827
828 acp_dma_start(rtd->acp_mmio,
829 ACP_TO_I2S_DMA_CH_NUM, true);
830
831 } else {
832 acp_dma_start(rtd->acp_mmio,
833 I2S_TO_ACP_DMA_CH_NUM, true);
834 }
835 ret = 0;
836 break;
837 case SNDRV_PCM_TRIGGER_STOP:
838 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
839 case SNDRV_PCM_TRIGGER_SUSPEND:
840 /* Need to stop only circular DMA channels :
841 * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular
842 * channels will stopped automatically after its transfer
843 * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
844 */
845 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
846 ret = acp_dma_stop(rtd->acp_mmio,
847 ACP_TO_I2S_DMA_CH_NUM);
848 else
849 ret = acp_dma_stop(rtd->acp_mmio,
850 I2S_TO_ACP_DMA_CH_NUM);
851 break;
852 default:
853 ret = -EINVAL;
854
855 }
856 return ret;
857}
858
859static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
860{
861 return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
862 SNDRV_DMA_TYPE_DEV,
863 NULL, MIN_BUFFER,
864 MAX_BUFFER);
865}
866
867static int acp_dma_close(struct snd_pcm_substream *substream)
868{
c36d9b3f 869 u16 bank;
7c31335a
MSB		 870 struct snd_pcm_runtime *runtime = substream->runtime;
871 struct audio_substream_data *rtd = runtime->private_data;
872 struct snd_soc_pcm_runtime *prtd = substream->private_data;
873 struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev);
874
875 kfree(rtd);
876
c36d9b3f 877 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
7c31335a 878 adata->play_stream = NULL;
c36d9b3f
MSB		 879 for (bank = 1; bank <= 4; bank++)
880 acp_set_sram_bank_state(adata->acp_mmio, bank,
881 false);
882 } else {
7c31335a 883 adata->capture_stream = NULL;
c36d9b3f
MSB		 884 for (bank = 5; bank <= 8; bank++)
885 acp_set_sram_bank_state(adata->acp_mmio, bank,
886 false);
887 }
7c31335a
MSB		 888
889 /* Disable ACP irq, when the current stream is being closed and
890 * another stream is also not active.
891 */
892 if (!adata->play_stream && !adata->capture_stream)
893 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
894
895 return 0;
896}
897
898static struct snd_pcm_ops acp_dma_ops = {
899 .open = acp_dma_open,
900 .close = acp_dma_close,
901 .ioctl = snd_pcm_lib_ioctl,
902 .hw_params = acp_dma_hw_params,
903 .hw_free = acp_dma_hw_free,
904 .trigger = acp_dma_trigger,
905 .pointer = acp_dma_pointer,
906 .mmap = acp_dma_mmap,
907 .prepare = acp_dma_prepare,
908};
909
910static struct snd_soc_platform_driver acp_asoc_platform = {
911 .ops = &acp_dma_ops,
912 .pcm_new = acp_dma_new,
913};
914
915static int acp_audio_probe(struct platform_device *pdev)
916{
917 int status;
918 struct audio_drv_data *audio_drv_data;
919 struct resource *res;
920
921 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
922 GFP_KERNEL);
923 if (audio_drv_data == NULL)
924 return -ENOMEM;
925
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
928
929 /* The following members gets populated in device 'open'
930 * function. Till then interrupts are disabled in 'acp_init'
931 * and device doesn't generate any interrupts.
932 */
933
934 audio_drv_data->play_stream = NULL;
935 audio_drv_data->capture_stream = NULL;
936
937 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
938 if (!res) {
939 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
940 return -ENODEV;
941 }
942
943 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
944 0, "ACP_IRQ", &pdev->dev);
945 if (status) {
946 dev_err(&pdev->dev, "ACP IRQ request failed\n");
947 return status;
948 }
949
950 dev_set_drvdata(&pdev->dev, audio_drv_data);
951
952 /* Initialize the ACP */
953 acp_init(audio_drv_data->acp_mmio);
954
955 status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform);
956 if (status != 0) {
957 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
958 return status;
959 }
960
1927da93
MSB		 961 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
962 pm_runtime_use_autosuspend(&pdev->dev);
963 pm_runtime_enable(&pdev->dev);
964
7c31335a
MSB		 965 return status;
966}
967
968static int acp_audio_remove(struct platform_device *pdev)
969{
970 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
971
972 acp_deinit(adata->acp_mmio);
973 snd_soc_unregister_platform(&pdev->dev);
1927da93 974 pm_runtime_disable(&pdev->dev);
7c31335a
MSB		 975
976 return 0;
977}
978
1927da93
MSB		 979static int acp_pcm_resume(struct device *dev)
980{
c36d9b3f 981 u16 bank;
1927da93
MSB		 982 struct audio_drv_data *adata = dev_get_drvdata(dev);
983
984 acp_init(adata->acp_mmio);
985
c36d9b3f
MSB		 986 if (adata->play_stream && adata->play_stream->runtime) {
987 for (bank = 1; bank <= 4; bank++)
988 acp_set_sram_bank_state(adata->acp_mmio, bank,
989 true);
1927da93
MSB		 990 config_acp_dma(adata->acp_mmio,
991 adata->play_stream->runtime->private_data);
c36d9b3f
MSB		 992 }
993 if (adata->capture_stream && adata->capture_stream->runtime) {
994 for (bank = 5; bank <= 8; bank++)
995 acp_set_sram_bank_state(adata->acp_mmio, bank,
996 true);
1927da93
MSB		 997 config_acp_dma(adata->acp_mmio,
998 adata->capture_stream->runtime->private_data);
c36d9b3f 999 }
1927da93
MSB		 1000 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1001 return 0;
1002}
1003
1004static int acp_pcm_runtime_suspend(struct device *dev)
1005{
1006 struct audio_drv_data *adata = dev_get_drvdata(dev);
1007
1008 acp_deinit(adata->acp_mmio);
1009 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1010 return 0;
1011}
1012
1013static int acp_pcm_runtime_resume(struct device *dev)
1014{
1015 struct audio_drv_data *adata = dev_get_drvdata(dev);
1016
1017 acp_init(adata->acp_mmio);
1018 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1019 return 0;
1020}
1021
1022static const struct dev_pm_ops acp_pm_ops = {
1023 .resume = acp_pcm_resume,
1024 .runtime_suspend = acp_pcm_runtime_suspend,
1025 .runtime_resume = acp_pcm_runtime_resume,
1026};
1027
7c31335a
MSB		 1028static struct platform_driver acp_dma_driver = {
1029 .probe = acp_audio_probe,
1030 .remove = acp_audio_remove,
1031 .driver = {
1032 .name = "acp_audio_dma",
1927da93 1033 .pm = &acp_pm_ops,
7c31335a
MSB		 1034 },
1035};
1036
1037module_platform_driver(acp_dma_driver);
1038
1039MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1040MODULE_DESCRIPTION("AMD ACP PCM Driver");
1041MODULE_LICENSE("GPL v2");
1042MODULE_ALIAS("platform:acp-dma-audio");
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