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ASoC: samsung: i2s: Fix prescaler setting for the secondary DAI
[mirror_ubuntu-bionic-kernel.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
074b89bb 13#include <dt-bindings/sound/samsung-i2s.h>
1c7ac018
JB		 14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
074b89bb 17#include <linux/clk-provider.h>
1c7ac018 18#include <linux/io.h>
da155d5b 19#include <linux/module.h>
40476f61 20#include <linux/of.h>
2f7b5d14 21#include <linux/of_device.h>
40476f61 22#include <linux/of_gpio.h>
c5cf4dbc 23#include <linux/pm_runtime.h>
1c7ac018 24
1c7ac018 25#include <sound/soc.h>
0378b6ac 26#include <sound/pcm_params.h>
1c7ac018 27
436d42c6 28#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 29
30#include "dma.h"
61100f40 31#include "idma.h"
1c7ac018 32#include "i2s.h"
172a453d 33#include "i2s-regs.h"
1c7ac018
JB		 34
35#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
36
a5a56871
PV		 37struct samsung_i2s_variant_regs {
38 unsigned int bfs_off;
39 unsigned int rfs_off;
40 unsigned int sdf_off;
41 unsigned int txr_off;
42 unsigned int rclksrc_off;
43 unsigned int mss_off;
44 unsigned int cdclkcon_off;
45 unsigned int lrp_off;
46 unsigned int bfs_mask;
47 unsigned int rfs_mask;
48 unsigned int ftx0cnt_off;
49};
50
40476f61 51struct samsung_i2s_dai_data {
7da493e9 52 u32 quirks;
4720c2fe 53 unsigned int pcm_rates;
a5a56871 54 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 55};
56
1c7ac018
JB		 57struct i2s_dai {
58 /* Platform device for this DAI */
59 struct platform_device *pdev;
af1cf5cf 60 /* Memory mapped SFR region */
1c7ac018 61 void __iomem *addr;
1c7ac018
JB		 62 /* Rate of RCLK source clock */
63 unsigned long rclk_srcrate;
64 /* Frame Clock */
65 unsigned frmclk;
66 /*
67 * Specifically requested RCLK,BCLK by MACHINE Driver.
68 * 0 indicates CPU driver is free to choose any value.
69 */
70 unsigned rfs, bfs;
71 /* I2S Controller's core clock */
72 struct clk *clk;
73 /* Clock for generating I2S signals */
74 struct clk *op_clk;
1c7ac018
JB		 75 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
76 struct i2s_dai *pri_dai;
77 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
78 struct i2s_dai *sec_dai;
79#define DAI_OPENED (1 << 0) /* Dai is opened */
80#define DAI_MANAGER (1 << 1) /* Dai is the manager */
81 unsigned mode;
82 /* Driver for this DAI */
83 struct snd_soc_dai_driver i2s_dai_drv;
84 /* DMA parameters */
69e7a69a
SN		 85 struct snd_dmaengine_dai_dma_data dma_playback;
86 struct snd_dmaengine_dai_dma_data dma_capture;
87 struct snd_dmaengine_dai_dma_data idma_playback;
9bdca822 88 dma_filter_fn filter;
1c7ac018
JB		 89 u32 quirks;
90 u32 suspend_i2smod;
91 u32 suspend_i2scon;
92 u32 suspend_i2spsr;
a5a56871 93 const struct samsung_i2s_variant_regs *variant_regs;
f3670536
SN		 94
95 /* Spinlock protecting access to the device's registers */
96 spinlock_t spinlock;
97 spinlock_t *lock;
074b89bb
SN		 98
99 /* Below fields are only valid if this is the primary FIFO */
100 struct clk *clk_table[3];
101 struct clk_onecell_data clk_data;
1c7ac018
JB		 102};
103
104/* Lock for cross i/f checks */
105static DEFINE_SPINLOCK(lock);
106
107/* If this is the 'overlay' stereo DAI */
108static inline bool is_secondary(struct i2s_dai *i2s)
109{
110 return i2s->pri_dai ? true : false;
111}
112
113/* If operating in SoC-Slave mode */
114static inline bool is_slave(struct i2s_dai *i2s)
115{
a5a56871
PV		 116 u32 mod = readl(i2s->addr + I2SMOD);
117 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 118}
119
120/* If this interface of the controller is transmitting data */
121static inline bool tx_active(struct i2s_dai *i2s)
122{
123 u32 active;
124
125 if (!i2s)
126 return false;
127
33195500 128 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 129
130 if (is_secondary(i2s))
131 active &= CON_TXSDMA_ACTIVE;
132 else
133 active &= CON_TXDMA_ACTIVE;
134
135 return active ? true : false;
136}
137
dcd60fc3
SN		 138/* Return pointer to the other DAI */
139static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
140{
141 return i2s->pri_dai ? : i2s->sec_dai;
142}
143
1c7ac018
JB		 144/* If the other interface of the controller is transmitting data */
145static inline bool other_tx_active(struct i2s_dai *i2s)
146{
dcd60fc3 147 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 148
149 return tx_active(other);
150}
151
152/* If any interface of the controller is transmitting data */
153static inline bool any_tx_active(struct i2s_dai *i2s)
154{
155 return tx_active(i2s) || other_tx_active(i2s);
156}
157
158/* If this interface of the controller is receiving data */
159static inline bool rx_active(struct i2s_dai *i2s)
160{
161 u32 active;
162
163 if (!i2s)
164 return false;
165
33195500 166 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 167
168 return active ? true : false;
169}
170
171/* If the other interface of the controller is receiving data */
172static inline bool other_rx_active(struct i2s_dai *i2s)
173{
dcd60fc3 174 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 175
176 return rx_active(other);
177}
178
179/* If any interface of the controller is receiving data */
180static inline bool any_rx_active(struct i2s_dai *i2s)
181{
182 return rx_active(i2s) || other_rx_active(i2s);
183}
184
185/* If the other DAI is transmitting or receiving data */
186static inline bool other_active(struct i2s_dai *i2s)
187{
188 return other_rx_active(i2s) || other_tx_active(i2s);
189}
190
191/* If this DAI is transmitting or receiving data */
192static inline bool this_active(struct i2s_dai *i2s)
193{
194 return tx_active(i2s) || rx_active(i2s);
195}
196
197/* If the controller is active anyway */
198static inline bool any_active(struct i2s_dai *i2s)
199{
200 return this_active(i2s) || other_active(i2s);
201}
202
203static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
204{
205 return snd_soc_dai_get_drvdata(dai);
206}
207
208static inline bool is_opened(struct i2s_dai *i2s)
209{
210 if (i2s && (i2s->mode & DAI_OPENED))
211 return true;
212 else
213 return false;
214}
215
216static inline bool is_manager(struct i2s_dai *i2s)
217{
218 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
219 return true;
220 else
221 return false;
222}
223
224/* Read RCLK of I2S (in multiples of LRCLK) */
225static inline unsigned get_rfs(struct i2s_dai *i2s)
226{
4ca0c0d4 227 u32 rfs;
a5a56871
PV		 228 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
229 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 230
231 switch (rfs) {
a5a56871
PV		 232 case 7: return 192;
233 case 6: return 96;
234 case 5: return 128;
235 case 4: return 64;
1c7ac018
JB		 236 case 3: return 768;
237 case 2: return 384;
238 case 1: return 512;
239 default: return 256;
240 }
241}
242
243/* Write RCLK of I2S (in multiples of LRCLK) */
244static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
245{
246 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 247 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 248
a5a56871 249 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 250
251 switch (rfs) {
a5a56871
PV		 252 case 192:
253 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
254 break;
255 case 96:
256 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
257 break;
258 case 128:
259 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
260 break;
261 case 64:
262 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
263 break;
1c7ac018 264 case 768:
b60be4aa 265 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 266 break;
267 case 512:
b60be4aa 268 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 269 break;
270 case 384:
b60be4aa 271 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 272 break;
273 default:
b60be4aa 274 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 275 break;
276 }
277
278 writel(mod, i2s->addr + I2SMOD);
279}
280
281/* Read Bit-Clock of I2S (in multiples of LRCLK) */
282static inline unsigned get_bfs(struct i2s_dai *i2s)
283{
4ca0c0d4 284 u32 bfs;
a5a56871
PV		 285 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
286 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 287
288 switch (bfs) {
4ca0c0d4
PV		 289 case 8: return 256;
290 case 7: return 192;
291 case 6: return 128;
292 case 5: return 96;
293 case 4: return 64;
1c7ac018
JB		 294 case 3: return 24;
295 case 2: return 16;
296 case 1: return 48;
297 default: return 32;
298 }
299}
300
301/* Write Bit-Clock of I2S (in multiples of LRCLK) */
302static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
303{
304 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 305 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 306 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 307
308 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
309 if (!tdm && bfs > 48) {
310 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
311 return;
312 }
1c7ac018 313
a5a56871
PV		 314 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
315
1c7ac018
JB		 316 switch (bfs) {
317 case 48:
b60be4aa 318 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 319 break;
320 case 32:
b60be4aa 321 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 322 break;
323 case 24:
b60be4aa 324 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 325 break;
326 case 16:
b60be4aa 327 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 328 break;
4ca0c0d4
PV		 329 case 64:
330 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
331 break;
332 case 96:
333 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
334 break;
335 case 128:
336 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
337 break;
338 case 192:
339 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
340 break;
341 case 256:
342 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 343 break;
344 default:
345 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
346 return;
347 }
348
349 writel(mod, i2s->addr + I2SMOD);
350}
351
352/* Sample-Size */
353static inline int get_blc(struct i2s_dai *i2s)
354{
355 int blc = readl(i2s->addr + I2SMOD);
356
357 blc = (blc >> 13) & 0x3;
358
359 switch (blc) {
360 case 2: return 24;
361 case 1: return 8;
362 default: return 16;
363 }
364}
365
366/* TX Channel Control */
367static void i2s_txctrl(struct i2s_dai *i2s, int on)
368{
369 void __iomem *addr = i2s->addr;
a5a56871 370 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 371 u32 con = readl(addr + I2SCON);
a5a56871 372 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 373
374 if (on) {
375 con |= CON_ACTIVE;
376 con &= ~CON_TXCH_PAUSE;
377
378 if (is_secondary(i2s)) {
379 con |= CON_TXSDMA_ACTIVE;
380 con &= ~CON_TXSDMA_PAUSE;
381 } else {
382 con |= CON_TXDMA_ACTIVE;
383 con &= ~CON_TXDMA_PAUSE;
384 }
385
386 if (any_rx_active(i2s))
a5a56871 387 mod |= 2 << txr_off;
1c7ac018 388 else
a5a56871 389 mod |= 0 << txr_off;
1c7ac018
JB		 390 } else {
391 if (is_secondary(i2s)) {
392 con |= CON_TXSDMA_PAUSE;
393 con &= ~CON_TXSDMA_ACTIVE;
394 } else {
395 con |= CON_TXDMA_PAUSE;
396 con &= ~CON_TXDMA_ACTIVE;
397 }
398
399 if (other_tx_active(i2s)) {
400 writel(con, addr + I2SCON);
401 return;
402 }
403
404 con |= CON_TXCH_PAUSE;
405
406 if (any_rx_active(i2s))
a5a56871 407 mod |= 1 << txr_off;
1c7ac018
JB		 408 else
409 con &= ~CON_ACTIVE;
410 }
411
412 writel(mod, addr + I2SMOD);
413 writel(con, addr + I2SCON);
414}
415
416/* RX Channel Control */
417static void i2s_rxctrl(struct i2s_dai *i2s, int on)
418{
419 void __iomem *addr = i2s->addr;
a5a56871 420 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 421 u32 con = readl(addr + I2SCON);
a5a56871 422 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 423
424 if (on) {
425 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
426 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
427
428 if (any_tx_active(i2s))
a5a56871 429 mod |= 2 << txr_off;
1c7ac018 430 else
a5a56871 431 mod |= 1 << txr_off;
1c7ac018
JB		 432 } else {
433 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
434 con &= ~CON_RXDMA_ACTIVE;
435
436 if (any_tx_active(i2s))
a5a56871 437 mod |= 0 << txr_off;
1c7ac018
JB		 438 else
439 con &= ~CON_ACTIVE;
440 }
441
442 writel(mod, addr + I2SMOD);
443 writel(con, addr + I2SCON);
444}
445
446/* Flush FIFO of an interface */
447static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
448{
449 void __iomem *fic;
450 u32 val;
451
452 if (!i2s)
453 return;
454
455 if (is_secondary(i2s))
456 fic = i2s->addr + I2SFICS;
457 else
458 fic = i2s->addr + I2SFIC;
459
460 /* Flush the FIFO */
461 writel(readl(fic) | flush, fic);
462
463 /* Be patient */
464 val = msecs_to_loops(1) / 1000; /* 1 usec */
465 while (--val)
466 cpu_relax();
467
468 writel(readl(fic) & ~flush, fic);
469}
470
471static int i2s_set_sysclk(struct snd_soc_dai *dai,
472 int clk_id, unsigned int rfs, int dir)
473{
474 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 475 struct i2s_dai *other = get_other_dai(i2s);
a5a56871
PV		 476 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
477 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
478 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
ce8bcdbb 479 u32 mod, mask, val = 0;
316fa9e0 480 unsigned long flags;
dc938ddb
MS		 481 int ret = 0;
482
483 pm_runtime_get_sync(dai->dev);
ce8bcdbb 484
316fa9e0 485 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 486 mod = readl(i2s->addr + I2SMOD);
316fa9e0 487 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 488
489 switch (clk_id) {
c86d50f9 490 case SAMSUNG_I2S_OPCLK:
ce8bcdbb
SN		 491 mask = MOD_OPCLK_MASK;
492 val = dir;
c86d50f9 493 break;
1c7ac018 494 case SAMSUNG_I2S_CDCLK:
ce8bcdbb 495 mask = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 496 /* Shouldn't matter in GATING(CLOCK_IN) mode */
497 if (dir == SND_SOC_CLOCK_IN)
498 rfs = 0;
499
133c2681 500 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 501 (any_active(i2s) &&
502 (((dir == SND_SOC_CLOCK_IN)
a5a56871 503 && !(mod & cdcon_mask)) ||
1c7ac018 504 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 505 && (mod & cdcon_mask))))) {
1c7ac018
JB		 506 dev_err(&i2s->pdev->dev,
507 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 508 ret = -EAGAIN;
509 goto err;
1c7ac018
JB		 510 }
511
512 if (dir == SND_SOC_CLOCK_IN)
ce8bcdbb 513 val = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 514
515 i2s->rfs = rfs;
516 break;
517
518 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
519 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
ce8bcdbb
SN		 520 mask = 1 << i2s_regs->rclksrc_off;
521
1c7ac018
JB		 522 if ((i2s->quirks & QUIRK_NO_MUXPSR)
523 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
524 clk_id = 0;
525 else
526 clk_id = 1;
527
528 if (!any_active(i2s)) {
a6aba536 529 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 530 if ((clk_id && !(mod & rsrc_mask)) ||
531 (!clk_id && (mod & rsrc_mask))) {
98614cf6 532 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 533 clk_put(i2s->op_clk);
534 } else {
6ce534aa
JB		 535 i2s->rclk_srcrate =
536 clk_get_rate(i2s->op_clk);
dc938ddb 537 goto done;
1c7ac018
JB		 538 }
539 }
540
1974a042
PV		 541 if (clk_id)
542 i2s->op_clk = clk_get(&i2s->pdev->dev,
543 "i2s_opclk1");
544 else
545 i2s->op_clk = clk_get(&i2s->pdev->dev,
546 "i2s_opclk0");
a6aba536 547
dc938ddb
MS		 548 if (WARN_ON(IS_ERR(i2s->op_clk))) {
549 ret = PTR_ERR(i2s->op_clk);
afa99da8 550 i2s->op_clk = NULL;
dc938ddb
MS		 551 goto err;
552 }
a6aba536 553
f5c97c7b 554 ret = clk_prepare_enable(i2s->op_clk);
6431a7e3
CJ		 555 if (ret) {
556 clk_put(i2s->op_clk);
557 i2s->op_clk = NULL;
f5c97c7b 558 goto err;
6431a7e3 559 }
1c7ac018
JB		 560 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
561
562 /* Over-ride the other's */
563 if (other) {
564 other->op_clk = i2s->op_clk;
565 other->rclk_srcrate = i2s->rclk_srcrate;
566 }
a5a56871
PV		 567 } else if ((!clk_id && (mod & rsrc_mask))
568 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 569 dev_err(&i2s->pdev->dev,
570 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 571 ret = -EAGAIN;
572 goto err;
1c7ac018
JB		 573 } else {
574 /* Call can't be on the active DAI */
575 i2s->op_clk = other->op_clk;
576 i2s->rclk_srcrate = other->rclk_srcrate;
dc938ddb 577 goto done;
1c7ac018
JB		 578 }
579
ce8bcdbb
SN		 580 if (clk_id == 1)
581 val = 1 << i2s_regs->rclksrc_off;
b2de1d20 582 break;
1c7ac018
JB		 583 default:
584 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
dc938ddb
MS		 585 ret = -EINVAL;
586 goto err;
1c7ac018
JB		 587 }
588
316fa9e0 589 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 590 mod = readl(i2s->addr + I2SMOD);
591 mod = (mod & ~mask) | val;
1c7ac018 592 writel(mod, i2s->addr + I2SMOD);
316fa9e0 593 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb
MS		 594done:
595 pm_runtime_put(dai->dev);
1c7ac018
JB		 596
597 return 0;
dc938ddb
MS		 598err:
599 pm_runtime_put(dai->dev);
600 return ret;
1c7ac018
JB		 601}
602
603static int i2s_set_fmt(struct snd_soc_dai *dai,
604 unsigned int fmt)
605{
606 struct i2s_dai *i2s = to_info(dai);
27548335 607 struct i2s_dai *other = get_other_dai(i2s);
a5a56871 608 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
ce8bcdbb 609 u32 mod, tmp = 0;
316fa9e0 610 unsigned long flags;
1c7ac018 611
a5a56871
PV		 612 lrp_shift = i2s->variant_regs->lrp_off;
613 sdf_shift = i2s->variant_regs->sdf_off;
614 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 615
b60be4aa
PV		 616 sdf_mask = MOD_SDF_MASK << sdf_shift;
617 lrp_rlow = MOD_LR_RLOW << lrp_shift;
618
1c7ac018
JB		 619 /* Format is priority */
620 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
621 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 622 tmp |= lrp_rlow;
623 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 624 break;
625 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 626 tmp |= lrp_rlow;
627 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 628 break;
629 case SND_SOC_DAIFMT_I2S:
b60be4aa 630 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 631 break;
632 default:
633 dev_err(&i2s->pdev->dev, "Format not supported\n");
634 return -EINVAL;
635 }
636
637 /*
638 * INV flag is relative to the FORMAT flag - if set it simply
639 * flips the polarity specified by the Standard
640 */
641 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
642 case SND_SOC_DAIFMT_NB_NF:
643 break;
644 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 645 if (tmp & lrp_rlow)
646 tmp &= ~lrp_rlow;
1c7ac018 647 else
b60be4aa 648 tmp |= lrp_rlow;
1c7ac018
JB		 649 break;
650 default:
651 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
652 return -EINVAL;
653 }
654
655 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
656 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 657 tmp |= mod_slave;
1c7ac018
JB		 658 break;
659 case SND_SOC_DAIFMT_CBS_CFS:
1370f9ec
SN		 660 /*
661 * Set default source clock in Master mode, only when the
662 * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
663 * clock configuration assigned in DT is not overwritten.
664 */
27548335
SN		 665 if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL &&
666 other->clk_data.clks == NULL)
1c7ac018
JB		 667 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
668 0, SND_SOC_CLOCK_IN);
669 break;
670 default:
671 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
672 return -EINVAL;
673 }
674
dc938ddb 675 pm_runtime_get_sync(dai->dev);
316fa9e0 676 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 677 mod = readl(i2s->addr + I2SMOD);
b60be4aa
PV		 678 /*
679 * Don't change the I2S mode if any controller is active on this
680 * channel.
681 */
1c7ac018 682 if (any_active(i2s) &&
a5a56871 683 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
316fa9e0 684 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 685 pm_runtime_put(dai->dev);
1c7ac018
JB		 686 dev_err(&i2s->pdev->dev,
687 "%s:%d Other DAI busy\n", __func__, __LINE__);
688 return -EAGAIN;
689 }
690
a5a56871 691 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 692 mod |= tmp;
693 writel(mod, i2s->addr + I2SMOD);
316fa9e0 694 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 695 pm_runtime_put(dai->dev);
1c7ac018
JB		 696
697 return 0;
698}
699
700static int i2s_hw_params(struct snd_pcm_substream *substream,
701 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
702{
703 struct i2s_dai *i2s = to_info(dai);
27548335 704 struct i2s_dai *other = get_other_dai(i2s);
ce8bcdbb 705 u32 mod, mask = 0, val = 0;
bb7612f6 706 struct clk *rclksrc;
316fa9e0 707 unsigned long flags;
1c7ac018 708
dc938ddb
MS		 709 WARN_ON(!pm_runtime_active(dai->dev));
710
1c7ac018 711 if (!is_secondary(i2s))
ce8bcdbb 712 mask |= (MOD_DC2_EN | MOD_DC1_EN);
1c7ac018
JB		 713
714 switch (params_channels(params)) {
715 case 6:
ce8bcdbb 716 val |= MOD_DC2_EN;
1c7ac018 717 case 4:
ce8bcdbb 718 val |= MOD_DC1_EN;
1c7ac018
JB		 719 break;
720 case 2:
588fb705 721 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 722 i2s->dma_playback.addr_width = 4;
588fb705 723 else
69e7a69a 724 i2s->dma_capture.addr_width = 4;
588fb705
SP		 725 break;
726 case 1:
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 728 i2s->dma_playback.addr_width = 2;
588fb705 729 else
69e7a69a 730 i2s->dma_capture.addr_width = 2;
588fb705 731
1c7ac018
JB		 732 break;
733 default:
734 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
735 params_channels(params));
736 return -EINVAL;
737 }
738
739 if (is_secondary(i2s))
ce8bcdbb 740 mask |= MOD_BLCS_MASK;
1c7ac018 741 else
ce8bcdbb 742 mask |= MOD_BLCP_MASK;
1c7ac018
JB		 743
744 if (is_manager(i2s))
ce8bcdbb 745 mask |= MOD_BLC_MASK;
1c7ac018 746
88ce1465
TB		 747 switch (params_width(params)) {
748 case 8:
1c7ac018 749 if (is_secondary(i2s))
ce8bcdbb 750 val |= MOD_BLCS_8BIT;
1c7ac018 751 else
ce8bcdbb 752 val |= MOD_BLCP_8BIT;
1c7ac018 753 if (is_manager(i2s))
ce8bcdbb 754 val |= MOD_BLC_8BIT;
1c7ac018 755 break;
88ce1465 756 case 16:
1c7ac018 757 if (is_secondary(i2s))
ce8bcdbb 758 val |= MOD_BLCS_16BIT;
1c7ac018 759 else
ce8bcdbb 760 val |= MOD_BLCP_16BIT;
1c7ac018 761 if (is_manager(i2s))
ce8bcdbb 762 val |= MOD_BLC_16BIT;
1c7ac018 763 break;
88ce1465 764 case 24:
1c7ac018 765 if (is_secondary(i2s))
ce8bcdbb 766 val |= MOD_BLCS_24BIT;
1c7ac018 767 else
ce8bcdbb 768 val |= MOD_BLCP_24BIT;
1c7ac018 769 if (is_manager(i2s))
ce8bcdbb 770 val |= MOD_BLC_24BIT;
1c7ac018
JB		 771 break;
772 default:
773 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
774 params_format(params));
775 return -EINVAL;
776 }
ce8bcdbb 777
316fa9e0 778 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 779 mod = readl(i2s->addr + I2SMOD);
780 mod = (mod & ~mask) | val;
1c7ac018 781 writel(mod, i2s->addr + I2SMOD);
316fa9e0 782 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018 783
69e7a69a 784 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
d37bdf73 785
1c7ac018
JB		 786 i2s->frmclk = params_rate(params);
787
bb7612f6 788 rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC];
27548335
SN		 789 if (!rclksrc || IS_ERR(rclksrc))
790 rclksrc = other->clk_table[CLK_I2S_RCLK_SRC];
791
bb7612f6
SN		 792 if (rclksrc && !IS_ERR(rclksrc))
793 i2s->rclk_srcrate = clk_get_rate(rclksrc);
794
1c7ac018
JB		 795 return 0;
796}
797
798/* We set constraints on the substream acc to the version of I2S */
799static int i2s_startup(struct snd_pcm_substream *substream,
800 struct snd_soc_dai *dai)
801{
802 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 803 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 804 unsigned long flags;
805
dc938ddb
MS		 806 pm_runtime_get_sync(dai->dev);
807
1c7ac018
JB		 808 spin_lock_irqsave(&lock, flags);
809
810 i2s->mode |= DAI_OPENED;
811
812 if (is_manager(other))
813 i2s->mode &= ~DAI_MANAGER;
814 else
815 i2s->mode |= DAI_MANAGER;
816
2d77828d
PV		 817 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
818 writel(CON_RSTCLR, i2s->addr + I2SCON);
819
1c7ac018
JB		 820 spin_unlock_irqrestore(&lock, flags);
821
822 return 0;
823}
824
825static void i2s_shutdown(struct snd_pcm_substream *substream,
826 struct snd_soc_dai *dai)
827{
828 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 829 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 830 unsigned long flags;
831
832 spin_lock_irqsave(&lock, flags);
833
834 i2s->mode &= ~DAI_OPENED;
835 i2s->mode &= ~DAI_MANAGER;
836
074b89bb 837 if (is_opened(other))
1c7ac018 838 other->mode |= DAI_MANAGER;
074b89bb 839
1c7ac018
JB		 840 /* Reset any constraint on RFS and BFS */
841 i2s->rfs = 0;
842 i2s->bfs = 0;
843
844 spin_unlock_irqrestore(&lock, flags);
dc938ddb
MS		 845
846 pm_runtime_put(dai->dev);
1c7ac018
JB		 847}
848
849static int config_setup(struct i2s_dai *i2s)
850{
dcd60fc3 851 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 852 unsigned rfs, bfs, blc;
853 u32 psr;
854
855 blc = get_blc(i2s);
856
857 bfs = i2s->bfs;
858
859 if (!bfs && other)
860 bfs = other->bfs;
861
862 /* Select least possible multiple(2) if no constraint set */
863 if (!bfs)
864 bfs = blc * 2;
865
866 rfs = i2s->rfs;
867
868 if (!rfs && other)
869 rfs = other->rfs;
870
871 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
872 dev_err(&i2s->pdev->dev,
873 "%d-RFS not supported for 24-blc\n", rfs);
874 return -EINVAL;
875 }
876
877 if (!rfs) {
878 if (bfs == 16 || bfs == 32)
879 rfs = 256;
880 else
881 rfs = 384;
882 }
883
884 /* If already setup and running */
885 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
886 dev_err(&i2s->pdev->dev,
887 "%s:%d Other DAI busy\n", __func__, __LINE__);
888 return -EAGAIN;
889 }
890
1c7ac018
JB		 891 set_bfs(i2s, bfs);
892 set_rfs(i2s, rfs);
893
77010010
PV		 894 /* Don't bother with PSR in Slave mode */
895 if (is_slave(i2s))
896 return 0;
897
1c7ac018
JB		 898 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
899 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
900 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
901 dev_dbg(&i2s->pdev->dev,
902 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
903 i2s->rclk_srcrate, psr, rfs, bfs);
904 }
905
906 return 0;
907}
908
909static int i2s_trigger(struct snd_pcm_substream *substream,
910 int cmd, struct snd_soc_dai *dai)
911{
912 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
913 struct snd_soc_pcm_runtime *rtd = substream->private_data;
914 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
915 unsigned long flags;
916
917 switch (cmd) {
918 case SNDRV_PCM_TRIGGER_START:
919 case SNDRV_PCM_TRIGGER_RESUME:
920 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dc938ddb 921 pm_runtime_get_sync(dai->dev);
f3670536 922 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 923
1c7ac018 924 if (config_setup(i2s)) {
f3670536 925 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 926 return -EINVAL;
927 }
928
929 if (capture)
930 i2s_rxctrl(i2s, 1);
931 else
932 i2s_txctrl(i2s, 1);
933
f3670536 934 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 935 break;
936 case SNDRV_PCM_TRIGGER_STOP:
937 case SNDRV_PCM_TRIGGER_SUSPEND:
938 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f3670536 939 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 940
c90887fe 941 if (capture) {
1c7ac018 942 i2s_rxctrl(i2s, 0);
775bc971 943 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 944 } else {
945 i2s_txctrl(i2s, 0);
775bc971 946 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 947 }
775bc971 948
f3670536 949 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 950 pm_runtime_put(dai->dev);
1c7ac018
JB		 951 break;
952 }
953
954 return 0;
955}
956
957static int i2s_set_clkdiv(struct snd_soc_dai *dai,
958 int div_id, int div)
959{
960 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 961 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 962
963 switch (div_id) {
964 case SAMSUNG_I2S_DIV_BCLK:
dc938ddb 965 pm_runtime_get_sync(dai->dev);
1c7ac018
JB		 966 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
967 || (other && other->bfs && (other->bfs != div))) {
dc938ddb 968 pm_runtime_put(dai->dev);
1c7ac018
JB		 969 dev_err(&i2s->pdev->dev,
970 "%s:%d Other DAI busy\n", __func__, __LINE__);
971 return -EAGAIN;
972 }
973 i2s->bfs = div;
dc938ddb 974 pm_runtime_put(dai->dev);
1c7ac018
JB		 975 break;
976 default:
977 dev_err(&i2s->pdev->dev,
978 "Invalid clock divider(%d)\n", div_id);
979 return -EINVAL;
980 }
981
982 return 0;
983}
984
985static snd_pcm_sframes_t
986i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
987{
988 struct i2s_dai *i2s = to_info(dai);
989 u32 reg = readl(i2s->addr + I2SFIC);
990 snd_pcm_sframes_t delay;
a5a56871 991 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018 992
dc938ddb
MS		 993 WARN_ON(!pm_runtime_active(dai->dev));
994
1c7ac018
JB		 995 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
996 delay = FIC_RXCOUNT(reg);
997 else if (is_secondary(i2s))
998 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
999 else
a5a56871 1000 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 1001
1002 return delay;
1003}
1004
1005#ifdef CONFIG_PM
1006static int i2s_suspend(struct snd_soc_dai *dai)
1007{
e7e52dfc 1008 return pm_runtime_force_suspend(dai->dev);
1c7ac018
JB		 1009}
1010
1011static int i2s_resume(struct snd_soc_dai *dai)
1012{
e7e52dfc 1013 return pm_runtime_force_resume(dai->dev);
1c7ac018
JB		 1014}
1015#else
1016#define i2s_suspend NULL
1017#define i2s_resume NULL
1018#endif
1019
1020static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
1021{
1022 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 1023 struct i2s_dai *other = get_other_dai(i2s);
ce8bcdbb 1024 unsigned long flags;
1c7ac018 1025
dc938ddb
MS		 1026 pm_runtime_get_sync(dai->dev);
1027
0ec2ba80 1028 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
69e7a69a 1029 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback,
3688569e 1030 NULL);
872c26bd 1031 } else {
69e7a69a 1032 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
872c26bd 1033 &i2s->dma_capture);
511e3033 1034
872c26bd
SN		 1035 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1036 writel(CON_RSTCLR, i2s->addr + I2SCON);
1c7ac018 1037
872c26bd
SN		 1038 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1039 idma_reg_addr_init(i2s->addr,
69e7a69a 1040 i2s->sec_dai->idma_playback.addr);
872c26bd 1041 }
61100f40 1042
1c7ac018
JB		 1043 /* Reset any constraint on RFS and BFS */
1044 i2s->rfs = 0;
1045 i2s->bfs = 0;
d66eac3e 1046 i2s->rclk_srcrate = 0;
ce8bcdbb
SN		 1047
1048 spin_lock_irqsave(i2s->lock, flags);
1c7ac018
JB		 1049 i2s_txctrl(i2s, 0);
1050 i2s_rxctrl(i2s, 0);
1051 i2s_fifo(i2s, FIC_TXFLUSH);
1052 i2s_fifo(other, FIC_TXFLUSH);
1053 i2s_fifo(i2s, FIC_RXFLUSH);
ce8bcdbb 1054 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 1055
1056 /* Gate CDCLK by default */
1057 if (!is_opened(other))
1058 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1059 0, SND_SOC_CLOCK_IN);
dc938ddb 1060 pm_runtime_put(dai->dev);
1c7ac018
JB		 1061
1062 return 0;
1063}
1064
1065static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1066{
1067 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
5faf071d 1068 unsigned long flags;
1c7ac018 1069
dc938ddb
MS		 1070 pm_runtime_get_sync(dai->dev);
1071
c92f1d0e 1072 if (!is_secondary(i2s)) {
ce8bcdbb 1073 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
5faf071d 1074 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 1075 writel(0, i2s->addr + I2SCON);
5faf071d 1076 spin_unlock_irqrestore(i2s->lock, flags);
ce8bcdbb 1077 }
1c7ac018
JB		 1078 }
1079
dc938ddb
MS		 1080 pm_runtime_put(dai->dev);
1081
1c7ac018
JB		 1082 return 0;
1083}
1084
85e7652d 1085static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1086 .trigger = i2s_trigger,
1087 .hw_params = i2s_hw_params,
1088 .set_fmt = i2s_set_fmt,
1089 .set_clkdiv = i2s_set_clkdiv,
1090 .set_sysclk = i2s_set_sysclk,
1091 .startup = i2s_startup,
1092 .shutdown = i2s_shutdown,
1093 .delay = i2s_delay,
1094};
1095
4b828535
KM		 1096static const struct snd_soc_component_driver samsung_i2s_component = {
1097 .name = "samsung-i2s",
1098};
1099
1c7ac018
JB		 1100#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1101 SNDRV_PCM_FMTBIT_S16_LE | \
1102 SNDRV_PCM_FMTBIT_S24_LE)
1103
4720c2fe
JL		 1104static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
1105 const struct samsung_i2s_dai_data *i2s_dai_data,
1106 bool sec)
1c7ac018
JB		 1107{
1108 struct i2s_dai *i2s;
1109
b960ce74 1110 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1111 if (i2s == NULL)
1112 return NULL;
1113
1114 i2s->pdev = pdev;
1115 i2s->pri_dai = NULL;
1116 i2s->sec_dai = NULL;
22289ddc 1117 i2s->i2s_dai_drv.id = 1;
1c7ac018
JB		 1118 i2s->i2s_dai_drv.symmetric_rates = 1;
1119 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1120 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1121 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1122 i2s->i2s_dai_drv.suspend = i2s_suspend;
1123 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1124 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018 1125 i2s->i2s_dai_drv.playback.channels_max = 2;
4720c2fe 1126 i2s->i2s_dai_drv.playback.rates = i2s_dai_data->pcm_rates;
1c7ac018
JB		 1127 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1128
1129 if (!sec) {
22289ddc 1130 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI;
588fb705 1131 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018 1132 i2s->i2s_dai_drv.capture.channels_max = 2;
4720c2fe 1133 i2s->i2s_dai_drv.capture.rates = i2s_dai_data->pcm_rates;
1c7ac018 1134 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
22289ddc
JL		 1135 } else {
1136 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI_SEC;
c6f9b1eb 1137 }
1c7ac018
JB		 1138 return i2s;
1139}
1140
641d334b 1141#ifdef CONFIG_PM
5b1d3c34
C		 1142static int i2s_runtime_suspend(struct device *dev)
1143{
1144 struct i2s_dai *i2s = dev_get_drvdata(dev);
1145
e7e52dfc
MS		 1146 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
1147 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
1148 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1149
afa99da8
MS		 1150 if (i2s->op_clk)
1151 clk_disable_unprepare(i2s->op_clk);
5b1d3c34
C		 1152 clk_disable_unprepare(i2s->clk);
1153
1154 return 0;
1155}
1156
1157static int i2s_runtime_resume(struct device *dev)
1158{
1159 struct i2s_dai *i2s = dev_get_drvdata(dev);
f5c97c7b 1160 int ret;
5b1d3c34 1161
f5c97c7b
AY		 1162 ret = clk_prepare_enable(i2s->clk);
1163 if (ret)
1164 return ret;
1165
1166 if (i2s->op_clk) {
1167 ret = clk_prepare_enable(i2s->op_clk);
1168 if (ret) {
1169 clk_disable_unprepare(i2s->clk);
1170 return ret;
1171 }
1172 }
5b1d3c34 1173
e7e52dfc
MS		 1174 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
1175 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
1176 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
5b1d3c34
C		 1177
1178 return 0;
1179}
641d334b 1180#endif /* CONFIG_PM */
5b1d3c34 1181
074b89bb
SN		 1182static void i2s_unregister_clocks(struct i2s_dai *i2s)
1183{
1184 int i;
1185
1186 for (i = 0; i < i2s->clk_data.clk_num; i++) {
1187 if (!IS_ERR(i2s->clk_table[i]))
1188 clk_unregister(i2s->clk_table[i]);
1189 }
1190}
1191
1192static void i2s_unregister_clock_provider(struct platform_device *pdev)
1193{
1194 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev);
1195
1196 of_clk_del_provider(pdev->dev.of_node);
1197 i2s_unregister_clocks(i2s);
1198}
1199
1200static int i2s_register_clock_provider(struct platform_device *pdev)
1201{
1202 struct device *dev = &pdev->dev;
1203 struct i2s_dai *i2s = dev_get_drvdata(dev);
1204 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
1205 const char *p_names[2] = { NULL };
1206 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs;
1207 struct clk *rclksrc;
1208 int ret, i;
1209
1210 /* Register the clock provider only if it's expected in the DTB */
1211 if (!of_find_property(dev->of_node, "#clock-cells", NULL))
1212 return 0;
1213
1214 /* Get the RCLKSRC mux clock parent clock names */
1215 for (i = 0; i < ARRAY_SIZE(p_names); i++) {
1216 rclksrc = clk_get(dev, clk_name[i]);
1217 if (IS_ERR(rclksrc))
1218 continue;
1219 p_names[i] = __clk_get_name(rclksrc);
1220 clk_put(rclksrc);
1221 }
1222
1223 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1224 /* Activate the prescaler */
1225 u32 val = readl(i2s->addr + I2SPSR);
1226 writel(val | PSR_PSREN, i2s->addr + I2SPSR);
1227
9b41da80 1228 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
074b89bb
SN		 1229 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
1230 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
1231 i2s->addr + I2SMOD, reg_info->rclksrc_off,
1232 1, 0, i2s->lock);
1233
9b41da80 1234 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
074b89bb
SN		 1235 "i2s_presc", "i2s_rclksrc",
1236 CLK_SET_RATE_PARENT,
1237 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
1238
1239 p_names[0] = "i2s_presc";
1240 i2s->clk_data.clk_num = 2;
1241 }
1242 of_property_read_string_index(dev->of_node,
1243 "clock-output-names", 0, &clk_name[0]);
1244
9b41da80 1245 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, clk_name[0],
074b89bb
SN		 1246 p_names[0], CLK_SET_RATE_PARENT,
1247 i2s->addr + I2SMOD, reg_info->cdclkcon_off,
1248 CLK_GATE_SET_TO_DISABLE, i2s->lock);
1249
1250 i2s->clk_data.clk_num += 1;
1251 i2s->clk_data.clks = i2s->clk_table;
1252
1253 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1254 &i2s->clk_data);
1255 if (ret < 0) {
1256 dev_err(dev, "failed to add clock provider: %d\n", ret);
1257 i2s_unregister_clocks(i2s);
1258 }
1259
1260 return ret;
1261}
1262
fdca21ad 1263static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1264{
1c7ac018 1265 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61 1266 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1c7ac018 1267 struct resource *res;
40476f61
PV		 1268 u32 regs_base, quirks = 0, idma_addr = 0;
1269 struct device_node *np = pdev->dev.of_node;
7da493e9 1270 const struct samsung_i2s_dai_data *i2s_dai_data;
c92f1d0e 1271 int ret;
1c7ac018 1272
2f7b5d14
SN		 1273 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
1274 i2s_dai_data = of_device_get_match_data(&pdev->dev);
1275 else
1276 i2s_dai_data = (struct samsung_i2s_dai_data *)
1277 platform_get_device_id(pdev)->driver_data;
7c62eebb 1278
4720c2fe 1279 pri_dai = i2s_alloc_dai(pdev, i2s_dai_data, false);
40476f61
PV		 1280 if (!pri_dai) {
1281 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1282 return -ENOMEM;
1c7ac018
JB		 1283 }
1284
f3670536
SN		 1285 spin_lock_init(&pri_dai->spinlock);
1286 pri_dai->lock = &pri_dai->spinlock;
1287
40476f61 1288 if (!np) {
40476f61
PV		 1289 if (i2s_pdata == NULL) {
1290 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1291 return -EINVAL;
1292 }
1293
69e7a69a
SN		 1294 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
1295 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
9bdca822 1296 pri_dai->filter = i2s_pdata->dma_filter;
b9a1a743 1297
409c69be
KK		 1298 quirks = i2s_pdata->type.quirks;
1299 idma_addr = i2s_pdata->type.idma_addr;
40476f61 1300 } else {
7da493e9 1301 quirks = i2s_dai_data->quirks;
40476f61
PV		 1302 if (of_property_read_u32(np, "samsung,idma-addr",
1303 &idma_addr)) {
b0759736
PV		 1304 if (quirks & QUIRK_SUPPORTS_IDMA) {
1305 dev_info(&pdev->dev, "idma address is not"\
40476f61 1306 "specified");
40476f61
PV		 1307 }
1308 }
1309 }
064970a0 1310 quirks &= ~(QUIRK_SEC_DAI | QUIRK_SUPPORTS_IDMA);
1c7ac018
JB		 1311
1312 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af1cf5cf
SN		 1313 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1314 if (IS_ERR(pri_dai->addr))
1315 return PTR_ERR(pri_dai->addr);
1c7ac018 1316
1c7ac018
JB		 1317 regs_base = res->start;
1318
0ec2ba80
SN		 1319 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1320 if (IS_ERR(pri_dai->clk)) {
1321 dev_err(&pdev->dev, "Failed to get iis clock\n");
1322 return PTR_ERR(pri_dai->clk);
1323 }
c92f1d0e
SN		 1324
1325 ret = clk_prepare_enable(pri_dai->clk);
1326 if (ret != 0) {
1327 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1328 return ret;
1329 }
69e7a69a
SN		 1330 pri_dai->dma_playback.addr = regs_base + I2STXD;
1331 pri_dai->dma_capture.addr = regs_base + I2SRXD;
b8ab0ccc
SN		 1332 pri_dai->dma_playback.chan_name = "tx";
1333 pri_dai->dma_capture.chan_name = "rx";
69e7a69a
SN		 1334 pri_dai->dma_playback.addr_width = 4;
1335 pri_dai->dma_capture.addr_width = 4;
1c7ac018 1336 pri_dai->quirks = quirks;
a5a56871 1337 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1338
1339 if (quirks & QUIRK_PRI_6CHAN)
1340 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1341
73f5dfc6
MS		 1342 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
1343 NULL, NULL);
1344 if (ret < 0)
1345 goto err_disable_clk;
1346
be2c92eb
MS		 1347 ret = devm_snd_soc_register_component(&pdev->dev,
1348 &samsung_i2s_component,
1349 &pri_dai->i2s_dai_drv, 1);
1350 if (ret < 0)
1351 goto err_disable_clk;
1352
1c7ac018 1353 if (quirks & QUIRK_SEC_DAI) {
4720c2fe 1354 sec_dai = i2s_alloc_dai(pdev, i2s_dai_data, true);
1c7ac018
JB		 1355 if (!sec_dai) {
1356 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
fd61576f
WY		 1357 ret = -ENOMEM;
1358 goto err_disable_clk;
1c7ac018 1359 }
7e5d8706 1360
f3670536 1361 sec_dai->lock = &pri_dai->spinlock;
7e5d8706 1362 sec_dai->variant_regs = pri_dai->variant_regs;
69e7a69a 1363 sec_dai->dma_playback.addr = regs_base + I2STXDS;
b8ab0ccc 1364 sec_dai->dma_playback.chan_name = "tx-sec";
40476f61 1365
9bdca822 1366 if (!np) {
69e7a69a 1367 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
9bdca822
AB		 1368 sec_dai->filter = i2s_pdata->dma_filter;
1369 }
40476f61 1370
69e7a69a 1371 sec_dai->dma_playback.addr_width = 4;
af1cf5cf 1372 sec_dai->addr = pri_dai->addr;
0ec2ba80 1373 sec_dai->clk = pri_dai->clk;
1c7ac018 1374 sec_dai->quirks = quirks;
69e7a69a 1375 sec_dai->idma_playback.addr = idma_addr;
1c7ac018
JB		 1376 sec_dai->pri_dai = pri_dai;
1377 pri_dai->sec_dai = sec_dai;
be2c92eb
MS		 1378
1379 ret = samsung_asoc_dma_platform_register(&pdev->dev,
1380 sec_dai->filter, "tx-sec", NULL);
1381 if (ret < 0)
1382 goto err_disable_clk;
1383
1384 ret = devm_snd_soc_register_component(&pdev->dev,
1385 &samsung_i2s_component,
1386 &sec_dai->i2s_dai_drv, 1);
1387 if (ret < 0)
1388 goto err_disable_clk;
1c7ac018
JB		 1389 }
1390
0429ffef
MB		 1391 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1392 dev_err(&pdev->dev, "Unable to configure gpio\n");
fd61576f
WY		 1393 ret = -EINVAL;
1394 goto err_disable_clk;
1c7ac018
JB		 1395 }
1396
be2c92eb 1397 dev_set_drvdata(&pdev->dev, pri_dai);
1c7ac018 1398
dc938ddb 1399 pm_runtime_set_active(&pdev->dev);
c5cf4dbc
MB		 1400 pm_runtime_enable(&pdev->dev);
1401
2b960386
SN		 1402 ret = i2s_register_clock_provider(pdev);
1403 if (!ret)
1404 return 0;
a08485d8 1405
2b960386 1406 pm_runtime_disable(&pdev->dev);
fd61576f
WY		 1407err_disable_clk:
1408 clk_disable_unprepare(pri_dai->clk);
2b960386 1409 return ret;
1c7ac018
JB		 1410}
1411
fdca21ad 1412static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018 1413{
7b814a7d 1414 struct i2s_dai *pri_dai;
1c7ac018 1415
be2c92eb 1416 pri_dai = dev_get_drvdata(&pdev->dev);
1c7ac018 1417
dc938ddb 1418 pm_runtime_get_sync(&pdev->dev);
be2c92eb 1419 pm_runtime_disable(&pdev->dev);
c92f1d0e 1420
be2c92eb
MS		 1421 i2s_unregister_clock_provider(pdev);
1422 clk_disable_unprepare(pri_dai->clk);
dc938ddb 1423 pm_runtime_put_noidle(&pdev->dev);
1c7ac018 1424
1c7ac018
JB		 1425 return 0;
1426}
1427
a5a56871
PV		 1428static const struct samsung_i2s_variant_regs i2sv3_regs = {
1429 .bfs_off = 1,
1430 .rfs_off = 3,
1431 .sdf_off = 5,
1432 .txr_off = 8,
1433 .rclksrc_off = 10,
1434 .mss_off = 11,
1435 .cdclkcon_off = 12,
1436 .lrp_off = 7,
1437 .bfs_mask = 0x3,
1438 .rfs_mask = 0x3,
1439 .ftx0cnt_off = 8,
1440};
1441
1442static const struct samsung_i2s_variant_regs i2sv6_regs = {
1443 .bfs_off = 0,
1444 .rfs_off = 4,
1445 .sdf_off = 6,
1446 .txr_off = 8,
1447 .rclksrc_off = 10,
1448 .mss_off = 11,
1449 .cdclkcon_off = 12,
1450 .lrp_off = 15,
1451 .bfs_mask = 0xf,
1452 .rfs_mask = 0x3,
1453 .ftx0cnt_off = 8,
1454};
1455
1456static const struct samsung_i2s_variant_regs i2sv7_regs = {
1457 .bfs_off = 0,
1458 .rfs_off = 4,
1459 .sdf_off = 7,
1460 .txr_off = 9,
1461 .rclksrc_off = 11,
1462 .mss_off = 12,
1463 .cdclkcon_off = 22,
1464 .lrp_off = 15,
1465 .bfs_mask = 0xf,
1466 .rfs_mask = 0x7,
1467 .ftx0cnt_off = 0,
1468};
1469
1470static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1471 .bfs_off = 0,
1472 .rfs_off = 3,
1473 .sdf_off = 6,
1474 .txr_off = 8,
1475 .rclksrc_off = 10,
1476 .mss_off = 11,
1477 .cdclkcon_off = 12,
1478 .lrp_off = 15,
1479 .bfs_mask = 0x7,
1480 .rfs_mask = 0x7,
1481 .ftx0cnt_off = 8,
1482};
1483
7da493e9 1484static const struct samsung_i2s_dai_data i2sv3_dai_type = {
7da493e9 1485 .quirks = QUIRK_NO_MUXPSR,
4720c2fe 1486 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1487 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1488};
1489
1490static const struct samsung_i2s_dai_data i2sv5_dai_type = {
b0759736
PV		 1491 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1492 QUIRK_SUPPORTS_IDMA,
4720c2fe 1493 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1494 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1495};
1496
4ca0c0d4 1497static const struct samsung_i2s_dai_data i2sv6_dai_type = {
4ca0c0d4 1498 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1499 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
4720c2fe 1500 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871
PV		 1501 .i2s_variant_regs = &i2sv6_regs,
1502};
1503
1504static const struct samsung_i2s_dai_data i2sv7_dai_type = {
a5a56871
PV		 1505 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1506 QUIRK_SUPPORTS_TDM,
4720c2fe 1507 .pcm_rates = SNDRV_PCM_RATE_8000_192000,
a5a56871
PV		 1508 .i2s_variant_regs = &i2sv7_regs,
1509};
1510
1511static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
a5a56871 1512 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
4720c2fe 1513 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1514 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1515};
1516
eb8ca0fa 1517static const struct platform_device_id samsung_i2s_driver_ids[] = {
7c62eebb
PV		 1518 {
1519 .name = "samsung-i2s",
3f024980 1520 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1521 },
1522 {},
1523};
2af19558 1524MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1525
40476f61 1526#ifdef CONFIG_OF
40476f61 1527static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1528 {
1529 .compatible = "samsung,s3c6410-i2s",
1530 .data = &i2sv3_dai_type,
1531 }, {
1532 .compatible = "samsung,s5pv210-i2s",
1533 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1534 }, {
1535 .compatible = "samsung,exynos5420-i2s",
1536 .data = &i2sv6_dai_type,
a5a56871
PV		 1537 }, {
1538 .compatible = "samsung,exynos7-i2s",
1539 .data = &i2sv7_dai_type,
1540 }, {
1541 .compatible = "samsung,exynos7-i2s1",
1542 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1543 },
1544 {},
1545};
1546MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1547#endif
1548
5b1d3c34
C		 1549static const struct dev_pm_ops samsung_i2s_pm = {
1550 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1551 i2s_runtime_resume, NULL)
e7e52dfc
MS		 1552 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1553 pm_runtime_force_resume)
5b1d3c34
C		 1554};
1555
1c7ac018
JB		 1556static struct platform_driver samsung_i2s_driver = {
1557 .probe = samsung_i2s_probe,
fdca21ad 1558 .remove = samsung_i2s_remove,
7c62eebb 1559 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1560 .driver = {
1561 .name = "samsung-i2s",
40476f61 1562 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1563 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1564 },
1565};
1566
e00c3f55 1567module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1568
1569/* Module information */
df8ad335 1570MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1571MODULE_DESCRIPTION("Samsung I2S Interface");
1572MODULE_ALIAS("platform:samsung-i2s");
1573MODULE_LICENSE("GPL");
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