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Document the binutils source files used in constructing sparc-dis.c
[qemu.git] / sparc-dis.c
CommitLineData
d4abd567
BS		 1/*
2 * These files from binutils are concatenated:
3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
4 */
5
6/* include/opcode/sparc.h */
7
aa0aa4fa
FB		 8/* Print SPARC instructions.
9 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
10 2000, 2002 Free Software Foundation, Inc.
11
12This program is free software; you can redistribute it and/or modify
13it under the terms of the GNU General Public License as published by
14the Free Software Foundation; either version 2 of the License, or
15(at your option) any later version.
16
17This program is distributed in the hope that it will be useful,
18but WITHOUT ANY WARRANTY; without even the implied warranty of
19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20GNU General Public License for more details.
21
22You should have received a copy of the GNU General Public License
23along with this program; if not, write to the Free Software
24Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25#include <stdlib.h>
26#include "dis-asm.h"
27
28/* The SPARC opcode table (and other related data) is defined in
29 the opcodes library in sparc-opc.c. If you change anything here, make
30 sure you fix up that file, and vice versa. */
31
32 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
33 instruction's name rather than the args. This would make gas faster, pinsn
34 slower, but would mess up some macros a bit. xoxorich. */
35
36/* List of instruction sets variations.
37 These values are such that each element is either a superset of a
38 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
39 returns non-zero.
40 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
41 Don't change this without updating sparc-opc.c. */
42
43enum sparc_opcode_arch_val {
44 SPARC_OPCODE_ARCH_V6 = 0,
45 SPARC_OPCODE_ARCH_V7,
46 SPARC_OPCODE_ARCH_V8,
47 SPARC_OPCODE_ARCH_SPARCLET,
48 SPARC_OPCODE_ARCH_SPARCLITE,
49 /* v9 variants must appear last */
50 SPARC_OPCODE_ARCH_V9,
51 SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
52 SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
53 SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
54};
55
56/* The highest architecture in the table. */
57#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
58
59/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
60 insn encoding/decoding. */
61#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
62
63/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
64#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
65
66/* Table of cpu variants. */
67
68struct sparc_opcode_arch {
69 const char *name;
70 /* Mask of sparc_opcode_arch_val's supported.
71 EG: For v7 this would be
72 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
73 These are short's because sparc_opcode.architecture is. */
74 short supported;
75};
76
f82a3d48 77static const struct sparc_opcode_arch sparc_opcode_archs[];
aa0aa4fa 78
aa0aa4fa
FB		 79/* Return the bitmask of supported architectures for ARCH. */
80#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
81
82/* Non-zero if ARCH1 conflicts with ARCH2.
83 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
84#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
85(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
86 != SPARC_OPCODE_SUPPORTED (ARCH1)) \
87 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
88 != SPARC_OPCODE_SUPPORTED (ARCH2)))
89
90/* Structure of an opcode table entry. */
91
92struct sparc_opcode {
93 const char *name;
f930d07e
BS		 94 unsigned long match; /* Bits that must be set. */
95 unsigned long lose; /* Bits that must not be set. */
aa0aa4fa
FB		 96 const char *args;
97 /* This was called "delayed" in versions before the flags. */
98 char flags;
f930d07e 99 short architecture; /* Bitmask of sparc_opcode_arch_val's. */
aa0aa4fa
FB		 100};
101
f930d07e
BS		 102#define F_DELAYED 1 /* Delayed branch */
103#define F_ALIAS 2 /* Alias for a "real" instruction */
104#define F_UNBR 4 /* Unconditional branch */
105#define F_CONDBR 8 /* Conditional branch */
106#define F_JSR 16 /* Subroutine call */
107#define F_FLOAT 32 /* Floating point instruction (not a branch) */
108#define F_FBR 64 /* Floating point branch */
aa0aa4fa
FB		 109/* FIXME: Add F_ANACHRONISTIC flag for v9. */
110
111/*
112
113All sparc opcodes are 32 bits, except for the `set' instruction (really a
114macro), which is 64 bits. It is handled as a special case.
115
116The match component is a mask saying which bits must match a particular
117opcode in order for an instruction to be an instance of that opcode.
118
119The args component is a string containing one character for each operand of the
120instruction.
121
122Kinds of operands:
f930d07e
BS		 123 # Number used by optimizer. It is ignored.
124 1 rs1 register.
125 2 rs2 register.
126 d rd register.
127 e frs1 floating point register.
128 v frs1 floating point register (double/even).
129 V frs1 floating point register (quad/multiple of 4).
130 f frs2 floating point register.
131 B frs2 floating point register (double/even).
132 R frs2 floating point register (quad/multiple of 4).
133 g frsd floating point register.
134 H frsd floating point register (double/even).
135 J frsd floating point register (quad/multiple of 4).
136 b crs1 coprocessor register
137 c crs2 coprocessor register
138 D crsd coprocessor register
139 m alternate space register (asr) in rd
140 M alternate space register (asr) in rs1
141 h 22 high bits.
142 X 5 bit unsigned immediate
143 Y 6 bit unsigned immediate
144 3 SIAM mode (3 bits). (v9b)
145 K MEMBAR mask (7 bits). (v9)
146 j 10 bit Immediate. (v9)
147 I 11 bit Immediate. (v9)
148 i 13 bit Immediate.
149 n 22 bit immediate.
150 k 2+14 bit PC relative immediate. (v9)
151 G 19 bit PC relative immediate. (v9)
152 l 22 bit PC relative immediate.
153 L 30 bit PC relative immediate.
154 a Annul. The annul bit is set.
155 A Alternate address space. Stored as 8 bits.
156 C Coprocessor state register.
157 F floating point state register.
158 p Processor state register.
159 N Branch predict clear ",pn" (v9)
160 T Branch predict set ",pt" (v9)
161 z %icc. (v9)
162 Z %xcc. (v9)
163 q Floating point queue.
164 r Single register that is both rs1 and rd.
165 O Single register that is both rs2 and rd.
166 Q Coprocessor queue.
167 S Special case.
168 t Trap base register.
169 w Window invalid mask register.
170 y Y register.
171 u sparclet coprocessor registers in rd position
172 U sparclet coprocessor registers in rs1 position
173 E %ccr. (v9)
174 s %fprs. (v9)
175 P %pc. (v9)
176 W %tick. (v9)
177 o %asi. (v9)
178 6 %fcc0. (v9)
179 7 %fcc1. (v9)
180 8 %fcc2. (v9)
181 9 %fcc3. (v9)
182 ! Privileged Register in rd (v9)
183 ? Privileged Register in rs1 (v9)
184 * Prefetch function constant. (v9)
185 x OPF field (v9 impdep).
186 0 32/64 bit immediate for set or setx (v9) insns
187 _ Ancillary state register in rd (v9a)
188 / Ancillary state register in rs1 (v9a)
aa0aa4fa
FB		 189
190The following chars are unused: (note: ,[] are used as punctuation)
191[45]
192
193*/
194
f930d07e
BS		 195#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
196#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
197#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
198#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
199#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
200#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
201#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
202#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
203#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
204#define F1(x) (OP(x))
205#define DISP30(x) ((x)&0x3fffffff)
206#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
207#define RS2(x) ((x)&0x1f) /* rs2 field */
208#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
209#define RD(x) (((x)&0x1f) << 25) /* destination register field */
210#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
211#define ASI_RS2(x) (SIMM13(x))
212#define MEMBAR(x) ((x)&0x7f)
213#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
214
215#define ANNUL (1<<29)
216#define BPRED (1<<19) /* v9 */
217#define IMMED F3I(1)
218#define RD_G0 RD(~0)
219#define RS1_G0 RS1(~0)
220#define RS2_G0 RS2(~0)
aa0aa4fa 221
f82a3d48
BS		 222static const struct sparc_opcode sparc_opcodes[];
223static const int sparc_num_opcodes;
aa0aa4fa 224
f82a3d48
BS		 225static const char *sparc_decode_asi_v8 PARAMS ((int));
226static const char *sparc_decode_asi_v9 PARAMS ((int));
227static const char *sparc_decode_membar PARAMS ((int));
228static const char *sparc_decode_prefetch PARAMS ((int));
229static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
aa0aa4fa 230
d4abd567
BS		 231/* opcodes/sparc-opc.c */
232
aa0aa4fa 233/* Some defines to make life easy. */
f930d07e
BS		 234#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
235#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
236#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
237#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
238#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
239#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
240#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
241#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
aa0aa4fa
FB		 242
243/* Bit masks of architectures supporting the insn. */
244
f930d07e
BS		 245#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
246 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
aa0aa4fa 247/* v6 insns not supported on the sparclet */
f930d07e
BS		 248#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
249 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
250#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
251 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
aa0aa4fa
FB		 252/* Although not all insns are implemented in hardware, sparclite is defined
253 to be a superset of v8. Unimplemented insns trap and are then theoretically
254 implemented in software.
255 It's not clear that the same is true for sparclet, although the docs
256 suggest it is. Rather than complicating things, the sparclet assembler
257 recognizes all v8 insns. */
f930d07e
BS		 258#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
259 | MASK_V9 | MASK_V9A | MASK_V9B)
260#define sparclet (MASK_SPARCLET)
261#define sparclite (MASK_SPARCLITE)
262#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
263#define v9a (MASK_V9A | MASK_V9B)
264#define v9b (MASK_V9B)
aa0aa4fa 265/* v6 insns not supported by v9 */
f930d07e
BS		 266#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
267 | MASK_SPARCLET | MASK_SPARCLITE)
aa0aa4fa
FB		 268/* v9a instructions which would appear to be aliases to v9's impdep's
269 otherwise */
f930d07e 270#define v9notv9a (MASK_V9)
aa0aa4fa
FB		 271
272/* Table of opcode architectures.
273 The order is defined in opcode/sparc.h. */
274
f82a3d48 275static const struct sparc_opcode_arch sparc_opcode_archs[] = {
aa0aa4fa
FB		 276 { "v6", MASK_V6 },
277 { "v7", MASK_V6 | MASK_V7 },
278 { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
279 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
280 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
7f75ffd3 281 /* ??? Don't some v8 privileged insns conflict with v9? */
aa0aa4fa
FB		 282 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
283 /* v9 with ultrasparc additions */
284 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
285 /* v9 with cheetah additions */
286 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
287 { NULL, 0 }
288};
289
aa0aa4fa 290/* Branch condition field. */
f930d07e 291#define COND(x) (((x)&0xf)<<25)
aa0aa4fa
FB		 292
293/* v9: Move (MOVcc and FMOVcc) condition field. */
f930d07e 294#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
aa0aa4fa
FB		 295
296/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
f930d07e
BS		 297#define RCOND(x) (((x)&0x7)<<10) /* v9 */
298
299#define CONDA (COND(0x8))
300#define CONDCC (COND(0xd))
301#define CONDCS (COND(0x5))
302#define CONDE (COND(0x1))
303#define CONDG (COND(0xa))
304#define CONDGE (COND(0xb))
305#define CONDGU (COND(0xc))
306#define CONDL (COND(0x3))
307#define CONDLE (COND(0x2))
308#define CONDLEU (COND(0x4))
309#define CONDN (COND(0x0))
310#define CONDNE (COND(0x9))
311#define CONDNEG (COND(0x6))
312#define CONDPOS (COND(0xe))
313#define CONDVC (COND(0xf))
314#define CONDVS (COND(0x7))
315
316#define CONDNZ CONDNE
317#define CONDZ CONDE
318#define CONDGEU CONDCC
319#define CONDLU CONDCS
320
321#define FCONDA (COND(0x8))
322#define FCONDE (COND(0x9))
323#define FCONDG (COND(0x6))
324#define FCONDGE (COND(0xb))
325#define FCONDL (COND(0x4))
326#define FCONDLE (COND(0xd))
327#define FCONDLG (COND(0x2))
328#define FCONDN (COND(0x0))
329#define FCONDNE (COND(0x1))
330#define FCONDO (COND(0xf))
331#define FCONDU (COND(0x7))
332#define FCONDUE (COND(0xa))
333#define FCONDUG (COND(0x5))
334#define FCONDUGE (COND(0xc))
335#define FCONDUL (COND(0x3))
336#define FCONDULE (COND(0xe))
337
338#define FCONDNZ FCONDNE
339#define FCONDZ FCONDE
340
341#define ICC (0) /* v9 */
aa0aa4fa 342#define XCC (1<<12) /* v9 */
f930d07e
BS		 343#define FCC(x) (((x)&0x3)<<11) /* v9 */
344#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
aa0aa4fa
FB		 345\f
346/* The order of the opcodes in the table is significant:
5fafdf24 347
f930d07e
BS		 348 * The assembler requires that all instances of the same mnemonic must
349 be consecutive. If they aren't, the assembler will bomb at runtime.
aa0aa4fa 350
f930d07e 351 * The disassembler should not care about the order of the opcodes.
aa0aa4fa
FB		 352
353*/
354
355/* Entries for commutative arithmetic operations. */
356/* ??? More entries can make use of this. */
357#define COMMUTEOP(opcode, op3, arch_mask) \
f930d07e
BS		 358{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
359{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
360{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
aa0aa4fa 361
f82a3d48 362static const struct sparc_opcode sparc_opcodes[] = {
aa0aa4fa 363
f930d07e
BS		 364{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
365{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
366{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
367{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
368{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
369{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
370{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
371{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
372{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 },
373{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 },
374{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 },
375{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */
376
377{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
378{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
379{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
380{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
381{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
382{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
383
384{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 },
385{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
386{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 },
387{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 },
388{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
389{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
390{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 },
391{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
392{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 },
393{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 },
394{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 },
395{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
aa0aa4fa
FB		 396
397/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
398 'ld' pseudo-op in v9. */
f930d07e
BS		 399{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 },
400{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
401{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 },
402{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 },
403{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 },
404{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
405
406{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
407{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
408{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 },
409{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 },
410{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 },
411{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */
412{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
413{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
414{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 },
415{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 },
416{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 },
417{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */
418
419{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
420{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
421{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 },
422{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 },
423{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
424{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
425
426{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
427{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
428{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 },
429{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 },
430{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 },
431{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */
432
433{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
434{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
435{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 },
436{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 },
437{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 },
438{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
439
440{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
441{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
442{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 },
443{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 },
444{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 },
445{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
446
447{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
448{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
449{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 },
450{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 },
451{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 },
452{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
453
454{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
455{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
456{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 },
457{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 },
458{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 },
459{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
460
461{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
462{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
463{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 },
464{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 },
465{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 },
466{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */
467
468{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
469{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
470{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 },
471{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 },
472{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 },
473{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */
474
475{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
476{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
477{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 },
478{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 },
479{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 },
480{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */
481
482{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
483{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
484{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
485{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
486{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
487{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
488
489{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
490{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
491{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
492{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 },
493{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 },
494{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
495{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 },
496{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
497{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 },
498{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 },
499{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 },
500{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
501
502{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 },
503{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
504{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 },
505{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 },
506{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 },
507{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
508
509{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 },
510{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
511{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 },
512{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 },
513{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 },
514{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
515
516{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 },
517{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
518{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 },
519{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 },
520{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 },
521{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
522
523{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 },
524{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
525{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 },
526{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 },
527{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 },
528{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
529
530{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 },
531{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
532{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 },
533{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 },
534{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 },
535{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
536
537{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 },
538{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
539{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 },
540{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 },
541{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 },
542{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
543
544{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 },
545{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
546{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 },
547{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 },
548{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 },
549{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
550
551{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 },
552{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
553{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 },
554{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 },
555{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 },
556{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
557
558{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 },
559{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
560{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 },
561{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 },
562{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 },
563{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
564
565{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
566{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
567{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 },
568{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 },
569{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 },
570{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
571
572{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 },
573{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
574{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 },
575{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 },
576{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 },
577{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
578
579{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
580{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
581{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 },
582{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 },
583{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 },
584{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */
585{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
586{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
587{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 },
588{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 },
589{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 },
590{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */
591
592{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
593{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
594{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 },
595{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 },
596{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
597{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
598{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
599{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
600{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 },
601{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 },
602{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 },
603{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
604
605{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
606{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
607{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 },
608{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 },
609{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 },
610{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */
611
612{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
613{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
614{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
615{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
616{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
617{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
618{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
619{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
620{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
621{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
622{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
623{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
624{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
625{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
626{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
627{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
628{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
629{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
630
631{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
632{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
633{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 },
634{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 },
635{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
636{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
637
638{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 },
639{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
640{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 },
641{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 },
642{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 },
643{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
644
645{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 },
646{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
647{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 },
648{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 },
649{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 },
650{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
651
652{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
653{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
654{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
655{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
656{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
657{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
658{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
659{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
660{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
661{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
662{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
663{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
664{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
665{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
666{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
667{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
668{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
669{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
670
671{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
672{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
673{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 },
674{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 },
675{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 },
676{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
677
678{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
679{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
680{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
681{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
682{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
683{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
684{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
685{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
686{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
687{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
688{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
689{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
690
691{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 },
692{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
693{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 },
694{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 },
695{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 },
696{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
697
698{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
699{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
700{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
701{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
702{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
703{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
704{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
705{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
706{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
707{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
708{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
709{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
710
711{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
712{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
713{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 },
714{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 },
715{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 },
716{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */
717
718{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
719{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
720{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 },
721{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 },
722{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 },
723{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
724{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
725{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
726{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 },
727{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 },
728{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 },
729{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */
730
731{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
732{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
733{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 },
734{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 },
735{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 },
736{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
737{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
738{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
739{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 },
740{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 },
741{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
742{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
743
744{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
745{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
746{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 },
747{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 },
748{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
749{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
750
751{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 },
752{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
753{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 },
754{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 },
755{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 },
756{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
757{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 },
758{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
759{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 },
760{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 },
761{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 },
762{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
763
764{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
765{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
766{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 },
767{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 },
768{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 },
769{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
770
771{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
772{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
773{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
774{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
775{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
776{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
777{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
778{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
779{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
780{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
781{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
782{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
783
784{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 },
785{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
786{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 },
787{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 },
788{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 },
789{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
790
791{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
792{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
793{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
794{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
795{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
796{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
797{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
798{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
799{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
800{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
801{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
802{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
803
804{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
805{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
806{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 },
807{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 },
808{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 },
809{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
810
811{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
812{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
813{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 },
814{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 },
815{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 },
816{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
817
818{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 },
819{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
820{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 },
821{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 },
822{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 },
823{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
824
825{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
826{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
827{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 },
828{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 },
829{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 },
830{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */
831
832{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
833{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
834{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 },
835{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 },
836{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 },
837{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
838
839{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
840{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
841{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
842{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
843{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
844{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */
845
846{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
847{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
848{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 },
849{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 },
850{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 },
851{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
852
853{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
854{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */
855{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 },
856{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */
857
858{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
859{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
860{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
861{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
862{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
863{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */
864{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
865
866{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
867{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
868{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
869
870{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
aa0aa4fa
FB		 871{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
872
f930d07e
BS		 873{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
874{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
875{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
876{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
877{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 },
878{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 },
879
880{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
881{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
882{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
883{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
884{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
885
886{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
887{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */
888{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */
889{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */
890{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
891{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
aa0aa4fa
FB		 892
893/* IFLUSH was renamed to FLUSH in v8. */
f930d07e
BS		 894{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
895{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
896{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */
897{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 },
898{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 },
899{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 },
900
901{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
902{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */
903{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */
904{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */
905{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
906{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
907
908{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 },
909
910{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
911{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
912
913{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 },
914{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
915{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 },
916{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 },
917{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 },
918{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
919{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 },
920{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
921{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 },
922{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 },
923{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 },
924{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
925
926{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
927{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
928{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
929{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
930{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
931{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
932
933{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
934{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
935{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
936{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
937{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
938{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
939
940{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
941{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 },
942
943{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
944{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite },
945
946{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
947{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite },
948
949{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
950{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 },
951
952{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
953{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */
954{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
955{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
956{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
957{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
958{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
959{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
960
961{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
962{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
963{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
964{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
965{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
966{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
967
968{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
969{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
970{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
971{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
972{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
973{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
974
975{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
976{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
977{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 },
978{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 },
979{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 },
980{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
981
982{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
983{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 },
984{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 },
aa0aa4fa
FB		 985
986/* This is not a commutative instruction. */
f930d07e
BS		 987{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
988{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 989
990/* This is not a commutative instruction. */
f930d07e
BS		 991{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
992{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 },
993
994{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
995{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
996{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */
997
998{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
999{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
1000{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1001{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
1002{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
1003{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1004{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
1005{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
1006{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1007{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
1008{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1009{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1010{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1011{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1012{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1013
1014{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
1015{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */
1016{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
1017{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
1018{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
1019{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */
1020
1021{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1022{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */
1023{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
1024{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */
1025{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1026{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */
1027{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1028{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */
1029{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1030{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
1031{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1032{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
1033{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
1034{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
1035{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1036{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
1037{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1038{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
1039{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1040{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
1041
1042{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
1043{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
1044{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
1045{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
1046{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
1047
1048{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
1049{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1050{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
1051{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
1052{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
1053
1054{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
1055{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
1056{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
1057{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
1058{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
1059{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1060{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
1061{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
1062
1063{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
1064{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
1065{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */
1066{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
1067{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1068{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
aa0aa4fa
FB		 1069
1070/* ??? This group seems wrong. A three operand move? */
f930d07e
BS		 1071{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1072{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1073{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1074{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1075{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1076{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1077{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1078{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1079{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1080{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
1081
1082{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1083{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
1084{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1085{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1086{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
1087
1088{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1089{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
1090{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
1091{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1092{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
1093{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
1094{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1095{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
1096{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
1097{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1098{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
1099{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
1100{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1101{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
1102{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
1103
1104{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
1105{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */
1106{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */
1107{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */
1108
1109{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
1110{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 },
1111{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 },
1112
1113{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */
1114{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */
aa0aa4fa
FB		 1115
1116/* This is not a commutative instruction. */
f930d07e
BS		 1117{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
1118{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 1119
1120/* This is not a commutative instruction. */
f930d07e
BS		 1121{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
1122{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 },
1123
1124{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */
1125{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */
1126
1127{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
1128{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
1129
1130{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
1131{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 },
1132
1133{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
1134{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 },
1135
1136{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1137{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 },
1138{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1139{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 },
1140
1141{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1142{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 },
1143{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1144{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 },
1145
1146{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
1147{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 },
1148{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 },
1149
1150{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
1151{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 },
1152{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 },
1153
1154{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */
1155{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
1156{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
1157{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
1158{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */
1159{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
1160{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
1161{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
1162
1163{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
1164{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */
1165
1166{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
1167{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
1168
1169{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
1170{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 },
1171{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 },
1172{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
1173{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 },
1174{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 },
1175
1176{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1177{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 },
1178{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 },
1179{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 },
1180{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 },
1181{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 },
1182
1183{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1184{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 },
1185{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 },
1186{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 },
1187{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 },
1188{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 },
1189
1190{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1191{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 },
1192{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 },
1193{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1194{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 },
1195{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 },
1196{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1197{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 },
1198{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 },
1199{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1200{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 },
1201{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 },
1202{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1203{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 },
1204{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 },
1205{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1206{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 },
1207{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 },
1208{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1209{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 },
1210{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 },
1211{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1212{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 },
1213{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 },
1214
1215{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1216{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 },
1217{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1218{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 },
1219{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1220{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 },
1221
1222{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1223{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
1224
1225{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1226{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 },
1227{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1228{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
1229{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1230{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 },
1231{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1232{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 },
1233{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1234{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 },
1235{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1236{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
aa0aa4fa
FB		 1237
1238
1239/* Conditional instructions.
1240
1241 Because this part of the table was such a mess earlier, I have
1242 macrofied it so that all the branches and traps are generated from
1243 a single-line description of each condition value. John Gilmore. */
1244
1245/* Define branches -- one annulled, one without, etc. */
1246#define br(opcode, mask, lose, flags) \
1247 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
1248 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
1249
1250#define brx(opcode, mask, lose, flags) /* v9 */ \
1251 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
1252 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
1253 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
1254 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1255 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
1256 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1257 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
1258 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
1259 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
1260 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1261 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
1262 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1263
1264/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1265#define tr(opcode, mask, lose, flags) \
f930d07e
BS		 1266 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
1267 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1268 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1269 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
1270 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1271 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1272 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1273 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1274 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
1275 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
1276 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
1277 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
aa0aa4fa
FB		 1278
1279/* v9: We must put `brx' before `br', to ensure that we never match something
1280 v9: against an expression unless it is an expression. Otherwise, we end
1281 v9: up with undefined symbol tables entries, because they get added, but
1282 v9: are not deleted if the pattern fails to match. */
1283
1284/* Define both branches and traps based on condition mask */
1285#define cond(bop, top, mask, flags) \
1286 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1287 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1288 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1289
1290/* Define all the conditions, all the branches, all the traps. */
1291
1292/* Standard branch, trap mnemonics */
f930d07e 1293cond ("b", "ta", CONDA, F_UNBR),
aa0aa4fa 1294/* Alternative form (just for assembly, not for disassembly) */
f930d07e
BS		 1295cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
1296
1297cond ("bcc", "tcc", CONDCC, F_CONDBR),
1298cond ("bcs", "tcs", CONDCS, F_CONDBR),
1299cond ("be", "te", CONDE, F_CONDBR),
1300cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
1301cond ("bg", "tg", CONDG, F_CONDBR),
1302cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
1303cond ("bge", "tge", CONDGE, F_CONDBR),
1304cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1305cond ("bgu", "tgu", CONDGU, F_CONDBR),
1306cond ("bl", "tl", CONDL, F_CONDBR),
1307cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
1308cond ("ble", "tle", CONDLE, F_CONDBR),
1309cond ("bleu", "tleu", CONDLEU, F_CONDBR),
1310cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1311cond ("bn", "tn", CONDN, F_CONDBR),
1312cond ("bne", "tne", CONDNE, F_CONDBR),
1313cond ("bneg", "tneg", CONDNEG, F_CONDBR),
1314cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1315cond ("bpos", "tpos", CONDPOS, F_CONDBR),
1316cond ("bvc", "tvc", CONDVC, F_CONDBR),
1317cond ("bvs", "tvs", CONDVS, F_CONDBR),
1318cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
aa0aa4fa
FB		 1319
1320#undef cond
1321#undef br
1322#undef brr /* v9 */
1323#undef tr
1324
1325#define brr(opcode, mask, lose, flags) /* v9 */ \
1326 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
1327 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
1328 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
1329 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1330 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
1331 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1332
1333#define condr(bop, mask, flags) /* v9 */ \
1334 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1335
1336/* v9 */ condr("brnz", 0x5, F_CONDBR),
1337/* v9 */ condr("brz", 0x1, F_CONDBR),
1338/* v9 */ condr("brgez", 0x7, F_CONDBR),
1339/* v9 */ condr("brlz", 0x3, F_CONDBR),
1340/* v9 */ condr("brlez", 0x2, F_CONDBR),
1341/* v9 */ condr("brgz", 0x6, F_CONDBR),
1342
1343#undef condr /* v9 */
1344#undef brr /* v9 */
1345
1346#define movr(opcode, mask, flags) /* v9 */ \
1347 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1348 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1349
1350#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1351 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1352#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1353 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1354#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1355 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1356
1357#define fmovrs(mop, mask, flags) /* v9 */ \
1358 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1359#define fmovrd(mop, mask, flags) /* v9 */ \
1360 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1361#define fmovrq(mop, mask, flags) /* v9 */ \
1362 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1363
1364/* v9 */ movr("movrne", 0x5, 0),
1365/* v9 */ movr("movre", 0x1, 0),
1366/* v9 */ movr("movrgez", 0x7, 0),
1367/* v9 */ movr("movrlz", 0x3, 0),
1368/* v9 */ movr("movrlez", 0x2, 0),
1369/* v9 */ movr("movrgz", 0x6, 0),
1370/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1371/* v9 */ movr("movrz", 0x1, F_ALIAS),
1372
1373/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1374/* v9 */ fmovrs("fmovrse", 0x1, 0),
1375/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1376/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1377/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1378/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1379/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1380/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1381
1382/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1383/* v9 */ fmovrd("fmovrde", 0x1, 0),
1384/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1385/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1386/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1387/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1388/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1389/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1390
1391/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1392/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1393/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1394/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1395/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1396/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1397/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1398/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1399
1400#undef movr /* v9 */
1401#undef fmovr /* v9 */
1402#undef fmrr /* v9 */
1403
1404#define movicc(opcode, cond, flags) /* v9 */ \
1405 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1406 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1407 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
1408 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
1409
1410#define movfcc(opcode, fcond, flags) /* v9 */ \
1411 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1412 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1413 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1414 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1415 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1416 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1417 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1418 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1419
1420#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1421 movfcc (opcode, fcond, flags), /* v9 */ \
1422 movicc (opcode, cond, flags) /* v9 */
1423
f930d07e
BS		 1424/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
1425/* v9 */ movicc ("movcc", CONDCC, 0),
1426/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
1427/* v9 */ movicc ("movcs", CONDCS, 0),
1428/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
1429/* v9 */ movcc ("move", CONDE, FCONDE, 0),
1430/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
1431/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
1432/* v9 */ movicc ("movgu", CONDGU, 0),
1433/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
1434/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
1435/* v9 */ movicc ("movleu", CONDLEU, 0),
1436/* v9 */ movfcc ("movlg", FCONDLG, 0),
1437/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
1438/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
1439/* v9 */ movicc ("movneg", CONDNEG, 0),
1440/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
1441/* v9 */ movfcc ("movo", FCONDO, 0),
1442/* v9 */ movicc ("movpos", CONDPOS, 0),
1443/* v9 */ movfcc ("movu", FCONDU, 0),
1444/* v9 */ movfcc ("movue", FCONDUE, 0),
1445/* v9 */ movfcc ("movug", FCONDUG, 0),
1446/* v9 */ movfcc ("movuge", FCONDUGE, 0),
1447/* v9 */ movfcc ("movul", FCONDUL, 0),
1448/* v9 */ movfcc ("movule", FCONDULE, 0),
1449/* v9 */ movicc ("movvc", CONDVC, 0),
1450/* v9 */ movicc ("movvs", CONDVS, 0),
1451/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
aa0aa4fa
FB		 1452
1453#undef movicc /* v9 */
1454#undef movfcc /* v9 */
1455#undef movcc /* v9 */
1456
f930d07e
BS		 1457#define FM_SF 1 /* v9 - values for fpsize */
1458#define FM_DF 2 /* v9 */
1459#define FM_QF 3 /* v9 */
aa0aa4fa
FB		 1460
1461#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
1462{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
1463{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }
1464
1465#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
1466{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
1467{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
1468{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
1469{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
1470
1471/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1472#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
1473{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \
1474{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \
1475{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \
1476{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \
1477{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \
1478{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }
1479
f930d07e
BS		 1480/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0),
1481/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0),
1482/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0),
1483/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0),
1484/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0),
1485/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0),
1486/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0),
1487/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0),
1488/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0),
1489/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0),
1490/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0),
1491/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0),
1492/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0),
1493/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0),
1494/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0),
1495/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0),
1496/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0),
1497/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0),
1498/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS),
1499/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS),
1500/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS),
1501/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0),
1502/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0),
1503/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0),
1504/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0),
1505/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0),
1506/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0),
1507/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0),
1508/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0),
1509/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0),
1510/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0),
1511/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0),
1512/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0),
1513/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0),
1514/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0),
1515/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0),
1516/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS),
1517/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS),
1518/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS),
1519/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0),
1520/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0),
1521/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0),
1522/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0),
1523/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0),
1524/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0),
1525/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0),
1526/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0),
1527/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0),
1528/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS),
1529/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS),
1530/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS),
1531/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0),
1532/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0),
1533/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0),
1534/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0),
1535/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0),
1536/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0),
1537/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0),
1538/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0),
1539/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0),
1540/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0),
1541/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0),
1542/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0),
1543/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0),
1544/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0),
1545/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0),
1546/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0),
1547/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0),
1548/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0),
1549/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0),
1550/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0),
1551/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0),
1552/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0),
1553/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0),
1554/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0),
1555/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0),
1556/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0),
1557/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0),
1558/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0),
1559/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0),
1560/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0),
1561/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS),
1562/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS),
1563/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS),
aa0aa4fa
FB		 1564
1565#undef fmovicc /* v9 */
1566#undef fmovfcc /* v9 */
1567#undef fmovcc /* v9 */
1568#undef FM_DF /* v9 */
1569#undef FM_QF /* v9 */
1570#undef FM_SF /* v9 */
1571
1572/* Coprocessor branches. */
1573#define CBR(opcode, mask, lose, flags, arch) \
1574 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
1575 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
1576
1577/* Floating point branches. */
1578#define FBR(opcode, mask, lose, flags) \
1579 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \
1580 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
1581
1582/* V9 extended floating point branches. */
1583#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1584 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
1585 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1586 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1587 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1588 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1589 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1590 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
1591 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1592 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1593 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1594 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1595 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1596 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
1597 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1598 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1599 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1600 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1601 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1602 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
1603 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1604 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1605 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1606 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1607 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1608
1609/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1610 v9: something against an expression unless it is an expression. Otherwise,
1611 v9: we end up with undefined symbol tables entries, because they get added,
1612 v9: but are not deleted if the pattern fails to match. */
1613
1614#define CONDFC(fop, cop, mask, flags) \
1615 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1616 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1617 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1618
1619#define CONDFCL(fop, cop, mask, flags) \
1620 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1621 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1622 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1623
1624#define CONDF(fop, mask, flags) \
1625 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1626 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1627
1628CONDFC ("fb", "cb", 0x8, F_UNBR),
f930d07e
BS		 1629CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
1630CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
aa0aa4fa 1631CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
f930d07e 1632CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
aa0aa4fa 1633CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
f930d07e 1634CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
aa0aa4fa
FB		 1635CONDFC ("fble", "cb01", 0xd, F_CONDBR),
1636CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
f930d07e 1637CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
aa0aa4fa
FB		 1638CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
1639CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
f930d07e
BS		 1640CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
1641CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
aa0aa4fa
FB		 1642CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
1643CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
1644CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
1645CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
1646CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
1647
1648#undef CONDFC
1649#undef CONDFCL
1650#undef CONDF
1651#undef CBR
1652#undef FBR
f930d07e 1653#undef FBRX /* v9 */
aa0aa4fa 1654
f930d07e
BS		 1655{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1656{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1657{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1658{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1659{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1660{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
aa0aa4fa 1661
f930d07e 1662{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
aa0aa4fa 1663
f930d07e
BS		 1664{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1665{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1666{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1667{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
aa0aa4fa 1668
f930d07e 1669{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
aa0aa4fa 1670
f930d07e
BS		 1671{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1672{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },
1673{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 },
1674{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1675{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 },
1676{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1677
f930d07e
BS		 1678{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1679{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 },
1680{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1681{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 },
aa0aa4fa 1682
f930d07e
BS		 1683{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1684{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
aa0aa4fa
FB		 1685
1686/* This *is* a commutative instruction. */
f930d07e
BS		 1687{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1688{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 },
1689{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1690/* This *is* a commutative instruction. */
f930d07e
BS		 1691{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1692{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 },
1693{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 },
1694{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1695{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 },
1696{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 },
1697{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1698{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 },
1699{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 },
1700
1701{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1702{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1703
1704{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1705{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
aa0aa4fa
FB		 1706
1707/* FPop1 and FPop2 are not instructions. Don't accept them. */
1708
f930d07e
BS		 1709{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1710{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1711{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1712
1713{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },
1714{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },
1715{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 },
1716
1717{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1718{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1719{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1720
1721{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },
1722{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },
1723{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 },
1724
1725{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1726{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1727{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1728{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1729{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1730{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
1731
1732{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1733{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1734{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1735{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1736{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1737{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1738{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1739{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
1740
1741{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1742{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1743{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
1744
1745{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1746{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1747{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1748{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1749
1750{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1751{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1752{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1753{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1754{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1755{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1756{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1757{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1758{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1759{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1760{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1761{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
1762
1763{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1764{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1765{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1766{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1767{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1768{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1769{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1770{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
1771
1772#define CMPFCC(x) (((x)&0x3)<<25)
1773
1774{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 },
1775{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 },
1776{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 },
1777{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 },
1778{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 },
1779{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 },
1780{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 },
1781{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 },
1782{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 },
1783{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 },
1784{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 },
1785{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 },
1786{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 },
1787{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 },
1788{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 },
1789{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 },
1790{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 },
1791{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 },
1792{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 },
1793{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 },
1794{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1795{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1796{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1797{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1798{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1799{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1800{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1801{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1802{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1803{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1804{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 },
1805{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 },
1806{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 },
1807{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 },
1808{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 },
1809{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 },
1810{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 },
1811{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 },
1812{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 },
1813{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 },
aa0aa4fa
FB		 1814
1815/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1816 MB86934, replacing the CPop instructions from v6 and later
1817 processors. */
1818
1819#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1820#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
1821#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
1822
f930d07e
BS		 1823EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1824EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1825EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1826EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1827EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1828EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1829EFPOP1_2 ("efmovs", 0x001, "f,g"),
1830EFPOP1_2 ("efnegs", 0x005, "f,g"),
1831EFPOP1_2 ("efabss", 0x009, "f,g"),
1832EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1833EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1834EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1835EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1836EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1837EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1838EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1839EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1840EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1841EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1842EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1843EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1844EFPOP2_2 ("efcmped", 0x056, "v,B"),
1845EFPOP2_2 ("efcmps", 0x051, "e,f"),
1846EFPOP2_2 ("efcmpes", 0x055, "e,f"),
aa0aa4fa
FB		 1847
1848#undef EFPOP1_2
1849#undef EFPOP1_3
1850#undef EFPOP2_2
1851
1852/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1853 present. Otherwise, the F_ALIAS flag is ignored. */
f930d07e
BS		 1854{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1855{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
aa0aa4fa
FB		 1856
1857/* sparclet specific insns */
1858
1859COMMUTEOP ("umac", 0x3e, sparclet),
1860COMMUTEOP ("smac", 0x3f, sparclet),
1861COMMUTEOP ("umacd", 0x2e, sparclet),
1862COMMUTEOP ("smacd", 0x2f, sparclet),
1863COMMUTEOP ("umuld", 0x09, sparclet),
1864COMMUTEOP ("smuld", 0x0d, sparclet),
1865
f930d07e
BS		 1866{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1867{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet },
aa0aa4fa
FB		 1868
1869/* The manual isn't completely accurate on these insns. The `rs2' field is
1870 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1871 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1872#define BIT5 (1<<5)
f930d07e
BS		 1873{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1874{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1875{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1876{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet },
1877{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1878{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet },
1879{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
aa0aa4fa
FB		 1880#undef BIT5
1881
1882/* sparclet coprocessor branch insns */
1883#define SLCBCC2(opcode, mask, lose) \
1884 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
1885 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1886#define SLCBCC(opcode, mask) \
1887 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1888
1889/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1890 requires all mnemonics of the same name to be consecutive. */
1891/*SLCBCC("cbn", 0), - already defined */
1892SLCBCC("cbe", 1),
1893SLCBCC("cbf", 2),
1894SLCBCC("cbef", 3),
1895SLCBCC("cbr", 4),
1896SLCBCC("cber", 5),
1897SLCBCC("cbfr", 6),
1898SLCBCC("cbefr", 7),
1899/*SLCBCC("cba", 8), - already defined */
1900SLCBCC("cbne", 9),
1901SLCBCC("cbnf", 10),
1902SLCBCC("cbnef", 11),
1903SLCBCC("cbnr", 12),
1904SLCBCC("cbner", 13),
1905SLCBCC("cbnfr", 14),
1906SLCBCC("cbnefr", 15),
1907
1908#undef SLCBCC2
1909#undef SLCBCC
1910
f930d07e
BS		 1911{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1912{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1913{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1914{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
aa0aa4fa
FB		 1915
1916/* v9 synthetic insns */
f930d07e
BS		 1917{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1918{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1919{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1920{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1921{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1922{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1923{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1924{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1925{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
aa0aa4fa
FB		 1926
1927/* Ultrasparc extensions */
f930d07e 1928{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
aa0aa4fa
FB		 1929
1930/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
f930d07e
BS		 1931{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1932{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1933{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1934{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1935{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1936{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1937{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1938{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
1939
1940{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1941{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1942{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1943{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1944{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
aa0aa4fa
FB		 1945
1946/* Note that the mixing of 32/64 bit regs is intentional. */
f930d07e
BS		 1947{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1948{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1949{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1950{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1951{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1952{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1953{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
1954
1955{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1956{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1957{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
1958
1959{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1960{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1961{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1962{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1963{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1964{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1965{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1966{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1967{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1968{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1969{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1970{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1971{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1972{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1973{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1974{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1975{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1976{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1977{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1978{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1979{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1980{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1981{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1982{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1983{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1984{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
1985{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
1986{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
1987{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
1988{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
1989{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
1990{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
1991
1992{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
1993{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
1994{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
1995{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
1996{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
1997{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
1998{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
1999{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
2000
2001{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
2002{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
2003{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
2004{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
2005{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
2006{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
2007
2008{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
2009
2010{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
2011{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
2012{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
aa0aa4fa
FB		 2013
2014/* Cheetah instructions */
2015{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
2016{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
2017{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
2018{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
2019{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
2020{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
2021
2022{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
2023{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
2024
2025{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
2026
2027/* More v9 specific insns, these need to come last so they do not clash
2028 with v9a instructions such as "edge8" which looks like impdep1. */
2029
2030#define IMPDEP(name, code) \
f930d07e
BS		 2031{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2032{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
aa0aa4fa
FB		 2033{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
2034{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
2035
2036IMPDEP ("impdep1", 0x36),
2037IMPDEP ("impdep2", 0x37),
2038
2039#undef IMPDEP
2040
2041};
2042
f82a3d48 2043static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
aa0aa4fa
FB		 2044\f
2045/* Utilities for argument parsing. */
2046
2047typedef struct
2048{
2049 int value;
2050 const char *name;
2051} arg;
2052
2053/* Look up NAME in TABLE. */
2054
aa0aa4fa
FB		 2055static const char *lookup_value PARAMS ((const arg *, int));
2056
aa0aa4fa
FB		 2057/* Look up VALUE in TABLE. */
2058
2059static const char *
2060lookup_value (table, value)
2061 const arg *table;
2062 int value;
2063{
2064 const arg *p;
2065
2066 for (p = table; p->name; ++p)
2067 if (value == p->value)
2068 return p->name;
2069
2070 return (char *) 0;
2071}
2072\f
2073/* Handle ASI's. */
2074
1983a395
FB		 2075static const arg asi_table_v8[] =
2076{
2077 { 0x00, "#ASI_M_RES00" },
2078 { 0x01, "#ASI_M_UNA01" },
2079 { 0x02, "#ASI_M_MXCC" },
2080 { 0x03, "#ASI_M_FLUSH_PROBE" },
2081 { 0x04, "#ASI_M_MMUREGS" },
2082 { 0x05, "#ASI_M_TLBDIAG" },
2083 { 0x06, "#ASI_M_DIAGS" },
2084 { 0x07, "#ASI_M_IODIAG" },
2085 { 0x08, "#ASI_M_USERTXT" },
2086 { 0x09, "#ASI_M_KERNELTXT" },
2087 { 0x0A, "#ASI_M_USERDATA" },
2088 { 0x0B, "#ASI_M_KERNELDATA" },
2089 { 0x0C, "#ASI_M_TXTC_TAG" },
2090 { 0x0D, "#ASI_M_TXTC_DATA" },
2091 { 0x0E, "#ASI_M_DATAC_TAG" },
2092 { 0x0F, "#ASI_M_DATAC_DATA" },
2093 { 0x10, "#ASI_M_FLUSH_PAGE" },
2094 { 0x11, "#ASI_M_FLUSH_SEG" },
2095 { 0x12, "#ASI_M_FLUSH_REGION" },
2096 { 0x13, "#ASI_M_FLUSH_CTX" },
2097 { 0x14, "#ASI_M_FLUSH_USER" },
2098 { 0x17, "#ASI_M_BCOPY" },
2099 { 0x18, "#ASI_M_IFLUSH_PAGE" },
2100 { 0x19, "#ASI_M_IFLUSH_SEG" },
2101 { 0x1A, "#ASI_M_IFLUSH_REGION" },
2102 { 0x1B, "#ASI_M_IFLUSH_CTX" },
2103 { 0x1C, "#ASI_M_IFLUSH_USER" },
2104 { 0x1F, "#ASI_M_BFILL" },
2105 { 0x20, "#ASI_M_BYPASS" },
2106 { 0x29, "#ASI_M_FBMEM" },
2107 { 0x2A, "#ASI_M_VMEUS" },
2108 { 0x2B, "#ASI_M_VMEPS" },
2109 { 0x2C, "#ASI_M_VMEUT" },
2110 { 0x2D, "#ASI_M_VMEPT" },
2111 { 0x2E, "#ASI_M_SBUS" },
2112 { 0x2F, "#ASI_M_CTL" },
2113 { 0x31, "#ASI_M_FLUSH_IWHOLE" },
2114 { 0x36, "#ASI_M_IC_FLCLEAR" },
2115 { 0x37, "#ASI_M_DC_FLCLEAR" },
2116 { 0x39, "#ASI_M_DCDR" },
2117 { 0x40, "#ASI_M_VIKING_TMP1" },
2118 { 0x41, "#ASI_M_VIKING_TMP2" },
2119 { 0x4c, "#ASI_M_ACTION" },
2120 { 0, 0 }
2121};
2122
2123static const arg asi_table_v9[] =
aa0aa4fa
FB		 2124{
2125 /* These are in the v9 architecture manual. */
2126 /* The shorter versions appear first, they're here because Sun's as has them.
2127 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2128 UltraSPARC architecture manual). */
2129 { 0x04, "#ASI_N" },
2130 { 0x0c, "#ASI_N_L" },
2131 { 0x10, "#ASI_AIUP" },
2132 { 0x11, "#ASI_AIUS" },
2133 { 0x18, "#ASI_AIUP_L" },
2134 { 0x19, "#ASI_AIUS_L" },
2135 { 0x80, "#ASI_P" },
2136 { 0x81, "#ASI_S" },
2137 { 0x82, "#ASI_PNF" },
2138 { 0x83, "#ASI_SNF" },
2139 { 0x88, "#ASI_P_L" },
2140 { 0x89, "#ASI_S_L" },
2141 { 0x8a, "#ASI_PNF_L" },
2142 { 0x8b, "#ASI_SNF_L" },
2143 { 0x04, "#ASI_NUCLEUS" },
2144 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2145 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2146 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2147 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2148 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2149 { 0x80, "#ASI_PRIMARY" },
2150 { 0x81, "#ASI_SECONDARY" },
2151 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2152 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2153 { 0x88, "#ASI_PRIMARY_LITTLE" },
2154 { 0x89, "#ASI_SECONDARY_LITTLE" },
2155 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2156 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2157 /* These are UltraSPARC extensions. */
2158 /* FIXME: There are dozens of them. Not sure we want them all.
2159 Most are for kernel building but some are for vis type stuff. */
2160 { 0, 0 }
2161};
2162
1983a395 2163/* Return the name for ASI value VALUE or NULL if not found. */
aa0aa4fa 2164
1983a395
FB		 2165static const char *
2166sparc_decode_asi_v9 (int value)
aa0aa4fa 2167{
1983a395 2168 return lookup_value (asi_table_v9, value);
aa0aa4fa
FB		 2169}
2170
1983a395
FB		 2171static const char *
2172sparc_decode_asi_v8 (int value)
aa0aa4fa 2173{
1983a395 2174 return lookup_value (asi_table_v8, value);
aa0aa4fa
FB		 2175}
2176\f
2177/* Handle membar masks. */
2178
d88bbf95 2179static const arg membar_table[] =
aa0aa4fa
FB		 2180{
2181 { 0x40, "#Sync" },
2182 { 0x20, "#MemIssue" },
2183 { 0x10, "#Lookaside" },
2184 { 0x08, "#StoreStore" },
2185 { 0x04, "#LoadStore" },
2186 { 0x02, "#StoreLoad" },
2187 { 0x01, "#LoadLoad" },
2188 { 0, 0 }
2189};
2190
aa0aa4fa
FB		 2191/* Return the name for membar value VALUE or NULL if not found. */
2192
b1d8e52e 2193static const char *
aa0aa4fa
FB		 2194sparc_decode_membar (value)
2195 int value;
2196{
2197 return lookup_value (membar_table, value);
2198}
2199\f
2200/* Handle prefetch args. */
2201
d88bbf95 2202static const arg prefetch_table[] =
aa0aa4fa
FB		 2203{
2204 { 0, "#n_reads" },
2205 { 1, "#one_read" },
2206 { 2, "#n_writes" },
2207 { 3, "#one_write" },
2208 { 4, "#page" },
2209 { 16, "#invalidate" },
2210 { 0, 0 }
2211};
2212
aa0aa4fa
FB		 2213/* Return the name for prefetch value VALUE or NULL if not found. */
2214
b1d8e52e 2215static const char *
aa0aa4fa
FB		 2216sparc_decode_prefetch (value)
2217 int value;
2218{
2219 return lookup_value (prefetch_table, value);
2220}
2221\f
2222/* Handle sparclet coprocessor registers. */
2223
d88bbf95 2224static const arg sparclet_cpreg_table[] =
aa0aa4fa
FB		 2225{
2226 { 0, "%ccsr" },
2227 { 1, "%ccfr" },
2228 { 2, "%cccrcr" },
2229 { 3, "%ccpr" },
2230 { 4, "%ccsr2" },
2231 { 5, "%cccrr" },
2232 { 6, "%ccrstr" },
2233 { 0, 0 }
2234};
2235
aa0aa4fa
FB		 2236/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2237
b1d8e52e 2238static const char *
aa0aa4fa
FB		 2239sparc_decode_sparclet_cpreg (value)
2240 int value;
2241{
2242 return lookup_value (sparclet_cpreg_table, value);
2243}
2244
2245#undef MASK_V9
2246
d4abd567
BS		 2247/* opcodes/sparc-dis.c */
2248
aa0aa4fa
FB		 2249/* Bitmask of v9 architectures. */
2250#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
f930d07e
BS		 2251 | (1 << SPARC_OPCODE_ARCH_V9A) \
2252 | (1 << SPARC_OPCODE_ARCH_V9B))
aa0aa4fa
FB		 2253/* 1 if INSN is for v9 only. */
2254#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2255/* 1 if INSN is for v9. */
2256#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2257
2258/* The sorted opcode table. */
2259static const struct sparc_opcode **sorted_opcodes;
2260
2261/* For faster lookup, after insns are sorted they are hashed. */
2262/* ??? I think there is room for even more improvement. */
2263
2264#define HASH_SIZE 256
2265/* It is important that we only look at insn code bits as that is how the
2266 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2267 of the main types (0,1,2,3). */
d88bbf95 2268static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
aa0aa4fa
FB		 2269#define HASH_INSN(INSN) \
2270 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
2271struct opcode_hash {
2272 struct opcode_hash *next;
2273 const struct sparc_opcode *opcode;
2274};
2275static struct opcode_hash *opcode_hash_table[HASH_SIZE];
2276
2277static void build_hash_table
2278 PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
2279static int is_delayed_branch PARAMS ((unsigned long));
2280static int compare_opcodes PARAMS ((const void *, const void *));
2281static int compute_arch_mask PARAMS ((unsigned long));
2282
2283/* Sign-extend a value which is N bits long. */
f930d07e
BS		 2284#define SEX(value, bits) \
2285 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2286 >> ((8 * sizeof (int)) - bits) )
aa0aa4fa 2287
d88bbf95 2288static const char * const reg_names[] =
5fafdf24
TS		 2289{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2290 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2291 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2292 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2293 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2294 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
aa0aa4fa
FB		 2295 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2296 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5fafdf24
TS		 2297 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
2298 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
aa0aa4fa
FB		 2299 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2300 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2301/* psr, wim, tbr, fpsr, cpsr are v8 only. */
2302 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2303};
2304
f930d07e 2305#define freg_names (&reg_names[4 * 8])
aa0aa4fa
FB		 2306
2307/* These are ordered according to there register number in
2308 rdpr and wrpr insns. */
d88bbf95 2309static const char * const v9_priv_reg_names[] =
aa0aa4fa
FB		 2310{
2311 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2312 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2313 "wstate", "fq"
2314 /* "ver" - special cased */
2315};
2316
2317/* These are ordered according to there register number in
2318 rd and wr insns (-16). */
d88bbf95 2319static const char * const v9a_asr_reg_names[] =
aa0aa4fa
FB		 2320{
2321 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2322 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
2323};
2324
2325/* Macros used to extract instruction fields. Not all fields have
2326 macros defined here, only those which are actually used. */
2327
2328#define X_RD(i) (((i) >> 25) & 0x1f)
2329#define X_RS1(i) (((i) >> 14) & 0x1f)
2330#define X_LDST_I(i) (((i) >> 13) & 1)
2331#define X_ASI(i) (((i) >> 5) & 0xff)
2332#define X_RS2(i) (((i) >> 0) & 0x1f)
2333#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2334#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
2335#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
2336#define X_IMM22(i) X_DISP22 (i)
2337#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
2338
2339/* These are for v9. */
2340#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2341#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
2342#define X_MEMBAR(i) ((i) & 0x7f)
2343
2344/* Here is the union which was used to extract instruction fields
2345 before the shift and mask macros were written.
2346
2347 union sparc_insn
2348 {
2349 unsigned long int code;
2350 struct
f930d07e
BS		 2351 {
2352 unsigned int anop:2;
2353 #define op ldst.anop
2354 unsigned int anrd:5;
2355 #define rd ldst.anrd
2356 unsigned int op3:6;
2357 unsigned int anrs1:5;
2358 #define rs1 ldst.anrs1
2359 unsigned int i:1;
2360 unsigned int anasi:8;
2361 #define asi ldst.anasi
2362 unsigned int anrs2:5;
2363 #define rs2 ldst.anrs2
2364 #define shcnt rs2
2365 } ldst;
aa0aa4fa 2366 struct
f930d07e
BS		 2367 {
2368 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
2369 unsigned int IMM13:13;
2370 #define imm13 IMM13.IMM13
2371 } IMM13;
aa0aa4fa 2372 struct
f930d07e
BS		 2373 {
2374 unsigned int anop:2;
2375 unsigned int a:1;
2376 unsigned int cond:4;
2377 unsigned int op2:3;
2378 unsigned int DISP22:22;
2379 #define disp22 branch.DISP22
2380 #define imm22 disp22
2381 } branch;
aa0aa4fa 2382 struct
f930d07e
BS		 2383 {
2384 unsigned int anop:2;
2385 unsigned int a:1;
2386 unsigned int z:1;
2387 unsigned int rcond:3;
2388 unsigned int op2:3;
2389 unsigned int DISP16HI:2;
2390 unsigned int p:1;
2391 unsigned int _rs1:5;
2392 unsigned int DISP16LO:14;
2393 } branch16;
aa0aa4fa 2394 struct
f930d07e
BS		 2395 {
2396 unsigned int anop:2;
2397 unsigned int adisp30:30;
2398 #define disp30 call.adisp30
2399 } call;
aa0aa4fa
FB		 2400 };
2401
2402 */
2403
2404/* Nonzero if INSN is the opcode for a delayed branch. */
2405static int
2406is_delayed_branch (insn)
2407 unsigned long insn;
2408{
2409 struct opcode_hash *op;
2410
2411 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2412 {
2413 const struct sparc_opcode *opcode = op->opcode;
2414 if ((opcode->match & insn) == opcode->match
f930d07e
BS		 2415 && (opcode->lose & insn) == 0)
2416 return (opcode->flags & F_DELAYED);
aa0aa4fa
FB		 2417 }
2418 return 0;
2419}
2420
2421/* extern void qsort (); */
2422
2423/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
2424 to compare_opcodes. */
2425static unsigned int current_arch_mask;
2426
2427/* Print one instruction from MEMADDR on INFO->STREAM.
2428
2429 We suffix the instruction with a comment that gives the absolute
2430 address involved, as well as its symbolic form, if the instruction
2431 is preceded by a findable `sethi' and it either adds an immediate
2432 displacement to that register, or it is an `add' or `or' instruction
2433 on that register. */
2434
2435int
2436print_insn_sparc (memaddr, info)
2437 bfd_vma memaddr;
2438 disassemble_info *info;
2439{
2440 FILE *stream = info->stream;
2441 bfd_byte buffer[4];
2442 unsigned long insn;
2443 register struct opcode_hash *op;
2444 /* Nonzero of opcode table has been initialized. */
2445 static int opcodes_initialized = 0;
2446 /* bfd mach number of last call. */
2447 static unsigned long current_mach = 0;
2448 bfd_vma (*getword) PARAMS ((const unsigned char *));
2449
2450 if (!opcodes_initialized
2451 || info->mach != current_mach)
2452 {
2453 int i;
2454
2455 current_arch_mask = compute_arch_mask (info->mach);
2456
2457 if (!opcodes_initialized)
f930d07e 2458 sorted_opcodes = (const struct sparc_opcode **)
aa0aa4fa
FB		 2459 malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
2460 /* Reset the sorted table so we can resort it. */
2461 for (i = 0; i < sparc_num_opcodes; ++i)
f930d07e 2462 sorted_opcodes[i] = &sparc_opcodes[i];
aa0aa4fa 2463 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
f930d07e 2464 sizeof (sorted_opcodes[0]), compare_opcodes);
aa0aa4fa
FB		 2465
2466 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
2467 current_mach = info->mach;
2468 opcodes_initialized = 1;
2469 }
2470
2471 {
2472 int status =
2473 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
2474 if (status != 0)
2475 {
f930d07e
BS		 2476 (*info->memory_error_func) (status, memaddr, info);
2477 return -1;
aa0aa4fa
FB		 2478 }
2479 }
2480
2481 /* On SPARClite variants such as DANlite (sparc86x), instructions
2482 are always big-endian even when the machine is in little-endian mode. */
2483 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
2484 getword = bfd_getb32;
2485 else
2486 getword = bfd_getl32;
2487
2488 insn = getword (buffer);
2489
f930d07e
BS		 2490 info->insn_info_valid = 1; /* We do return this info */
2491 info->insn_type = dis_nonbranch; /* Assume non branch insn */
2492 info->branch_delay_insns = 0; /* Assume no delay */
2493 info->target = 0; /* Assume no target known */
aa0aa4fa
FB		 2494
2495 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2496 {
2497 const struct sparc_opcode *opcode = op->opcode;
2498
2499 /* If the insn isn't supported by the current architecture, skip it. */
2500 if (! (opcode->architecture & current_arch_mask))
f930d07e 2501 continue;
aa0aa4fa
FB		 2502
2503 if ((opcode->match & insn) == opcode->match
f930d07e
BS		 2504 && (opcode->lose & insn) == 0)
2505 {
2506 /* Nonzero means that we have found an instruction which has
2507 the effect of adding or or'ing the imm13 field to rs1. */
2508 int imm_added_to_rs1 = 0;
2509 int imm_ored_to_rs1 = 0;
aa0aa4fa 2510
f930d07e
BS		 2511 /* Nonzero means that we have found a plus sign in the args
2512 field of the opcode table. */
2513 int found_plus = 0;
3b46e624 2514
f930d07e
BS		 2515 /* Nonzero means we have an annulled branch. */
2516 int is_annulled = 0;
aa0aa4fa 2517
f930d07e 2518 /* Do we have an `add' or `or' instruction combining an
aa0aa4fa 2519 immediate with rs1? */
f930d07e
BS		 2520 if (opcode->match == 0x80102000) /* or */
2521 imm_ored_to_rs1 = 1;
2522 if (opcode->match == 0x80002000) /* add */
2523 imm_added_to_rs1 = 1;
2524
2525 if (X_RS1 (insn) != X_RD (insn)
2526 && strchr (opcode->args, 'r') != 0)
2527 /* Can't do simple format if source and dest are different. */
2528 continue;
2529 if (X_RS2 (insn) != X_RD (insn)
2530 && strchr (opcode->args, 'O') != 0)
2531 /* Can't do simple format if source and dest are different. */
2532 continue;
2533
2534 (*info->fprintf_func) (stream, opcode->name);
2535
2536 {
2537 register const char *s;
2538
2539 if (opcode->args[0] != ',')
2540 (*info->fprintf_func) (stream, " ");
2541 for (s = opcode->args; *s != '\0'; ++s)
2542 {
2543 while (*s == ',')
2544 {
2545 (*info->fprintf_func) (stream, ",");
2546 ++s;
2547 switch (*s) {
2548 case 'a':
2549 (*info->fprintf_func) (stream, "a");
2550 is_annulled = 1;
2551 ++s;
2552 continue;
2553 case 'N':
2554 (*info->fprintf_func) (stream, "pn");
2555 ++s;
2556 continue;
2557
2558 case 'T':
2559 (*info->fprintf_func) (stream, "pt");
2560 ++s;
2561 continue;
2562
2563 default:
2564 break;
2565 } /* switch on arg */
2566 } /* while there are comma started args */
2567
2568 (*info->fprintf_func) (stream, " ");
2569
2570 switch (*s)
2571 {
2572 case '+':
2573 found_plus = 1;
2574
2575 /* note fall-through */
2576 default:
2577 (*info->fprintf_func) (stream, "%c", *s);
2578 break;
2579
2580 case '#':
2581 (*info->fprintf_func) (stream, "0");
2582 break;
2583
2584#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
2585 case '1':
2586 case 'r':
2587 reg (X_RS1 (insn));
2588 break;
2589
2590 case '2':
2591 case 'O':
2592 reg (X_RS2 (insn));
2593 break;
2594
2595 case 'd':
2596 reg (X_RD (insn));
2597 break;
2598#undef reg
2599
2600#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
2601#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
2602 case 'e':
2603 freg (X_RS1 (insn));
2604 break;
2605 case 'v': /* double/even */
2606 case 'V': /* quad/multiple of 4 */
2607 fregx (X_RS1 (insn));
2608 break;
2609
2610 case 'f':
2611 freg (X_RS2 (insn));
2612 break;
2613 case 'B': /* double/even */
2614 case 'R': /* quad/multiple of 4 */
2615 fregx (X_RS2 (insn));
2616 break;
2617
2618 case 'g':
2619 freg (X_RD (insn));
2620 break;
2621 case 'H': /* double/even */
2622 case 'J': /* quad/multiple of 4 */
2623 fregx (X_RD (insn));
2624 break;
2625#undef freg
2626#undef fregx
2627
2628#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
2629 case 'b':
2630 creg (X_RS1 (insn));
2631 break;
2632
2633 case 'c':
2634 creg (X_RS2 (insn));
2635 break;
2636
2637 case 'D':
2638 creg (X_RD (insn));
2639 break;
2640#undef creg
2641
2642 case 'h':
2643 (*info->fprintf_func) (stream, "%%hi(%#x)",
2644 ((unsigned) 0xFFFFFFFF
2645 & ((int) X_IMM22 (insn) << 10)));
2646 break;
2647
2648 case 'i': /* 13 bit immediate */
2649 case 'I': /* 11 bit immediate */
2650 case 'j': /* 10 bit immediate */
2651 {
2652 int imm;
2653
2654 if (*s == 'i')
2655 imm = X_SIMM (insn, 13);
2656 else if (*s == 'I')
2657 imm = X_SIMM (insn, 11);
2658 else
2659 imm = X_SIMM (insn, 10);
2660
2661 /* Check to see whether we have a 1+i, and take
2662 note of that fact.
2663
2664 Note: because of the way we sort the table,
2665 we will be matching 1+i rather than i+1,
2666 so it is OK to assume that i is after +,
2667 not before it. */
2668 if (found_plus)
2669 imm_added_to_rs1 = 1;
2670
2671 if (imm <= 9)
2672 (*info->fprintf_func) (stream, "%d", imm);
2673 else
2674 (*info->fprintf_func) (stream, "%#x", imm);
2675 }
2676 break;
2677
2678 case 'X': /* 5 bit unsigned immediate */
2679 case 'Y': /* 6 bit unsigned immediate */
2680 {
2681 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
2682
2683 if (imm <= 9)
2684 (info->fprintf_func) (stream, "%d", imm);
2685 else
2686 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
2687 }
2688 break;
2689
2690 case '3':
2691 (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
2692 break;
2693
2694 case 'K':
2695 {
2696 int mask = X_MEMBAR (insn);
2697 int bit = 0x40, printed_one = 0;
2698 const char *name;
2699
2700 if (mask == 0)
2701 (info->fprintf_func) (stream, "0");
2702 else
2703 while (bit)
2704 {
2705 if (mask & bit)
2706 {
2707 if (printed_one)
2708 (info->fprintf_func) (stream, "|");
2709 name = sparc_decode_membar (bit);
2710 (info->fprintf_func) (stream, "%s", name);
2711 printed_one = 1;
2712 }
2713 bit >>= 1;
2714 }
2715 break;
2716 }
2717
2718 case 'k':
2719 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
2720 (*info->print_address_func) (info->target, info);
2721 break;
2722
2723 case 'G':
2724 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
2725 (*info->print_address_func) (info->target, info);
2726 break;
2727
2728 case '6':
2729 case '7':
2730 case '8':
2731 case '9':
2732 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
2733 break;
2734
2735 case 'z':
2736 (*info->fprintf_func) (stream, "%%icc");
2737 break;
2738
2739 case 'Z':
2740 (*info->fprintf_func) (stream, "%%xcc");
2741 break;
2742
2743 case 'E':
2744 (*info->fprintf_func) (stream, "%%ccr");
2745 break;
2746
2747 case 's':
2748 (*info->fprintf_func) (stream, "%%fprs");
2749 break;
2750
2751 case 'o':
2752 (*info->fprintf_func) (stream, "%%asi");
2753 break;
2754
2755 case 'W':
2756 (*info->fprintf_func) (stream, "%%tick");
2757 break;
2758
2759 case 'P':
2760 (*info->fprintf_func) (stream, "%%pc");
2761 break;
2762
2763 case '?':
2764 if (X_RS1 (insn) == 31)
2765 (*info->fprintf_func) (stream, "%%ver");
2766 else if ((unsigned) X_RS1 (insn) < 16)
2767 (*info->fprintf_func) (stream, "%%%s",
2768 v9_priv_reg_names[X_RS1 (insn)]);
2769 else
2770 (*info->fprintf_func) (stream, "%%reserved");
2771 break;
2772
2773 case '!':
2774 if ((unsigned) X_RD (insn) < 15)
2775 (*info->fprintf_func) (stream, "%%%s",
2776 v9_priv_reg_names[X_RD (insn)]);
2777 else
2778 (*info->fprintf_func) (stream, "%%reserved");
2779 break;
2780
2781 case '/':
2782 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
2783 (*info->fprintf_func) (stream, "%%reserved");
2784 else
2785 (*info->fprintf_func) (stream, "%%%s",
2786 v9a_asr_reg_names[X_RS1 (insn)-16]);
2787 break;
2788
2789 case '_':
2790 if (X_RD (insn) < 16 || X_RD (insn) > 25)
2791 (*info->fprintf_func) (stream, "%%reserved");
2792 else
2793 (*info->fprintf_func) (stream, "%%%s",
2794 v9a_asr_reg_names[X_RD (insn)-16]);
2795 break;
2796
2797 case '*':
2798 {
2799 const char *name = sparc_decode_prefetch (X_RD (insn));
2800
2801 if (name)
2802 (*info->fprintf_func) (stream, "%s", name);
2803 else
2804 (*info->fprintf_func) (stream, "%d", X_RD (insn));
2805 break;
2806 }
2807
2808 case 'M':
2809 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
2810 break;
2811
2812 case 'm':
2813 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
2814 break;
2815
2816 case 'L':
2817 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
2818 (*info->print_address_func) (info->target, info);
2819 break;
2820
2821 case 'n':
2822 (*info->fprintf_func)
2823 (stream, "%#x", SEX (X_DISP22 (insn), 22));
2824 break;
2825
2826 case 'l':
2827 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
2828 (*info->print_address_func) (info->target, info);
2829 break;
2830
2831 case 'A':
2832 {
2833 const char *name;
2834
2835 if ((info->mach == bfd_mach_sparc_v8plusa) ||
725cb90b
FB		 2836 ((info->mach >= bfd_mach_sparc_v9) &&
2837 (info->mach <= bfd_mach_sparc_v9b)))
f930d07e
BS		 2838 name = sparc_decode_asi_v9 (X_ASI (insn));
2839 else
2840 name = sparc_decode_asi_v8 (X_ASI (insn));
2841
2842 if (name)
2843 (*info->fprintf_func) (stream, "%s", name);
2844 else
2845 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
2846 break;
2847 }
2848
2849 case 'C':
2850 (*info->fprintf_func) (stream, "%%csr");
2851 break;
2852
2853 case 'F':
2854 (*info->fprintf_func) (stream, "%%fsr");
2855 break;
2856
2857 case 'p':
2858 (*info->fprintf_func) (stream, "%%psr");
2859 break;
2860
2861 case 'q':
2862 (*info->fprintf_func) (stream, "%%fq");
2863 break;
2864
2865 case 'Q':
2866 (*info->fprintf_func) (stream, "%%cq");
2867 break;
2868
2869 case 't':
2870 (*info->fprintf_func) (stream, "%%tbr");
2871 break;
2872
2873 case 'w':
2874 (*info->fprintf_func) (stream, "%%wim");
2875 break;
2876
2877 case 'x':
2878 (*info->fprintf_func) (stream, "%d",
2879 ((X_LDST_I (insn) << 8)
2880 + X_ASI (insn)));
2881 break;
2882
2883 case 'y':
2884 (*info->fprintf_func) (stream, "%%y");
2885 break;
2886
2887 case 'u':
2888 case 'U':
2889 {
2890 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
2891 const char *name = sparc_decode_sparclet_cpreg (val);
2892
2893 if (name)
2894 (*info->fprintf_func) (stream, "%s", name);
2895 else
2896 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
2897 break;
2898 }
2899 }
2900 }
2901 }
2902
2903 /* If we are adding or or'ing something to rs1, then
2904 check to see whether the previous instruction was
2905 a sethi to the same register as in the sethi.
2906 If so, attempt to print the result of the add or
2907 or (in this context add and or do the same thing)
2908 and its symbolic value. */
2909 if (imm_ored_to_rs1 || imm_added_to_rs1)
2910 {
2911 unsigned long prev_insn;
2912 int errcode;
2913
2914 errcode =
2915 (*info->read_memory_func)
2916 (memaddr - 4, buffer, sizeof (buffer), info);
2917 prev_insn = getword (buffer);
2918
2919 if (errcode == 0)
2920 {
2921 /* If it is a delayed branch, we need to look at the
2922 instruction before the delayed branch. This handles
2923 sequences such as
2924
2925 sethi %o1, %hi(_foo), %o1
2926 call _printf
2927 or %o1, %lo(_foo), %o1
2928 */
2929
2930 if (is_delayed_branch (prev_insn))
2931 {
2932 errcode = (*info->read_memory_func)
2933 (memaddr - 8, buffer, sizeof (buffer), info);
2934 prev_insn = getword (buffer);
2935 }
2936 }
2937
2938 /* If there was a problem reading memory, then assume
2939 the previous instruction was not sethi. */
2940 if (errcode == 0)
2941 {
2942 /* Is it sethi to the same register? */
2943 if ((prev_insn & 0xc1c00000) == 0x01000000
2944 && X_RD (prev_insn) == X_RS1 (insn))
2945 {
2946 (*info->fprintf_func) (stream, "\t! ");
2947 info->target =
2948 ((unsigned) 0xFFFFFFFF
2949 & ((int) X_IMM22 (prev_insn) << 10));
2950 if (imm_added_to_rs1)
2951 info->target += X_SIMM (insn, 13);
2952 else
2953 info->target |= X_SIMM (insn, 13);
2954 (*info->print_address_func) (info->target, info);
2955 info->insn_type = dis_dref;
2956 info->data_size = 4; /* FIXME!!! */
2957 }
2958 }
2959 }
2960
2961 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
2962 {
2963 /* FIXME -- check is_annulled flag */
2964 if (opcode->flags & F_UNBR)
2965 info->insn_type = dis_branch;
2966 if (opcode->flags & F_CONDBR)
2967 info->insn_type = dis_condbranch;
2968 if (opcode->flags & F_JSR)
2969 info->insn_type = dis_jsr;
2970 if (opcode->flags & F_DELAYED)
2971 info->branch_delay_insns = 1;
2972 }
2973
2974 return sizeof (buffer);
2975 }
aa0aa4fa
FB		 2976 }
2977
f930d07e 2978 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
aa0aa4fa
FB		 2979 (*info->fprintf_func) (stream, _("unknown"));
2980 return sizeof (buffer);
2981}
2982
2983/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
2984
2985static int
2986compute_arch_mask (mach)
2987 unsigned long mach;
2988{
2989 switch (mach)
2990 {
2991 case 0 :
2992 case bfd_mach_sparc :
2993 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
2994 case bfd_mach_sparc_sparclet :
2995 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
2996 case bfd_mach_sparc_sparclite :
2997 case bfd_mach_sparc_sparclite_le :
2998 /* sparclites insns are recognized by default (because that's how
f930d07e
BS		 2999 they've always been treated, for better or worse). Kludge this by
3000 indicating generic v8 is also selected. */
aa0aa4fa 3001 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
f930d07e 3002 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
aa0aa4fa
FB		 3003 case bfd_mach_sparc_v8plus :
3004 case bfd_mach_sparc_v9 :
3005 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
3006 case bfd_mach_sparc_v8plusa :
3007 case bfd_mach_sparc_v9a :
3008 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
3009 case bfd_mach_sparc_v8plusb :
3010 case bfd_mach_sparc_v9b :
3011 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
3012 }
3013 abort ();
3014}
3015
3016/* Compare opcodes A and B. */
3017
3018static int
3019compare_opcodes (const void *a, const void *b)
3020{
3021 struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
3022 struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
3023 unsigned long int match0 = op0->match, match1 = op1->match;
3024 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
3025 register unsigned int i;
3026
3027 /* If one (and only one) insn isn't supported by the current architecture,
3028 prefer the one that is. If neither are supported, but they're both for
3029 the same architecture, continue processing. Otherwise (both unsupported
3030 and for different architectures), prefer lower numbered arch's (fudged
3031 by comparing the bitmasks). */
3032 if (op0->architecture & current_arch_mask)
3033 {
3034 if (! (op1->architecture & current_arch_mask))
f930d07e 3035 return -1;
aa0aa4fa
FB		 3036 }
3037 else
3038 {
3039 if (op1->architecture & current_arch_mask)
f930d07e 3040 return 1;
aa0aa4fa 3041 else if (op0->architecture != op1->architecture)
f930d07e 3042 return op0->architecture - op1->architecture;
aa0aa4fa
FB		 3043 }
3044
3045 /* If a bit is set in both match and lose, there is something
3046 wrong with the opcode table. */
3047 if (match0 & lose0)
3048 {
3049 fprintf
f930d07e
BS		 3050 (stderr,
3051 /* xgettext:c-format */
3052 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3053 op0->name, match0, lose0);
aa0aa4fa
FB		 3054 op0->lose &= ~op0->match;
3055 lose0 = op0->lose;
3056 }
3057
3058 if (match1 & lose1)
3059 {
3060 fprintf
f930d07e
BS		 3061 (stderr,
3062 /* xgettext:c-format */
3063 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3064 op1->name, match1, lose1);
aa0aa4fa
FB		 3065 op1->lose &= ~op1->match;
3066 lose1 = op1->lose;
3067 }
3068
3069 /* Because the bits that are variable in one opcode are constant in
3070 another, it is important to order the opcodes in the right order. */
3071 for (i = 0; i < 32; ++i)
3072 {
3073 unsigned long int x = 1 << i;
3074 int x0 = (match0 & x) != 0;
3075 int x1 = (match1 & x) != 0;
3076
3077 if (x0 != x1)
f930d07e 3078 return x1 - x0;
aa0aa4fa
FB		 3079 }
3080
3081 for (i = 0; i < 32; ++i)
3082 {
3083 unsigned long int x = 1 << i;
3084 int x0 = (lose0 & x) != 0;
3085 int x1 = (lose1 & x) != 0;
3086
3087 if (x0 != x1)
f930d07e 3088 return x1 - x0;
aa0aa4fa
FB		 3089 }
3090
3091 /* They are functionally equal. So as long as the opcode table is
3092 valid, we can put whichever one first we want, on aesthetic grounds. */
3093
3094 /* Our first aesthetic ground is that aliases defer to real insns. */
3095 {
3096 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
3097 if (alias_diff != 0)
3098 /* Put the one that isn't an alias first. */
3099 return alias_diff;
3100 }
3101
3102 /* Except for aliases, two "identical" instructions had
3103 better have the same opcode. This is a sanity check on the table. */
3104 i = strcmp (op0->name, op1->name);
3105 if (i)
3106 {
3107 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
f930d07e 3108 return i;
aa0aa4fa 3109 else
f930d07e
BS		 3110 fprintf (stderr,
3111 /* xgettext:c-format */
3112 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
3113 op0->name, op1->name);
aa0aa4fa
FB		 3114 }
3115
3116 /* Fewer arguments are preferred. */
3117 {
3118 int length_diff = strlen (op0->args) - strlen (op1->args);
3119 if (length_diff != 0)
3120 /* Put the one with fewer arguments first. */
3121 return length_diff;
3122 }
3123
3124 /* Put 1+i before i+1. */
3125 {
3126 char *p0 = (char *) strchr (op0->args, '+');
3127 char *p1 = (char *) strchr (op1->args, '+');
3128
3129 if (p0 && p1)
3130 {
f930d07e
BS		 3131 /* There is a plus in both operands. Note that a plus
3132 sign cannot be the first character in args,
3133 so the following [-1]'s are valid. */
3134 if (p0[-1] == 'i' && p1[1] == 'i')
3135 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
3136 return 1;
3137 if (p0[1] == 'i' && p1[-1] == 'i')
3138 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
3139 return -1;
aa0aa4fa
FB		 3140 }
3141 }
3142
3143 /* Put 1,i before i,1. */
3144 {
3145 int i0 = strncmp (op0->args, "i,1", 3) == 0;
3146 int i1 = strncmp (op1->args, "i,1", 3) == 0;
3147
3148 if (i0 ^ i1)
3149 return i0 - i1;
3150 }
3151
3152 /* They are, as far as we can tell, identical.
3153 Since qsort may have rearranged the table partially, there is
3154 no way to tell which one was first in the opcode table as
3155 written, so just say there are equal. */
3156 /* ??? This is no longer true now that we sort a vector of pointers,
3157 not the table itself. */
3158 return 0;
3159}
3160
3161/* Build a hash table from the opcode table.
3162 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
3163
3164static void
3165build_hash_table (opcode_table, hash_table, num_opcodes)
3166 const struct sparc_opcode **opcode_table;
3167 struct opcode_hash **hash_table;
3168 int num_opcodes;
3169{
3170 register int i;
3171 int hash_count[HASH_SIZE];
3172 static struct opcode_hash *hash_buf = NULL;
3173
3174 /* Start at the end of the table and work backwards so that each
3175 chain is sorted. */
3176
3177 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
3178 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
3179 if (hash_buf != NULL)
3180 free (hash_buf);
3181 hash_buf = (struct opcode_hash *) malloc (sizeof (struct opcode_hash) * num_opcodes);
3182 for (i = num_opcodes - 1; i >= 0; --i)
3183 {
3184 register int hash = HASH_INSN (opcode_table[i]->match);
3185 register struct opcode_hash *h = &hash_buf[i];
3186 h->next = hash_table[hash];
3187 h->opcode = opcode_table[i];
3188 hash_table[hash] = h;
3189 ++hash_count[hash];
3190 }
3191
3192#if 0 /* for debugging */
3193 {
3194 int min_count = num_opcodes, max_count = 0;
3195 int total;
3196
3197 for (i = 0; i < HASH_SIZE; ++i)
3198 {
3199 if (hash_count[i] < min_count)
f930d07e
BS		 3200 min_count = hash_count[i];
3201 if (hash_count[i] > max_count)
3202 max_count = hash_count[i];
3203 total += hash_count[i];
aa0aa4fa
FB		 3204 }
3205
3206 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
f930d07e 3207 min_count, max_count, (double) total / HASH_SIZE);
aa0aa4fa
FB		 3208 }
3209#endif
3210}
Qemu copy for testing