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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
cd617484 | 10 | #include "qemu/log.h" |
194cbc49 | 11 | #include "trace.h" |
b5ff1b31 | 12 | #include "cpu.h" |
ccd38087 | 13 | #include "internals.h" |
2ef6175a | 14 | #include "exec/helper-proto.h" |
db725815 | 15 | #include "qemu/main-loop.h" |
b8012ecf | 16 | #include "qemu/timer.h" |
1de7afc9 | 17 | #include "qemu/bitops.h" |
eb0ecd5a | 18 | #include "qemu/crc32c.h" |
0442428a | 19 | #include "qemu/qemu-print.h" |
63c91552 | 20 | #include "exec/exec-all.h" |
eb0ecd5a | 21 | #include <zlib.h> /* For crc32 */ |
64552b6b | 22 | #include "hw/irq.h" |
740b1759 | 23 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 24 | #include "sysemu/kvm.h" |
0c1aaa66 | 25 | #include "sysemu/tcg.h" |
de390645 RH |
26 | #include "qapi/error.h" |
27 | #include "qemu/guest-random.h" | |
91f78c58 | 28 | #ifdef CONFIG_TCG |
6b5fe137 | 29 | #include "semihosting/common-semi.h" |
91f78c58 | 30 | #endif |
cf7c6d10 | 31 | #include "cpregs.h" |
0b03bdfc | 32 | |
352c98e5 LV |
33 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
34 | ||
affdb64d PM |
35 | static void switch_mode(CPUARMState *env, int mode); |
36 | ||
c4241c7d | 37 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 38 | { |
375421cc | 39 | assert(ri->fieldoffset); |
67ed771d | 40 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 41 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 42 | } else { |
c4241c7d | 43 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 44 | } |
d4e6df63 PM |
45 | } |
46 | ||
f43ee493 | 47 | void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
d4e6df63 | 48 | { |
375421cc | 49 | assert(ri->fieldoffset); |
67ed771d | 50 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
51 | CPREG_FIELD64(env, ri) = value; |
52 | } else { | |
53 | CPREG_FIELD32(env, ri) = value; | |
54 | } | |
d4e6df63 PM |
55 | } |
56 | ||
11f136ee FA |
57 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
58 | { | |
59 | return (char *)env + ri->fieldoffset; | |
60 | } | |
61 | ||
49a66191 | 62 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 63 | { |
59a1c327 | 64 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 65 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 66 | return ri->resetvalue; |
721fae12 | 67 | } else if (ri->raw_readfn) { |
59a1c327 | 68 | return ri->raw_readfn(env, ri); |
721fae12 | 69 | } else if (ri->readfn) { |
59a1c327 | 70 | return ri->readfn(env, ri); |
721fae12 | 71 | } else { |
59a1c327 | 72 | return raw_read(env, ri); |
721fae12 | 73 | } |
721fae12 PM |
74 | } |
75 | ||
59a1c327 | 76 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 77 | uint64_t v) |
721fae12 | 78 | { |
9b37a28c FR |
79 | /* |
80 | * Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
81 | * Note that constant registers are treated as write-ignored; the |
82 | * caller should check for success by whether a readback gives the | |
83 | * value written. | |
84 | */ | |
85 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 86 | return; |
721fae12 | 87 | } else if (ri->raw_writefn) { |
c4241c7d | 88 | ri->raw_writefn(env, ri, v); |
721fae12 | 89 | } else if (ri->writefn) { |
c4241c7d | 90 | ri->writefn(env, ri, v); |
721fae12 | 91 | } else { |
afb2530f | 92 | raw_write(env, ri, v); |
721fae12 | 93 | } |
721fae12 PM |
94 | } |
95 | ||
375421cc PM |
96 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
97 | { | |
9b37a28c FR |
98 | /* |
99 | * Return true if the regdef would cause an assertion if you called | |
375421cc PM |
100 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a |
101 | * program bug for it not to have the NO_RAW flag). | |
102 | * NB that returning false here doesn't necessarily mean that calling | |
103 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
104 | * read/write access functions which are safe for raw use" from "has | |
105 | * read/write access functions which have side effects but has forgotten | |
106 | * to provide raw access functions". | |
107 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
108 | * and assertions in raw_read()/raw_write(). | |
109 | */ | |
110 | if ((ri->type & ARM_CP_CONST) || | |
111 | ri->fieldoffset || | |
112 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
113 | return false; | |
114 | } | |
115 | return true; | |
116 | } | |
117 | ||
b698e4ee | 118 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
119 | { |
120 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
121 | int i; | |
122 | bool ok = true; | |
123 | ||
124 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
125 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
126 | const ARMCPRegInfo *ri; | |
b698e4ee | 127 | uint64_t newval; |
59a1c327 | 128 | |
60322b39 | 129 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
130 | if (!ri) { |
131 | ok = false; | |
132 | continue; | |
133 | } | |
7a0e58fa | 134 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
135 | continue; |
136 | } | |
b698e4ee PM |
137 | |
138 | newval = read_raw_cp_reg(&cpu->env, ri); | |
139 | if (kvm_sync) { | |
140 | /* | |
141 | * Only sync if the previous list->cpustate sync succeeded. | |
142 | * Rather than tracking the success/failure state for every | |
143 | * item in the list, we just recheck "does the raw write we must | |
144 | * have made in write_list_to_cpustate() read back OK" here. | |
145 | */ | |
146 | uint64_t oldval = cpu->cpreg_values[i]; | |
147 | ||
148 | if (oldval == newval) { | |
149 | continue; | |
150 | } | |
151 | ||
152 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
153 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
154 | continue; | |
155 | } | |
156 | ||
157 | write_raw_cp_reg(&cpu->env, ri, newval); | |
158 | } | |
159 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
160 | } |
161 | return ok; | |
162 | } | |
163 | ||
164 | bool write_list_to_cpustate(ARMCPU *cpu) | |
165 | { | |
166 | int i; | |
167 | bool ok = true; | |
168 | ||
169 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
170 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
171 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
172 | const ARMCPRegInfo *ri; |
173 | ||
60322b39 | 174 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
175 | if (!ri) { |
176 | ok = false; | |
177 | continue; | |
178 | } | |
7a0e58fa | 179 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
180 | continue; |
181 | } | |
9b37a28c FR |
182 | /* |
183 | * Write value and confirm it reads back as written | |
721fae12 PM |
184 | * (to catch read-only registers and partially read-only |
185 | * registers where the incoming migration value doesn't match) | |
186 | */ | |
59a1c327 PM |
187 | write_raw_cp_reg(&cpu->env, ri, v); |
188 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
189 | ok = false; |
190 | } | |
191 | } | |
192 | return ok; | |
193 | } | |
194 | ||
195 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
196 | { | |
197 | ARMCPU *cpu = opaque; | |
5860362d RH |
198 | uint32_t regidx = (uintptr_t)key; |
199 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | |
721fae12 | 200 | |
04215eb1 | 201 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
202 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
203 | /* The value array need not be initialized at this point */ | |
204 | cpu->cpreg_array_len++; | |
205 | } | |
206 | } | |
207 | ||
208 | static void count_cpreg(gpointer key, gpointer opaque) | |
209 | { | |
210 | ARMCPU *cpu = opaque; | |
721fae12 PM |
211 | const ARMCPRegInfo *ri; |
212 | ||
5860362d | 213 | ri = g_hash_table_lookup(cpu->cp_regs, key); |
721fae12 | 214 | |
04215eb1 | 215 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
216 | cpu->cpreg_array_len++; |
217 | } | |
218 | } | |
219 | ||
220 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
221 | { | |
5860362d RH |
222 | uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); |
223 | uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | |
721fae12 | 224 | |
cbf239b7 AR |
225 | if (aidx > bidx) { |
226 | return 1; | |
227 | } | |
228 | if (aidx < bidx) { | |
229 | return -1; | |
230 | } | |
231 | return 0; | |
721fae12 PM |
232 | } |
233 | ||
234 | void init_cpreg_list(ARMCPU *cpu) | |
235 | { | |
9b37a28c FR |
236 | /* |
237 | * Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
721fae12 PM |
238 | * Note that we require cpreg_tuples[] to be sorted by key ID. |
239 | */ | |
57b6d95e | 240 | GList *keys; |
721fae12 PM |
241 | int arraylen; |
242 | ||
57b6d95e | 243 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
244 | keys = g_list_sort(keys, cpreg_key_compare); |
245 | ||
246 | cpu->cpreg_array_len = 0; | |
247 | ||
248 | g_list_foreach(keys, count_cpreg, cpu); | |
249 | ||
250 | arraylen = cpu->cpreg_array_len; | |
251 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
252 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
253 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
254 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
255 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
256 | cpu->cpreg_array_len = 0; | |
257 | ||
258 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
259 | ||
260 | assert(cpu->cpreg_array_len == arraylen); | |
261 | ||
262 | g_list_free(keys); | |
263 | } | |
264 | ||
68e9c2fe | 265 | /* |
93dd1e61 | 266 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
267 | */ |
268 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
269 | const ARMCPRegInfo *ri, |
270 | bool isread) | |
68e9c2fe | 271 | { |
93dd1e61 EI |
272 | if (!is_a64(env) && arm_current_el(env) == 3 && |
273 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
274 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
275 | } | |
276 | return CP_ACCESS_OK; | |
277 | } | |
278 | ||
9b37a28c FR |
279 | /* |
280 | * Some secure-only AArch32 registers trap to EL3 if used from | |
5513c3ab PM |
281 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). |
282 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
283 | * We assume that the .access field is set to PL1_RW. | |
284 | */ | |
285 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
286 | const ARMCPRegInfo *ri, |
287 | bool isread) | |
5513c3ab PM |
288 | { |
289 | if (arm_current_el(env) == 3) { | |
290 | return CP_ACCESS_OK; | |
291 | } | |
292 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
293 | if (env->cp15.scr_el3 & SCR_EEL2) { |
294 | return CP_ACCESS_TRAP_EL2; | |
295 | } | |
5513c3ab PM |
296 | return CP_ACCESS_TRAP_EL3; |
297 | } | |
298 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
299 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
300 | } | |
301 | ||
9b37a28c FR |
302 | /* |
303 | * Check for traps to performance monitor registers, which are controlled | |
1fce1ba9 PM |
304 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. |
305 | */ | |
306 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
307 | bool isread) | |
308 | { | |
309 | int el = arm_current_el(env); | |
59dd089c | 310 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 311 | |
59dd089c | 312 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
313 | return CP_ACCESS_TRAP_EL2; |
314 | } | |
315 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
316 | return CP_ACCESS_TRAP_EL3; | |
317 | } | |
318 | return CP_ACCESS_OK; | |
319 | } | |
320 | ||
84929218 | 321 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
6d482423 RH |
322 | CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
323 | bool isread) | |
84929218 RH |
324 | { |
325 | if (arm_current_el(env) == 1) { | |
326 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
327 | if (arm_hcr_el2_eff(env) & trap) { | |
328 | return CP_ACCESS_TRAP_EL2; | |
329 | } | |
330 | } | |
331 | return CP_ACCESS_OK; | |
332 | } | |
333 | ||
1803d271 RH |
334 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
335 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
336 | bool isread) | |
337 | { | |
338 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
339 | return CP_ACCESS_TRAP_EL2; | |
340 | } | |
341 | return CP_ACCESS_OK; | |
342 | } | |
343 | ||
99602377 RH |
344 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
345 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
346 | bool isread) | |
347 | { | |
348 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
349 | return CP_ACCESS_TRAP_EL2; | |
350 | } | |
351 | return CP_ACCESS_OK; | |
352 | } | |
353 | ||
30881b73 RH |
354 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
355 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
356 | bool isread) | |
357 | { | |
358 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
359 | return CP_ACCESS_TRAP_EL2; | |
360 | } | |
361 | return CP_ACCESS_OK; | |
362 | } | |
363 | ||
0f66d223 PM |
364 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ |
365 | static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, | |
366 | bool isread) | |
367 | { | |
368 | if (arm_current_el(env) == 1 && | |
369 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { | |
370 | return CP_ACCESS_TRAP_EL2; | |
371 | } | |
372 | return CP_ACCESS_OK; | |
373 | } | |
374 | ||
fe3ca86c PM |
375 | #ifdef TARGET_AARCH64 |
376 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ | |
377 | static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, | |
378 | bool isread) | |
379 | { | |
380 | if (arm_current_el(env) == 1 && | |
381 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) { | |
382 | return CP_ACCESS_TRAP_EL2; | |
383 | } | |
384 | return CP_ACCESS_OK; | |
385 | } | |
386 | #endif | |
387 | ||
c4241c7d | 388 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 389 | { |
2fc0cc0e | 390 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 391 | |
8d5c773e | 392 | raw_write(env, ri, value); |
d10eb08f | 393 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
394 | } |
395 | ||
c4241c7d | 396 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 397 | { |
2fc0cc0e | 398 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 399 | |
8d5c773e | 400 | if (raw_read(env, ri) != value) { |
9b37a28c FR |
401 | /* |
402 | * Unlike real hardware the qemu TLB uses virtual addresses, | |
08de207b PM |
403 | * not modified virtual addresses, so this causes a TLB flush. |
404 | */ | |
d10eb08f | 405 | tlb_flush(CPU(cpu)); |
8d5c773e | 406 | raw_write(env, ri, value); |
08de207b | 407 | } |
08de207b | 408 | } |
c4241c7d PM |
409 | |
410 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
411 | uint64_t value) | |
08de207b | 412 | { |
2fc0cc0e | 413 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 414 | |
452a0955 | 415 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 416 | && !extended_addresses_enabled(env)) { |
9b37a28c FR |
417 | /* |
418 | * For VMSA (when not using the LPAE long descriptor page table | |
08de207b PM |
419 | * format) this register includes the ASID, so do a TLB flush. |
420 | * For PMSA it is purely a process ID and no action is needed. | |
421 | */ | |
d10eb08f | 422 | tlb_flush(CPU(cpu)); |
08de207b | 423 | } |
8d5c773e | 424 | raw_write(env, ri, value); |
08de207b PM |
425 | } |
426 | ||
575a94af RH |
427 | static int alle1_tlbmask(CPUARMState *env) |
428 | { | |
429 | /* | |
430 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
431 | * stage 2 translations, whereas most other scopes only invalidate | |
432 | * stage 1 translations. | |
433 | */ | |
434 | return (ARMMMUIdxBit_E10_1 | | |
435 | ARMMMUIdxBit_E10_1_PAN | | |
436 | ARMMMUIdxBit_E10_0 | | |
437 | ARMMMUIdxBit_Stage2 | | |
438 | ARMMMUIdxBit_Stage2_S); | |
439 | } | |
440 | ||
441 | ||
b4ab8ce9 PM |
442 | /* IS variants of TLB operations must affect all cores */ |
443 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
444 | uint64_t value) | |
445 | { | |
29a0af61 | 446 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
447 | |
448 | tlb_flush_all_cpus_synced(cs); | |
449 | } | |
450 | ||
451 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
452 | uint64_t value) | |
453 | { | |
29a0af61 | 454 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
455 | |
456 | tlb_flush_all_cpus_synced(cs); | |
457 | } | |
458 | ||
459 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
460 | uint64_t value) | |
461 | { | |
29a0af61 | 462 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
463 | |
464 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
465 | } | |
466 | ||
467 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
468 | uint64_t value) | |
469 | { | |
29a0af61 | 470 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
471 | |
472 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
473 | } | |
474 | ||
475 | /* | |
476 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 477 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
478 | * force broadcast of these operations. |
479 | */ | |
480 | static bool tlb_force_broadcast(CPUARMState *env) | |
481 | { | |
373e7ffd | 482 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
483 | } |
484 | ||
c4241c7d PM |
485 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
486 | uint64_t value) | |
d929823f PM |
487 | { |
488 | /* Invalidate all (TLBIALL) */ | |
527db2be | 489 | CPUState *cs = env_cpu(env); |
00c8cb0a | 490 | |
b4ab8ce9 | 491 | if (tlb_force_broadcast(env)) { |
527db2be RH |
492 | tlb_flush_all_cpus_synced(cs); |
493 | } else { | |
494 | tlb_flush(cs); | |
b4ab8ce9 | 495 | } |
d929823f PM |
496 | } |
497 | ||
c4241c7d PM |
498 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
499 | uint64_t value) | |
d929823f PM |
500 | { |
501 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 502 | CPUState *cs = env_cpu(env); |
31b030d4 | 503 | |
527db2be | 504 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 505 | if (tlb_force_broadcast(env)) { |
527db2be RH |
506 | tlb_flush_page_all_cpus_synced(cs, value); |
507 | } else { | |
508 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 509 | } |
d929823f PM |
510 | } |
511 | ||
c4241c7d PM |
512 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
513 | uint64_t value) | |
d929823f PM |
514 | { |
515 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 516 | CPUState *cs = env_cpu(env); |
00c8cb0a | 517 | |
b4ab8ce9 | 518 | if (tlb_force_broadcast(env)) { |
527db2be RH |
519 | tlb_flush_all_cpus_synced(cs); |
520 | } else { | |
521 | tlb_flush(cs); | |
b4ab8ce9 | 522 | } |
d929823f PM |
523 | } |
524 | ||
c4241c7d PM |
525 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
526 | uint64_t value) | |
d929823f PM |
527 | { |
528 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 529 | CPUState *cs = env_cpu(env); |
31b030d4 | 530 | |
527db2be | 531 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 532 | if (tlb_force_broadcast(env)) { |
527db2be RH |
533 | tlb_flush_page_all_cpus_synced(cs, value); |
534 | } else { | |
535 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 536 | } |
fa439fc5 PM |
537 | } |
538 | ||
541ef8c2 SS |
539 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
540 | uint64_t value) | |
541 | { | |
29a0af61 | 542 | CPUState *cs = env_cpu(env); |
541ef8c2 | 543 | |
575a94af | 544 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
545 | } |
546 | ||
547 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
548 | uint64_t value) | |
549 | { | |
29a0af61 | 550 | CPUState *cs = env_cpu(env); |
541ef8c2 | 551 | |
575a94af | 552 | tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
553 | } |
554 | ||
541ef8c2 SS |
555 | |
556 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
557 | uint64_t value) | |
558 | { | |
29a0af61 | 559 | CPUState *cs = env_cpu(env); |
541ef8c2 | 560 | |
e013b741 | 561 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
562 | } |
563 | ||
564 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
565 | uint64_t value) | |
566 | { | |
29a0af61 | 567 | CPUState *cs = env_cpu(env); |
541ef8c2 | 568 | |
e013b741 | 569 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
570 | } |
571 | ||
572 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
573 | uint64_t value) | |
574 | { | |
29a0af61 | 575 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
576 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
577 | ||
e013b741 | 578 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
579 | } |
580 | ||
581 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
582 | uint64_t value) | |
583 | { | |
29a0af61 | 584 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
585 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
586 | ||
a67cf277 | 587 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 588 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
589 | } |
590 | ||
575a94af RH |
591 | static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, |
592 | uint64_t value) | |
593 | { | |
594 | CPUState *cs = env_cpu(env); | |
595 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
596 | ||
597 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
598 | } | |
599 | ||
600 | static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
601 | uint64_t value) | |
602 | { | |
603 | CPUState *cs = env_cpu(env); | |
604 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
605 | ||
606 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
607 | } | |
608 | ||
e9aa6c21 | 609 | static const ARMCPRegInfo cp_reginfo[] = { |
9b37a28c FR |
610 | /* |
611 | * Define the secure and non-secure FCSE identifier CP registers | |
54bf36ed FA |
612 | * separately because there is no secure bank in V8 (no _EL3). This allows |
613 | * the secure register to be properly reset and migrated. There is also no | |
614 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
615 | */ | |
9c513e78 | 616 | { .name = "FCSEIDR", |
54bf36ed FA |
617 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
618 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
619 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
620 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 621 | { .name = "FCSEIDR_S", |
54bf36ed FA |
622 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
623 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
624 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 625 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
9b37a28c FR |
626 | /* |
627 | * Define the secure and non-secure context identifier CP registers | |
54bf36ed FA |
628 | * separately because there is no secure bank in V8 (no _EL3). This allows |
629 | * the secure register to be properly reset and migrated. In the | |
630 | * non-secure case, the 32-bit register will have reset and migration | |
631 | * disabled during registration as it is handled by the 64-bit instance. | |
632 | */ | |
633 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 634 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 | 635 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 636 | .fgt = FGT_CONTEXTIDR_EL1, |
84929218 | 637 | .secure = ARM_CP_SECSTATE_NS, |
54bf36ed FA |
638 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
639 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 640 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 641 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
642 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
643 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 644 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 645 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
646 | }; |
647 | ||
648 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
9b37a28c FR |
649 | /* |
650 | * NB: Some of these registers exist in v8 but with more precise | |
9449fdf6 PM |
651 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). |
652 | */ | |
653 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
654 | { .name = "DACR", |
655 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 656 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
657 | .writefn = dacr_write, .raw_writefn = raw_write, |
658 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
659 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
9b37a28c FR |
660 | /* |
661 | * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. | |
a903c449 | 662 | * For v6 and v5, these mappings are overly broad. |
4fdd17dd | 663 | */ |
a903c449 EI |
664 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
665 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
666 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
667 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
668 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
669 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
670 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 671 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
672 | /* Cache maintenance ops; some of this space may be overridden later. */ |
673 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
674 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
675 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
676 | }; |
677 | ||
7d57f408 | 678 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
9b37a28c FR |
679 | /* |
680 | * Not all pre-v6 cores implemented this WFI, so this is slightly | |
7d57f408 PM |
681 | * over-broad. |
682 | */ | |
683 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
684 | .access = PL1_W, .type = ARM_CP_WFI }, | |
7d57f408 PM |
685 | }; |
686 | ||
687 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
9b37a28c FR |
688 | /* |
689 | * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
7d57f408 PM |
690 | * is UNPREDICTABLE; we choose to NOP as most implementations do). |
691 | */ | |
692 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
693 | .access = PL1_W, .type = ARM_CP_WFI }, | |
9b37a28c FR |
694 | /* |
695 | * L1 cache lockdown. Not architectural in v6 and earlier but in practice | |
34f90529 PM |
696 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and |
697 | * OMAPCP will override this space. | |
698 | */ | |
699 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
700 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
701 | .resetvalue = 0 }, | |
702 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
703 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
704 | .resetvalue = 0 }, | |
776d4e5c PM |
705 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
706 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 707 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 708 | .resetvalue = 0 }, |
9b37a28c FR |
709 | /* |
710 | * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; | |
50300698 PM |
711 | * implementing it as RAZ means the "debug architecture version" bits |
712 | * will read as a reserved value, which should cause Linux to not try | |
713 | * to use the debug hardware. | |
714 | */ | |
715 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
716 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9b37a28c FR |
717 | /* |
718 | * MMU TLB control. Note that the wildcarding means we cover not just | |
995939a6 PM |
719 | * the unified TLB ops but also the dside/iside/inner-shareable variants. |
720 | */ | |
721 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
722 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 723 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
724 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
725 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 726 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
727 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
728 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 729 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
730 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
731 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 732 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
733 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
734 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
735 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
736 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
737 | }; |
738 | ||
c4241c7d PM |
739 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
740 | uint64_t value) | |
2771db27 | 741 | { |
f0aff255 FA |
742 | uint32_t mask = 0; |
743 | ||
744 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
745 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
9b37a28c FR |
746 | /* |
747 | * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
f0aff255 FA |
748 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. |
749 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
750 | */ | |
7fbc6a40 | 751 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 | 752 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
fab8ad39 RH |
753 | mask |= R_CPACR_ASEDIS_MASK | |
754 | R_CPACR_D32DIS_MASK | | |
755 | R_CPACR_CP11_MASK | | |
756 | R_CPACR_CP10_MASK; | |
f0aff255 FA |
757 | |
758 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
759 | /* ASEDIS [31] bit is RAO/WI */ | |
fab8ad39 | 760 | value |= R_CPACR_ASEDIS_MASK; |
f0aff255 FA |
761 | } |
762 | ||
9b37a28c FR |
763 | /* |
764 | * VFPv3 and upwards with NEON implement 32 double precision | |
f0aff255 FA |
765 | * registers (D0-D31). |
766 | */ | |
a6627f5f | 767 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 | 768 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
fab8ad39 | 769 | value |= R_CPACR_D32DIS_MASK; |
f0aff255 FA |
770 | } |
771 | } | |
772 | value &= mask; | |
2771db27 | 773 | } |
fc1120a7 PM |
774 | |
775 | /* | |
776 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
777 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
778 | */ | |
779 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
780 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
781 | mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; |
782 | value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); | |
fc1120a7 PM |
783 | } |
784 | ||
7ebd5f2e | 785 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
786 | } |
787 | ||
fc1120a7 PM |
788 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
789 | { | |
790 | /* | |
791 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
792 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
793 | */ | |
794 | uint64_t value = env->cp15.cpacr_el1; | |
795 | ||
796 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
797 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 798 | value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); |
fc1120a7 PM |
799 | } |
800 | return value; | |
801 | } | |
802 | ||
803 | ||
5deac39c PM |
804 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
805 | { | |
9b37a28c FR |
806 | /* |
807 | * Call cpacr_write() so that we reset with the correct RAO bits set | |
5deac39c PM |
808 | * for our CPU features. |
809 | */ | |
810 | cpacr_write(env, ri, 0); | |
811 | } | |
812 | ||
3f208fd7 PM |
813 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
814 | bool isread) | |
c6f19164 GB |
815 | { |
816 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
817 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 | 818 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
fab8ad39 | 819 | FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { |
c6f19164 GB |
820 | return CP_ACCESS_TRAP_EL2; |
821 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
822 | } else if (arm_current_el(env) < 3 && | |
fab8ad39 | 823 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { |
c6f19164 GB |
824 | return CP_ACCESS_TRAP_EL3; |
825 | } | |
826 | } | |
827 | ||
828 | return CP_ACCESS_OK; | |
829 | } | |
830 | ||
3f208fd7 PM |
831 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
832 | bool isread) | |
c6f19164 GB |
833 | { |
834 | /* Check if CPTR accesses are set to trap to EL3 */ | |
fab8ad39 RH |
835 | if (arm_current_el(env) == 2 && |
836 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { | |
c6f19164 GB |
837 | return CP_ACCESS_TRAP_EL3; |
838 | } | |
839 | ||
840 | return CP_ACCESS_OK; | |
841 | } | |
842 | ||
7d57f408 PM |
843 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
844 | /* prefetch by MVA in v6, NOP in v7 */ | |
845 | { .name = "MVA_prefetch", | |
846 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
847 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
848 | /* |
849 | * We need to break the TB after ISB to execute self-modifying code | |
6df99dec SS |
850 | * correctly and also to take any pending interrupts immediately. |
851 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
852 | */ | |
7d57f408 | 853 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 854 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 855 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 856 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 857 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 858 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 859 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 860 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
861 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
862 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 | 863 | .resetvalue = 0, }, |
9b37a28c FR |
864 | /* |
865 | * Watchpoint Fault Address Register : should actually only be present | |
06d76f31 PM |
866 | * for 1136, 1176, 11MPCore. |
867 | */ | |
868 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
869 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 870 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 871 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
b19ed03c | 872 | .fgt = FGT_CPACR_EL1, |
7ebd5f2e | 873 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 874 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
875 | }; |
876 | ||
57a4a11b AL |
877 | typedef struct pm_event { |
878 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
879 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
880 | bool (*supported)(CPUARMState *); | |
881 | /* | |
882 | * Retrieve the current count of the underlying event. The programmed | |
883 | * counters hold a difference from the return value from this function | |
884 | */ | |
885 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
886 | /* |
887 | * Return how many nanoseconds it will take (at a minimum) for count events | |
888 | * to occur. A negative value indicates the counter will never overflow, or | |
889 | * that the counter has otherwise arranged for the overflow bit to be set | |
890 | * and the PMU interrupt to be raised on overflow. | |
891 | */ | |
892 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
893 | } pm_event; |
894 | ||
b2e23725 AL |
895 | static bool event_always_supported(CPUARMState *env) |
896 | { | |
897 | return true; | |
898 | } | |
899 | ||
0d4bfd7d AL |
900 | static uint64_t swinc_get_count(CPUARMState *env) |
901 | { | |
902 | /* | |
903 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
904 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
905 | */ | |
906 | return 0; | |
907 | } | |
908 | ||
4e7beb0c AL |
909 | static int64_t swinc_ns_per(uint64_t ignored) |
910 | { | |
911 | return -1; | |
912 | } | |
913 | ||
b2e23725 AL |
914 | /* |
915 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
916 | * usermode, simply return 0. | |
917 | */ | |
918 | static uint64_t cycles_get_count(CPUARMState *env) | |
919 | { | |
920 | #ifndef CONFIG_USER_ONLY | |
921 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
922 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
923 | #else | |
924 | return cpu_get_host_ticks(); | |
925 | #endif | |
926 | } | |
927 | ||
928 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
929 | static int64_t cycles_ns_per(uint64_t cycles) |
930 | { | |
931 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
932 | } | |
933 | ||
b2e23725 AL |
934 | static bool instructions_supported(CPUARMState *env) |
935 | { | |
740b1759 | 936 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
937 | } |
938 | ||
939 | static uint64_t instructions_get_count(CPUARMState *env) | |
940 | { | |
8191d368 | 941 | return (uint64_t)icount_get_raw(); |
b2e23725 | 942 | } |
4e7beb0c AL |
943 | |
944 | static int64_t instructions_ns_per(uint64_t icount) | |
945 | { | |
8191d368 | 946 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 947 | } |
b2e23725 AL |
948 | #endif |
949 | ||
a793bcd0 | 950 | static bool pmuv3p1_events_supported(CPUARMState *env) |
0727f63b PM |
951 | { |
952 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 953 | return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); |
0727f63b PM |
954 | } |
955 | ||
a793bcd0 | 956 | static bool pmuv3p4_events_supported(CPUARMState *env) |
15dd1ebd PM |
957 | { |
958 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 959 | return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); |
15dd1ebd PM |
960 | } |
961 | ||
0727f63b PM |
962 | static uint64_t zero_event_get_count(CPUARMState *env) |
963 | { | |
964 | /* For events which on QEMU never fire, so their count is always zero */ | |
965 | return 0; | |
966 | } | |
967 | ||
968 | static int64_t zero_event_ns_per(uint64_t cycles) | |
969 | { | |
970 | /* An event which never fires can never overflow */ | |
971 | return -1; | |
972 | } | |
973 | ||
57a4a11b | 974 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
975 | { .number = 0x000, /* SW_INCR */ |
976 | .supported = event_always_supported, | |
977 | .get_count = swinc_get_count, | |
4e7beb0c | 978 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 979 | }, |
b2e23725 AL |
980 | #ifndef CONFIG_USER_ONLY |
981 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
982 | .supported = instructions_supported, | |
983 | .get_count = instructions_get_count, | |
4e7beb0c | 984 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
985 | }, |
986 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
987 | .supported = event_always_supported, | |
988 | .get_count = cycles_get_count, | |
4e7beb0c | 989 | .ns_per_count = cycles_ns_per, |
0727f63b | 990 | }, |
b2e23725 | 991 | #endif |
0727f63b | 992 | { .number = 0x023, /* STALL_FRONTEND */ |
a793bcd0 | 993 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
994 | .get_count = zero_event_get_count, |
995 | .ns_per_count = zero_event_ns_per, | |
996 | }, | |
997 | { .number = 0x024, /* STALL_BACKEND */ | |
a793bcd0 | 998 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
999 | .get_count = zero_event_get_count, |
1000 | .ns_per_count = zero_event_ns_per, | |
1001 | }, | |
15dd1ebd | 1002 | { .number = 0x03c, /* STALL */ |
a793bcd0 | 1003 | .supported = pmuv3p4_events_supported, |
15dd1ebd PM |
1004 | .get_count = zero_event_get_count, |
1005 | .ns_per_count = zero_event_ns_per, | |
1006 | }, | |
57a4a11b AL |
1007 | }; |
1008 | ||
1009 | /* | |
1010 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1011 | * events (i.e. the statistical profiling extension), this implementation | |
1012 | * should first be updated to something sparse instead of the current | |
1013 | * supported_event_map[] array. | |
1014 | */ | |
15dd1ebd | 1015 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1016 | #define UNSUPPORTED_EVENT UINT16_MAX |
1017 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1018 | ||
1019 | /* | |
bf8d0969 AL |
1020 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1021 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1022 | * |
1023 | * Note: Events in the 0x40XX range are not currently supported. | |
1024 | */ | |
bf8d0969 | 1025 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1026 | { |
57a4a11b AL |
1027 | unsigned int i; |
1028 | ||
bf8d0969 AL |
1029 | /* |
1030 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1031 | * events to them | |
1032 | */ | |
57a4a11b AL |
1033 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1034 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1035 | } | |
bf8d0969 AL |
1036 | cpu->pmceid0 = 0; |
1037 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1038 | |
1039 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1040 | const pm_event *cnt = &pm_events[i]; | |
1041 | assert(cnt->number <= MAX_EVENT_ID); | |
1042 | /* We do not currently support events in the 0x40xx range */ | |
1043 | assert(cnt->number <= 0x3f); | |
1044 | ||
bf8d0969 | 1045 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1046 | supported_event_map[cnt->number] = i; |
67da43d6 | 1047 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1048 | if (cnt->number & 0x20) { |
1049 | cpu->pmceid1 |= event_mask; | |
1050 | } else { | |
1051 | cpu->pmceid0 |= event_mask; | |
1052 | } | |
57a4a11b AL |
1053 | } |
1054 | } | |
57a4a11b AL |
1055 | } |
1056 | ||
5ecdd3e4 AL |
1057 | /* |
1058 | * Check at runtime whether a PMU event is supported for the current machine | |
1059 | */ | |
1060 | static bool event_supported(uint16_t number) | |
1061 | { | |
1062 | if (number > MAX_EVENT_ID) { | |
1063 | return false; | |
1064 | } | |
1065 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1066 | } | |
1067 | ||
3f208fd7 PM |
1068 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1069 | bool isread) | |
200ac0ef | 1070 | { |
9b37a28c FR |
1071 | /* |
1072 | * Performance monitor registers user accessibility is controlled | |
1fce1ba9 PM |
1073 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1074 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1075 | */ |
1fce1ba9 | 1076 | int el = arm_current_el(env); |
59dd089c | 1077 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1078 | |
6ecd0b6b | 1079 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1080 | return CP_ACCESS_TRAP; |
200ac0ef | 1081 | } |
59dd089c | 1082 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1083 | return CP_ACCESS_TRAP_EL2; |
1084 | } | |
1085 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1086 | return CP_ACCESS_TRAP_EL3; | |
1087 | } | |
1088 | ||
fcd25206 | 1089 | return CP_ACCESS_OK; |
200ac0ef PM |
1090 | } |
1091 | ||
6ecd0b6b AB |
1092 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1093 | const ARMCPRegInfo *ri, | |
1094 | bool isread) | |
1095 | { | |
1096 | /* ER: event counter read trap control */ | |
1097 | if (arm_feature(env, ARM_FEATURE_V8) | |
1098 | && arm_current_el(env) == 0 | |
1099 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1100 | && isread) { | |
1101 | return CP_ACCESS_OK; | |
1102 | } | |
1103 | ||
1104 | return pmreg_access(env, ri, isread); | |
1105 | } | |
1106 | ||
1107 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1108 | const ARMCPRegInfo *ri, | |
1109 | bool isread) | |
1110 | { | |
1111 | /* SW: software increment write trap control */ | |
1112 | if (arm_feature(env, ARM_FEATURE_V8) | |
1113 | && arm_current_el(env) == 0 | |
1114 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1115 | && !isread) { | |
1116 | return CP_ACCESS_OK; | |
1117 | } | |
1118 | ||
1119 | return pmreg_access(env, ri, isread); | |
1120 | } | |
1121 | ||
6ecd0b6b AB |
1122 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1123 | const ARMCPRegInfo *ri, | |
1124 | bool isread) | |
1125 | { | |
1126 | /* ER: event counter read trap control */ | |
1127 | if (arm_feature(env, ARM_FEATURE_V8) | |
1128 | && arm_current_el(env) == 0 | |
1129 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1130 | return CP_ACCESS_OK; | |
1131 | } | |
1132 | ||
1133 | return pmreg_access(env, ri, isread); | |
1134 | } | |
1135 | ||
1136 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1137 | const ARMCPRegInfo *ri, | |
1138 | bool isread) | |
1139 | { | |
1140 | /* CR: cycle counter read trap control */ | |
1141 | if (arm_feature(env, ARM_FEATURE_V8) | |
1142 | && arm_current_el(env) == 0 | |
1143 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1144 | && isread) { | |
1145 | return CP_ACCESS_OK; | |
1146 | } | |
1147 | ||
1148 | return pmreg_access(env, ri, isread); | |
1149 | } | |
1150 | ||
01765386 PM |
1151 | /* |
1152 | * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. | |
1153 | * We use these to decide whether we need to wrap a write to MDCR_EL2 | |
1154 | * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. | |
1155 | */ | |
47b385da PM |
1156 | #define MDCR_EL2_PMU_ENABLE_BITS \ |
1157 | (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) | |
0b42f4fa | 1158 | #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) |
01765386 | 1159 | |
9b37a28c FR |
1160 | /* |
1161 | * Returns true if the counter (pass 31 for PMCCNTR) should count events using | |
033614c4 AL |
1162 | * the current EL, security state, and register configuration. |
1163 | */ | |
1164 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1165 | { |
033614c4 AL |
1166 | uint64_t filter; |
1167 | bool e, p, u, nsk, nsu, nsh, m; | |
872d2034 | 1168 | bool enabled, prohibited = false, filtered; |
033614c4 AL |
1169 | bool secure = arm_is_secure(env); |
1170 | int el = arm_current_el(env); | |
59dd089c RDC |
1171 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1172 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1173 | |
cbbb3041 AJ |
1174 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1175 | return false; | |
1176 | } | |
1177 | ||
033614c4 AL |
1178 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1179 | (counter < hpmn || counter == 31)) { | |
1180 | e = env->cp15.c9_pmcr & PMCRE; | |
1181 | } else { | |
59dd089c | 1182 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1183 | } |
033614c4 | 1184 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1185 | |
872d2034 PM |
1186 | /* Is event counting prohibited? */ |
1187 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1188 | prohibited = mdcr_el2 & MDCR_HPMD; | |
1189 | } | |
1190 | if (secure) { | |
1191 | prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); | |
033614c4 AL |
1192 | } |
1193 | ||
0b42f4fa PM |
1194 | if (counter == 31) { |
1195 | /* | |
1196 | * The cycle counter defaults to running. PMCR.DP says "disable | |
1197 | * the cycle counter when event counting is prohibited". | |
1198 | * Some MDCR bits disable the cycle counter specifically. | |
1199 | */ | |
1200 | prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; | |
1201 | if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1202 | if (secure) { | |
1203 | prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); | |
1204 | } | |
1205 | if (el == 2) { | |
1206 | prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); | |
1207 | } | |
1208 | } | |
033614c4 AL |
1209 | } |
1210 | ||
5ecdd3e4 AL |
1211 | if (counter == 31) { |
1212 | filter = env->cp15.pmccfiltr_el0; | |
1213 | } else { | |
1214 | filter = env->cp15.c14_pmevtyper[counter]; | |
1215 | } | |
033614c4 AL |
1216 | |
1217 | p = filter & PMXEVTYPER_P; | |
1218 | u = filter & PMXEVTYPER_U; | |
1219 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1220 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1221 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1222 | m = arm_el_is_aa64(env, 1) && | |
1223 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1224 | ||
1225 | if (el == 0) { | |
1226 | filtered = secure ? u : u != nsu; | |
1227 | } else if (el == 1) { | |
1228 | filtered = secure ? p : p != nsk; | |
1229 | } else if (el == 2) { | |
1230 | filtered = !nsh; | |
1231 | } else { /* EL3 */ | |
1232 | filtered = m != p; | |
1233 | } | |
1234 | ||
5ecdd3e4 AL |
1235 | if (counter != 31) { |
1236 | /* | |
1237 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1238 | * support | |
1239 | */ | |
1240 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1241 | if (!event_supported(event)) { | |
1242 | return false; | |
1243 | } | |
1244 | } | |
1245 | ||
033614c4 | 1246 | return enabled && !prohibited && !filtered; |
87124fde | 1247 | } |
033614c4 | 1248 | |
f4efb4b2 AL |
1249 | static void pmu_update_irq(CPUARMState *env) |
1250 | { | |
2fc0cc0e | 1251 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1252 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1253 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1254 | } | |
1255 | ||
b57aa7bd PM |
1256 | static bool pmccntr_clockdiv_enabled(CPUARMState *env) |
1257 | { | |
1258 | /* | |
1259 | * Return true if the clock divider is enabled and the cycle counter | |
1260 | * is supposed to tick only once every 64 clock cycles. This is | |
1261 | * controlled by PMCR.D, but if PMCR.LC is set to enable the long | |
1262 | * (64-bit) cycle counter PMCR.D has no effect. | |
1263 | */ | |
1264 | return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; | |
1265 | } | |
1266 | ||
47b385da PM |
1267 | static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) |
1268 | { | |
1269 | /* Return true if the specified event counter is configured to be 64 bit */ | |
1270 | ||
1271 | /* This isn't intended to be used with the cycle counter */ | |
1272 | assert(counter < 31); | |
1273 | ||
1274 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1275 | return false; | |
1276 | } | |
1277 | ||
1278 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
1279 | /* | |
1280 | * MDCR_EL2.HLP still applies even when EL2 is disabled in the | |
1281 | * current security state, so we don't use arm_mdcr_el2_eff() here. | |
1282 | */ | |
1283 | bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; | |
1284 | int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
1285 | ||
1286 | if (hpmn != 0 && counter >= hpmn) { | |
1287 | return hlp; | |
1288 | } | |
1289 | } | |
1290 | return env->cp15.c9_pmcr & PMCRLP; | |
1291 | } | |
1292 | ||
5d05b9d4 AL |
1293 | /* |
1294 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1295 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1296 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1297 | * not enabled at the time of the call. | |
1298 | */ | |
f2b2f53f | 1299 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1300 | { |
b2e23725 | 1301 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1302 | |
033614c4 | 1303 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 | 1304 | uint64_t eff_cycles = cycles; |
b57aa7bd | 1305 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1306 | eff_cycles /= 64; |
1307 | } | |
1308 | ||
f4efb4b2 AL |
1309 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1310 | ||
1311 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1312 | 1ull << 63 : 1ull << 31; | |
1313 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
76e25d41 | 1314 | env->cp15.c9_pmovsr |= (1ULL << 31); |
f4efb4b2 AL |
1315 | pmu_update_irq(env); |
1316 | } | |
1317 | ||
1318 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1319 | } |
5d05b9d4 AL |
1320 | env->cp15.c15_ccnt_delta = cycles; |
1321 | } | |
ec7b4ce4 | 1322 | |
5d05b9d4 AL |
1323 | /* |
1324 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1325 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1326 | * pmccntr_op_start. | |
1327 | */ | |
f2b2f53f | 1328 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1329 | { |
033614c4 | 1330 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1331 | #ifndef CONFIG_USER_ONLY |
1332 | /* Calculate when the counter will next overflow */ | |
1333 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1334 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1335 | remaining_cycles = (uint32_t)remaining_cycles; | |
1336 | } | |
1337 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1338 | ||
1339 | if (overflow_in > 0) { | |
f1dd2506 PM |
1340 | int64_t overflow_at; |
1341 | ||
1342 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1343 | overflow_in, &overflow_at)) { | |
1344 | ARMCPU *cpu = env_archcpu(env); | |
1345 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1346 | } | |
4e7beb0c AL |
1347 | } |
1348 | #endif | |
5d05b9d4 | 1349 | |
4e7beb0c | 1350 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
b57aa7bd | 1351 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1352 | prev_cycles /= 64; |
1353 | } | |
5d05b9d4 | 1354 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1355 | } |
1356 | } | |
1357 | ||
5ecdd3e4 AL |
1358 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1359 | { | |
1360 | ||
1361 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1362 | uint64_t count = 0; | |
1363 | if (event_supported(event)) { | |
1364 | uint16_t event_idx = supported_event_map[event]; | |
1365 | count = pm_events[event_idx].get_count(env); | |
1366 | } | |
1367 | ||
1368 | if (pmu_counter_enabled(env, counter)) { | |
47b385da PM |
1369 | uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1370 | uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? | |
1371 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1372 | |
47b385da | 1373 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { |
f4efb4b2 AL |
1374 | env->cp15.c9_pmovsr |= (1 << counter); |
1375 | pmu_update_irq(env); | |
1376 | } | |
1377 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1378 | } |
1379 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1380 | } | |
1381 | ||
1382 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1383 | { | |
1384 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1385 | #ifndef CONFIG_USER_ONLY |
1386 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1387 | uint16_t event_idx = supported_event_map[event]; | |
47b385da PM |
1388 | uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); |
1389 | int64_t overflow_in; | |
1390 | ||
1391 | if (!pmevcntr_is_64_bit(env, counter)) { | |
1392 | delta = (uint32_t)delta; | |
1393 | } | |
1394 | overflow_in = pm_events[event_idx].ns_per_count(delta); | |
4e7beb0c AL |
1395 | |
1396 | if (overflow_in > 0) { | |
f1dd2506 PM |
1397 | int64_t overflow_at; |
1398 | ||
1399 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1400 | overflow_in, &overflow_at)) { | |
1401 | ARMCPU *cpu = env_archcpu(env); | |
1402 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1403 | } | |
4e7beb0c AL |
1404 | } |
1405 | #endif | |
1406 | ||
5ecdd3e4 AL |
1407 | env->cp15.c14_pmevcntr_delta[counter] -= |
1408 | env->cp15.c14_pmevcntr[counter]; | |
1409 | } | |
1410 | } | |
1411 | ||
5d05b9d4 AL |
1412 | void pmu_op_start(CPUARMState *env) |
1413 | { | |
5ecdd3e4 | 1414 | unsigned int i; |
5d05b9d4 | 1415 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1416 | for (i = 0; i < pmu_num_counters(env); i++) { |
1417 | pmevcntr_op_start(env, i); | |
1418 | } | |
5d05b9d4 AL |
1419 | } |
1420 | ||
1421 | void pmu_op_finish(CPUARMState *env) | |
1422 | { | |
5ecdd3e4 | 1423 | unsigned int i; |
5d05b9d4 | 1424 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1425 | for (i = 0; i < pmu_num_counters(env); i++) { |
1426 | pmevcntr_op_finish(env, i); | |
1427 | } | |
5d05b9d4 AL |
1428 | } |
1429 | ||
033614c4 AL |
1430 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1431 | { | |
1432 | pmu_op_start(&cpu->env); | |
1433 | } | |
1434 | ||
1435 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1436 | { | |
1437 | pmu_op_finish(&cpu->env); | |
1438 | } | |
1439 | ||
4e7beb0c AL |
1440 | void arm_pmu_timer_cb(void *opaque) |
1441 | { | |
1442 | ARMCPU *cpu = opaque; | |
1443 | ||
1444 | /* | |
1445 | * Update all the counter values based on the current underlying counts, | |
1446 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1447 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1448 | * counter may expire. | |
1449 | */ | |
1450 | pmu_op_start(&cpu->env); | |
1451 | pmu_op_finish(&cpu->env); | |
1452 | } | |
1453 | ||
c4241c7d PM |
1454 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1455 | uint64_t value) | |
200ac0ef | 1456 | { |
5d05b9d4 | 1457 | pmu_op_start(env); |
7c2cb42b AF |
1458 | |
1459 | if (value & PMCRC) { | |
1460 | /* The counter has been reset */ | |
1461 | env->cp15.c15_ccnt = 0; | |
1462 | } | |
1463 | ||
5ecdd3e4 AL |
1464 | if (value & PMCRP) { |
1465 | unsigned int i; | |
1466 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1467 | env->cp15.c14_pmevcntr[i] = 0; | |
1468 | } | |
1469 | } | |
1470 | ||
9323e79f PM |
1471 | env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; |
1472 | env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); | |
7c2cb42b | 1473 | |
5d05b9d4 | 1474 | pmu_op_finish(env); |
7c2cb42b AF |
1475 | } |
1476 | ||
0d4bfd7d AL |
1477 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1478 | uint64_t value) | |
1479 | { | |
1480 | unsigned int i; | |
47b385da PM |
1481 | uint64_t overflow_mask, new_pmswinc; |
1482 | ||
0d4bfd7d AL |
1483 | for (i = 0; i < pmu_num_counters(env); i++) { |
1484 | /* Increment a counter's count iff: */ | |
1485 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1486 | /* counter is enabled and not filtered */ | |
1487 | pmu_counter_enabled(env, i) && | |
1488 | /* counter is SW_INCR */ | |
1489 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1490 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1491 | |
1492 | /* | |
1493 | * Detect if this write causes an overflow since we can't predict | |
1494 | * PMSWINC overflows like we can for other events | |
1495 | */ | |
47b385da PM |
1496 | new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; |
1497 | ||
1498 | overflow_mask = pmevcntr_is_64_bit(env, i) ? | |
1499 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1500 | |
47b385da | 1501 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { |
f4efb4b2 AL |
1502 | env->cp15.c9_pmovsr |= (1 << i); |
1503 | pmu_update_irq(env); | |
1504 | } | |
1505 | ||
1506 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1507 | ||
0d4bfd7d AL |
1508 | pmevcntr_op_finish(env, i); |
1509 | } | |
1510 | } | |
1511 | } | |
1512 | ||
7c2cb42b AF |
1513 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1514 | { | |
5d05b9d4 AL |
1515 | uint64_t ret; |
1516 | pmccntr_op_start(env); | |
1517 | ret = env->cp15.c15_ccnt; | |
1518 | pmccntr_op_finish(env); | |
1519 | return ret; | |
7c2cb42b AF |
1520 | } |
1521 | ||
6b040780 WH |
1522 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1523 | uint64_t value) | |
1524 | { | |
9b37a28c FR |
1525 | /* |
1526 | * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
6b040780 WH |
1527 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the |
1528 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1529 | * accessed. | |
1530 | */ | |
1531 | env->cp15.c9_pmselr = value & 0x1f; | |
1532 | } | |
1533 | ||
7c2cb42b AF |
1534 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1535 | uint64_t value) | |
1536 | { | |
5d05b9d4 AL |
1537 | pmccntr_op_start(env); |
1538 | env->cp15.c15_ccnt = value; | |
1539 | pmccntr_op_finish(env); | |
200ac0ef | 1540 | } |
421c7ebd PC |
1541 | |
1542 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1543 | uint64_t value) | |
1544 | { | |
1545 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1546 | ||
1547 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1548 | } | |
1549 | ||
0614601c AF |
1550 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1551 | uint64_t value) | |
1552 | { | |
5d05b9d4 | 1553 | pmccntr_op_start(env); |
4b8afa1f AL |
1554 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1555 | pmccntr_op_finish(env); | |
1556 | } | |
1557 | ||
1558 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1559 | uint64_t value) | |
1560 | { | |
1561 | pmccntr_op_start(env); | |
1562 | /* M is not accessible from AArch32 */ | |
1563 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1564 | (value & PMCCFILTR); | |
5d05b9d4 | 1565 | pmccntr_op_finish(env); |
0614601c AF |
1566 | } |
1567 | ||
4b8afa1f AL |
1568 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1569 | { | |
1570 | /* M is not visible in AArch32 */ | |
1571 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1572 | } | |
1573 | ||
c4241c7d | 1574 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1575 | uint64_t value) |
1576 | { | |
01765386 | 1577 | pmu_op_start(env); |
7ece99b1 | 1578 | value &= pmu_counter_mask(env); |
200ac0ef | 1579 | env->cp15.c9_pmcnten |= value; |
01765386 | 1580 | pmu_op_finish(env); |
200ac0ef PM |
1581 | } |
1582 | ||
c4241c7d PM |
1583 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1584 | uint64_t value) | |
200ac0ef | 1585 | { |
01765386 | 1586 | pmu_op_start(env); |
7ece99b1 | 1587 | value &= pmu_counter_mask(env); |
200ac0ef | 1588 | env->cp15.c9_pmcnten &= ~value; |
01765386 | 1589 | pmu_op_finish(env); |
200ac0ef PM |
1590 | } |
1591 | ||
c4241c7d PM |
1592 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1593 | uint64_t value) | |
200ac0ef | 1594 | { |
599b71e2 | 1595 | value &= pmu_counter_mask(env); |
200ac0ef | 1596 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1597 | pmu_update_irq(env); |
200ac0ef PM |
1598 | } |
1599 | ||
327dd510 AL |
1600 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1601 | uint64_t value) | |
1602 | { | |
1603 | value &= pmu_counter_mask(env); | |
1604 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1605 | pmu_update_irq(env); |
327dd510 AL |
1606 | } |
1607 | ||
5ecdd3e4 AL |
1608 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1609 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1610 | { |
5ecdd3e4 AL |
1611 | if (counter == 31) { |
1612 | pmccfiltr_write(env, ri, value); | |
1613 | } else if (counter < pmu_num_counters(env)) { | |
1614 | pmevcntr_op_start(env, counter); | |
1615 | ||
1616 | /* | |
1617 | * If this counter's event type is changing, store the current | |
1618 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1619 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1620 | * a delta. | |
1621 | */ | |
1622 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1623 | PMXEVTYPER_EVTCOUNT; | |
1624 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1625 | if (old_event != new_event) { | |
1626 | uint64_t count = 0; | |
1627 | if (event_supported(new_event)) { | |
1628 | uint16_t event_idx = supported_event_map[new_event]; | |
1629 | count = pm_events[event_idx].get_count(env); | |
1630 | } | |
1631 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1632 | } | |
1633 | ||
1634 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1635 | pmevcntr_op_finish(env, counter); | |
1636 | } | |
9b37a28c FR |
1637 | /* |
1638 | * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when | |
fdb86656 WH |
1639 | * PMSELR value is equal to or greater than the number of implemented |
1640 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1641 | */ | |
5ecdd3e4 AL |
1642 | } |
1643 | ||
1644 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1645 | const uint8_t counter) | |
1646 | { | |
1647 | if (counter == 31) { | |
1648 | return env->cp15.pmccfiltr_el0; | |
1649 | } else if (counter < pmu_num_counters(env)) { | |
1650 | return env->cp15.c14_pmevtyper[counter]; | |
1651 | } else { | |
1652 | /* | |
1653 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1654 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1655 | */ | |
1656 | return 0; | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1661 | uint64_t value) | |
1662 | { | |
1663 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1664 | pmevtyper_write(env, ri, value, counter); | |
1665 | } | |
1666 | ||
1667 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1668 | uint64_t value) | |
1669 | { | |
1670 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1671 | env->cp15.c14_pmevtyper[counter] = value; | |
1672 | ||
1673 | /* | |
1674 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1675 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1676 | * we're potentially updating the type of event here, the value written to | |
673d8215 | 1677 | * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a |
5ecdd3e4 AL |
1678 | * different counter type. Therefore, we need to set this value to the |
1679 | * current count for the counter type we're writing so that pmu_op_finish | |
1680 | * has the correct count for its calculation. | |
1681 | */ | |
1682 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1683 | if (event_supported(event)) { | |
1684 | uint16_t event_idx = supported_event_map[event]; | |
1685 | env->cp15.c14_pmevcntr_delta[counter] = | |
1686 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1687 | } |
1688 | } | |
1689 | ||
5ecdd3e4 AL |
1690 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1691 | { | |
1692 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1693 | return pmevtyper_read(env, ri, counter); | |
1694 | } | |
1695 | ||
1696 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1697 | uint64_t value) | |
1698 | { | |
1699 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1700 | } | |
1701 | ||
fdb86656 WH |
1702 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1703 | { | |
5ecdd3e4 AL |
1704 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1705 | } | |
1706 | ||
1707 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1708 | uint64_t value, uint8_t counter) | |
1709 | { | |
47b385da PM |
1710 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1711 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1712 | value &= MAKE_64BIT_MASK(0, 32); | |
1713 | } | |
5ecdd3e4 AL |
1714 | if (counter < pmu_num_counters(env)) { |
1715 | pmevcntr_op_start(env, counter); | |
1716 | env->cp15.c14_pmevcntr[counter] = value; | |
1717 | pmevcntr_op_finish(env, counter); | |
1718 | } | |
1719 | /* | |
1720 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1721 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1722 | */ |
5ecdd3e4 AL |
1723 | } |
1724 | ||
1725 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1726 | uint8_t counter) | |
1727 | { | |
1728 | if (counter < pmu_num_counters(env)) { | |
1729 | uint64_t ret; | |
1730 | pmevcntr_op_start(env, counter); | |
1731 | ret = env->cp15.c14_pmevcntr[counter]; | |
1732 | pmevcntr_op_finish(env, counter); | |
47b385da PM |
1733 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1734 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1735 | ret &= MAKE_64BIT_MASK(0, 32); | |
1736 | } | |
5ecdd3e4 | 1737 | return ret; |
fdb86656 | 1738 | } else { |
9b37a28c FR |
1739 | /* |
1740 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1741 | * are CONSTRAINED UNPREDICTABLE. | |
1742 | */ | |
fdb86656 WH |
1743 | return 0; |
1744 | } | |
200ac0ef PM |
1745 | } |
1746 | ||
5ecdd3e4 AL |
1747 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1748 | uint64_t value) | |
1749 | { | |
1750 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1751 | pmevcntr_write(env, ri, value, counter); | |
1752 | } | |
1753 | ||
1754 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1755 | { | |
1756 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1757 | return pmevcntr_read(env, ri, counter); | |
1758 | } | |
1759 | ||
1760 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1761 | uint64_t value) | |
1762 | { | |
1763 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1764 | assert(counter < pmu_num_counters(env)); | |
1765 | env->cp15.c14_pmevcntr[counter] = value; | |
1766 | pmevcntr_write(env, ri, value, counter); | |
1767 | } | |
1768 | ||
1769 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1770 | { | |
1771 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1772 | assert(counter < pmu_num_counters(env)); | |
1773 | return env->cp15.c14_pmevcntr[counter]; | |
1774 | } | |
1775 | ||
1776 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1777 | uint64_t value) | |
1778 | { | |
1779 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1780 | } | |
1781 | ||
1782 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1783 | { | |
1784 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1785 | } | |
1786 | ||
c4241c7d | 1787 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1788 | uint64_t value) |
1789 | { | |
6ecd0b6b AB |
1790 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1791 | env->cp15.c9_pmuserenr = value & 0xf; | |
1792 | } else { | |
1793 | env->cp15.c9_pmuserenr = value & 1; | |
1794 | } | |
200ac0ef PM |
1795 | } |
1796 | ||
c4241c7d PM |
1797 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1798 | uint64_t value) | |
200ac0ef PM |
1799 | { |
1800 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1801 | value &= pmu_counter_mask(env); |
200ac0ef | 1802 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1803 | pmu_update_irq(env); |
200ac0ef PM |
1804 | } |
1805 | ||
c4241c7d PM |
1806 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1807 | uint64_t value) | |
200ac0ef | 1808 | { |
7ece99b1 | 1809 | value &= pmu_counter_mask(env); |
200ac0ef | 1810 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1811 | pmu_update_irq(env); |
200ac0ef PM |
1812 | } |
1813 | ||
c4241c7d PM |
1814 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1815 | uint64_t value) | |
8641136c | 1816 | { |
9b37a28c FR |
1817 | /* |
1818 | * Note that even though the AArch64 view of this register has bits | |
a505d7fe PM |
1819 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the |
1820 | * architectural requirements for bits which are RES0 only in some | |
1821 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1822 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1823 | */ | |
855ea66d | 1824 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1825 | } |
1826 | ||
64e0e2de EI |
1827 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1828 | { | |
ea22747c | 1829 | /* Begin with base v8.0 state. */ |
06f2adcc | 1830 | uint64_t valid_mask = 0x3fff; |
2fc0cc0e | 1831 | ARMCPU *cpu = env_archcpu(env); |
d902ae75 | 1832 | uint64_t changed; |
ea22747c | 1833 | |
bfe43e3d RH |
1834 | /* |
1835 | * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always | |
1836 | * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. | |
1837 | * Instead, choose the format based on the mode of EL3. | |
1838 | */ | |
1839 | if (arm_el_is_aa64(env, 3)) { | |
1840 | value |= SCR_FW | SCR_AW; /* RES1 */ | |
1841 | valid_mask &= ~SCR_NET; /* RES0 */ | |
252e8c69 | 1842 | |
6bcbb07a RH |
1843 | if (!cpu_isar_feature(aa64_aa32_el1, cpu) && |
1844 | !cpu_isar_feature(aa64_aa32_el2, cpu)) { | |
1845 | value |= SCR_RW; /* RAO/WI */ | |
1846 | } | |
da3d8b13 RH |
1847 | if (cpu_isar_feature(aa64_ras, cpu)) { |
1848 | valid_mask |= SCR_TERR; | |
1849 | } | |
252e8c69 RH |
1850 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1851 | valid_mask |= SCR_TLOR; | |
1852 | } | |
1853 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1854 | valid_mask |= SCR_API | SCR_APK; | |
1855 | } | |
926c1b97 RDC |
1856 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1857 | valid_mask |= SCR_EEL2; | |
87bfbfe7 RH |
1858 | } else if (cpu_isar_feature(aa64_rme, cpu)) { |
1859 | /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ | |
1860 | value |= SCR_NS; | |
926c1b97 | 1861 | } |
8ddb300b RH |
1862 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1863 | valid_mask |= SCR_ATA; | |
1864 | } | |
7cb1e618 RH |
1865 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
1866 | valid_mask |= SCR_ENSCXT; | |
1867 | } | |
7ac61020 PM |
1868 | if (cpu_isar_feature(aa64_doublefault, cpu)) { |
1869 | valid_mask |= SCR_EASE | SCR_NMEA; | |
1870 | } | |
06f2adcc JF |
1871 | if (cpu_isar_feature(aa64_sme, cpu)) { |
1872 | valid_mask |= SCR_ENTP2; | |
1873 | } | |
08899b5c EI |
1874 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
1875 | valid_mask |= SCR_HXEN; | |
1876 | } | |
15126d9c PM |
1877 | if (cpu_isar_feature(aa64_fgt, cpu)) { |
1878 | valid_mask |= SCR_FGTEN; | |
1879 | } | |
aa3cc42c RH |
1880 | if (cpu_isar_feature(aa64_rme, cpu)) { |
1881 | valid_mask |= SCR_NSE | SCR_GPF; | |
1882 | } | |
ea22747c RH |
1883 | } else { |
1884 | valid_mask &= ~(SCR_RW | SCR_ST); | |
da3d8b13 RH |
1885 | if (cpu_isar_feature(aa32_ras, cpu)) { |
1886 | valid_mask |= SCR_TERR; | |
1887 | } | |
ea22747c | 1888 | } |
64e0e2de EI |
1889 | |
1890 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1891 | valid_mask &= ~SCR_HCE; | |
1892 | ||
9b37a28c FR |
1893 | /* |
1894 | * On ARMv7, SMD (or SCD as it is called in v7) is only | |
64e0e2de EI |
1895 | * supported if EL2 exists. The bit is UNK/SBZP when |
1896 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1897 | * when EL2 is unavailable. | |
4eb27640 | 1898 | * On ARMv8, this bit is always available. |
64e0e2de | 1899 | */ |
4eb27640 GB |
1900 | if (arm_feature(env, ARM_FEATURE_V7) && |
1901 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1902 | valid_mask &= ~SCR_SMD; |
1903 | } | |
1904 | } | |
1905 | ||
1906 | /* Clear all-context RES0 bits. */ | |
1907 | value &= valid_mask; | |
d902ae75 RH |
1908 | changed = env->cp15.scr_el3 ^ value; |
1909 | env->cp15.scr_el3 = value; | |
1910 | ||
1911 | /* | |
aa3cc42c | 1912 | * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, |
d902ae75 RH |
1913 | * we must invalidate all TLBs below EL3. |
1914 | */ | |
aa3cc42c | 1915 | if (changed & (SCR_NS | SCR_NSE)) { |
d902ae75 RH |
1916 | tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | |
1917 | ARMMMUIdxBit_E20_0 | | |
1918 | ARMMMUIdxBit_E10_1 | | |
1919 | ARMMMUIdxBit_E20_2 | | |
1920 | ARMMMUIdxBit_E10_1_PAN | | |
1921 | ARMMMUIdxBit_E20_2_PAN | | |
1922 | ARMMMUIdxBit_E2)); | |
1923 | } | |
64e0e2de EI |
1924 | } |
1925 | ||
10d0ef3e MN |
1926 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1927 | { | |
1928 | /* | |
1929 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1930 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1931 | */ | |
1932 | scr_write(env, ri, 0); | |
1933 | } | |
1934 | ||
e2ce5fcd PM |
1935 | static CPAccessResult access_tid4(CPUARMState *env, |
1936 | const ARMCPRegInfo *ri, | |
1937 | bool isread) | |
630fcd4d | 1938 | { |
e2ce5fcd PM |
1939 | if (arm_current_el(env) == 1 && |
1940 | (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { | |
630fcd4d MZ |
1941 | return CP_ACCESS_TRAP_EL2; |
1942 | } | |
1943 | ||
1944 | return CP_ACCESS_OK; | |
1945 | } | |
1946 | ||
c4241c7d | 1947 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1948 | { |
2fc0cc0e | 1949 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 | 1950 | |
9b37a28c FR |
1951 | /* |
1952 | * Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
b85a1fd6 FA |
1953 | * bank |
1954 | */ | |
1955 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1956 | ri->secure & ARM_CP_SECSTATE_S); | |
1957 | ||
1958 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1959 | } |
1960 | ||
c4241c7d PM |
1961 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1962 | uint64_t value) | |
776d4e5c | 1963 | { |
8d5c773e | 1964 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1965 | } |
1966 | ||
1090b9c6 PM |
1967 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1968 | { | |
29a0af61 | 1969 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1970 | bool el1 = arm_current_el(env) == 1; |
1971 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1972 | uint64_t ret = 0; |
1973 | ||
cc974d5c | 1974 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1975 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1976 | ret |= CPSR_I; | |
1977 | } | |
1978 | } else { | |
1979 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1980 | ret |= CPSR_I; | |
1981 | } | |
1090b9c6 | 1982 | } |
636540e9 | 1983 | |
cc974d5c | 1984 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1985 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1986 | ret |= CPSR_F; | |
1987 | } | |
1988 | } else { | |
1989 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1990 | ret |= CPSR_F; | |
1991 | } | |
1090b9c6 | 1992 | } |
636540e9 | 1993 | |
3c29632f RH |
1994 | if (hcr_el2 & HCR_AMO) { |
1995 | if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | |
1996 | ret |= CPSR_A; | |
1997 | } | |
1998 | } | |
1999 | ||
1090b9c6 PM |
2000 | return ret; |
2001 | } | |
2002 | ||
93fbc983 MZ |
2003 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
2004 | bool isread) | |
2005 | { | |
2006 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
2007 | return CP_ACCESS_TRAP_EL2; | |
2008 | } | |
2009 | ||
2010 | return CP_ACCESS_OK; | |
2011 | } | |
2012 | ||
2013 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
2014 | bool isread) | |
2015 | { | |
2016 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
2017 | return access_aa64_tid1(env, ri, isread); | |
2018 | } | |
2019 | ||
2020 | return CP_ACCESS_OK; | |
2021 | } | |
2022 | ||
e9aa6c21 | 2023 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
2024 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
2025 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
2026 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
2027 | /* |
2028 | * Performance monitors are implementation defined in v7, | |
200ac0ef | 2029 | * but with an ARM recommended set of registers, which we |
ac689a2e | 2030 | * follow. |
200ac0ef PM |
2031 | * |
2032 | * Performance registers fall into three categories: | |
2033 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
2034 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
2035 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
2036 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
2037 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
2038 | */ | |
2039 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7f4fbfb5 | 2040 | .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b | 2041 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
2042 | .writefn = pmcntenset_write, |
2043 | .accessfn = pmreg_access, | |
dc780233 | 2044 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2045 | .raw_writefn = raw_write }, |
7f4fbfb5 | 2046 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, |
8521466b AF |
2047 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, |
2048 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2049 | .fgt = FGT_PMCNTEN, |
8521466b AF |
2050 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, |
2051 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 2052 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
2053 | .access = PL0_RW, |
2054 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 | 2055 | .accessfn = pmreg_access, |
dc780233 | 2056 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2057 | .writefn = pmcntenclr_write, |
7f4fbfb5 | 2058 | .type = ARM_CP_ALIAS | ARM_CP_IO }, |
8521466b AF |
2059 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
2060 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
2061 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2062 | .fgt = FGT_PMCNTEN, |
7f4fbfb5 | 2063 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b AF |
2064 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
2065 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2066 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2067 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2068 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 | 2069 | .accessfn = pmreg_access, |
dc780233 | 2070 | .fgt = FGT_PMOVS, |
fcd25206 PM |
2071 | .writefn = pmovsr_write, |
2072 | .raw_writefn = raw_write }, | |
978364f1 AF |
2073 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2074 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2075 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2076 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2077 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2078 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2079 | .writefn = pmovsr_write, | |
2080 | .raw_writefn = raw_write }, | |
200ac0ef | 2081 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 | 2082 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2083 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2084 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d AL |
2085 | .writefn = pmswinc_write }, |
2086 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2087 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 | 2088 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2089 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2090 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d | 2091 | .writefn = pmswinc_write }, |
6b040780 WH |
2092 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2093 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
dc780233 | 2094 | .fgt = FGT_PMSELR_EL0, |
6b040780 | 2095 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), |
6ecd0b6b | 2096 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2097 | .raw_writefn = raw_write}, |
2098 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2099 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2100 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
dc780233 | 2101 | .fgt = FGT_PMSELR_EL0, |
6b040780 WH |
2102 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2103 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2104 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2105 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
dc780233 | 2106 | .fgt = FGT_PMCCNTR_EL0, |
421c7ebd | 2107 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2108 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2109 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2110 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2111 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
dc780233 | 2112 | .fgt = FGT_PMCCNTR_EL0, |
8521466b | 2113 | .type = ARM_CP_IO, |
980ebe87 AL |
2114 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2115 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2116 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2117 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2118 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2119 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2120 | .fgt = FGT_PMCCFILTR_EL0, |
4b8afa1f AL |
2121 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
2122 | .resetvalue = 0, }, | |
8521466b AF |
2123 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2124 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2125 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b | 2126 | .access = PL0_RW, .accessfn = pmreg_access, |
dc780233 | 2127 | .fgt = FGT_PMCCFILTR_EL0, |
8521466b AF |
2128 | .type = ARM_CP_IO, |
2129 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2130 | .resetvalue = 0, }, | |
200ac0ef | 2131 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2132 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2133 | .accessfn = pmreg_access, | |
dc780233 | 2134 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 WH |
2135 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2136 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2137 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2138 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2139 | .accessfn = pmreg_access, | |
dc780233 | 2140 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 | 2141 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2142 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2143 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2144 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2145 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 AL |
2146 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
2147 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2148 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2149 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2150 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2151 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 | 2152 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
200ac0ef | 2153 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2154 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2155 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2156 | .resetvalue = 0, |
d4e6df63 | 2157 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2158 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2159 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2160 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2161 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2162 | .resetvalue = 0, | |
2163 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2164 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2165 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2166 | .fgt = FGT_PMINTEN, |
b7d793ad | 2167 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2168 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2169 | .resetvalue = 0, |
d4e6df63 | 2170 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2171 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2172 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2173 | .access = PL1_RW, .accessfn = access_tpm, | |
dc780233 | 2174 | .fgt = FGT_PMINTEN, |
e6ec5457 WH |
2175 | .type = ARM_CP_IO, |
2176 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2177 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2178 | .resetvalue = 0x0 }, | |
200ac0ef | 2179 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2180 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2181 | .fgt = FGT_PMINTEN, |
887c0f15 | 2182 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2183 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2184 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2185 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2186 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2187 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2188 | .fgt = FGT_PMINTEN, |
887c0f15 | 2189 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2190 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2191 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2192 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2193 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d | 2194 | .access = PL1_R, |
e2ce5fcd | 2195 | .accessfn = access_tid4, |
158c276c | 2196 | .fgt = FGT_CCSIDR_EL1, |
630fcd4d | 2197 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
2198 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2199 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d | 2200 | .access = PL1_RW, |
e2ce5fcd | 2201 | .accessfn = access_tid4, |
b19ed03c | 2202 | .fgt = FGT_CSSELR_EL1, |
630fcd4d | 2203 | .writefn = csselr_write, .resetvalue = 0, |
b85a1fd6 FA |
2204 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2205 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
9b37a28c FR |
2206 | /* |
2207 | * Auxiliary ID register: this actually has an IMPDEF value but for now | |
776d4e5c PM |
2208 | * just RAZ for all cores: |
2209 | */ | |
0ff644a7 PM |
2210 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2211 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2212 | .access = PL1_R, .type = ARM_CP_CONST, |
2213 | .accessfn = access_aa64_tid1, | |
158c276c | 2214 | .fgt = FGT_AIDR_EL1, |
93fbc983 | 2215 | .resetvalue = 0 }, |
9b37a28c FR |
2216 | /* |
2217 | * Auxiliary fault status registers: these also are IMPDEF, and we | |
f32cdad5 PM |
2218 | * choose to RAZ/WI for all cores. |
2219 | */ | |
2220 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2221 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 | 2222 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2223 | .fgt = FGT_AFSR0_EL1, |
84929218 | 2224 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
2225 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2226 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 | 2227 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2228 | .fgt = FGT_AFSR1_EL1, |
84929218 | 2229 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
9b37a28c FR |
2230 | /* |
2231 | * MAIR can just read-as-written because we don't implement caches | |
b0fe2427 PM |
2232 | * and so don't need to care about memory attributes. |
2233 | */ | |
2234 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2235 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 | 2236 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 2237 | .fgt = FGT_MAIR_EL1, |
84929218 | 2238 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 2239 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2240 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2241 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2242 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2243 | .resetvalue = 0 }, | |
9b37a28c FR |
2244 | /* |
2245 | * For non-long-descriptor page tables these are PRRR and NMRR; | |
b0fe2427 | 2246 | * regardless they still act as reads-as-written for QEMU. |
b0fe2427 | 2247 | */ |
9b37a28c FR |
2248 | /* |
2249 | * MAIR0/1 are defined separately from their 64-bit counterpart which | |
be693c87 GB |
2250 | * allows them to assign the correct fieldoffset based on the endianness |
2251 | * handled in the field definitions. | |
2252 | */ | |
a903c449 | 2253 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2254 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2255 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2256 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2257 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2258 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2259 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2260 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2261 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2262 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2263 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2264 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2265 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2266 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
b19ed03c | 2267 | .fgt = FGT_ISR_EL1, |
7a0e58fa | 2268 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2269 | /* 32 bit ITLB invalidates */ |
2270 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2271 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2272 | .writefn = tlbiall_write }, | |
995939a6 | 2273 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2274 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2275 | .writefn = tlbimva_write }, | |
995939a6 | 2276 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2277 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2278 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2279 | /* 32 bit DTLB invalidates */ |
2280 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2281 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2282 | .writefn = tlbiall_write }, | |
995939a6 | 2283 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2284 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2285 | .writefn = tlbimva_write }, | |
995939a6 | 2286 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2287 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2288 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2289 | /* 32 bit TLB invalidates */ |
2290 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2291 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2292 | .writefn = tlbiall_write }, | |
995939a6 | 2293 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2294 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2295 | .writefn = tlbimva_write }, | |
995939a6 | 2296 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2297 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2298 | .writefn = tlbiasid_write }, | |
995939a6 | 2299 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2300 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2301 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2302 | }; |
2303 | ||
2304 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2305 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2306 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
0f66d223 | 2307 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2308 | .writefn = tlbiall_is_write }, |
995939a6 | 2309 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 2310 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2311 | .writefn = tlbimva_is_write }, |
995939a6 | 2312 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 2313 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2314 | .writefn = tlbiasid_is_write }, |
995939a6 | 2315 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 2316 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2317 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2318 | }; |
2319 | ||
327dd510 AL |
2320 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2321 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2322 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2323 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2324 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2325 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2326 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2327 | .writefn = pmovsset_write, | |
2328 | .raw_writefn = raw_write }, | |
2329 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2330 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2331 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2332 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2333 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2334 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2335 | .writefn = pmovsset_write, | |
2336 | .raw_writefn = raw_write }, | |
327dd510 AL |
2337 | }; |
2338 | ||
c4241c7d PM |
2339 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2340 | uint64_t value) | |
c326b979 PM |
2341 | { |
2342 | value &= 1; | |
2343 | env->teecr = value; | |
c326b979 PM |
2344 | } |
2345 | ||
cc7613bf PM |
2346 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2347 | bool isread) | |
2348 | { | |
2349 | /* | |
2350 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2351 | * at all, so we don't need to check whether we're v8A. | |
2352 | */ | |
2353 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2354 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2355 | return CP_ACCESS_TRAP_EL2; | |
2356 | } | |
2357 | return CP_ACCESS_OK; | |
2358 | } | |
2359 | ||
3f208fd7 PM |
2360 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2361 | bool isread) | |
c326b979 | 2362 | { |
dcbff19b | 2363 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2364 | return CP_ACCESS_TRAP; |
c326b979 | 2365 | } |
cc7613bf | 2366 | return teecr_access(env, ri, isread); |
c326b979 PM |
2367 | } |
2368 | ||
2369 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2370 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2371 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2372 | .resetvalue = 0, | |
cc7613bf | 2373 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2374 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2375 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2376 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2377 | }; |
2378 | ||
4d31c596 | 2379 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2380 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2381 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2382 | .access = PL0_RW, | |
67dd8030 | 2383 | .fgt = FGT_TPIDR_EL0, |
54bf36ed | 2384 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2385 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2386 | .access = PL0_RW, | |
67dd8030 | 2387 | .fgt = FGT_TPIDR_EL0, |
54bf36ed FA |
2388 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2389 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2390 | .resetfn = arm_cp_reset_ignore }, |
2391 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2392 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
04215eb1 | 2393 | .access = PL0_R | PL1_W, |
67dd8030 | 2394 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2395 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2396 | .resetvalue = 0}, | |
4d31c596 | 2397 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
04215eb1 | 2398 | .access = PL0_R | PL1_W, |
67dd8030 | 2399 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2400 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2401 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2402 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2403 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2404 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2405 | .access = PL1_RW, |
67dd8030 | 2406 | .fgt = FGT_TPIDR_EL1, |
54bf36ed FA |
2407 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2408 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2409 | .access = PL1_RW, | |
2410 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2411 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2412 | .resetvalue = 0 }, | |
4d31c596 PM |
2413 | }; |
2414 | ||
55d284af PM |
2415 | #ifndef CONFIG_USER_ONLY |
2416 | ||
3f208fd7 PM |
2417 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2418 | bool isread) | |
00108f2d | 2419 | { |
9b37a28c FR |
2420 | /* |
2421 | * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. | |
75502672 PM |
2422 | * Writable only at the highest implemented exception level. |
2423 | */ | |
2424 | int el = arm_current_el(env); | |
5bc84371 RH |
2425 | uint64_t hcr; |
2426 | uint32_t cntkctl; | |
75502672 PM |
2427 | |
2428 | switch (el) { | |
2429 | case 0: | |
5bc84371 RH |
2430 | hcr = arm_hcr_el2_eff(env); |
2431 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2432 | cntkctl = env->cp15.cnthctl_el2; | |
2433 | } else { | |
2434 | cntkctl = env->cp15.c14_cntkctl; | |
2435 | } | |
2436 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2437 | return CP_ACCESS_TRAP; |
2438 | } | |
2439 | break; | |
2440 | case 1: | |
2441 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2442 | arm_is_secure_below_el3(env)) { | |
2443 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2444 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2445 | } | |
2446 | break; | |
2447 | case 2: | |
2448 | case 3: | |
2449 | break; | |
00108f2d | 2450 | } |
75502672 PM |
2451 | |
2452 | if (!isread && el < arm_highest_el(env)) { | |
2453 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2454 | } | |
2455 | ||
00108f2d PM |
2456 | return CP_ACCESS_OK; |
2457 | } | |
2458 | ||
3f208fd7 PM |
2459 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2460 | bool isread) | |
00108f2d | 2461 | { |
0b6440af | 2462 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2463 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2464 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2465 | |
5bc84371 RH |
2466 | switch (cur_el) { |
2467 | case 0: | |
2468 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2469 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2470 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2471 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2472 | } | |
0b6440af | 2473 | |
5bc84371 RH |
2474 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2475 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2476 | return CP_ACCESS_TRAP; | |
2477 | } | |
2478 | ||
2479 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ | |
2480 | if (hcr & HCR_E2H) { | |
2481 | if (timeridx == GTIMER_PHYS && | |
2482 | !extract32(env->cp15.cnthctl_el2, 10, 1)) { | |
2483 | return CP_ACCESS_TRAP_EL2; | |
2484 | } | |
2485 | } else { | |
2486 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
e6ef0169 | 2487 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2488 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { |
2489 | return CP_ACCESS_TRAP_EL2; | |
2490 | } | |
2491 | } | |
2492 | break; | |
2493 | ||
2494 | case 1: | |
2495 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2496 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2497 | (hcr & HCR_E2H |
2498 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2499 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2500 | return CP_ACCESS_TRAP_EL2; | |
2501 | } | |
2502 | break; | |
0b6440af | 2503 | } |
00108f2d PM |
2504 | return CP_ACCESS_OK; |
2505 | } | |
2506 | ||
3f208fd7 PM |
2507 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2508 | bool isread) | |
00108f2d | 2509 | { |
0b6440af | 2510 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2511 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2512 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2513 | |
5bc84371 RH |
2514 | switch (cur_el) { |
2515 | case 0: | |
2516 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2517 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2518 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2519 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2520 | } | |
0b6440af | 2521 | |
5bc84371 RH |
2522 | /* |
2523 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2524 | * EL0 if EL0[PV]TEN is zero. | |
2525 | */ | |
2526 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2527 | return CP_ACCESS_TRAP; | |
2528 | } | |
2529 | /* fall through */ | |
2530 | ||
2531 | case 1: | |
e6ef0169 | 2532 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2533 | if (hcr & HCR_E2H) { |
2534 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2535 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2536 | return CP_ACCESS_TRAP_EL2; | |
2537 | } | |
2538 | } else { | |
2539 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2540 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2541 | return CP_ACCESS_TRAP_EL2; | |
2542 | } | |
2543 | } | |
2544 | } | |
2545 | break; | |
0b6440af | 2546 | } |
00108f2d PM |
2547 | return CP_ACCESS_OK; |
2548 | } | |
2549 | ||
2550 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2551 | const ARMCPRegInfo *ri, |
2552 | bool isread) | |
00108f2d | 2553 | { |
3f208fd7 | 2554 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2555 | } |
2556 | ||
2557 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2558 | const ARMCPRegInfo *ri, |
2559 | bool isread) | |
00108f2d | 2560 | { |
3f208fd7 | 2561 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2562 | } |
2563 | ||
3f208fd7 PM |
2564 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2565 | bool isread) | |
00108f2d | 2566 | { |
3f208fd7 | 2567 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2568 | } |
2569 | ||
3f208fd7 PM |
2570 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2571 | bool isread) | |
00108f2d | 2572 | { |
3f208fd7 | 2573 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2574 | } |
2575 | ||
b4d3978c | 2576 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2577 | const ARMCPRegInfo *ri, |
2578 | bool isread) | |
b4d3978c | 2579 | { |
9b37a28c FR |
2580 | /* |
2581 | * The AArch64 register view of the secure physical timer is | |
b4d3978c PM |
2582 | * always accessible from EL3, and configurably accessible from |
2583 | * Secure EL1. | |
2584 | */ | |
2585 | switch (arm_current_el(env)) { | |
2586 | case 1: | |
2587 | if (!arm_is_secure(env)) { | |
2588 | return CP_ACCESS_TRAP; | |
2589 | } | |
2590 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2591 | return CP_ACCESS_TRAP_EL3; | |
2592 | } | |
2593 | return CP_ACCESS_OK; | |
2594 | case 0: | |
2595 | case 2: | |
2596 | return CP_ACCESS_TRAP; | |
2597 | case 3: | |
2598 | return CP_ACCESS_OK; | |
2599 | default: | |
2600 | g_assert_not_reached(); | |
2601 | } | |
2602 | } | |
2603 | ||
55d284af PM |
2604 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2605 | { | |
7def8754 AJ |
2606 | ARMCPU *cpu = env_archcpu(env); |
2607 | ||
2608 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2609 | } |
2610 | ||
f6fc36de JPB |
2611 | static void gt_update_irq(ARMCPU *cpu, int timeridx) |
2612 | { | |
2613 | CPUARMState *env = &cpu->env; | |
2614 | uint64_t cnthctl = env->cp15.cnthctl_el2; | |
2615 | ARMSecuritySpace ss = arm_security_space(env); | |
2616 | /* ISTATUS && !IMASK */ | |
2617 | int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; | |
2618 | ||
2619 | /* | |
2620 | * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK. | |
2621 | * It is RES0 in Secure and NonSecure state. | |
2622 | */ | |
2623 | if ((ss == ARMSS_Root || ss == ARMSS_Realm) && | |
2624 | ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || | |
2625 | (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { | |
2626 | irqstate = 0; | |
2627 | } | |
2628 | ||
2629 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2630 | trace_arm_gt_update_irq(timeridx, irqstate); | |
2631 | } | |
2632 | ||
2633 | void gt_rme_post_el_change(ARMCPU *cpu, void *ignored) | |
2634 | { | |
2635 | /* | |
2636 | * Changing security state between Root and Secure/NonSecure, which may | |
2637 | * happen when switching EL, can change the effective value of CNTHCTL_EL2 | |
2638 | * mask bits. Update the IRQ state accordingly. | |
2639 | */ | |
2640 | gt_update_irq(cpu, GTIMER_VIRT); | |
2641 | gt_update_irq(cpu, GTIMER_PHYS); | |
2642 | } | |
2643 | ||
55d284af PM |
2644 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
2645 | { | |
2646 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2647 | ||
2648 | if (gt->ctl & 1) { | |
9b37a28c FR |
2649 | /* |
2650 | * Timer enabled: calculate and set current ISTATUS, irq, and | |
55d284af PM |
2651 | * reset timer to when ISTATUS next has to change |
2652 | */ | |
edac4d8a EI |
2653 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2654 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2655 | uint64_t count = gt_get_countervalue(&cpu->env); |
2656 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2657 | int istatus = count - offset >= gt->cval; |
55d284af PM |
2658 | uint64_t nexttick; |
2659 | ||
2660 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 | 2661 | |
55d284af PM |
2662 | if (istatus) { |
2663 | /* Next transition is when count rolls back over to zero */ | |
2664 | nexttick = UINT64_MAX; | |
2665 | } else { | |
2666 | /* Next transition is when we hit cval */ | |
edac4d8a | 2667 | nexttick = gt->cval + offset; |
55d284af | 2668 | } |
9b37a28c FR |
2669 | /* |
2670 | * Note that the desired next expiry time might be beyond the | |
55d284af PM |
2671 | * signed-64-bit range of a QEMUTimer -- in this case we just |
2672 | * set the timer for as far in the future as possible. When the | |
2673 | * timer expires we will reset the timer for any remaining period. | |
2674 | */ | |
7def8754 | 2675 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2676 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2677 | } else { | |
2678 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2679 | } |
f6fc36de | 2680 | trace_arm_gt_recalc(timeridx, nexttick); |
55d284af PM |
2681 | } else { |
2682 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2683 | gt->ctl &= ~4; | |
bc72ad67 | 2684 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2685 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af | 2686 | } |
f6fc36de | 2687 | gt_update_irq(cpu, timeridx); |
55d284af PM |
2688 | } |
2689 | ||
0e3eca4c EI |
2690 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2691 | int timeridx) | |
55d284af | 2692 | { |
2fc0cc0e | 2693 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2694 | |
bc72ad67 | 2695 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2696 | } |
2697 | ||
c4241c7d | 2698 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2699 | { |
c4241c7d | 2700 | return gt_get_countervalue(env); |
55d284af PM |
2701 | } |
2702 | ||
53d1f856 RH |
2703 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2704 | { | |
2705 | uint64_t hcr; | |
2706 | ||
2707 | switch (arm_current_el(env)) { | |
2708 | case 2: | |
2709 | hcr = arm_hcr_el2_eff(env); | |
2710 | if (hcr & HCR_E2H) { | |
2711 | return 0; | |
2712 | } | |
2713 | break; | |
2714 | case 0: | |
2715 | hcr = arm_hcr_el2_eff(env); | |
2716 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2717 | return 0; | |
2718 | } | |
2719 | break; | |
2720 | } | |
2721 | ||
2722 | return env->cp15.cntvoff_el2; | |
2723 | } | |
2724 | ||
edac4d8a EI |
2725 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2726 | { | |
53d1f856 | 2727 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2728 | } |
2729 | ||
c4241c7d | 2730 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2731 | int timeridx, |
c4241c7d | 2732 | uint64_t value) |
55d284af | 2733 | { |
194cbc49 | 2734 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2735 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2736 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2737 | } |
c4241c7d | 2738 | |
0e3eca4c EI |
2739 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2740 | int timeridx) | |
55d284af | 2741 | { |
53d1f856 RH |
2742 | uint64_t offset = 0; |
2743 | ||
2744 | switch (timeridx) { | |
2745 | case GTIMER_VIRT: | |
8c94b071 | 2746 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2747 | offset = gt_virt_cnt_offset(env); |
2748 | break; | |
2749 | } | |
55d284af | 2750 | |
c4241c7d | 2751 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2752 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2753 | } |
2754 | ||
c4241c7d | 2755 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2756 | int timeridx, |
c4241c7d | 2757 | uint64_t value) |
55d284af | 2758 | { |
53d1f856 RH |
2759 | uint64_t offset = 0; |
2760 | ||
2761 | switch (timeridx) { | |
2762 | case GTIMER_VIRT: | |
8c94b071 | 2763 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2764 | offset = gt_virt_cnt_offset(env); |
2765 | break; | |
2766 | } | |
55d284af | 2767 | |
194cbc49 | 2768 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2769 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2770 | sextract64(value, 0, 32); |
2fc0cc0e | 2771 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2772 | } |
2773 | ||
c4241c7d | 2774 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2775 | int timeridx, |
c4241c7d | 2776 | uint64_t value) |
55d284af | 2777 | { |
2fc0cc0e | 2778 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2779 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2780 | ||
194cbc49 | 2781 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2782 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2783 | if ((oldval ^ value) & 1) { |
2784 | /* Enable toggled */ | |
2785 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2786 | } else if ((oldval ^ value) & 2) { |
9b37a28c FR |
2787 | /* |
2788 | * IMASK toggled: don't need to recalculate, | |
55d284af PM |
2789 | * just set the interrupt line based on ISTATUS |
2790 | */ | |
f6fc36de JPB |
2791 | trace_arm_gt_imask_toggle(timeridx); |
2792 | gt_update_irq(cpu, timeridx); | |
55d284af | 2793 | } |
55d284af PM |
2794 | } |
2795 | ||
0e3eca4c EI |
2796 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2797 | { | |
2798 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2799 | } | |
2800 | ||
2801 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2802 | uint64_t value) | |
2803 | { | |
2804 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2805 | } | |
2806 | ||
2807 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2808 | { | |
2809 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2810 | } | |
2811 | ||
2812 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2813 | uint64_t value) | |
2814 | { | |
2815 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2816 | } | |
2817 | ||
2818 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2819 | uint64_t value) | |
2820 | { | |
2821 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2822 | } | |
2823 | ||
bb5972e4 RH |
2824 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2825 | { | |
2826 | switch (arm_mmu_idx(env)) { | |
2827 | case ARMMMUIdx_E20_0: | |
2828 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2829 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2830 | return GTIMER_HYP; |
2831 | default: | |
2832 | return GTIMER_PHYS; | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2837 | { | |
2838 | switch (arm_mmu_idx(env)) { | |
2839 | case ARMMMUIdx_E20_0: | |
2840 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2841 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2842 | return GTIMER_HYPVIRT; |
2843 | default: | |
2844 | return GTIMER_VIRT; | |
2845 | } | |
2846 | } | |
2847 | ||
2848 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2849 | const ARMCPRegInfo *ri) | |
2850 | { | |
2851 | int timeridx = gt_phys_redir_timeridx(env); | |
2852 | return env->cp15.c14_timer[timeridx].cval; | |
2853 | } | |
2854 | ||
2855 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2856 | uint64_t value) | |
2857 | { | |
2858 | int timeridx = gt_phys_redir_timeridx(env); | |
2859 | gt_cval_write(env, ri, timeridx, value); | |
2860 | } | |
2861 | ||
2862 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2863 | const ARMCPRegInfo *ri) | |
2864 | { | |
2865 | int timeridx = gt_phys_redir_timeridx(env); | |
2866 | return gt_tval_read(env, ri, timeridx); | |
2867 | } | |
2868 | ||
2869 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2870 | uint64_t value) | |
2871 | { | |
2872 | int timeridx = gt_phys_redir_timeridx(env); | |
2873 | gt_tval_write(env, ri, timeridx, value); | |
2874 | } | |
2875 | ||
2876 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2877 | const ARMCPRegInfo *ri) | |
2878 | { | |
2879 | int timeridx = gt_phys_redir_timeridx(env); | |
2880 | return env->cp15.c14_timer[timeridx].ctl; | |
2881 | } | |
2882 | ||
2883 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2884 | uint64_t value) | |
2885 | { | |
2886 | int timeridx = gt_phys_redir_timeridx(env); | |
2887 | gt_ctl_write(env, ri, timeridx, value); | |
2888 | } | |
2889 | ||
0e3eca4c EI |
2890 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2891 | { | |
2892 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2893 | } | |
2894 | ||
2895 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2896 | uint64_t value) | |
2897 | { | |
2898 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2899 | } | |
2900 | ||
2901 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2902 | { | |
2903 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2904 | } | |
2905 | ||
2906 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2907 | uint64_t value) | |
2908 | { | |
2909 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2910 | } | |
2911 | ||
2912 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2913 | uint64_t value) | |
2914 | { | |
2915 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2916 | } | |
2917 | ||
f6fc36de JPB |
2918 | static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2919 | uint64_t value) | |
2920 | { | |
2921 | ARMCPU *cpu = env_archcpu(env); | |
2922 | uint32_t oldval = env->cp15.cnthctl_el2; | |
2923 | ||
2924 | raw_write(env, ri, value); | |
2925 | ||
2926 | if ((oldval ^ value) & CNTHCTL_CNTVMASK) { | |
2927 | gt_update_irq(cpu, GTIMER_VIRT); | |
2928 | } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { | |
2929 | gt_update_irq(cpu, GTIMER_PHYS); | |
2930 | } | |
2931 | } | |
2932 | ||
edac4d8a EI |
2933 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2934 | uint64_t value) | |
2935 | { | |
2fc0cc0e | 2936 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2937 | |
194cbc49 | 2938 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2939 | raw_write(env, ri, value); |
2940 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2941 | } | |
2942 | ||
bb5972e4 RH |
2943 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2944 | const ARMCPRegInfo *ri) | |
2945 | { | |
2946 | int timeridx = gt_virt_redir_timeridx(env); | |
2947 | return env->cp15.c14_timer[timeridx].cval; | |
2948 | } | |
2949 | ||
2950 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2951 | uint64_t value) | |
2952 | { | |
2953 | int timeridx = gt_virt_redir_timeridx(env); | |
2954 | gt_cval_write(env, ri, timeridx, value); | |
2955 | } | |
2956 | ||
2957 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2958 | const ARMCPRegInfo *ri) | |
2959 | { | |
2960 | int timeridx = gt_virt_redir_timeridx(env); | |
2961 | return gt_tval_read(env, ri, timeridx); | |
2962 | } | |
2963 | ||
2964 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2965 | uint64_t value) | |
2966 | { | |
2967 | int timeridx = gt_virt_redir_timeridx(env); | |
2968 | gt_tval_write(env, ri, timeridx, value); | |
2969 | } | |
2970 | ||
2971 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2972 | const ARMCPRegInfo *ri) | |
2973 | { | |
2974 | int timeridx = gt_virt_redir_timeridx(env); | |
2975 | return env->cp15.c14_timer[timeridx].ctl; | |
2976 | } | |
2977 | ||
2978 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2979 | uint64_t value) | |
2980 | { | |
2981 | int timeridx = gt_virt_redir_timeridx(env); | |
2982 | gt_ctl_write(env, ri, timeridx, value); | |
2983 | } | |
2984 | ||
b0e66d95 EI |
2985 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2986 | { | |
2987 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2988 | } | |
2989 | ||
2990 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2991 | uint64_t value) | |
2992 | { | |
2993 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2994 | } | |
2995 | ||
2996 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2997 | { | |
2998 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2999 | } | |
3000 | ||
3001 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3002 | uint64_t value) | |
3003 | { | |
3004 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
3005 | } | |
3006 | ||
3007 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3008 | uint64_t value) | |
3009 | { | |
3010 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
3011 | } | |
3012 | ||
b4d3978c PM |
3013 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3014 | { | |
3015 | gt_timer_reset(env, ri, GTIMER_SEC); | |
3016 | } | |
3017 | ||
3018 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3019 | uint64_t value) | |
3020 | { | |
3021 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
3022 | } | |
3023 | ||
3024 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3025 | { | |
3026 | return gt_tval_read(env, ri, GTIMER_SEC); | |
3027 | } | |
3028 | ||
3029 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3030 | uint64_t value) | |
3031 | { | |
3032 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
3033 | } | |
3034 | ||
3035 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3036 | uint64_t value) | |
3037 | { | |
3038 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
3039 | } | |
3040 | ||
8c94b071 RH |
3041 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3042 | { | |
3043 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
3044 | } | |
3045 | ||
3046 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3047 | uint64_t value) | |
3048 | { | |
3049 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
3050 | } | |
3051 | ||
3052 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3053 | { | |
3054 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
3055 | } | |
3056 | ||
3057 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3058 | uint64_t value) | |
3059 | { | |
3060 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
3061 | } | |
3062 | ||
3063 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3064 | uint64_t value) | |
3065 | { | |
3066 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
3067 | } | |
3068 | ||
55d284af PM |
3069 | void arm_gt_ptimer_cb(void *opaque) |
3070 | { | |
3071 | ARMCPU *cpu = opaque; | |
3072 | ||
3073 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
3074 | } | |
3075 | ||
3076 | void arm_gt_vtimer_cb(void *opaque) | |
3077 | { | |
3078 | ARMCPU *cpu = opaque; | |
3079 | ||
3080 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
3081 | } | |
3082 | ||
b0e66d95 EI |
3083 | void arm_gt_htimer_cb(void *opaque) |
3084 | { | |
3085 | ARMCPU *cpu = opaque; | |
3086 | ||
3087 | gt_recalc_timer(cpu, GTIMER_HYP); | |
3088 | } | |
3089 | ||
b4d3978c PM |
3090 | void arm_gt_stimer_cb(void *opaque) |
3091 | { | |
3092 | ARMCPU *cpu = opaque; | |
3093 | ||
3094 | gt_recalc_timer(cpu, GTIMER_SEC); | |
3095 | } | |
3096 | ||
8c94b071 RH |
3097 | void arm_gt_hvtimer_cb(void *opaque) |
3098 | { | |
3099 | ARMCPU *cpu = opaque; | |
3100 | ||
3101 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
3102 | } | |
3103 | ||
96eec6b2 AJ |
3104 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
3105 | { | |
3106 | ARMCPU *cpu = env_archcpu(env); | |
3107 | ||
3108 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
3109 | } | |
3110 | ||
55d284af | 3111 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
9b37a28c FR |
3112 | /* |
3113 | * Note that CNTFRQ is purely reads-as-written for the benefit | |
55d284af PM |
3114 | * of software; writing it doesn't actually change the timer frequency. |
3115 | * Our reset value matches the fixed frequency we implement the timer at. | |
3116 | */ | |
3117 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3118 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
3119 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
3120 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
3121 | }, |
3122 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
3123 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3124 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 3125 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 3126 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
3127 | }, |
3128 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
3129 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
3130 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
3131 | .access = PL1_RW, |
3132 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
3133 | .resetvalue = 0, | |
3134 | }, | |
3135 | /* per-timer control */ | |
3136 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 3137 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3138 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3139 | .accessfn = gt_ptimer_access, |
3140 | .fieldoffset = offsetoflow32(CPUARMState, | |
3141 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
3142 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3143 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3144 | }, |
9c513e78 | 3145 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
3146 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
3147 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3148 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
3149 | .accessfn = gt_ptimer_access, |
3150 | .fieldoffset = offsetoflow32(CPUARMState, | |
3151 | cp15.c14_timer[GTIMER_SEC].ctl), | |
3152 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3153 | }, | |
a7adc4b7 PM |
3154 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
3155 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 3156 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3157 | .accessfn = gt_ptimer_access, |
55d284af PM |
3158 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
3159 | .resetvalue = 0, | |
bb5972e4 RH |
3160 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3161 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3162 | }, |
3163 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 3164 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3165 | .accessfn = gt_vtimer_access, |
3166 | .fieldoffset = offsetoflow32(CPUARMState, | |
3167 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
3168 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3169 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3170 | }, |
3171 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
3172 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 3173 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3174 | .accessfn = gt_vtimer_access, |
55d284af PM |
3175 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
3176 | .resetvalue = 0, | |
bb5972e4 RH |
3177 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3178 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3179 | }, |
3180 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
3181 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 3182 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3183 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3184 | .accessfn = gt_ptimer_access, |
bb5972e4 | 3185 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 3186 | }, |
9c513e78 | 3187 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
3188 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
3189 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3190 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
3191 | .accessfn = gt_ptimer_access, |
3192 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
3193 | }, | |
a7adc4b7 PM |
3194 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3195 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 3196 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3197 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 3198 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 3199 | }, |
55d284af | 3200 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 3201 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3202 | .accessfn = gt_vtimer_access, |
bb5972e4 | 3203 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 3204 | }, |
a7adc4b7 PM |
3205 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3206 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 3207 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3208 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 3209 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 3210 | }, |
55d284af PM |
3211 | /* The counter itself */ |
3212 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 3213 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3214 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
3215 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3216 | }, | |
3217 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3218 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3219 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3220 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3221 | }, |
3222 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3223 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3224 | .accessfn = gt_vct_access, |
edac4d8a | 3225 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3226 | }, |
3227 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3228 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3229 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3230 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3231 | }, |
3232 | /* Comparison value, indicating when the timer goes off */ | |
3233 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3234 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3235 | .access = PL0_RW, |
7a0e58fa | 3236 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3237 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3238 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3239 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3240 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3241 | }, |
9c513e78 | 3242 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3243 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3244 | .access = PL0_RW, |
9ff9dd3c PM |
3245 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3246 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3247 | .accessfn = gt_ptimer_access, | |
3248 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3249 | }, | |
a7adc4b7 PM |
3250 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3251 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3252 | .access = PL0_RW, |
a7adc4b7 PM |
3253 | .type = ARM_CP_IO, |
3254 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3255 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3256 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3257 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3258 | }, |
3259 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3260 | .access = PL0_RW, |
7a0e58fa | 3261 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3262 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3263 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3264 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3265 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3266 | }, |
3267 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3268 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3269 | .access = PL0_RW, |
a7adc4b7 PM |
3270 | .type = ARM_CP_IO, |
3271 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3272 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3273 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3274 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3275 | }, |
9b37a28c FR |
3276 | /* |
3277 | * Secure timer -- this is actually restricted to only EL3 | |
b4d3978c PM |
3278 | * and configurably Secure-EL1 via the accessfn. |
3279 | */ | |
3280 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3281 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3282 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3283 | .accessfn = gt_stimer_access, | |
3284 | .readfn = gt_sec_tval_read, | |
3285 | .writefn = gt_sec_tval_write, | |
3286 | .resetfn = gt_sec_timer_reset, | |
3287 | }, | |
3288 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3289 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3290 | .type = ARM_CP_IO, .access = PL1_RW, | |
3291 | .accessfn = gt_stimer_access, | |
3292 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3293 | .resetvalue = 0, | |
3294 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3295 | }, | |
3296 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3297 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3298 | .type = ARM_CP_IO, .access = PL1_RW, | |
3299 | .accessfn = gt_stimer_access, | |
3300 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3301 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3302 | }, | |
55d284af PM |
3303 | }; |
3304 | ||
bb5972e4 RH |
3305 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3306 | bool isread) | |
3307 | { | |
3308 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3309 | return CP_ACCESS_TRAP; | |
3310 | } | |
3311 | return CP_ACCESS_OK; | |
3312 | } | |
3313 | ||
55d284af | 3314 | #else |
26c4a83b | 3315 | |
9b37a28c FR |
3316 | /* |
3317 | * In user-mode most of the generic timer registers are inaccessible | |
26c4a83b | 3318 | * however modern kernels (4.12+) allow access to cntvct_el0 |
55d284af | 3319 | */ |
26c4a83b AB |
3320 | |
3321 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3322 | { | |
7def8754 AJ |
3323 | ARMCPU *cpu = env_archcpu(env); |
3324 | ||
9b37a28c FR |
3325 | /* |
3326 | * Currently we have no support for QEMUTimer in linux-user so we | |
26c4a83b AB |
3327 | * can't call gt_get_countervalue(env), instead we directly |
3328 | * call the lower level functions. | |
3329 | */ | |
7def8754 | 3330 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3331 | } |
3332 | ||
6cc7a3ae | 3333 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3334 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3335 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3336 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3337 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3338 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3339 | }, | |
3340 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3341 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3342 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3343 | .readfn = gt_virt_cnt_read, | |
3344 | }, | |
6cc7a3ae PM |
3345 | }; |
3346 | ||
55d284af PM |
3347 | #endif |
3348 | ||
c4241c7d | 3349 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3350 | { |
891a2fe7 | 3351 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3352 | raw_write(env, ri, value); |
891a2fe7 | 3353 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3354 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3355 | } else { |
8d5c773e | 3356 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3357 | } |
4a501606 PM |
3358 | } |
3359 | ||
3360 | #ifndef CONFIG_USER_ONLY | |
3361 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3362 | |
3f208fd7 PM |
3363 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3364 | bool isread) | |
92611c00 PM |
3365 | { |
3366 | if (ri->opc2 & 4) { | |
9b37a28c FR |
3367 | /* |
3368 | * The ATS12NSO* operations must trap to EL3 or EL2 if executed in | |
87562e4f PM |
3369 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3370 | * They are simply UNDEF if executed from NS EL1. | |
3371 | * They function normally from EL2 or EL3. | |
92611c00 | 3372 | */ |
87562e4f PM |
3373 | if (arm_current_el(env) == 1) { |
3374 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 | 3375 | if (env->cp15.scr_el3 & SCR_EEL2) { |
ce9a8863 | 3376 | return CP_ACCESS_TRAP_EL2; |
926c1b97 | 3377 | } |
ce9a8863 | 3378 | return CP_ACCESS_TRAP_EL3; |
87562e4f PM |
3379 | } |
3380 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3381 | } | |
92611c00 PM |
3382 | } |
3383 | return CP_ACCESS_OK; | |
3384 | } | |
3385 | ||
9fb005b0 | 3386 | #ifdef CONFIG_TCG |
b17d86eb PM |
3387 | static int par_el1_shareability(GetPhysAddrResult *res) |
3388 | { | |
3389 | /* | |
3390 | * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC | |
3391 | * memory -- see pseudocode PAREncodeShareability(). | |
3392 | */ | |
3393 | if (((res->cacheattrs.attrs & 0xf0) == 0) || | |
3394 | res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { | |
3395 | return 2; | |
3396 | } | |
3397 | return res->cacheattrs.shareability; | |
3398 | } | |
3399 | ||
060e8a48 | 3400 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
7aee3cb9 | 3401 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
e1ee56ec | 3402 | ARMSecuritySpace ss) |
4a501606 | 3403 | { |
b7cc4e82 | 3404 | bool ret; |
01c097f7 | 3405 | uint64_t par64; |
1313e2d7 | 3406 | bool format64 = false; |
e14b5a23 | 3407 | ARMMMUFaultInfo fi = {}; |
de05a709 | 3408 | GetPhysAddrResult res = {}; |
4a501606 | 3409 | |
f1269a98 JPB |
3410 | /* |
3411 | * I_MXTJT: Granule protection checks are not performed on the final address | |
3412 | * of a successful translation. | |
3413 | */ | |
e1ee56ec JPB |
3414 | ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, |
3415 | &res, &fi); | |
1313e2d7 | 3416 | |
9f225e60 PM |
3417 | /* |
3418 | * ATS operations only do S1 or S1+S2 translations, so we never | |
3419 | * have to deal with the ARMCacheAttrs format for S2 only. | |
3420 | */ | |
de05a709 | 3421 | assert(!res.cacheattrs.is_s2_format); |
9f225e60 | 3422 | |
0710b2fa PM |
3423 | if (ret) { |
3424 | /* | |
3425 | * Some kinds of translation fault must cause exceptions rather | |
3426 | * than being reported in the PAR. | |
3427 | */ | |
3428 | int current_el = arm_current_el(env); | |
3429 | int target_el; | |
3430 | uint32_t syn, fsr, fsc; | |
3431 | bool take_exc = false; | |
3432 | ||
b1a10c86 | 3433 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3434 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3435 | /* |
3436 | * Synchronous stage 2 fault on an access made as part of the | |
3437 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3438 | * executed from NS EL1. If this is a synchronous external abort | |
3439 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3440 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3441 | * and HPFAR_EL2 holds the faulting IPA. | |
3442 | */ | |
3443 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3444 | (env->cp15.scr_el3 & SCR_EA)) { | |
3445 | target_el = 3; | |
3446 | } else { | |
3447 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3448 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3449 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3450 | } | |
0710b2fa PM |
3451 | target_el = 2; |
3452 | } | |
3453 | take_exc = true; | |
3454 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3455 | /* | |
3456 | * Synchronous external aborts during a translation table walk | |
3457 | * are taken as Data Abort exceptions. | |
3458 | */ | |
3459 | if (fi.stage2) { | |
3460 | if (current_el == 3) { | |
3461 | target_el = 3; | |
3462 | } else { | |
3463 | target_el = 2; | |
3464 | } | |
3465 | } else { | |
3466 | target_el = exception_target_el(env); | |
3467 | } | |
3468 | take_exc = true; | |
3469 | } | |
3470 | ||
3471 | if (take_exc) { | |
3472 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3473 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3474 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3475 | fsr = arm_fi_to_lfsc(&fi); | |
3476 | fsc = extract32(fsr, 0, 6); | |
3477 | } else { | |
3478 | fsr = arm_fi_to_sfsc(&fi); | |
3479 | fsc = 0x3f; | |
3480 | } | |
3481 | /* | |
3482 | * Report exception with ESR indicating a fault due to a | |
3483 | * translation table walk for a cache maintenance instruction. | |
3484 | */ | |
e24fd076 | 3485 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3486 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3487 | env->exception.vaddress = value; | |
3488 | env->exception.fsr = fsr; | |
3489 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3490 | } | |
3491 | } | |
3492 | ||
1313e2d7 EI |
3493 | if (is_a64(env)) { |
3494 | format64 = true; | |
3495 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3496 | /* | |
3497 | * ATS1Cxx: | |
3498 | * * TTBCR.EAE determines whether the result is returned using the | |
3499 | * 32-bit or the 64-bit PAR format | |
3500 | * * Instructions executed in Hyp mode always use the 64bit format | |
3501 | * | |
3502 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3503 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3504 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3505 | * | |
9d1bab33 PM |
3506 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3507 | * | |
23463e0e | 3508 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3509 | */ |
3510 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3511 | ||
3512 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3513 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3514 | mmu_idx == ARMMMUIdx_E10_1 || | |
3515 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3516 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3517 | } else { |
3518 | format64 |= arm_current_el(env) == 2; | |
3519 | } | |
3520 | } | |
3521 | } | |
3522 | ||
3523 | if (format64) { | |
5efe9ed4 | 3524 | /* Create a 64-bit PAR */ |
01c097f7 | 3525 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3526 | if (!ret) { |
7fa7ea8f RH |
3527 | par64 |= res.f.phys_addr & ~0xfffULL; |
3528 | if (!res.f.attrs.secure) { | |
8bf5b6a9 PM |
3529 | par64 |= (1 << 9); /* NS */ |
3530 | } | |
de05a709 | 3531 | par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ |
b17d86eb | 3532 | par64 |= par_el1_shareability(&res) << 7; /* SH */ |
4a501606 | 3533 | } else { |
5efe9ed4 PM |
3534 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3535 | ||
702a9357 | 3536 | par64 |= 1; /* F */ |
b7cc4e82 | 3537 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3538 | if (fi.stage2) { |
3539 | par64 |= (1 << 9); /* S */ | |
3540 | } | |
3541 | if (fi.s1ptw) { | |
3542 | par64 |= (1 << 8); /* PTW */ | |
3543 | } | |
4a501606 PM |
3544 | } |
3545 | } else { | |
9b37a28c FR |
3546 | /* |
3547 | * fsr is a DFSR/IFSR value for the short descriptor | |
702a9357 PM |
3548 | * translation table format (with WnR always clear). |
3549 | * Convert it to a 32-bit PAR. | |
3550 | */ | |
b7cc4e82 | 3551 | if (!ret) { |
702a9357 | 3552 | /* We do not set any attribute bits in the PAR */ |
7fa7ea8f | 3553 | if (res.f.lg_page_size == 24 |
702a9357 | 3554 | && arm_feature(env, ARM_FEATURE_V7)) { |
7fa7ea8f | 3555 | par64 = (res.f.phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3556 | } else { |
7fa7ea8f | 3557 | par64 = res.f.phys_addr & 0xfffff000; |
702a9357 | 3558 | } |
7fa7ea8f | 3559 | if (!res.f.attrs.secure) { |
8bf5b6a9 PM |
3560 | par64 |= (1 << 9); /* NS */ |
3561 | } | |
702a9357 | 3562 | } else { |
5efe9ed4 PM |
3563 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3564 | ||
b7cc4e82 PC |
3565 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3566 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3567 | } |
4a501606 | 3568 | } |
060e8a48 PM |
3569 | return par64; |
3570 | } | |
9fb005b0 | 3571 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3572 | |
3573 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3574 | { | |
9fb005b0 | 3575 | #ifdef CONFIG_TCG |
03ae85f8 | 3576 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3577 | uint64_t par64; |
d3649702 PM |
3578 | ARMMMUIdx mmu_idx; |
3579 | int el = arm_current_el(env); | |
e1ee56ec | 3580 | ARMSecuritySpace ss = arm_security_space(env); |
060e8a48 | 3581 | |
d3649702 PM |
3582 | switch (ri->opc2 & 6) { |
3583 | case 0: | |
04b07d29 | 3584 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3585 | switch (el) { |
3586 | case 3: | |
d902ae75 | 3587 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3588 | break; |
3589 | case 2: | |
e1ee56ec | 3590 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3591 | /* fall through */ |
d3649702 | 3592 | case 1: |
04b07d29 | 3593 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
d902ae75 | 3594 | mmu_idx = ARMMMUIdx_Stage1_E1_PAN; |
04b07d29 | 3595 | } else { |
d902ae75 | 3596 | mmu_idx = ARMMMUIdx_Stage1_E1; |
04b07d29 | 3597 | } |
d3649702 PM |
3598 | break; |
3599 | default: | |
3600 | g_assert_not_reached(); | |
3601 | } | |
3602 | break; | |
3603 | case 2: | |
3604 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3605 | switch (el) { | |
3606 | case 3: | |
d902ae75 | 3607 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3608 | break; |
3609 | case 2: | |
e1ee56ec | 3610 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3611 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3612 | break; |
3613 | case 1: | |
d902ae75 | 3614 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3615 | break; |
3616 | default: | |
3617 | g_assert_not_reached(); | |
3618 | } | |
3619 | break; | |
3620 | case 4: | |
3621 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3622 | mmu_idx = ARMMMUIdx_E10_1; |
e1ee56ec | 3623 | ss = ARMSS_NonSecure; |
d3649702 PM |
3624 | break; |
3625 | case 6: | |
3626 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3627 | mmu_idx = ARMMMUIdx_E10_0; |
e1ee56ec | 3628 | ss = ARMSS_NonSecure; |
d3649702 PM |
3629 | break; |
3630 | default: | |
3631 | g_assert_not_reached(); | |
3632 | } | |
3633 | ||
e1ee56ec | 3634 | par64 = do_ats_write(env, value, access_type, mmu_idx, ss); |
01c097f7 FA |
3635 | |
3636 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3637 | #else |
3638 | /* Handled by hardware accelerator. */ | |
3639 | g_assert_not_reached(); | |
3640 | #endif /* CONFIG_TCG */ | |
4a501606 | 3641 | } |
060e8a48 | 3642 | |
14db7fe0 PM |
3643 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3644 | uint64_t value) | |
3645 | { | |
9fb005b0 | 3646 | #ifdef CONFIG_TCG |
03ae85f8 | 3647 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3648 | uint64_t par64; |
3649 | ||
7aee3cb9 | 3650 | /* There is no SecureEL2 for AArch32. */ |
e1ee56ec JPB |
3651 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, |
3652 | ARMSS_NonSecure); | |
14db7fe0 PM |
3653 | |
3654 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3655 | #else |
3656 | /* Handled by hardware accelerator. */ | |
3657 | g_assert_not_reached(); | |
3658 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3659 | } |
3660 | ||
1acd00ef JPB |
3661 | static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3662 | bool isread) | |
3663 | { | |
3664 | /* | |
3665 | * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level | |
3666 | * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can | |
3667 | * only happen when executing at EL3 because that combination also causes an | |
3668 | * illegal exception return. We don't need to check FEAT_RME either, because | |
3669 | * scr_write() ensures that the NSE bit is not set otherwise. | |
3670 | */ | |
3671 | if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { | |
3672 | return CP_ACCESS_TRAP; | |
3673 | } | |
3674 | return CP_ACCESS_OK; | |
3675 | } | |
3676 | ||
3f208fd7 PM |
3677 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3678 | bool isread) | |
2a47df95 | 3679 | { |
926c1b97 RDC |
3680 | if (arm_current_el(env) == 3 && |
3681 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3682 | return CP_ACCESS_TRAP; |
3683 | } | |
1acd00ef | 3684 | return at_e012_access(env, ri, isread); |
2a47df95 PM |
3685 | } |
3686 | ||
060e8a48 PM |
3687 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3688 | uint64_t value) | |
3689 | { | |
9fb005b0 | 3690 | #ifdef CONFIG_TCG |
03ae85f8 | 3691 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 | 3692 | ARMMMUIdx mmu_idx; |
638d5dbd AK |
3693 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
3694 | bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); | |
d3649702 PM |
3695 | |
3696 | switch (ri->opc2 & 6) { | |
3697 | case 0: | |
3698 | switch (ri->opc1) { | |
04b07d29 RH |
3699 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3700 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
638d5dbd AK |
3701 | mmu_idx = regime_e20 ? |
3702 | ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; | |
04b07d29 | 3703 | } else { |
638d5dbd | 3704 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3705 | } |
d3649702 PM |
3706 | break; |
3707 | case 4: /* AT S1E2R, AT S1E2W */ | |
638d5dbd | 3708 | mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; |
d3649702 PM |
3709 | break; |
3710 | case 6: /* AT S1E3R, AT S1E3W */ | |
d902ae75 | 3711 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3712 | break; |
3713 | default: | |
3714 | g_assert_not_reached(); | |
3715 | } | |
3716 | break; | |
3717 | case 2: /* AT S1E0R, AT S1E0W */ | |
638d5dbd | 3718 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3719 | break; |
3720 | case 4: /* AT S12E1R, AT S12E1W */ | |
638d5dbd | 3721 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; |
d3649702 PM |
3722 | break; |
3723 | case 6: /* AT S12E0R, AT S12E0W */ | |
638d5dbd | 3724 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3725 | break; |
3726 | default: | |
3727 | g_assert_not_reached(); | |
3728 | } | |
060e8a48 | 3729 | |
7aee3cb9 | 3730 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, |
e1ee56ec | 3731 | mmu_idx, arm_security_space(env)); |
9fb005b0 PMD |
3732 | #else |
3733 | /* Handled by hardware accelerator. */ | |
3734 | g_assert_not_reached(); | |
3735 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3736 | } |
4a501606 PM |
3737 | #endif |
3738 | ||
3739 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3740 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3741 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3742 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3743 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3744 | .writefn = par_write }, |
3745 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3746 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3747 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3748 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3749 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 | 3750 | #endif |
4a501606 PM |
3751 | }; |
3752 | ||
18032bec PM |
3753 | /* Return basic MPU access permission bits. */ |
3754 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3755 | { | |
3756 | uint32_t ret; | |
3757 | uint32_t mask; | |
3758 | int i; | |
3759 | ret = 0; | |
3760 | mask = 3; | |
3761 | for (i = 0; i < 16; i += 2) { | |
3762 | ret |= (val >> i) & mask; | |
3763 | mask <<= 2; | |
3764 | } | |
3765 | return ret; | |
3766 | } | |
3767 | ||
3768 | /* Pad basic MPU access permission bits to extended format. */ | |
3769 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3770 | { | |
3771 | uint32_t ret; | |
3772 | uint32_t mask; | |
3773 | int i; | |
3774 | ret = 0; | |
3775 | mask = 3; | |
3776 | for (i = 0; i < 16; i += 2) { | |
3777 | ret |= (val & mask) << i; | |
3778 | mask <<= 2; | |
3779 | } | |
3780 | return ret; | |
3781 | } | |
3782 | ||
c4241c7d PM |
3783 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3784 | uint64_t value) | |
18032bec | 3785 | { |
7e09797c | 3786 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3787 | } |
3788 | ||
c4241c7d | 3789 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3790 | { |
7e09797c | 3791 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3792 | } |
3793 | ||
c4241c7d PM |
3794 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3795 | uint64_t value) | |
18032bec | 3796 | { |
7e09797c | 3797 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3798 | } |
3799 | ||
c4241c7d | 3800 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3801 | { |
7e09797c | 3802 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3803 | } |
3804 | ||
6cb0b013 PC |
3805 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3806 | { | |
3807 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3808 | ||
3809 | if (!u32p) { | |
3810 | return 0; | |
3811 | } | |
3812 | ||
1bc04a88 | 3813 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3814 | return *u32p; |
3815 | } | |
3816 | ||
3817 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3818 | uint64_t value) | |
3819 | { | |
2fc0cc0e | 3820 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3821 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3822 | ||
3823 | if (!u32p) { | |
3824 | return; | |
3825 | } | |
3826 | ||
1bc04a88 | 3827 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3828 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3829 | *u32p = value; |
3830 | } | |
3831 | ||
6cb0b013 PC |
3832 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3833 | uint64_t value) | |
3834 | { | |
2fc0cc0e | 3835 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3836 | uint32_t nrgs = cpu->pmsav7_dregion; |
3837 | ||
3838 | if (value >= nrgs) { | |
3839 | qemu_log_mask(LOG_GUEST_ERROR, | |
3840 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3841 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3842 | return; | |
3843 | } | |
3844 | ||
3845 | raw_write(env, ri, value); | |
3846 | } | |
3847 | ||
761c4642 TR |
3848 | static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3849 | uint64_t value) | |
3850 | { | |
3851 | ARMCPU *cpu = env_archcpu(env); | |
3852 | ||
3853 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3854 | env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3855 | } | |
3856 | ||
3857 | static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3858 | { | |
3859 | return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3860 | } | |
3861 | ||
3862 | static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3863 | uint64_t value) | |
3864 | { | |
3865 | ARMCPU *cpu = env_archcpu(env); | |
3866 | ||
3867 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3868 | env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3869 | } | |
3870 | ||
3871 | static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3872 | { | |
3873 | return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3874 | } | |
3875 | ||
3876 | static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3877 | uint64_t value) | |
3878 | { | |
3879 | ARMCPU *cpu = env_archcpu(env); | |
3880 | ||
3881 | /* | |
3882 | * Ignore writes that would select not implemented region. | |
3883 | * This is architecturally UNPREDICTABLE. | |
3884 | */ | |
3885 | if (value >= cpu->pmsav7_dregion) { | |
3886 | return; | |
3887 | } | |
3888 | ||
3889 | env->pmsav7.rnr[M_REG_NS] = value; | |
3890 | } | |
3891 | ||
3892 | static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3893 | uint64_t value) | |
3894 | { | |
3895 | ARMCPU *cpu = env_archcpu(env); | |
3896 | ||
3897 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3898 | env->pmsav8.hprbar[env->pmsav8.hprselr] = value; | |
3899 | } | |
3900 | ||
3901 | static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3902 | { | |
3903 | return env->pmsav8.hprbar[env->pmsav8.hprselr]; | |
3904 | } | |
3905 | ||
3906 | static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3907 | uint64_t value) | |
3908 | { | |
3909 | ARMCPU *cpu = env_archcpu(env); | |
3910 | ||
3911 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3912 | env->pmsav8.hprlar[env->pmsav8.hprselr] = value; | |
3913 | } | |
3914 | ||
3915 | static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3916 | { | |
3917 | return env->pmsav8.hprlar[env->pmsav8.hprselr]; | |
3918 | } | |
3919 | ||
3920 | static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3921 | uint64_t value) | |
3922 | { | |
3923 | uint32_t n; | |
3924 | uint32_t bit; | |
3925 | ARMCPU *cpu = env_archcpu(env); | |
3926 | ||
3927 | /* Ignore writes to unimplemented regions */ | |
3928 | int rmax = MIN(cpu->pmsav8r_hdregion, 32); | |
3929 | value &= MAKE_64BIT_MASK(0, rmax); | |
3930 | ||
3931 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3932 | ||
3933 | /* Register alias is only valid for first 32 indexes */ | |
3934 | for (n = 0; n < rmax; ++n) { | |
3935 | bit = extract32(value, n, 1); | |
3936 | env->pmsav8.hprlar[n] = deposit32( | |
3937 | env->pmsav8.hprlar[n], 0, 1, bit); | |
3938 | } | |
3939 | } | |
3940 | ||
3941 | static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3942 | { | |
3943 | uint32_t n; | |
3944 | uint32_t result = 0x0; | |
3945 | ARMCPU *cpu = env_archcpu(env); | |
3946 | ||
3947 | /* Register alias is only valid for first 32 indexes */ | |
3948 | for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { | |
3949 | if (env->pmsav8.hprlar[n] & 0x1) { | |
3950 | result |= (0x1 << n); | |
3951 | } | |
3952 | } | |
3953 | return result; | |
3954 | } | |
3955 | ||
3956 | static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3957 | uint64_t value) | |
3958 | { | |
3959 | ARMCPU *cpu = env_archcpu(env); | |
3960 | ||
3961 | /* | |
3962 | * Ignore writes that would select not implemented region. | |
3963 | * This is architecturally UNPREDICTABLE. | |
3964 | */ | |
3965 | if (value >= cpu->pmsav8r_hdregion) { | |
3966 | return; | |
3967 | } | |
3968 | ||
3969 | env->pmsav8.hprselr = value; | |
3970 | } | |
3971 | ||
3972 | static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3973 | uint64_t value) | |
3974 | { | |
3975 | ARMCPU *cpu = env_archcpu(env); | |
3976 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
3977 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
3978 | ||
3979 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3980 | ||
3981 | if (ri->opc1 & 4) { | |
3982 | if (index >= cpu->pmsav8r_hdregion) { | |
3983 | return; | |
3984 | } | |
3985 | if (ri->opc2 & 0x1) { | |
3986 | env->pmsav8.hprlar[index] = value; | |
3987 | } else { | |
3988 | env->pmsav8.hprbar[index] = value; | |
3989 | } | |
3990 | } else { | |
3991 | if (index >= cpu->pmsav7_dregion) { | |
3992 | return; | |
3993 | } | |
3994 | if (ri->opc2 & 0x1) { | |
3995 | env->pmsav8.rlar[M_REG_NS][index] = value; | |
3996 | } else { | |
3997 | env->pmsav8.rbar[M_REG_NS][index] = value; | |
3998 | } | |
3999 | } | |
4000 | } | |
4001 | ||
4002 | static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4003 | { | |
4004 | ARMCPU *cpu = env_archcpu(env); | |
4005 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
4006 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
4007 | ||
4008 | if (ri->opc1 & 4) { | |
4009 | if (index >= cpu->pmsav8r_hdregion) { | |
4010 | return 0x0; | |
4011 | } | |
4012 | if (ri->opc2 & 0x1) { | |
4013 | return env->pmsav8.hprlar[index]; | |
4014 | } else { | |
4015 | return env->pmsav8.hprbar[index]; | |
4016 | } | |
4017 | } else { | |
4018 | if (index >= cpu->pmsav7_dregion) { | |
4019 | return 0x0; | |
4020 | } | |
4021 | if (ri->opc2 & 0x1) { | |
4022 | return env->pmsav8.rlar[M_REG_NS][index]; | |
4023 | } else { | |
4024 | return env->pmsav8.rbar[M_REG_NS][index]; | |
4025 | } | |
4026 | } | |
4027 | } | |
4028 | ||
4029 | static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { | |
4030 | { .name = "PRBAR", | |
4031 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0, | |
4032 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4033 | .accessfn = access_tvm_trvm, | |
4034 | .readfn = prbar_read, .writefn = prbar_write }, | |
4035 | { .name = "PRLAR", | |
4036 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1, | |
4037 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4038 | .accessfn = access_tvm_trvm, | |
4039 | .readfn = prlar_read, .writefn = prlar_write }, | |
4040 | { .name = "PRSELR", .resetvalue = 0, | |
4041 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1, | |
4042 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
4043 | .writefn = prselr_write, | |
4044 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, | |
4045 | { .name = "HPRBAR", .resetvalue = 0, | |
4046 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0, | |
4047 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4048 | .readfn = hprbar_read, .writefn = hprbar_write }, | |
4049 | { .name = "HPRLAR", | |
4050 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1, | |
4051 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4052 | .readfn = hprlar_read, .writefn = hprlar_write }, | |
4053 | { .name = "HPRSELR", .resetvalue = 0, | |
4054 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1, | |
4055 | .access = PL2_RW, | |
4056 | .writefn = hprselr_write, | |
4057 | .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) }, | |
4058 | { .name = "HPRENR", | |
4059 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1, | |
4060 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4061 | .readfn = hprenr_read, .writefn = hprenr_write }, | |
4062 | }; | |
4063 | ||
6cb0b013 | 4064 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { |
9b37a28c FR |
4065 | /* |
4066 | * Reset for all these registers is handled in arm_cpu_reset(), | |
69ceea64 PM |
4067 | * because the PMSAv7 is also used by M-profile CPUs, which do |
4068 | * not register cpregs but still need the state to be reset. | |
4069 | */ | |
6cb0b013 PC |
4070 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
4071 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4072 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
4073 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4074 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4075 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
4076 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4077 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
4078 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4079 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4080 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
4081 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4082 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
4083 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4084 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4085 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
4086 | .access = PL1_RW, | |
1bc04a88 | 4087 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
4088 | .writefn = pmsav7_rgnr_write, |
4089 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4090 | }; |
4091 | ||
18032bec PM |
4092 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
4093 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 4094 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4095 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
4096 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
4097 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 4098 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4099 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
4100 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
4101 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
4102 | .access = PL1_RW, | |
7e09797c PM |
4103 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
4104 | .resetvalue = 0, }, | |
18032bec PM |
4105 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
4106 | .access = PL1_RW, | |
7e09797c PM |
4107 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
4108 | .resetvalue = 0, }, | |
ecce5c3c PM |
4109 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
4110 | .access = PL1_RW, | |
4111 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
4112 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
4113 | .access = PL1_RW, | |
4114 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 4115 | /* Protection region base and size registers */ |
e508a92b PM |
4116 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
4117 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4118 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
4119 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
4120 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4121 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
4122 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
4123 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4124 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
4125 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
4126 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4127 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
4128 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
4129 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4130 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
4131 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
4132 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4133 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
4134 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
4135 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4136 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
4137 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
4138 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4139 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
4140 | }; |
4141 | ||
cb4a0a34 PM |
4142 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4143 | uint64_t value) | |
ecce5c3c | 4144 | { |
cb4a0a34 | 4145 | ARMCPU *cpu = env_archcpu(env); |
2ebcebe2 | 4146 | |
e389be16 FA |
4147 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4148 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
cb4a0a34 PM |
4149 | /* |
4150 | * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
4151 | * using Long-descriptor translation table format | |
4152 | */ | |
e389be16 FA |
4153 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
4154 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
cb4a0a34 PM |
4155 | /* |
4156 | * In an implementation that includes the Security Extensions | |
e389be16 FA |
4157 | * TTBCR has additional fields PD0 [4] and PD1 [5] for |
4158 | * Short-descriptor translation table format. | |
4159 | */ | |
4160 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
4161 | } else { | |
4162 | value &= TTBCR_N; | |
4163 | } | |
e42c4db3 | 4164 | } |
e389be16 | 4165 | |
d4e6df63 | 4166 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
9b37a28c FR |
4167 | /* |
4168 | * With LPAE the TTBCR could result in a change of ASID | |
d4e6df63 PM |
4169 | * via the TTBCR.A1 bit, so do a TLB flush. |
4170 | */ | |
d10eb08f | 4171 | tlb_flush(CPU(cpu)); |
d4e6df63 | 4172 | } |
cb4a0a34 | 4173 | raw_write(env, ri, value); |
ecce5c3c PM |
4174 | } |
4175 | ||
d06dc933 | 4176 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
4177 | uint64_t value) |
4178 | { | |
2fc0cc0e | 4179 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 4180 | |
cb2e37df | 4181 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 4182 | tlb_flush(CPU(cpu)); |
cb4a0a34 | 4183 | raw_write(env, ri, value); |
cb2e37df PM |
4184 | } |
4185 | ||
327ed10f PM |
4186 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4187 | uint64_t value) | |
4188 | { | |
93f379b0 RH |
4189 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
4190 | if (cpreg_field_is_64bit(ri) && | |
4191 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 4192 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 4193 | tlb_flush(CPU(cpu)); |
327ed10f PM |
4194 | } |
4195 | raw_write(env, ri, value); | |
4196 | } | |
4197 | ||
ed30da8e RH |
4198 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4199 | uint64_t value) | |
4200 | { | |
d06dc933 RH |
4201 | /* |
4202 | * If we are running with E2&0 regime, then an ASID is active. | |
4203 | * Flush if that might be changing. Note we're not checking | |
4204 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
4205 | * holds the active ASID, only checking the field that might. | |
4206 | */ | |
4207 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
4208 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
4209 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
4210 | ARMMMUIdxBit_E20_2_PAN | | |
4211 | ARMMMUIdxBit_E20_0; | |
b6ad6062 | 4212 | tlb_flush_by_mmuidx(env_cpu(env), mask); |
d06dc933 | 4213 | } |
ed30da8e RH |
4214 | raw_write(env, ri, value); |
4215 | } | |
4216 | ||
b698e9cf EI |
4217 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4218 | uint64_t value) | |
4219 | { | |
2fc0cc0e | 4220 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
4221 | CPUState *cs = CPU(cpu); |
4222 | ||
97fa9350 RH |
4223 | /* |
4224 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
575a94af | 4225 | * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0). |
97fa9350 | 4226 | */ |
00b20ee4 | 4227 | if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { |
575a94af | 4228 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
b698e9cf | 4229 | } |
00b20ee4 | 4230 | raw_write(env, ri, value); |
b698e9cf EI |
4231 | } |
4232 | ||
8e5d75c9 | 4233 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 4234 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 4235 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 4236 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 4237 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 4238 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 4239 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
4240 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
4241 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 4242 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 4243 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
4244 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
4245 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
4246 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
4247 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 | 4248 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4249 | .fgt = FGT_FAR_EL1, |
84929218 | 4250 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
8e5d75c9 | 4251 | .resetvalue = 0, }, |
8e5d75c9 PC |
4252 | }; |
4253 | ||
4254 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
4255 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
4256 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 4257 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4258 | .fgt = FGT_ESR_EL1, |
d81c519c | 4259 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 4260 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4261 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 | 4262 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4263 | .fgt = FGT_TTBR0_EL1, |
587f8b33 | 4264 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4265 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4266 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 4267 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4268 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 | 4269 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4270 | .fgt = FGT_TTBR1_EL1, |
587f8b33 | 4271 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4272 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4273 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
4274 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
4275 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 | 4276 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 4277 | .fgt = FGT_TCR_EL1, |
84929218 | 4278 | .writefn = vmsa_tcr_el12_write, |
cb4a0a34 PM |
4279 | .raw_writefn = raw_write, |
4280 | .resetvalue = 0, | |
11f136ee | 4281 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 4282 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
4283 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4284 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
cb4a0a34 PM |
4285 | .raw_writefn = raw_write, |
4286 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), | |
4287 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
4288 | }; |
4289 | ||
9b37a28c FR |
4290 | /* |
4291 | * Note that unlike TTBCR, writing to TTBCR2 does not require flushing | |
ab638a32 RH |
4292 | * qemu tlbs nor adjusting cached masks. |
4293 | */ | |
4294 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
4295 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
4296 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4297 | .type = ARM_CP_ALIAS, | |
d102058e | 4298 | .bank_fieldoffsets = { |
cb4a0a34 PM |
4299 | offsetofhigh32(CPUARMState, cp15.tcr_el[3]), |
4300 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]), | |
d102058e | 4301 | }, |
ab638a32 RH |
4302 | }; |
4303 | ||
c4241c7d PM |
4304 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4305 | uint64_t value) | |
1047b9d7 PM |
4306 | { |
4307 | env->cp15.c15_ticonfig = value & 0xe7; | |
4308 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
4309 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
4310 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
4311 | } |
4312 | ||
c4241c7d PM |
4313 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4314 | uint64_t value) | |
1047b9d7 PM |
4315 | { |
4316 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
4317 | } |
4318 | ||
c4241c7d PM |
4319 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4320 | uint64_t value) | |
1047b9d7 PM |
4321 | { |
4322 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 4323 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
4324 | } |
4325 | ||
c4241c7d PM |
4326 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4327 | uint64_t value) | |
c4804214 | 4328 | { |
9b37a28c FR |
4329 | /* |
4330 | * On OMAP there are registers indicating the max/min index of dcache lines | |
c4804214 PM |
4331 | * containing a dirty line; cache flush operations have to reset these. |
4332 | */ | |
4333 | env->cp15.c15_i_max = 0x000; | |
4334 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
4335 | } |
4336 | ||
18032bec PM |
4337 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
4338 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
4339 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 4340 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 4341 | .resetvalue = 0, }, |
1047b9d7 PM |
4342 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
4343 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4344 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
4345 | .access = PL1_RW, | |
4346 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
4347 | .writefn = omap_ticonfig_write }, | |
4348 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
4349 | .access = PL1_RW, | |
4350 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
4351 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
4352 | .access = PL1_RW, .resetvalue = 0xff0, | |
4353 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
4354 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
4355 | .access = PL1_RW, | |
4356 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
4357 | .writefn = omap_threadid_write }, | |
4358 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
4359 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 4360 | .type = ARM_CP_NO_RAW, |
1047b9d7 | 4361 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
9b37a28c FR |
4362 | /* |
4363 | * TODO: Peripheral port remap register: | |
1047b9d7 PM |
4364 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller |
4365 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
4366 | * when MMU is off. | |
4367 | */ | |
c4804214 | 4368 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 4369 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 4370 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 4371 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
4372 | { .name = "C9", .cp = 15, .crn = 9, |
4373 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
4374 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
4375 | }; |
4376 | ||
c4241c7d PM |
4377 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4378 | uint64_t value) | |
1047b9d7 | 4379 | { |
c0f4af17 | 4380 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
4381 | } |
4382 | ||
4383 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
4384 | { .name = "XSCALE_CPAR", | |
4385 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
4386 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
4387 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
4388 | { .name = "XSCALE_AUXCR", |
4389 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
4390 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
4391 | .resetvalue = 0, }, | |
9b37a28c FR |
4392 | /* |
4393 | * XScale specific cache-lockdown: since we have no cache we NOP these | |
3b771579 PM |
4394 | * and hope the guest does not really rely on cache behaviour. |
4395 | */ | |
4396 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
4397 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
4398 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4399 | { .name = "XSCALE_UNLOCK_ICACHE", | |
4400 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
4401 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4402 | { .name = "XSCALE_DCACHE_LOCK", | |
4403 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
4404 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4405 | { .name = "XSCALE_UNLOCK_DCACHE", | |
4406 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
4407 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
4408 | }; |
4409 | ||
4410 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
9b37a28c FR |
4411 | /* |
4412 | * RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1047b9d7 PM |
4413 | * implementation of this implementation-defined space. |
4414 | * Ideally this should eventually disappear in favour of actually | |
4415 | * implementing the correct behaviour for all cores. | |
4416 | */ | |
4417 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
4418 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 4419 | .access = PL1_RW, |
7a0e58fa | 4420 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 4421 | .resetvalue = 0 }, |
18032bec PM |
4422 | }; |
4423 | ||
c4804214 PM |
4424 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
4425 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
4426 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 4427 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4428 | .resetvalue = 0 }, |
c4804214 PM |
4429 | }; |
4430 | ||
4431 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
a07d9df0 | 4432 | /* We never have a block transfer operation in progress */ |
c4804214 | 4433 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, |
7a0e58fa | 4434 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4435 | .resetvalue = 0 }, |
30b05bba PM |
4436 | /* The cache ops themselves: these all NOP for QEMU */ |
4437 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
04215eb1 | 4438 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4439 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, |
04215eb1 | 4440 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4441 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, |
04215eb1 | 4442 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4443 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, |
04215eb1 | 4444 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4445 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, |
04215eb1 | 4446 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4447 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, |
04215eb1 | 4448 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
c4804214 PM |
4449 | }; |
4450 | ||
4451 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
9b37a28c FR |
4452 | /* |
4453 | * The cache test-and-clean instructions always return (1 << 30) | |
c4804214 PM |
4454 | * to indicate that there are no dirty cache lines. |
4455 | */ | |
4456 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4457 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4458 | .resetvalue = (1 << 30) }, |
c4804214 | 4459 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4460 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4461 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4462 | }; |
4463 | ||
34f90529 PM |
4464 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4465 | /* Ignore ReadBuffer accesses */ | |
4466 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4467 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4468 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4469 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4470 | }; |
4471 | ||
731de9e6 EI |
4472 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4473 | { | |
731de9e6 | 4474 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4475 | |
e6ef0169 | 4476 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4477 | return env->cp15.vpidr_el2; |
4478 | } | |
4479 | return raw_read(env, ri); | |
4480 | } | |
4481 | ||
06a7e647 | 4482 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4483 | { |
2fc0cc0e | 4484 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4485 | uint64_t mpidr = cpu->mp_affinity; |
4486 | ||
81bdde9d | 4487 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4488 | mpidr |= (1U << 31); |
9b37a28c FR |
4489 | /* |
4490 | * Cores which are uniprocessor (non-coherent) | |
81bdde9d | 4491 | * but still implement the MP extensions set |
a8e81b31 | 4492 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4493 | */ |
a8e81b31 PC |
4494 | if (cpu->mp_is_up) { |
4495 | mpidr |= (1u << 30); | |
4496 | } | |
81bdde9d | 4497 | } |
c4241c7d | 4498 | return mpidr; |
81bdde9d PM |
4499 | } |
4500 | ||
06a7e647 EI |
4501 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4502 | { | |
f0d574d6 | 4503 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4504 | |
e6ef0169 | 4505 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4506 | return env->cp15.vmpidr_el2; |
4507 | } | |
06a7e647 EI |
4508 | return mpidr_read_val(env); |
4509 | } | |
4510 | ||
7ac681cf | 4511 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4512 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4513 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4514 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 | 4515 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 4516 | .fgt = FGT_AMAIR_EL1, |
84929218 | 4517 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
b0fe2427 | 4518 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4519 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4520 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4521 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4522 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4523 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4524 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4525 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4526 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4527 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4528 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4529 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4530 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
587f8b33 | 4531 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
891a2fe7 | 4532 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4533 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4534 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4535 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4536 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
587f8b33 | 4537 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
7ac681cf PM |
4538 | }; |
4539 | ||
c4241c7d | 4540 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4541 | { |
c4241c7d | 4542 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4543 | } |
4544 | ||
c4241c7d PM |
4545 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4546 | uint64_t value) | |
b0d2b7d0 PM |
4547 | { |
4548 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4549 | } |
4550 | ||
c4241c7d | 4551 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4552 | { |
c4241c7d | 4553 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4554 | } |
4555 | ||
c4241c7d PM |
4556 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4557 | uint64_t value) | |
b0d2b7d0 PM |
4558 | { |
4559 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4560 | } |
4561 | ||
3f208fd7 PM |
4562 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4563 | bool isread) | |
c2b820fe | 4564 | { |
aaec1432 | 4565 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4566 | return CP_ACCESS_TRAP; |
4567 | } | |
4568 | return CP_ACCESS_OK; | |
4569 | } | |
4570 | ||
4571 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4572 | uint64_t value) | |
4573 | { | |
4574 | env->daif = value & PSTATE_DAIF; | |
4575 | } | |
4576 | ||
220f508f RH |
4577 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4578 | { | |
4579 | return env->pstate & PSTATE_PAN; | |
4580 | } | |
4581 | ||
4582 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4583 | uint64_t value) | |
4584 | { | |
4585 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4586 | } | |
4587 | ||
4588 | static const ARMCPRegInfo pan_reginfo = { | |
4589 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4590 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4591 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4592 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4593 | }; | |
4594 | ||
9eeb7a1c RH |
4595 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4596 | { | |
4597 | return env->pstate & PSTATE_UAO; | |
4598 | } | |
4599 | ||
4600 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4601 | uint64_t value) | |
4602 | { | |
4603 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4604 | } | |
4605 | ||
4606 | static const ARMCPRegInfo uao_reginfo = { | |
4607 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4608 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4609 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4610 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4611 | }; | |
4612 | ||
dc8b1853 RC |
4613 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4614 | { | |
4615 | return env->pstate & PSTATE_DIT; | |
4616 | } | |
4617 | ||
4618 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4619 | uint64_t value) | |
4620 | { | |
4621 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4622 | } | |
4623 | ||
4624 | static const ARMCPRegInfo dit_reginfo = { | |
4625 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4626 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4627 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4628 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4629 | }; | |
4630 | ||
f2f68a78 RC |
4631 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4632 | { | |
4633 | return env->pstate & PSTATE_SSBS; | |
4634 | } | |
4635 | ||
4636 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4637 | uint64_t value) | |
4638 | { | |
4639 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4640 | } | |
4641 | ||
4642 | static const ARMCPRegInfo ssbs_reginfo = { | |
4643 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4644 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4645 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4646 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4647 | }; | |
4648 | ||
38262d8a RH |
4649 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4650 | const ARMCPRegInfo *ri, | |
4651 | bool isread) | |
8af35c37 | 4652 | { |
38262d8a RH |
4653 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4654 | switch (arm_current_el(env)) { | |
4655 | case 0: | |
4656 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4657 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4658 | return CP_ACCESS_TRAP; | |
4659 | } | |
4660 | /* fall through */ | |
4661 | case 1: | |
4662 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4663 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4664 | return CP_ACCESS_TRAP_EL2; | |
4665 | } | |
4666 | break; | |
8af35c37 PM |
4667 | } |
4668 | return CP_ACCESS_OK; | |
4669 | } | |
4670 | ||
2d3ce4c6 | 4671 | static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) |
1bed4d2e | 4672 | { |
38262d8a | 4673 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4674 | switch (arm_current_el(env)) { |
4675 | case 0: | |
4676 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4677 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4678 | return CP_ACCESS_TRAP; | |
4679 | } | |
4680 | /* fall through */ | |
4681 | case 1: | |
2d3ce4c6 PM |
4682 | /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ |
4683 | if (arm_hcr_el2_eff(env) & hcrflags) { | |
1bed4d2e RH |
4684 | return CP_ACCESS_TRAP_EL2; |
4685 | } | |
4686 | break; | |
4687 | } | |
4688 | return CP_ACCESS_OK; | |
4689 | } | |
4690 | ||
2d3ce4c6 PM |
4691 | static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, |
4692 | bool isread) | |
4693 | { | |
4694 | return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); | |
4695 | } | |
4696 | ||
4697 | static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, | |
4698 | bool isread) | |
4699 | { | |
4700 | return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); | |
4701 | } | |
4702 | ||
9b37a28c FR |
4703 | /* |
4704 | * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | |
dbb1fb27 AB |
4705 | * Page D4-1736 (DDI0487A.b) |
4706 | */ | |
4707 | ||
b7e0730d RH |
4708 | static int vae1_tlbmask(CPUARMState *env) |
4709 | { | |
e04a5752 | 4710 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4711 | uint16_t mask; |
e04a5752 RDC |
4712 | |
4713 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4714 | mask = ARMMMUIdxBit_E20_2 | |
4715 | ARMMMUIdxBit_E20_2_PAN | | |
4716 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4717 | } else { |
bc944d3a | 4718 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4719 | ARMMMUIdxBit_E10_1_PAN | |
4720 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4721 | } |
bc944d3a | 4722 | return mask; |
b7e0730d RH |
4723 | } |
4724 | ||
ceaa9746 JPB |
4725 | static int vae2_tlbmask(CPUARMState *env) |
4726 | { | |
4727 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4728 | uint16_t mask; | |
4729 | ||
4730 | if (hcr & HCR_E2H) { | |
4731 | mask = ARMMMUIdxBit_E20_2 | | |
4732 | ARMMMUIdxBit_E20_2_PAN | | |
4733 | ARMMMUIdxBit_E20_0; | |
4734 | } else { | |
4735 | mask = ARMMMUIdxBit_E2; | |
4736 | } | |
4737 | return mask; | |
4738 | } | |
4739 | ||
ea04dce7 RH |
4740 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4741 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4742 | uint64_t addr) | |
4743 | { | |
c1547bba | 4744 | uint64_t tcr = regime_tcr(env, mmu_idx); |
ea04dce7 RH |
4745 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); |
4746 | int select = extract64(addr, 55, 1); | |
4747 | ||
4748 | return (tbi >> select) & 1 ? 56 : 64; | |
4749 | } | |
4750 | ||
4751 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4752 | { | |
b6ad6062 | 4753 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4754 | ARMMMUIdx mmu_idx; |
4755 | ||
4756 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4757 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4758 | mmu_idx = ARMMMUIdx_E20_0; |
4759 | } else { | |
4760 | mmu_idx = ARMMMUIdx_E10_0; | |
4761 | } | |
b6ad6062 | 4762 | |
ea04dce7 RH |
4763 | return tlbbits_for_regime(env, mmu_idx, addr); |
4764 | } | |
4765 | ||
ceaa9746 JPB |
4766 | static int vae2_tlbbits(CPUARMState *env, uint64_t addr) |
4767 | { | |
4768 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4769 | ARMMMUIdx mmu_idx; | |
4770 | ||
4771 | /* | |
4772 | * Only the regime of the mmu_idx below is significant. | |
4773 | * Regime EL2&0 has two ranges with separate TBI configuration, while EL2 | |
4774 | * only has one. | |
4775 | */ | |
4776 | if (hcr & HCR_E2H) { | |
4777 | mmu_idx = ARMMMUIdx_E20_2; | |
4778 | } else { | |
4779 | mmu_idx = ARMMMUIdx_E2; | |
4780 | } | |
4781 | ||
4782 | return tlbbits_for_regime(env, mmu_idx, addr); | |
4783 | } | |
4784 | ||
fd3ed969 PM |
4785 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4786 | uint64_t value) | |
168aa23b | 4787 | { |
29a0af61 | 4788 | CPUState *cs = env_cpu(env); |
b7e0730d | 4789 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4790 | |
b7e0730d | 4791 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4792 | } |
4793 | ||
b4ab8ce9 PM |
4794 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4795 | uint64_t value) | |
4796 | { | |
29a0af61 | 4797 | CPUState *cs = env_cpu(env); |
b7e0730d | 4798 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4799 | |
4800 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4801 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4802 | } else { | |
4803 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4804 | } |
b4ab8ce9 PM |
4805 | } |
4806 | ||
85d0dc9f RH |
4807 | static int e2_tlbmask(CPUARMState *env) |
4808 | { | |
d902ae75 RH |
4809 | return (ARMMMUIdxBit_E20_0 | |
4810 | ARMMMUIdxBit_E20_2 | | |
4811 | ARMMMUIdxBit_E20_2_PAN | | |
4812 | ARMMMUIdxBit_E2); | |
85d0dc9f RH |
4813 | } |
4814 | ||
90c19cdf RH |
4815 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4816 | uint64_t value) | |
4817 | { | |
4818 | CPUState *cs = env_cpu(env); | |
4819 | int mask = alle1_tlbmask(env); | |
4820 | ||
4821 | tlb_flush_by_mmuidx(cs, mask); | |
4822 | } | |
4823 | ||
fd3ed969 | 4824 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4825 | uint64_t value) |
4826 | { | |
85d0dc9f RH |
4827 | CPUState *cs = env_cpu(env); |
4828 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4829 | |
85d0dc9f | 4830 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4831 | } |
4832 | ||
43efaa33 PM |
4833 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4834 | uint64_t value) | |
4835 | { | |
2fc0cc0e | 4836 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4837 | CPUState *cs = CPU(cpu); |
4838 | ||
d902ae75 | 4839 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4840 | } |
4841 | ||
fd3ed969 PM |
4842 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4843 | uint64_t value) | |
4844 | { | |
29a0af61 | 4845 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4846 | int mask = alle1_tlbmask(env); |
4847 | ||
4848 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4849 | } |
4850 | ||
2bfb9d75 PM |
4851 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4852 | uint64_t value) | |
4853 | { | |
29a0af61 | 4854 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4855 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4856 | |
85d0dc9f | 4857 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4858 | } |
4859 | ||
43efaa33 PM |
4860 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4861 | uint64_t value) | |
4862 | { | |
29a0af61 | 4863 | CPUState *cs = env_cpu(env); |
43efaa33 | 4864 | |
d902ae75 | 4865 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4866 | } |
4867 | ||
fd3ed969 PM |
4868 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4869 | uint64_t value) | |
fa439fc5 | 4870 | { |
9b37a28c FR |
4871 | /* |
4872 | * Invalidate by VA, EL2 | |
fd3ed969 PM |
4873 | * Currently handles both VAE2 and VALE2, since we don't support |
4874 | * flush-last-level-only. | |
4875 | */ | |
85d0dc9f | 4876 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4877 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4878 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4879 | int bits = vae2_tlbbits(env, pageaddr); |
fd3ed969 | 4880 | |
ceaa9746 | 4881 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
fd3ed969 PM |
4882 | } |
4883 | ||
43efaa33 PM |
4884 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4885 | uint64_t value) | |
4886 | { | |
9b37a28c FR |
4887 | /* |
4888 | * Invalidate by VA, EL3 | |
43efaa33 PM |
4889 | * Currently handles both VAE3 and VALE3, since we don't support |
4890 | * flush-last-level-only. | |
4891 | */ | |
2fc0cc0e | 4892 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4893 | CPUState *cs = CPU(cpu); |
4894 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4895 | ||
d902ae75 | 4896 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); |
43efaa33 PM |
4897 | } |
4898 | ||
fd3ed969 PM |
4899 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4900 | uint64_t value) | |
4901 | { | |
90c19cdf RH |
4902 | CPUState *cs = env_cpu(env); |
4903 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4904 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4905 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4906 | |
ea04dce7 | 4907 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4908 | } |
4909 | ||
b4ab8ce9 PM |
4910 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4911 | uint64_t value) | |
4912 | { | |
9b37a28c FR |
4913 | /* |
4914 | * Invalidate by VA, EL1&0 (AArch64 version). | |
b4ab8ce9 PM |
4915 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, |
4916 | * since we don't support flush-for-specific-ASID-only or | |
4917 | * flush-last-level-only. | |
4918 | */ | |
90c19cdf RH |
4919 | CPUState *cs = env_cpu(env); |
4920 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4921 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4922 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4923 | |
4924 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4925 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4926 | } else { |
ea04dce7 | 4927 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4928 | } |
b4ab8ce9 PM |
4929 | } |
4930 | ||
fd3ed969 PM |
4931 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4932 | uint64_t value) | |
fa439fc5 | 4933 | { |
29a0af61 | 4934 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4935 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4936 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4937 | int bits = vae2_tlbbits(env, pageaddr); |
fa439fc5 | 4938 | |
ceaa9746 | 4939 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4940 | } |
4941 | ||
43efaa33 PM |
4942 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4943 | uint64_t value) | |
4944 | { | |
29a0af61 | 4945 | CPUState *cs = env_cpu(env); |
43efaa33 | 4946 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
d902ae75 | 4947 | int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); |
43efaa33 | 4948 | |
ea04dce7 | 4949 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
d902ae75 | 4950 | ARMMMUIdxBit_E3, bits); |
43efaa33 PM |
4951 | } |
4952 | ||
575a94af RH |
4953 | static int ipas2e1_tlbmask(CPUARMState *env, int64_t value) |
4954 | { | |
4955 | /* | |
4956 | * The MSB of value is the NS field, which only applies if SEL2 | |
4957 | * is implemented and SCR_EL3.NS is not set (i.e. in secure mode). | |
4958 | */ | |
4959 | return (value >= 0 | |
4960 | && cpu_isar_feature(aa64_sel2, env_archcpu(env)) | |
4961 | && arm_is_secure_below_el3(env) | |
4962 | ? ARMMMUIdxBit_Stage2_S | |
4963 | : ARMMMUIdxBit_Stage2); | |
4964 | } | |
4965 | ||
4966 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4967 | uint64_t value) | |
4968 | { | |
4969 | CPUState *cs = env_cpu(env); | |
4970 | int mask = ipas2e1_tlbmask(env, value); | |
4971 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4972 | ||
4973 | if (tlb_force_broadcast(env)) { | |
4974 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
4975 | } else { | |
4976 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); | |
4977 | } | |
4978 | } | |
4979 | ||
4980 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4981 | uint64_t value) | |
4982 | { | |
4983 | CPUState *cs = env_cpu(env); | |
4984 | int mask = ipas2e1_tlbmask(env, value); | |
4985 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4986 | ||
4987 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
4988 | } | |
4989 | ||
84940ed8 | 4990 | #ifdef TARGET_AARCH64 |
ab1cdb47 RH |
4991 | typedef struct { |
4992 | uint64_t base; | |
84940ed8 | 4993 | uint64_t length; |
ab1cdb47 RH |
4994 | } TLBIRange; |
4995 | ||
3c003f70 PM |
4996 | static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg) |
4997 | { | |
4998 | /* | |
4999 | * Note that the TLBI range TG field encoding differs from both | |
5000 | * TG0 and TG1 encodings. | |
5001 | */ | |
5002 | switch (tg) { | |
5003 | case 1: | |
5004 | return Gran4K; | |
5005 | case 2: | |
5006 | return Gran16K; | |
5007 | case 3: | |
5008 | return Gran64K; | |
5009 | default: | |
5010 | return GranInvalid; | |
5011 | } | |
5012 | } | |
5013 | ||
ab1cdb47 RH |
5014 | static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
5015 | uint64_t value) | |
5016 | { | |
5017 | unsigned int page_size_granule, page_shift, num, scale, exponent; | |
3974ff93 RH |
5018 | /* Extract one bit to represent the va selector in use. */ |
5019 | uint64_t select = sextract64(value, 36, 1); | |
478dccbb | 5020 | ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); |
ab1cdb47 | 5021 | TLBIRange ret = { }; |
3c003f70 | 5022 | ARMGranuleSize gran; |
84940ed8 | 5023 | |
84940ed8 | 5024 | page_size_granule = extract64(value, 46, 2); |
3c003f70 | 5025 | gran = tlbi_range_tg_to_gran_size(page_size_granule); |
84940ed8 | 5026 | |
3974ff93 | 5027 | /* The granule encoded in value must match the granule in use. */ |
3c003f70 | 5028 | if (gran != param.gran) { |
3974ff93 | 5029 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", |
84940ed8 | 5030 | page_size_granule); |
ab1cdb47 | 5031 | return ret; |
84940ed8 RC |
5032 | } |
5033 | ||
3c003f70 | 5034 | page_shift = arm_granule_bits(gran); |
ab1cdb47 RH |
5035 | num = extract64(value, 39, 5); |
5036 | scale = extract64(value, 44, 2); | |
84940ed8 | 5037 | exponent = (5 * scale) + 1; |
84940ed8 | 5038 | |
ab1cdb47 | 5039 | ret.length = (num + 1) << (exponent + page_shift); |
84940ed8 | 5040 | |
3974ff93 | 5041 | if (param.select) { |
d976de21 | 5042 | ret.base = sextract64(value, 0, 37); |
84940ed8 | 5043 | } else { |
d976de21 | 5044 | ret.base = extract64(value, 0, 37); |
84940ed8 | 5045 | } |
ef56c242 RH |
5046 | if (param.ds) { |
5047 | /* | |
5048 | * With DS=1, BaseADDR is always shifted 16 so that it is able | |
5049 | * to address all 52 va bits. The input address is perforce | |
5050 | * aligned on a 64k boundary regardless of translation granule. | |
5051 | */ | |
5052 | page_shift = 16; | |
5053 | } | |
d976de21 | 5054 | ret.base <<= page_shift; |
84940ed8 | 5055 | |
ab1cdb47 | 5056 | return ret; |
84940ed8 RC |
5057 | } |
5058 | ||
5059 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
5060 | int idxmap, bool synced) | |
5061 | { | |
5062 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
ab1cdb47 | 5063 | TLBIRange range; |
84940ed8 RC |
5064 | int bits; |
5065 | ||
ab1cdb47 RH |
5066 | range = tlbi_aa64_get_range(env, one_idx, value); |
5067 | bits = tlbbits_for_regime(env, one_idx, range.base); | |
84940ed8 RC |
5068 | |
5069 | if (synced) { | |
5070 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
ab1cdb47 RH |
5071 | range.base, |
5072 | range.length, | |
84940ed8 RC |
5073 | idxmap, |
5074 | bits); | |
5075 | } else { | |
ab1cdb47 RH |
5076 | tlb_flush_range_by_mmuidx(env_cpu(env), range.base, |
5077 | range.length, idxmap, bits); | |
84940ed8 RC |
5078 | } |
5079 | } | |
5080 | ||
5081 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
5082 | const ARMCPRegInfo *ri, | |
5083 | uint64_t value) | |
5084 | { | |
5085 | /* | |
5086 | * Invalidate by VA range, EL1&0. | |
5087 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
5088 | * since we don't support flush-for-specific-ASID-only or | |
5089 | * flush-last-level-only. | |
5090 | */ | |
5091 | ||
5092 | do_rvae_write(env, value, vae1_tlbmask(env), | |
5093 | tlb_force_broadcast(env)); | |
5094 | } | |
5095 | ||
5096 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
5097 | const ARMCPRegInfo *ri, | |
5098 | uint64_t value) | |
5099 | { | |
5100 | /* | |
5101 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
5102 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
5103 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
5104 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
5105 | * shareable specific flushes. | |
5106 | */ | |
5107 | ||
5108 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
5109 | } | |
5110 | ||
84940ed8 RC |
5111 | static void tlbi_aa64_rvae2_write(CPUARMState *env, |
5112 | const ARMCPRegInfo *ri, | |
5113 | uint64_t value) | |
5114 | { | |
5115 | /* | |
5116 | * Invalidate by VA range, EL2. | |
5117 | * Currently handles all of RVAE2 and RVALE2, | |
5118 | * since we don't support flush-for-specific-ASID-only or | |
5119 | * flush-last-level-only. | |
5120 | */ | |
5121 | ||
5122 | do_rvae_write(env, value, vae2_tlbmask(env), | |
5123 | tlb_force_broadcast(env)); | |
5124 | ||
5125 | ||
5126 | } | |
5127 | ||
5128 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
5129 | const ARMCPRegInfo *ri, | |
5130 | uint64_t value) | |
5131 | { | |
5132 | /* | |
5133 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
5134 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
5135 | * since we don't support flush-for-specific-ASID-only, | |
5136 | * flush-last-level-only or inner/outer shareable specific flushes. | |
5137 | */ | |
5138 | ||
5139 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
5140 | ||
5141 | } | |
5142 | ||
5143 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
5144 | const ARMCPRegInfo *ri, | |
5145 | uint64_t value) | |
5146 | { | |
5147 | /* | |
5148 | * Invalidate by VA range, EL3. | |
5149 | * Currently handles all of RVAE3 and RVALE3, | |
5150 | * since we don't support flush-for-specific-ASID-only or | |
5151 | * flush-last-level-only. | |
5152 | */ | |
5153 | ||
d902ae75 | 5154 | do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); |
84940ed8 RC |
5155 | } |
5156 | ||
5157 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
5158 | const ARMCPRegInfo *ri, | |
5159 | uint64_t value) | |
5160 | { | |
5161 | /* | |
5162 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
5163 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
5164 | * since we don't support flush-for-specific-ASID-only, | |
5165 | * flush-last-level-only or inner/outer specific flushes. | |
5166 | */ | |
5167 | ||
d902ae75 | 5168 | do_rvae_write(env, value, ARMMMUIdxBit_E3, true); |
84940ed8 | 5169 | } |
575a94af RH |
5170 | |
5171 | static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5172 | uint64_t value) | |
5173 | { | |
5174 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), | |
5175 | tlb_force_broadcast(env)); | |
5176 | } | |
5177 | ||
5178 | static void tlbi_aa64_ripas2e1is_write(CPUARMState *env, | |
5179 | const ARMCPRegInfo *ri, | |
5180 | uint64_t value) | |
5181 | { | |
5182 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true); | |
5183 | } | |
84940ed8 RC |
5184 | #endif |
5185 | ||
3f208fd7 PM |
5186 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5187 | bool isread) | |
aca3f40b | 5188 | { |
4351cb72 RH |
5189 | int cur_el = arm_current_el(env); |
5190 | ||
5191 | if (cur_el < 2) { | |
5192 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5193 | ||
5194 | if (cur_el == 0) { | |
5195 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5196 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
5197 | return CP_ACCESS_TRAP_EL2; | |
5198 | } | |
5199 | } else { | |
5200 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
5201 | return CP_ACCESS_TRAP; | |
5202 | } | |
5203 | if (hcr & HCR_TDZ) { | |
5204 | return CP_ACCESS_TRAP_EL2; | |
5205 | } | |
5206 | } | |
5207 | } else if (hcr & HCR_TDZ) { | |
5208 | return CP_ACCESS_TRAP_EL2; | |
5209 | } | |
aca3f40b PM |
5210 | } |
5211 | return CP_ACCESS_OK; | |
5212 | } | |
5213 | ||
5214 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5215 | { | |
2fc0cc0e | 5216 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
5217 | int dzp_bit = 1 << 4; |
5218 | ||
5219 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 5220 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
5221 | dzp_bit = 0; |
5222 | } | |
5223 | return cpu->dcz_blocksize | dzp_bit; | |
5224 | } | |
5225 | ||
3f208fd7 PM |
5226 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5227 | bool isread) | |
f502cfc2 | 5228 | { |
cdcf1405 | 5229 | if (!(env->pstate & PSTATE_SP)) { |
9b37a28c FR |
5230 | /* |
5231 | * Access to SP_EL0 is undefined if it's being used as | |
f502cfc2 PM |
5232 | * the stack pointer. |
5233 | */ | |
5234 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5235 | } | |
5236 | return CP_ACCESS_OK; | |
5237 | } | |
5238 | ||
5239 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5240 | { | |
5241 | return env->pstate & PSTATE_SP; | |
5242 | } | |
5243 | ||
5244 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
5245 | { | |
5246 | update_spsel(env, val); | |
5247 | } | |
5248 | ||
137feaa9 FA |
5249 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5250 | uint64_t value) | |
5251 | { | |
2fc0cc0e | 5252 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 5253 | |
f00faf13 RH |
5254 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
5255 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
5256 | value &= ~SCTLR_M; | |
5257 | } | |
5258 | ||
5259 | /* ??? Lots of these bits are not implemented. */ | |
5260 | ||
5261 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
5262 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
5263 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
5264 | } else { | |
5265 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
5266 | SCTLR_ATA0 | SCTLR_ATA); | |
5267 | } | |
5268 | } | |
5269 | ||
137feaa9 | 5270 | if (raw_read(env, ri) == value) { |
9b37a28c FR |
5271 | /* |
5272 | * Skip the TLB flush if nothing actually changed; Linux likes | |
137feaa9 FA |
5273 | * to do a lot of pointless SCTLR writes. |
5274 | */ | |
5275 | return; | |
5276 | } | |
5277 | ||
5278 | raw_write(env, ri, value); | |
f00faf13 | 5279 | |
137feaa9 | 5280 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 5281 | tlb_flush(CPU(cpu)); |
2e5dcf36 | 5282 | |
2b77ad4d | 5283 | if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { |
2e5dcf36 RH |
5284 | /* |
5285 | * Normally we would always end the TB on an SCTLR write; see the | |
5286 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
5287 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
5288 | * of hflags from the translator, so do it here. | |
5289 | */ | |
5290 | arm_rebuild_hflags(env); | |
5291 | } | |
137feaa9 FA |
5292 | } |
5293 | ||
80d2b43b PM |
5294 | static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5295 | uint64_t value) | |
a8d64e73 | 5296 | { |
01765386 PM |
5297 | /* |
5298 | * Some MDCR_EL3 bits affect whether PMU counters are running: | |
5299 | * if we are trying to change any of those then we must | |
5300 | * bracket this update with PMU start/finish calls. | |
5301 | */ | |
5302 | bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; | |
5303 | ||
5304 | if (pmu_op) { | |
5305 | pmu_op_start(env); | |
5306 | } | |
80d2b43b | 5307 | env->cp15.mdcr_el3 = value; |
01765386 PM |
5308 | if (pmu_op) { |
5309 | pmu_op_finish(env); | |
5310 | } | |
5311 | } | |
5312 | ||
80d2b43b PM |
5313 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5314 | uint64_t value) | |
5315 | { | |
5316 | /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */ | |
5317 | mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); | |
5318 | } | |
5319 | ||
01765386 PM |
5320 | static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5321 | uint64_t value) | |
5322 | { | |
5323 | /* | |
5324 | * Some MDCR_EL2 bits affect whether PMU counters are running: | |
5325 | * if we are trying to change any of those then we must | |
5326 | * bracket this update with PMU start/finish calls. | |
5327 | */ | |
5328 | bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; | |
5329 | ||
5330 | if (pmu_op) { | |
5331 | pmu_op_start(env); | |
5332 | } | |
5333 | env->cp15.mdcr_el2 = value; | |
5334 | if (pmu_op) { | |
5335 | pmu_op_finish(env); | |
5336 | } | |
a8d64e73 PM |
5337 | } |
5338 | ||
9719f125 JH |
5339 | #ifdef CONFIG_USER_ONLY |
5340 | /* | |
5341 | * `IC IVAU` is handled to improve compatibility with JITs that dual-map their | |
5342 | * code to get around W^X restrictions, where one region is writable and the | |
5343 | * other is executable. | |
5344 | * | |
5345 | * Since the executable region is never written to we cannot detect code | |
5346 | * changes when running in user mode, and rely on the emulated JIT telling us | |
5347 | * that the code has changed by executing this instruction. | |
5348 | */ | |
5349 | static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5350 | uint64_t value) | |
5351 | { | |
5352 | uint64_t icache_line_mask, start_address, end_address; | |
5353 | const ARMCPU *cpu; | |
5354 | ||
5355 | cpu = env_archcpu(env); | |
5356 | ||
5357 | icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; | |
5358 | start_address = value & ~icache_line_mask; | |
5359 | end_address = value | icache_line_mask; | |
5360 | ||
5361 | mmap_lock(); | |
5362 | ||
5363 | tb_invalidate_phys_range(start_address, end_address); | |
5364 | ||
5365 | mmap_unlock(); | |
5366 | } | |
5367 | #endif | |
5368 | ||
b0d2b7d0 | 5369 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
9b37a28c FR |
5370 | /* |
5371 | * Minimal set of EL0-visible registers. This will need to be expanded | |
b0d2b7d0 PM |
5372 | * significantly for system emulation of AArch64 CPUs. |
5373 | */ | |
5374 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
5375 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
5376 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
5377 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
5378 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 5379 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
5380 | .access = PL0_RW, .accessfn = aa64_daif_access, |
5381 | .fieldoffset = offsetof(CPUARMState, daif), | |
5382 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
5383 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
5384 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 5385 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5386 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
5387 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
5388 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 5389 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5390 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
5391 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
5392 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 5393 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
b19ed03c | 5394 | .fgt = FGT_DCZID_EL0, |
aca3f40b PM |
5395 | .readfn = aa64_dczid_read }, |
5396 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
5397 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
5398 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
5399 | #ifndef CONFIG_USER_ONLY | |
5400 | /* Avoid overhead of an access check that always passes in user-mode */ | |
5401 | .accessfn = aa64_zva_access, | |
dd345653 | 5402 | .fgt = FGT_DCZVA, |
aca3f40b PM |
5403 | #endif |
5404 | }, | |
0eef9d98 PM |
5405 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
5406 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
5407 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
9719f125 JH |
5408 | /* |
5409 | * Instruction cache ops. All of these except `IC IVAU` NOP because we | |
5410 | * don't emulate caches. | |
5411 | */ | |
8af35c37 PM |
5412 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, |
5413 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5414 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5415 | .fgt = FGT_ICIALLUIS, |
2d3ce4c6 | 5416 | .accessfn = access_ticab }, |
8af35c37 PM |
5417 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
5418 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5419 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5420 | .fgt = FGT_ICIALLU, |
2d3ce4c6 | 5421 | .accessfn = access_tocu }, |
8af35c37 PM |
5422 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
5423 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
9719f125 | 5424 | .access = PL0_W, |
dd345653 | 5425 | .fgt = FGT_ICIVAU, |
9719f125 JH |
5426 | .accessfn = access_tocu, |
5427 | #ifdef CONFIG_USER_ONLY | |
5428 | .type = ARM_CP_NO_RAW, | |
5429 | .writefn = ic_ivau_write | |
5430 | #else | |
5431 | .type = ARM_CP_NOP | |
5432 | #endif | |
5433 | }, | |
5434 | /* Cache ops: all NOPs since we don't emulate caches */ | |
8af35c37 PM |
5435 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
5436 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5437 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
dd345653 | 5438 | .fgt = FGT_DCIVAC, |
1bed4d2e | 5439 | .type = ARM_CP_NOP }, |
8af35c37 PM |
5440 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
5441 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
dd345653 | 5442 | .fgt = FGT_DCISW, |
1803d271 | 5443 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5444 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
5445 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
5446 | .access = PL0_W, .type = ARM_CP_NOP, | |
950037e2 | 5447 | .fgt = FGT_DCCVAC, |
1bed4d2e | 5448 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5449 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
5450 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
dd345653 | 5451 | .fgt = FGT_DCCSW, |
1803d271 | 5452 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5453 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
5454 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
5455 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5456 | .fgt = FGT_DCCVAU, |
2d3ce4c6 | 5457 | .accessfn = access_tocu }, |
8af35c37 PM |
5458 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
5459 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
5460 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5461 | .fgt = FGT_DCCIVAC, |
1bed4d2e | 5462 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5463 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
5464 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
dd345653 | 5465 | .fgt = FGT_DCCISW, |
1803d271 | 5466 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
5467 | /* TLBI operations */ |
5468 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 5469 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
0f66d223 | 5470 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5471 | .fgt = FGT_TLBIVMALLE1IS, |
fd3ed969 | 5472 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5473 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5474 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 5475 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5476 | .fgt = FGT_TLBIVAE1IS, |
fd3ed969 | 5477 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5478 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5479 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 5480 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5481 | .fgt = FGT_TLBIASIDE1IS, |
fd3ed969 | 5482 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5483 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5484 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 5485 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5486 | .fgt = FGT_TLBIVAAE1IS, |
fd3ed969 | 5487 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5488 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5489 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5490 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5491 | .fgt = FGT_TLBIVALE1IS, |
fd3ed969 | 5492 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5493 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5494 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5495 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5496 | .fgt = FGT_TLBIVAALE1IS, |
fd3ed969 | 5497 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5498 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5499 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 5500 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5501 | .fgt = FGT_TLBIVMALLE1, |
fd3ed969 | 5502 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5503 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5504 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 5505 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5506 | .fgt = FGT_TLBIVAE1, |
fd3ed969 | 5507 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5508 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5509 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 5510 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5511 | .fgt = FGT_TLBIASIDE1, |
fd3ed969 | 5512 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5513 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5514 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 5515 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5516 | .fgt = FGT_TLBIVAAE1, |
fd3ed969 | 5517 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5518 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5519 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 5520 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5521 | .fgt = FGT_TLBIVALE1, |
fd3ed969 | 5522 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5523 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5524 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 5525 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5526 | .fgt = FGT_TLBIVAALE1, |
fd3ed969 | 5527 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
5528 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
5529 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5530 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5531 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
cea66e91 PM |
5532 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
5533 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5534 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5535 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
5536 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
5537 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5538 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5539 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
5540 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
5541 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
5542 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5543 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
5544 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
5545 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5546 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5547 | .writefn = tlbi_aa64_ipas2e1_write }, | |
cea66e91 PM |
5548 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
5549 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5550 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5551 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
5552 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
5553 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5554 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5555 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
5556 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
5557 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
5558 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5559 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
5560 | #ifndef CONFIG_USER_ONLY |
5561 | /* 64 bit address translation operations */ | |
5562 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
5563 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa | 5564 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5565 | .fgt = FGT_ATS1E1R, |
1acd00ef | 5566 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5567 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
5568 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa | 5569 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5570 | .fgt = FGT_ATS1E1W, |
1acd00ef | 5571 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5572 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
5573 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa | 5574 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5575 | .fgt = FGT_ATS1E0R, |
1acd00ef | 5576 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5577 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
5578 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa | 5579 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5580 | .fgt = FGT_ATS1E0W, |
1acd00ef | 5581 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5582 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5583 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa | 5584 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5585 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5586 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5587 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa | 5588 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5589 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5590 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5591 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa | 5592 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5593 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5594 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5595 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa | 5596 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5597 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 PM |
5598 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
5599 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
5600 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
5601 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5602 | .writefn = ats_write64 }, | |
2a47df95 PM |
5603 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
5604 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
5605 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5606 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
5607 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
5608 | .type = ARM_CP_ALIAS, | |
5609 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
5610 | .access = PL1_RW, .resetvalue = 0, | |
67dd8030 | 5611 | .fgt = FGT_PAR_EL1, |
c96fc9b5 EI |
5612 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), |
5613 | .writefn = par_write }, | |
19525524 | 5614 | #endif |
995939a6 | 5615 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 5616 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5617 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 5618 | .writefn = tlbimva_is_write }, |
9449fdf6 | 5619 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5620 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 5621 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 5622 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
5623 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5624 | .writefn = tlbimva_write }, | |
9449fdf6 | 5625 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
5626 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5627 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
5628 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
5629 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5630 | .writefn = tlbimva_hyp_write }, | |
5631 | { .name = "TLBIMVALHIS", | |
5632 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5633 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5634 | .writefn = tlbimva_hyp_is_write }, | |
5635 | { .name = "TLBIIPAS2", | |
5636 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5637 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5638 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5639 | { .name = "TLBIIPAS2IS", |
5640 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5641 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5642 | .writefn = tlbiipas2is_hyp_write }, | |
541ef8c2 SS |
5643 | { .name = "TLBIIPAS2L", |
5644 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5645 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5646 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5647 | { .name = "TLBIIPAS2LIS", |
5648 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5649 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5650 | .writefn = tlbiipas2is_hyp_write }, | |
9449fdf6 PM |
5651 | /* 32 bit cache operations */ |
5652 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2d3ce4c6 | 5653 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab }, |
9449fdf6 PM |
5654 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5655 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5656 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2d3ce4c6 | 5657 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5658 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
2d3ce4c6 | 5659 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 PM |
5660 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5661 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5662 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5663 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5664 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5665 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5666 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5667 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5668 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5669 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5670 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5671 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5672 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
2d3ce4c6 | 5673 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5674 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5675 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5676 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5677 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5678 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5679 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5680 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5681 | .writefn = dacr_write, .raw_writefn = raw_write, |
5682 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5683 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5684 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5685 | .type = ARM_CP_ALIAS, |
a0618a19 | 5686 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5687 | .access = PL1_RW, |
5688 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5689 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5690 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5691 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5692 | .access = PL1_RW, |
5693 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
9b37a28c FR |
5694 | /* |
5695 | * We rely on the access checks not allowing the guest to write to the | |
f502cfc2 PM |
5696 | * state field when SPSel indicates that it's being used as the stack |
5697 | * pointer. | |
5698 | */ | |
5699 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5700 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5701 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5702 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5703 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5704 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5705 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
beeec926 | 5706 | .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, |
884b4dee | 5707 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5708 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5709 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5710 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5711 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
5712 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
5713 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
696ba377 RH |
5714 | .access = PL2_RW, |
5715 | .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | |
a4c88675 | 5716 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, |
6a43e0b6 PM |
5717 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
5718 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
696ba377 | 5719 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, |
6a43e0b6 PM |
5720 | .writefn = dacr_write, .raw_writefn = raw_write, |
5721 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5722 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5723 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
696ba377 | 5724 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, |
6a43e0b6 PM |
5725 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, |
5726 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
5727 | .type = ARM_CP_ALIAS, | |
5728 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5729 | .access = PL2_RW, | |
5730 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5731 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5732 | .type = ARM_CP_ALIAS, | |
5733 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5734 | .access = PL2_RW, | |
5735 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5736 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5737 | .type = ARM_CP_ALIAS, | |
5738 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5739 | .access = PL2_RW, | |
5740 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5741 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5742 | .type = ARM_CP_ALIAS, | |
5743 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5744 | .access = PL2_RW, | |
5745 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 | 5746 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
80d2b43b | 5747 | .type = ARM_CP_IO, |
a8d64e73 PM |
5748 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, |
5749 | .resetvalue = 0, | |
80d2b43b PM |
5750 | .access = PL3_RW, |
5751 | .writefn = mdcr_el3_write, | |
5752 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
7f4fbfb5 | 5753 | { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO, |
a8d64e73 PM |
5754 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, |
5755 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5756 | .writefn = sdcr_write, | |
5757 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5758 | }; |
5759 | ||
d1fb4da2 | 5760 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5761 | { |
2fc0cc0e | 5762 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5763 | |
5764 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5765 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5766 | } else { | |
5767 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5768 | } | |
f149e3e8 EI |
5769 | |
5770 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5771 | valid_mask &= ~HCR_HCD; | |
77077a83 | 5772 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
9b37a28c FR |
5773 | /* |
5774 | * Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
77077a83 JK |
5775 | * However, if we're using the SMC PSCI conduit then QEMU is |
5776 | * effectively acting like EL3 firmware and so the guest at | |
5777 | * EL2 should retain the ability to prevent EL1 from being | |
5778 | * able to make SMC calls into the ersatz firmware, so in | |
5779 | * that case HCR.TSC should be read/write. | |
5780 | */ | |
f149e3e8 EI |
5781 | valid_mask &= ~HCR_TSC; |
5782 | } | |
d1fb4da2 RH |
5783 | |
5784 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5785 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5786 | valid_mask |= HCR_E2H; | |
5787 | } | |
da3d8b13 RH |
5788 | if (cpu_isar_feature(aa64_ras, cpu)) { |
5789 | valid_mask |= HCR_TERR | HCR_TEA; | |
5790 | } | |
d1fb4da2 RH |
5791 | if (cpu_isar_feature(aa64_lor, cpu)) { |
5792 | valid_mask |= HCR_TLOR; | |
5793 | } | |
5794 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5795 | valid_mask |= HCR_API | HCR_APK; | |
5796 | } | |
8ddb300b RH |
5797 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5798 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5799 | } | |
7cb1e618 RH |
5800 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
5801 | valid_mask |= HCR_ENSCXT; | |
5802 | } | |
8c7e17ef PM |
5803 | if (cpu_isar_feature(aa64_fwb, cpu)) { |
5804 | valid_mask |= HCR_FWB; | |
5805 | } | |
aa3cc42c RH |
5806 | if (cpu_isar_feature(aa64_rme, cpu)) { |
5807 | valid_mask |= HCR_GPF; | |
5808 | } | |
ef682cdb | 5809 | } |
f149e3e8 | 5810 | |
d2fd9313 PM |
5811 | if (cpu_isar_feature(any_evt, cpu)) { |
5812 | valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5813 | } else if (cpu_isar_feature(any_half_evt, cpu)) { | |
5814 | valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5815 | } | |
5816 | ||
f149e3e8 EI |
5817 | /* Clear RES0 bits. */ |
5818 | value &= valid_mask; | |
5819 | ||
8ddb300b RH |
5820 | /* |
5821 | * These bits change the MMU setup: | |
f149e3e8 EI |
5822 | * HCR_VM enables stage 2 translation |
5823 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5824 | * HCR_DC disables stage1 and enables stage2 translation |
5825 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
8c7e17ef | 5826 | * HCR_FWB changes the interpretation of stage2 descriptor bits |
f149e3e8 | 5827 | */ |
8c7e17ef PM |
5828 | if ((env->cp15.hcr_el2 ^ value) & |
5829 | (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { | |
d10eb08f | 5830 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5831 | } |
ce4afed8 | 5832 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5833 | |
5834 | /* | |
5835 | * Updates to VI and VF require us to update the status of | |
5836 | * virtual interrupts, which are the logical OR of these bits | |
5837 | * and the state of the input lines from the GIC. (This requires | |
5838 | * that we have the iothread lock, which is done by marking the | |
5839 | * reginfo structs as ARM_CP_IO.) | |
5840 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5841 | * possible for it to be taken immediately, because VIRQ and | |
5842 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5843 | * can only be written at EL2. | |
5844 | */ | |
5845 | g_assert(qemu_mutex_iothread_locked()); | |
5846 | arm_cpu_update_virq(cpu); | |
5847 | arm_cpu_update_vfiq(cpu); | |
3c29632f | 5848 | arm_cpu_update_vserr(cpu); |
ce4afed8 PM |
5849 | } |
5850 | ||
d1fb4da2 RH |
5851 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5852 | { | |
5853 | do_hcr_write(env, value, 0); | |
5854 | } | |
5855 | ||
ce4afed8 PM |
5856 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5857 | uint64_t value) | |
5858 | { | |
5859 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5860 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5861 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5862 | } |
5863 | ||
5864 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5865 | uint64_t value) | |
5866 | { | |
5867 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5868 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5869 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5870 | } |
5871 | ||
f7778444 | 5872 | /* |
b74c0443 | 5873 | * Return the effective value of HCR_EL2, at the given security state. |
f7778444 RH |
5874 | * Bits that are not included here: |
5875 | * RW (read from SCR_EL3.RW as needed) | |
5876 | */ | |
2d12bb96 | 5877 | uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) |
f7778444 RH |
5878 | { |
5879 | uint64_t ret = env->cp15.hcr_el2; | |
5880 | ||
2d12bb96 PM |
5881 | assert(space != ARMSS_Root); |
5882 | ||
4477020d | 5883 | if (!arm_is_el2_enabled_secstate(env, space)) { |
f7778444 RH |
5884 | /* |
5885 | * "This register has no effect if EL2 is not enabled in the | |
5886 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5887 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5888 | * | |
5889 | * Prior to that, the language was "In an implementation that | |
5890 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5891 | * as if this field is 0 for all purposes other than a direct | |
5892 | * read or write access of HCR_EL2". With lots of enumeration | |
5893 | * on a per-field basis. In current QEMU, this is condition | |
5894 | * is arm_is_secure_below_el3. | |
5895 | * | |
5896 | * Since the v8.4 language applies to the entire register, and | |
5897 | * appears to be backward compatible, use that. | |
5898 | */ | |
4990e1d3 RH |
5899 | return 0; |
5900 | } | |
5901 | ||
5902 | /* | |
5903 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5904 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5905 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5906 | */ | |
5907 | if (!arm_el_is_aa64(env, 2)) { | |
5908 | uint64_t aa32_valid; | |
5909 | ||
5910 | /* | |
5911 | * These bits are up-to-date as of ARMv8.6. | |
5912 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5913 | * For HCR2, list those that are valid. | |
5914 | */ | |
5915 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5916 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5917 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5918 | ret &= aa32_valid; | |
5919 | } | |
5920 | ||
5921 | if (ret & HCR_TGE) { | |
5922 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5923 | if (ret & HCR_E2H) { |
5924 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5925 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5926 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5927 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5928 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5929 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5930 | } else { |
5931 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5932 | } | |
5933 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5934 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5935 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5936 | HCR_TLOR); | |
5937 | } | |
5938 | ||
5939 | return ret; | |
5940 | } | |
5941 | ||
b74c0443 RH |
5942 | uint64_t arm_hcr_el2_eff(CPUARMState *env) |
5943 | { | |
a0262ba6 RH |
5944 | if (arm_feature(env, ARM_FEATURE_M)) { |
5945 | return 0; | |
5946 | } | |
2d12bb96 | 5947 | return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); |
b74c0443 RH |
5948 | } |
5949 | ||
19668718 RH |
5950 | /* |
5951 | * Corresponds to ARM pseudocode function ELIsInHost(). | |
5952 | */ | |
5953 | bool el_is_in_host(CPUARMState *env, int el) | |
5954 | { | |
5955 | uint64_t mask; | |
5956 | ||
5957 | /* | |
5958 | * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). | |
5959 | * Perform the simplest bit tests first, and validate EL2 afterward. | |
5960 | */ | |
5961 | if (el & 1) { | |
5962 | return false; /* EL1 or EL3 */ | |
5963 | } | |
5964 | ||
5965 | /* | |
5966 | * Note that hcr_write() checks isar_feature_aa64_vh(), | |
5967 | * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. | |
5968 | */ | |
5969 | mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; | |
5970 | if ((env->cp15.hcr_el2 & mask) != mask) { | |
5971 | return false; | |
5972 | } | |
5973 | ||
5974 | /* TGE and/or E2H set: double check those bits are currently legal. */ | |
5975 | return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); | |
5976 | } | |
5977 | ||
5814d587 RH |
5978 | static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5979 | uint64_t value) | |
5980 | { | |
5981 | uint64_t valid_mask = 0; | |
5982 | ||
dbc678f9 PM |
5983 | /* FEAT_MOPS adds MSCEn and MCE2 */ |
5984 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
5985 | valid_mask |= HCRX_MSCEN | HCRX_MCE2; | |
5986 | } | |
5814d587 RH |
5987 | |
5988 | /* Clear RES0 bits. */ | |
5989 | env->cp15.hcrx_el2 = value & valid_mask; | |
5990 | } | |
5991 | ||
5992 | static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | |
5993 | bool isread) | |
5994 | { | |
5995 | if (arm_current_el(env) < 3 | |
5996 | && arm_feature(env, ARM_FEATURE_EL3) | |
5997 | && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5998 | return CP_ACCESS_TRAP_EL3; | |
5999 | } | |
6000 | return CP_ACCESS_OK; | |
6001 | } | |
6002 | ||
6003 | static const ARMCPRegInfo hcrx_el2_reginfo = { | |
6004 | .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, | |
6005 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, | |
6006 | .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, | |
6007 | .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), | |
6008 | }; | |
6009 | ||
6010 | /* Return the effective value of HCRX_EL2. */ | |
6011 | uint64_t arm_hcrx_el2_eff(CPUARMState *env) | |
6012 | { | |
6013 | /* | |
6014 | * The bits in this register behave as 0 for all purposes other than | |
dbc678f9 PM |
6015 | * direct reads of the register if SCR_EL3.HXEn is 0. |
6016 | * If EL2 is not enabled in the current security state, then the | |
6017 | * bit may behave as if 0, or as if 1, depending on the bit. | |
6018 | * For the moment, we treat the EL2-disabled case as taking | |
6019 | * priority over the HXEn-disabled case. This is true for the only | |
6020 | * bit for a feature which we implement where the answer is different | |
6021 | * for the two cases (MSCEn for FEAT_MOPS). | |
6022 | * This may need to be revisited for future bits. | |
5814d587 | 6023 | */ |
dbc678f9 PM |
6024 | if (!arm_is_el2_enabled(env)) { |
6025 | uint64_t hcrx = 0; | |
6026 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
6027 | /* MSCEn behaves as 1 if EL2 is not enabled */ | |
6028 | hcrx |= HCRX_MSCEN; | |
6029 | } | |
6030 | return hcrx; | |
6031 | } | |
6032 | if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5814d587 RH |
6033 | return 0; |
6034 | } | |
6035 | return env->cp15.hcrx_el2; | |
6036 | } | |
6037 | ||
fc1120a7 PM |
6038 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6039 | uint64_t value) | |
6040 | { | |
6041 | /* | |
6042 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6043 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6044 | */ | |
6045 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6046 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
6047 | uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
6048 | value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); | |
fc1120a7 PM |
6049 | } |
6050 | env->cp15.cptr_el[2] = value; | |
6051 | } | |
6052 | ||
6053 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6054 | { | |
6055 | /* | |
6056 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6057 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6058 | */ | |
6059 | uint64_t value = env->cp15.cptr_el[2]; | |
6060 | ||
6061 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6062 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 6063 | value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
fc1120a7 PM |
6064 | } |
6065 | return value; | |
6066 | } | |
6067 | ||
4771cd01 | 6068 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 6069 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 6070 | .type = ARM_CP_IO, |
f149e3e8 EI |
6071 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6072 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
587f8b33 | 6073 | .writefn = hcr_write, .raw_writefn = raw_write }, |
ce4afed8 | 6074 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 6075 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6076 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6077 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 6078 | .writefn = hcr_writelow }, |
831a2fca PM |
6079 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
6080 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
6081 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 6082 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6083 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
6084 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
6085 | .access = PL2_RW, | |
6086 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 6087 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
6088 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
6089 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 6090 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
6091 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
6092 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
6093 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
6094 | .type = ARM_CP_ALIAS, | |
6095 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
6096 | .access = PL2_RW, | |
6097 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 6098 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6099 | .type = ARM_CP_ALIAS, |
3b685ba7 | 6100 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6101 | .access = PL2_RW, |
6102 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 6103 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
6104 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
6105 | .access = PL2_RW, .writefn = vbar_write, | |
6106 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
6107 | .resetvalue = 0 }, | |
884b4dee GB |
6108 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
6109 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6110 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 6111 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
6112 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
6113 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
6114 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
6115 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
6116 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
6117 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6118 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
6119 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
6120 | .resetvalue = 0 }, | |
6121 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 6122 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
6123 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
6124 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
6125 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6126 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
6127 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6128 | .resetvalue = 0 }, | |
6129 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 6130 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 6131 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
6132 | .access = PL2_RW, .type = ARM_CP_CONST, |
6133 | .resetvalue = 0 }, | |
37cd6c24 PM |
6134 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
6135 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
6136 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6137 | .resetvalue = 0 }, | |
6138 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
6139 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
6140 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6141 | .resetvalue = 0 }, | |
06ec4c8c EI |
6142 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
6143 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 | 6144 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
587f8b33 | 6145 | .raw_writefn = raw_write, |
06ec4c8c | 6146 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
6147 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
6148 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6149 | .type = ARM_CP_ALIAS, |
68e9c2fe | 6150 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
afbb181c | 6151 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, |
68e9c2fe EI |
6152 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, |
6153 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6154 | .access = PL2_RW, |
988cc190 | 6155 | /* no .writefn needed as this can't cause an ASID change */ |
68e9c2fe | 6156 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
6157 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
6158 | .cp = 15, .opc1 = 6, .crm = 2, | |
6159 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
6160 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6161 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
587f8b33 | 6162 | .writefn = vttbr_write, .raw_writefn = raw_write }, |
b698e9cf EI |
6163 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, |
6164 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
587f8b33 | 6165 | .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, |
b698e9cf | 6166 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, |
b9cb5323 EI |
6167 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
6168 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
6169 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
6170 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
6171 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6172 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
6173 | .access = PL2_RW, .resetvalue = 0, | |
6174 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
6175 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
6176 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
587f8b33 EA |
6177 | .access = PL2_RW, .resetvalue = 0, |
6178 | .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, | |
a57633c0 EI |
6179 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
6180 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
6181 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 6182 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
6183 | { .name = "TLBIALLNSNH", |
6184 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
6185 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6186 | .writefn = tlbiall_nsnh_write }, | |
6187 | { .name = "TLBIALLNSNHIS", | |
6188 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
6189 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6190 | .writefn = tlbiall_nsnh_is_write }, | |
6191 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
6192 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6193 | .writefn = tlbiall_hyp_write }, | |
6194 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
6195 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6196 | .writefn = tlbiall_hyp_is_write }, | |
6197 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
6198 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6199 | .writefn = tlbimva_hyp_write }, | |
6200 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
6201 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6202 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
6203 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
6204 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
696ba377 | 6205 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6206 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
6207 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
6208 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
696ba377 | 6209 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6210 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
6211 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
6212 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
696ba377 | 6213 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 PM |
6214 | .writefn = tlbi_aa64_vae2_write }, |
6215 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
6216 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
696ba377 | 6217 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6218 | .writefn = tlbi_aa64_alle2is_write }, |
8742d49d EI |
6219 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
6220 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
696ba377 | 6221 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6222 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
6223 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
6224 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
696ba377 | 6225 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6226 | .writefn = tlbi_aa64_vae2is_write }, |
edac4d8a | 6227 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
6228 | /* |
6229 | * Unlike the other EL2-related AT operations, these must | |
2a47df95 PM |
6230 | * UNDEF from EL3 if EL2 is not implemented, which is why we |
6231 | * define them here rather than with the rest of the AT ops. | |
6232 | */ | |
6233 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
6234 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6235 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6236 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6237 | .writefn = ats_write64 }, | |
2a47df95 PM |
6238 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
6239 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
6240 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6241 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6242 | .writefn = ats_write64 }, | |
9b37a28c FR |
6243 | /* |
6244 | * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | |
14db7fe0 PM |
6245 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 |
6246 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
6247 | * to behave as if SCR.NS was 1. | |
6248 | */ | |
6249 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6250 | .access = PL2_W, | |
0710b2fa | 6251 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
6252 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
6253 | .access = PL2_W, | |
0710b2fa | 6254 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
6255 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
6256 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
9b37a28c FR |
6257 | /* |
6258 | * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
0b6440af EI |
6259 | * reset values as IMPDEF. We choose to reset to 3 to comply with |
6260 | * both ARMv7 and ARMv8. | |
6261 | */ | |
f6fc36de JPB |
6262 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 3, |
6263 | .writefn = gt_cnthctl_write, .raw_writefn = raw_write, | |
0b6440af | 6264 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, |
edac4d8a EI |
6265 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
6266 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
6267 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
6268 | .writefn = gt_cntvoff_write, | |
6269 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
6270 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
6271 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
6272 | .writefn = gt_cntvoff_write, | |
6273 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
6274 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
6275 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
6276 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6277 | .type = ARM_CP_IO, .access = PL2_RW, | |
6278 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6279 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
6280 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6281 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
6282 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6283 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
6284 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 6285 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
6286 | .resetfn = gt_hyp_timer_reset, |
6287 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
6288 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
6289 | .type = ARM_CP_IO, | |
6290 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
6291 | .access = PL2_RW, | |
6292 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
6293 | .resetvalue = 0, | |
6294 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 6295 | #endif |
59e05530 EI |
6296 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
6297 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6298 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6299 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
6300 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
6301 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6302 | .access = PL2_RW, | |
6303 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
6304 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
6305 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
6306 | .access = PL2_RW, | |
6307 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
6308 | }; |
6309 | ||
ce4afed8 PM |
6310 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
6311 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 6312 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6313 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
6314 | .access = PL2_RW, | |
6315 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
6316 | .writefn = hcr_writehigh }, | |
ce4afed8 PM |
6317 | }; |
6318 | ||
e9152ee9 RDC |
6319 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6320 | bool isread) | |
6321 | { | |
6322 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
6323 | return CP_ACCESS_OK; | |
6324 | } | |
6325 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6326 | } | |
6327 | ||
6328 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
6329 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
6330 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
6331 | .access = PL2_RW, .accessfn = sel2_access, | |
6332 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
6333 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
6334 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
6335 | .access = PL2_RW, .accessfn = sel2_access, | |
6336 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
e9152ee9 RDC |
6337 | }; |
6338 | ||
2f027fc5 PM |
6339 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6340 | bool isread) | |
6341 | { | |
9b37a28c FR |
6342 | /* |
6343 | * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 6344 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
6345 | */ |
6346 | if (arm_current_el(env) == 3) { | |
6347 | return CP_ACCESS_OK; | |
6348 | } | |
6349 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
6350 | if (env->cp15.scr_el3 & SCR_EEL2) { |
6351 | return CP_ACCESS_TRAP_EL2; | |
6352 | } | |
2f027fc5 PM |
6353 | return CP_ACCESS_TRAP_EL3; |
6354 | } | |
6355 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
6356 | if (isread) { | |
6357 | return CP_ACCESS_OK; | |
6358 | } | |
6359 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6360 | } | |
6361 | ||
60fb1a87 GB |
6362 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
6363 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
6364 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
6365 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6366 | .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, |
f80741d1 | 6367 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 6368 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
6369 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6370 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6371 | .writefn = scr_write, .raw_writefn = raw_write }, |
60fb1a87 GB |
6372 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
6373 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
6374 | .access = PL3_RW, .resetvalue = 0, | |
6375 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
6376 | { .name = "SDER", | |
6377 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
6378 | .access = PL3_RW, .resetvalue = 0, | |
6379 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 6380 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
6381 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6382 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 6383 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
6384 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
6385 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 6386 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 6387 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
6388 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
6389 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c | 6390 | .access = PL3_RW, |
cb4a0a34 PM |
6391 | /* no .writefn needed as this can't cause an ASID change */ |
6392 | .resetvalue = 0, | |
11f136ee | 6393 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 6394 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6395 | .type = ARM_CP_ALIAS, |
81547d66 EI |
6396 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
6397 | .access = PL3_RW, | |
6398 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 6399 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
6400 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
6401 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
6402 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
6403 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
6404 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 6405 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6406 | .type = ARM_CP_ALIAS, |
81547d66 | 6407 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6408 | .access = PL3_RW, |
6409 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
6410 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
6411 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
6412 | .access = PL3_RW, .writefn = vbar_write, | |
6413 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
6414 | .resetvalue = 0 }, | |
c6f19164 GB |
6415 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
6416 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
6417 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
6418 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
6419 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
6420 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
6421 | .access = PL3_RW, .resetvalue = 0, | |
6422 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
6423 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
6424 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
6425 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6426 | .resetvalue = 0 }, | |
37cd6c24 PM |
6427 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
6428 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
6429 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6430 | .resetvalue = 0 }, | |
6431 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
6432 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
6433 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6434 | .resetvalue = 0 }, | |
43efaa33 PM |
6435 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
6436 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
6437 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6438 | .writefn = tlbi_aa64_alle3is_write }, | |
6439 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
6440 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
6441 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6442 | .writefn = tlbi_aa64_vae3is_write }, | |
6443 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
6444 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
6445 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6446 | .writefn = tlbi_aa64_vae3is_write }, | |
6447 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
6448 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
6449 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6450 | .writefn = tlbi_aa64_alle3_write }, | |
6451 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
6452 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
6453 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6454 | .writefn = tlbi_aa64_vae3_write }, | |
6455 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
6456 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
6457 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6458 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
6459 | }; |
6460 | ||
e2cce18f RH |
6461 | #ifndef CONFIG_USER_ONLY |
6462 | /* Test if system register redirection is to occur in the current state. */ | |
6463 | static bool redirect_for_e2h(CPUARMState *env) | |
6464 | { | |
6465 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
6466 | } | |
6467 | ||
6468 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6469 | { | |
6470 | CPReadFn *readfn; | |
6471 | ||
6472 | if (redirect_for_e2h(env)) { | |
6473 | /* Switch to the saved EL2 version of the register. */ | |
6474 | ri = ri->opaque; | |
6475 | readfn = ri->readfn; | |
6476 | } else { | |
6477 | readfn = ri->orig_readfn; | |
6478 | } | |
6479 | if (readfn == NULL) { | |
6480 | readfn = raw_read; | |
6481 | } | |
6482 | return readfn(env, ri); | |
6483 | } | |
6484 | ||
6485 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6486 | uint64_t value) | |
6487 | { | |
6488 | CPWriteFn *writefn; | |
6489 | ||
6490 | if (redirect_for_e2h(env)) { | |
6491 | /* Switch to the saved EL2 version of the register. */ | |
6492 | ri = ri->opaque; | |
6493 | writefn = ri->writefn; | |
6494 | } else { | |
6495 | writefn = ri->orig_writefn; | |
6496 | } | |
6497 | if (writefn == NULL) { | |
6498 | writefn = raw_write; | |
6499 | } | |
6500 | writefn(env, ri, value); | |
6501 | } | |
6502 | ||
6503 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
6504 | { | |
6505 | struct E2HAlias { | |
6506 | uint32_t src_key, dst_key, new_key; | |
6507 | const char *src_name, *dst_name, *new_name; | |
6508 | bool (*feature)(const ARMISARegisters *id); | |
6509 | }; | |
6510 | ||
6511 | #define K(op0, op1, crn, crm, op2) \ | |
6512 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
6513 | ||
6514 | static const struct E2HAlias aliases[] = { | |
6515 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
6516 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
6517 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
6518 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
6519 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
6520 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
6521 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
6522 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
6523 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
6524 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
6525 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
6526 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
6527 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
6528 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
6529 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
6530 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
6531 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
6532 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
6533 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
6534 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
6535 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
6536 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
6537 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
6538 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
6539 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
6540 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
6541 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
6542 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
6543 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
6544 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
6545 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
6546 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
6547 | ||
6548 | /* | |
6549 | * Note that redirection of ZCR is mentioned in the description | |
6550 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
6551 | * not in the summary table. | |
6552 | */ | |
6553 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
6554 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
de561988 RH |
6555 | { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), |
6556 | "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, | |
e2cce18f | 6557 | |
4b779ceb RH |
6558 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
6559 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
6560 | ||
7cb1e618 RH |
6561 | { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), |
6562 | "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | |
6563 | isar_feature_aa64_scxtnum }, | |
6564 | ||
e2cce18f RH |
6565 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
6566 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
6567 | }; | |
6568 | #undef K | |
6569 | ||
6570 | size_t i; | |
6571 | ||
6572 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
6573 | const struct E2HAlias *a = &aliases[i]; | |
9da35a40 | 6574 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; |
9da35a40 | 6575 | bool ok; |
e2cce18f RH |
6576 | |
6577 | if (a->feature && !a->feature(&cpu->isar)) { | |
6578 | continue; | |
6579 | } | |
6580 | ||
5860362d RH |
6581 | src_reg = g_hash_table_lookup(cpu->cp_regs, |
6582 | (gpointer)(uintptr_t)a->src_key); | |
6583 | dst_reg = g_hash_table_lookup(cpu->cp_regs, | |
6584 | (gpointer)(uintptr_t)a->dst_key); | |
e2cce18f RH |
6585 | g_assert(src_reg != NULL); |
6586 | g_assert(dst_reg != NULL); | |
6587 | ||
6588 | /* Cross-compare names to detect typos in the keys. */ | |
6589 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
6590 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
6591 | ||
6592 | /* None of the core system registers use opaque; we will. */ | |
6593 | g_assert(src_reg->opaque == NULL); | |
6594 | ||
6595 | /* Create alias before redirection so we dup the right data. */ | |
9da35a40 | 6596 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); |
9da35a40 RH |
6597 | |
6598 | new_reg->name = a->new_name; | |
6599 | new_reg->type |= ARM_CP_ALIAS; | |
6600 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
6601 | new_reg->access &= PL2_RW | PL3_RW; | |
6602 | ||
5860362d RH |
6603 | ok = g_hash_table_insert(cpu->cp_regs, |
6604 | (gpointer)(uintptr_t)a->new_key, new_reg); | |
9da35a40 | 6605 | g_assert(ok); |
e2cce18f RH |
6606 | |
6607 | src_reg->opaque = dst_reg; | |
6608 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
6609 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
6610 | if (!src_reg->raw_readfn) { | |
6611 | src_reg->raw_readfn = raw_read; | |
6612 | } | |
6613 | if (!src_reg->raw_writefn) { | |
6614 | src_reg->raw_writefn = raw_write; | |
6615 | } | |
6616 | src_reg->readfn = el2_e2h_read; | |
6617 | src_reg->writefn = el2_e2h_write; | |
6618 | } | |
6619 | } | |
6620 | #endif | |
6621 | ||
3f208fd7 PM |
6622 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6623 | bool isread) | |
7da845b0 | 6624 | { |
97475a89 RH |
6625 | int cur_el = arm_current_el(env); |
6626 | ||
6627 | if (cur_el < 2) { | |
6628 | uint64_t hcr = arm_hcr_el2_eff(env); | |
6629 | ||
6630 | if (cur_el == 0) { | |
6631 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
6632 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
6633 | return CP_ACCESS_TRAP_EL2; | |
6634 | } | |
6635 | } else { | |
6636 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
6637 | return CP_ACCESS_TRAP; | |
6638 | } | |
6639 | if (hcr & HCR_TID2) { | |
6640 | return CP_ACCESS_TRAP_EL2; | |
6641 | } | |
6642 | } | |
6643 | } else if (hcr & HCR_TID2) { | |
6644 | return CP_ACCESS_TRAP_EL2; | |
6645 | } | |
7da845b0 | 6646 | } |
630fcd4d MZ |
6647 | |
6648 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
6649 | return CP_ACCESS_TRAP_EL2; | |
6650 | } | |
6651 | ||
7da845b0 PM |
6652 | return CP_ACCESS_OK; |
6653 | } | |
6654 | ||
58e93b48 RH |
6655 | /* |
6656 | * Check for traps to RAS registers, which are controlled | |
6657 | * by HCR_EL2.TERR and SCR_EL3.TERR. | |
6658 | */ | |
6659 | static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | |
6660 | bool isread) | |
6661 | { | |
6662 | int el = arm_current_el(env); | |
6663 | ||
6664 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | |
6665 | return CP_ACCESS_TRAP_EL2; | |
6666 | } | |
6667 | if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | |
6668 | return CP_ACCESS_TRAP_EL3; | |
6669 | } | |
6670 | return CP_ACCESS_OK; | |
6671 | } | |
6672 | ||
6673 | static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6674 | { | |
6675 | int el = arm_current_el(env); | |
6676 | ||
6677 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6678 | return env->cp15.vdisr_el2; | |
6679 | } | |
6680 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6681 | return 0; /* RAZ/WI */ | |
6682 | } | |
6683 | return env->cp15.disr_el1; | |
6684 | } | |
6685 | ||
6686 | static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
6687 | { | |
6688 | int el = arm_current_el(env); | |
6689 | ||
6690 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6691 | env->cp15.vdisr_el2 = val; | |
6692 | return; | |
6693 | } | |
6694 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6695 | return; /* RAZ/WI */ | |
6696 | } | |
6697 | env->cp15.disr_el1 = val; | |
6698 | } | |
6699 | ||
6700 | /* | |
6701 | * Minimal RAS implementation with no Error Records. | |
6702 | * Which means that all of the Error Record registers: | |
6703 | * ERXADDR_EL1 | |
6704 | * ERXCTLR_EL1 | |
6705 | * ERXFR_EL1 | |
6706 | * ERXMISC0_EL1 | |
6707 | * ERXMISC1_EL1 | |
6708 | * ERXMISC2_EL1 | |
6709 | * ERXMISC3_EL1 | |
6710 | * ERXPFGCDN_EL1 (RASv1p1) | |
6711 | * ERXPFGCTL_EL1 (RASv1p1) | |
6712 | * ERXPFGF_EL1 (RASv1p1) | |
6713 | * ERXSTATUS_EL1 | |
6714 | * and | |
6715 | * ERRSELR_EL1 | |
6716 | * may generate UNDEFINED, which is the effect we get by not | |
6717 | * listing them at all. | |
bd8db7d9 PM |
6718 | * |
6719 | * These registers have fine-grained trap bits, but UNDEF-to-EL1 | |
6720 | * is higher priority than FGT-to-EL2 so we do not need to list them | |
6721 | * in order to check for an FGT. | |
58e93b48 RH |
6722 | */ |
6723 | static const ARMCPRegInfo minimal_ras_reginfo[] = { | |
6724 | { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | |
6725 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | |
6726 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | |
6727 | .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | |
6728 | { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6729 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | |
6730 | .access = PL1_R, .accessfn = access_terr, | |
bd8db7d9 | 6731 | .fgt = FGT_ERRIDR_EL1, |
58e93b48 RH |
6732 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
6733 | { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | |
6734 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | |
6735 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | |
6736 | { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | |
6737 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | |
6738 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | |
6739 | }; | |
6740 | ||
397d922c RH |
6741 | /* |
6742 | * Return the exception level to which exceptions should be taken | |
6743 | * via SVEAccessTrap. This excludes the check for whether the exception | |
6744 | * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily | |
6745 | * be found by testing 0 < fp_exception_el < sve_exception_el. | |
6746 | * | |
6747 | * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the | |
6748 | * pseudocode does *not* separate out the FP trap checks, but has them | |
6749 | * all in one function. | |
5be5e8ed | 6750 | */ |
ced31551 | 6751 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6752 | { |
6753 | #ifndef CONFIG_USER_ONLY | |
aa4451b6 | 6754 | if (el <= 1 && !el_is_in_host(env, el)) { |
fab8ad39 | 6755 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { |
7701cee5 RH |
6756 | case 1: |
6757 | if (el != 0) { | |
6758 | break; | |
6759 | } | |
6760 | /* fall through */ | |
6761 | case 0: | |
6762 | case 2: | |
61a8c23a | 6763 | return 1; |
5be5e8ed | 6764 | } |
5be5e8ed RH |
6765 | } |
6766 | ||
7d38cb92 RH |
6767 | if (el <= 2 && arm_is_el2_enabled(env)) { |
6768 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6769 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
fab8ad39 | 6770 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { |
d5a6fa2d | 6771 | case 1: |
7d38cb92 | 6772 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { |
d5a6fa2d RH |
6773 | break; |
6774 | } | |
6775 | /* fall through */ | |
6776 | case 0: | |
6777 | case 2: | |
6778 | return 2; | |
6779 | } | |
7d38cb92 | 6780 | } else { |
fab8ad39 | 6781 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { |
d5a6fa2d RH |
6782 | return 2; |
6783 | } | |
60eed086 | 6784 | } |
5be5e8ed RH |
6785 | } |
6786 | ||
60eed086 RH |
6787 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6788 | if (arm_feature(env, ARM_FEATURE_EL3) | |
fab8ad39 | 6789 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { |
5be5e8ed RH |
6790 | return 3; |
6791 | } | |
6792 | #endif | |
6793 | return 0; | |
6794 | } | |
6795 | ||
6b2ca83e RH |
6796 | /* |
6797 | * Return the exception level to which exceptions should be taken for SME. | |
6798 | * C.f. the ARM pseudocode function CheckSMEAccess. | |
6799 | */ | |
6800 | int sme_exception_el(CPUARMState *env, int el) | |
6801 | { | |
6802 | #ifndef CONFIG_USER_ONLY | |
6803 | if (el <= 1 && !el_is_in_host(env, el)) { | |
6804 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { | |
6805 | case 1: | |
6806 | if (el != 0) { | |
6807 | break; | |
6808 | } | |
6809 | /* fall through */ | |
6810 | case 0: | |
6811 | case 2: | |
6812 | return 1; | |
6813 | } | |
6814 | } | |
6815 | ||
6816 | if (el <= 2 && arm_is_el2_enabled(env)) { | |
6817 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6818 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
6819 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { | |
6820 | case 1: | |
6821 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { | |
6822 | break; | |
6823 | } | |
6824 | /* fall through */ | |
6825 | case 0: | |
6826 | case 2: | |
6827 | return 2; | |
6828 | } | |
6829 | } else { | |
6830 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { | |
6831 | return 2; | |
6832 | } | |
6833 | } | |
6834 | } | |
6835 | ||
6836 | /* CPTR_EL3. Since ESM is negative we must check for EL3. */ | |
6837 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6838 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
6839 | return 3; | |
6840 | } | |
6841 | #endif | |
6842 | return 0; | |
6843 | } | |
6844 | ||
0ab5953b RH |
6845 | /* |
6846 | * Given that SVE is enabled, return the vector length for EL. | |
6847 | */ | |
6ca54aa9 | 6848 | uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) |
0ab5953b | 6849 | { |
2fc0cc0e | 6850 | ARMCPU *cpu = env_archcpu(env); |
6ca54aa9 RH |
6851 | uint64_t *cr = env->vfp.zcr_el; |
6852 | uint32_t map = cpu->sve_vq.map; | |
6853 | uint32_t len = ARM_MAX_VQ - 1; | |
6854 | ||
6855 | if (sm) { | |
6856 | cr = env->vfp.smcr_el; | |
6857 | map = cpu->sme_vq.map; | |
6858 | } | |
0ab5953b | 6859 | |
c6225beb | 6860 | if (el <= 1 && !el_is_in_host(env, el)) { |
6ca54aa9 | 6861 | len = MIN(len, 0xf & (uint32_t)cr[1]); |
0ab5953b | 6862 | } |
6a02a732 | 6863 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
6ca54aa9 | 6864 | len = MIN(len, 0xf & (uint32_t)cr[2]); |
0ab5953b | 6865 | } |
6a02a732 | 6866 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
6ca54aa9 RH |
6867 | len = MIN(len, 0xf & (uint32_t)cr[3]); |
6868 | } | |
6869 | ||
6870 | map &= MAKE_64BIT_MASK(0, len + 1); | |
6871 | if (map != 0) { | |
6872 | return 31 - clz32(map); | |
0ab5953b | 6873 | } |
0df9142d | 6874 | |
6ca54aa9 RH |
6875 | /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ |
6876 | assert(sm); | |
6877 | return ctz32(cpu->sme_vq.map); | |
6878 | } | |
6879 | ||
6880 | uint32_t sve_vqm1_for_el(CPUARMState *env, int el) | |
6881 | { | |
6882 | return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); | |
0ab5953b RH |
6883 | } |
6884 | ||
5be5e8ed RH |
6885 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6886 | uint64_t value) | |
6887 | { | |
0ab5953b | 6888 | int cur_el = arm_current_el(env); |
5ef3cc56 | 6889 | int old_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6890 | int new_len; |
6891 | ||
5be5e8ed | 6892 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6893 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6894 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6895 | |
6896 | /* | |
6897 | * Because we arrived here, we know both FP and SVE are enabled; | |
6898 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6899 | */ | |
5ef3cc56 | 6900 | new_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6901 | if (new_len < old_len) { |
6902 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6903 | } | |
5be5e8ed RH |
6904 | } |
6905 | ||
60360d82 RH |
6906 | static const ARMCPRegInfo zcr_reginfo[] = { |
6907 | { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6908 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
6909 | .access = PL1_RW, .type = ARM_CP_SVE, | |
6910 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | |
6911 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6912 | { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6913 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
6914 | .access = PL2_RW, .type = ARM_CP_SVE, | |
6915 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | |
6916 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6917 | { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6918 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
6919 | .access = PL3_RW, .type = ARM_CP_SVE, | |
6920 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | |
6921 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
5be5e8ed RH |
6922 | }; |
6923 | ||
9e5ec745 RH |
6924 | #ifdef TARGET_AARCH64 |
6925 | static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, | |
6926 | bool isread) | |
6927 | { | |
6928 | int el = arm_current_el(env); | |
6929 | ||
6930 | if (el == 0) { | |
6931 | uint64_t sctlr = arm_sctlr(env, el); | |
6932 | if (!(sctlr & SCTLR_EnTP2)) { | |
6933 | return CP_ACCESS_TRAP; | |
6934 | } | |
6935 | } | |
6936 | /* TODO: FEAT_FGT */ | |
6937 | if (el < 3 | |
6938 | && arm_feature(env, ARM_FEATURE_EL3) | |
6939 | && !(env->cp15.scr_el3 & SCR_ENTP2)) { | |
6940 | return CP_ACCESS_TRAP_EL3; | |
6941 | } | |
6942 | return CP_ACCESS_OK; | |
6943 | } | |
6944 | ||
d5b1223a RH |
6945 | static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, |
6946 | bool isread) | |
6947 | { | |
6948 | /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ | |
6949 | if (arm_current_el(env) < 3 | |
6950 | && arm_feature(env, ARM_FEATURE_EL3) | |
6951 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
6952 | return CP_ACCESS_TRAP_EL3; | |
6953 | } | |
6954 | return CP_ACCESS_OK; | |
6955 | } | |
6956 | ||
7f2a01e7 RH |
6957 | /* ResetSVEState */ |
6958 | static void arm_reset_sve_state(CPUARMState *env) | |
6959 | { | |
6960 | memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); | |
6961 | /* Recall that FFR is stored as pregs[16]. */ | |
6962 | memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); | |
6963 | vfp_set_fpcr(env, 0x0800009f); | |
6964 | } | |
6965 | ||
2a8af382 RH |
6966 | void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) |
6967 | { | |
6968 | uint64_t change = (env->svcr ^ new) & mask; | |
6969 | ||
f4318557 RH |
6970 | if (change == 0) { |
6971 | return; | |
6972 | } | |
2a8af382 | 6973 | env->svcr ^= change; |
7f2a01e7 RH |
6974 | |
6975 | if (change & R_SVCR_SM_MASK) { | |
6976 | arm_reset_sve_state(env); | |
6977 | } | |
fccb4918 RH |
6978 | |
6979 | /* | |
6980 | * ResetSMEState. | |
6981 | * | |
6982 | * SetPSTATE_ZA zeros on enable and disable. We can zero this only | |
6983 | * on enable: while disabled, the storage is inaccessible and the | |
6984 | * value does not matter. We're not saving the storage in vmstate | |
6985 | * when disabled either. | |
6986 | */ | |
6987 | if (change & new & R_SVCR_ZA_MASK) { | |
6988 | memset(env->zarray, 0, sizeof(env->zarray)); | |
6989 | } | |
f4318557 | 6990 | |
2b77ad4d FR |
6991 | if (tcg_enabled()) { |
6992 | arm_rebuild_hflags(env); | |
6993 | } | |
2a8af382 RH |
6994 | } |
6995 | ||
c37e6ac9 RH |
6996 | static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6997 | uint64_t value) | |
6998 | { | |
2a8af382 | 6999 | aarch64_set_svcr(env, value, -1); |
c37e6ac9 RH |
7000 | } |
7001 | ||
de561988 RH |
7002 | static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
7003 | uint64_t value) | |
7004 | { | |
7005 | int cur_el = arm_current_el(env); | |
7006 | int old_len = sve_vqm1_for_el(env, cur_el); | |
7007 | int new_len; | |
7008 | ||
7009 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); | |
7010 | value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; | |
7011 | raw_write(env, ri, value); | |
7012 | ||
7013 | /* | |
7014 | * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage | |
7015 | * when SVL is widened (old values kept, or zeros). Choose to keep the | |
7016 | * current values for simplicity. But for QEMU internals, we must still | |
7017 | * apply the narrower SVL to the Zregs and Pregs -- see the comment | |
7018 | * above aarch64_sve_narrow_vq. | |
7019 | */ | |
7020 | new_len = sve_vqm1_for_el(env, cur_el); | |
7021 | if (new_len < old_len) { | |
7022 | aarch64_sve_narrow_vq(env, new_len + 1); | |
7023 | } | |
7024 | } | |
7025 | ||
9e5ec745 RH |
7026 | static const ARMCPRegInfo sme_reginfo[] = { |
7027 | { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, | |
7028 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, | |
7029 | .access = PL0_RW, .accessfn = access_tpidr2, | |
bd8db7d9 | 7030 | .fgt = FGT_NTPIDR2_EL0, |
9e5ec745 | 7031 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, |
c37e6ac9 RH |
7032 | { .name = "SVCR", .state = ARM_CP_STATE_AA64, |
7033 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, | |
7034 | .access = PL0_RW, .type = ARM_CP_SME, | |
7035 | .fieldoffset = offsetof(CPUARMState, svcr), | |
7036 | .writefn = svcr_write, .raw_writefn = raw_write }, | |
de561988 RH |
7037 | { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, |
7038 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, | |
7039 | .access = PL1_RW, .type = ARM_CP_SME, | |
7040 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), | |
7041 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7042 | { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64, | |
7043 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6, | |
7044 | .access = PL2_RW, .type = ARM_CP_SME, | |
7045 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]), | |
7046 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7047 | { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64, | |
7048 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6, | |
7049 | .access = PL3_RW, .type = ARM_CP_SME, | |
7050 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), | |
7051 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
d5b1223a RH |
7052 | { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64, |
7053 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6, | |
7054 | .access = PL1_R, .accessfn = access_aa64_tid1, | |
7055 | /* | |
7056 | * IMPLEMENTOR = 0 (software) | |
7057 | * REVISION = 0 (implementation defined) | |
7058 | * SMPS = 0 (no streaming execution priority in QEMU) | |
7059 | * AFFINITY = 0 (streaming sve mode not shared with other PEs) | |
7060 | */ | |
7061 | .type = ARM_CP_CONST, .resetvalue = 0, }, | |
7062 | /* | |
7063 | * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. | |
7064 | */ | |
7065 | { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, | |
7066 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, | |
7067 | .access = PL1_RW, .accessfn = access_esm, | |
bd8db7d9 | 7068 | .fgt = FGT_NSMPRI_EL1, |
d5b1223a RH |
7069 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7070 | { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, | |
7071 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, | |
7072 | .access = PL2_RW, .accessfn = access_esm, | |
7073 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9e5ec745 | 7074 | }; |
ef1febe7 RH |
7075 | |
7076 | static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7077 | uint64_t value) | |
7078 | { | |
7079 | CPUState *cs = env_cpu(env); | |
7080 | ||
7081 | tlb_flush(cs); | |
7082 | } | |
7083 | ||
7084 | static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7085 | uint64_t value) | |
7086 | { | |
7087 | /* L0GPTSZ is RO; other bits not mentioned are RES0. */ | |
7088 | uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | | |
7089 | R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | | |
7090 | R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; | |
7091 | ||
7092 | env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); | |
7093 | } | |
7094 | ||
7095 | static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
7096 | { | |
7097 | env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, | |
7098 | env_archcpu(env)->reset_l0gptsz); | |
7099 | } | |
7100 | ||
7101 | static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7102 | uint64_t value) | |
7103 | { | |
7104 | CPUState *cs = env_cpu(env); | |
7105 | ||
7106 | tlb_flush_all_cpus_synced(cs); | |
7107 | } | |
7108 | ||
7109 | static const ARMCPRegInfo rme_reginfo[] = { | |
7110 | { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, | |
7111 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, | |
7112 | .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, | |
7113 | .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, | |
7114 | { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, | |
7115 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, | |
7116 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, | |
7117 | { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, | |
7118 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, | |
7119 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, | |
7120 | { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, | |
7121 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, | |
7122 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7123 | .writefn = tlbi_aa64_paall_write }, | |
7124 | { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, | |
7125 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, | |
7126 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7127 | .writefn = tlbi_aa64_paallos_write }, | |
7128 | /* | |
7129 | * QEMU does not have a way to invalidate by physical address, thus | |
7130 | * invalidating a range of physical addresses is accomplished by | |
673d8215 | 7131 | * flushing all tlb entries in the outer shareable domain, |
ef1febe7 RH |
7132 | * just like PAALLOS. |
7133 | */ | |
7134 | { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, | |
7135 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, | |
7136 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7137 | .writefn = tlbi_aa64_paallos_write }, | |
7138 | { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, | |
7139 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, | |
7140 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7141 | .writefn = tlbi_aa64_paallos_write }, | |
7142 | { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, | |
7143 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, | |
7144 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7145 | }; | |
7146 | ||
7147 | static const ARMCPRegInfo rme_mte_reginfo[] = { | |
7148 | { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, | |
7149 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, | |
7150 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7151 | }; | |
9e5ec745 RH |
7152 | #endif /* TARGET_AARCH64 */ |
7153 | ||
24183fb6 PM |
7154 | static void define_pmu_regs(ARMCPU *cpu) |
7155 | { | |
7156 | /* | |
7157 | * v7 performance monitor control register: same implementor | |
7158 | * field as main ID register, and we implement four counters in | |
7159 | * addition to the cycle count register. | |
7160 | */ | |
24526bb9 | 7161 | unsigned int i, pmcrn = pmu_num_counters(&cpu->env); |
24183fb6 PM |
7162 | ARMCPRegInfo pmcr = { |
7163 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
7164 | .access = PL0_RW, | |
dc780233 | 7165 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7166 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
7167 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
7168 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
7169 | .raw_writefn = raw_write, | |
7170 | }; | |
7171 | ARMCPRegInfo pmcr64 = { | |
7172 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
7173 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
7174 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7175 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7176 | .type = ARM_CP_IO, |
7177 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
24526bb9 | 7178 | .resetvalue = cpu->isar.reset_pmcr_el0, |
24183fb6 PM |
7179 | .writefn = pmcr_write, .raw_writefn = raw_write, |
7180 | }; | |
24526bb9 | 7181 | |
24183fb6 PM |
7182 | define_one_arm_cp_reg(cpu, &pmcr); |
7183 | define_one_arm_cp_reg(cpu, &pmcr64); | |
7184 | for (i = 0; i < pmcrn; i++) { | |
7185 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
7186 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
7187 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
7188 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
7189 | ARMCPRegInfo pmev_regs[] = { | |
7190 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
7191 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7192 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7193 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 | 7194 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
99a50d1a | 7195 | .accessfn = pmreg_access_xevcntr }, |
24183fb6 PM |
7196 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
7197 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
99a50d1a | 7198 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
24183fb6 | 7199 | .type = ARM_CP_IO, |
dc780233 | 7200 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 PM |
7201 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
7202 | .raw_readfn = pmevcntr_rawread, | |
7203 | .raw_writefn = pmevcntr_rawwrite }, | |
7204 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
7205 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7206 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7207 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7208 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, |
7209 | .accessfn = pmreg_access }, | |
7210 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
7211 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
7212 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7213 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7214 | .type = ARM_CP_IO, |
7215 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
7216 | .raw_writefn = pmevtyper_rawwrite }, | |
24183fb6 PM |
7217 | }; |
7218 | define_arm_cp_regs(cpu, pmev_regs); | |
7219 | g_free(pmevcntr_name); | |
7220 | g_free(pmevcntr_el0_name); | |
7221 | g_free(pmevtyper_name); | |
7222 | g_free(pmevtyper_el0_name); | |
7223 | } | |
a793bcd0 | 7224 | if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { |
24183fb6 PM |
7225 | ARMCPRegInfo v81_pmu_regs[] = { |
7226 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
7227 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
7228 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7229 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 PM |
7230 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, |
7231 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
7232 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
7233 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7234 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 | 7235 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, |
24183fb6 PM |
7236 | }; |
7237 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
7238 | } | |
a793bcd0 | 7239 | if (cpu_isar_feature(any_pmuv3p4, cpu)) { |
15dd1ebd PM |
7240 | static const ARMCPRegInfo v84_pmmir = { |
7241 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
7242 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
7243 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7244 | .fgt = FGT_PMMIR_EL1, |
15dd1ebd PM |
7245 | .resetvalue = 0 |
7246 | }; | |
7247 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
7248 | } | |
24183fb6 PM |
7249 | } |
7250 | ||
0f150c84 | 7251 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
7252 | /* |
7253 | * We don't know until after realize whether there's a GICv3 | |
96a8b92e PM |
7254 | * attached, and that is what registers the gicv3 sysregs. |
7255 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
7256 | * at runtime. | |
7257 | */ | |
7258 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7259 | { | |
2fc0cc0e | 7260 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 7261 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
7262 | |
7263 | if (env->gicv3state) { | |
7264 | pfr1 |= 1 << 28; | |
7265 | } | |
7266 | return pfr1; | |
7267 | } | |
7268 | ||
7269 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7270 | { | |
2fc0cc0e | 7271 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 7272 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
7273 | |
7274 | if (env->gicv3state) { | |
7275 | pfr0 |= 1 << 24; | |
7276 | } | |
7277 | return pfr0; | |
7278 | } | |
976b99b6 | 7279 | #endif |
96a8b92e | 7280 | |
9b37a28c FR |
7281 | /* |
7282 | * Shared logic between LORID and the rest of the LOR* registers. | |
9bd268ba | 7283 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 7284 | */ |
9bd268ba RDC |
7285 | static CPAccessResult access_lor_ns(CPUARMState *env, |
7286 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
7287 | { |
7288 | int el = arm_current_el(env); | |
7289 | ||
7290 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
7291 | return CP_ACCESS_TRAP_EL2; | |
7292 | } | |
7293 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
7294 | return CP_ACCESS_TRAP_EL3; | |
7295 | } | |
7296 | return CP_ACCESS_OK; | |
7297 | } | |
7298 | ||
2d7137c1 RH |
7299 | static CPAccessResult access_lor_other(CPUARMState *env, |
7300 | const ARMCPRegInfo *ri, bool isread) | |
7301 | { | |
7302 | if (arm_is_secure_below_el3(env)) { | |
7303 | /* Access denied in secure mode. */ | |
7304 | return CP_ACCESS_TRAP; | |
7305 | } | |
9bd268ba | 7306 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
7307 | } |
7308 | ||
d8564ee4 RH |
7309 | /* |
7310 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
7311 | * registers fixed at 0, which indicates that there are zero | |
7312 | * supported Limited Ordering regions. | |
7313 | */ | |
7314 | static const ARMCPRegInfo lor_reginfo[] = { | |
7315 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
7316 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
7317 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7318 | .fgt = FGT_LORSA_EL1, |
d8564ee4 RH |
7319 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7320 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
7321 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
7322 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7323 | .fgt = FGT_LOREA_EL1, |
d8564ee4 RH |
7324 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7325 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
7326 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
7327 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7328 | .fgt = FGT_LORN_EL1, |
d8564ee4 RH |
7329 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7330 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
7331 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
7332 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7333 | .fgt = FGT_LORC_EL1, |
d8564ee4 RH |
7334 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7335 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
7336 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 7337 | .access = PL1_R, .accessfn = access_lor_ns, |
b19ed03c | 7338 | .fgt = FGT_LORID_EL1, |
d8564ee4 | 7339 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
d8564ee4 RH |
7340 | }; |
7341 | ||
967aa94f RH |
7342 | #ifdef TARGET_AARCH64 |
7343 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
7344 | bool isread) | |
7345 | { | |
7346 | int el = arm_current_el(env); | |
7347 | ||
7348 | if (el < 2 && | |
07b034ea | 7349 | arm_is_el2_enabled(env) && |
967aa94f RH |
7350 | !(arm_hcr_el2_eff(env) & HCR_APK)) { |
7351 | return CP_ACCESS_TRAP_EL2; | |
7352 | } | |
7353 | if (el < 3 && | |
7354 | arm_feature(env, ARM_FEATURE_EL3) && | |
7355 | !(env->cp15.scr_el3 & SCR_APK)) { | |
7356 | return CP_ACCESS_TRAP_EL3; | |
7357 | } | |
7358 | return CP_ACCESS_OK; | |
7359 | } | |
7360 | ||
7361 | static const ARMCPRegInfo pauth_reginfo[] = { | |
7362 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
7363 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
7364 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7365 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7366 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
7367 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7368 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
7369 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7370 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7371 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
7372 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7373 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
7374 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7375 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7376 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
7377 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7378 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
7379 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7380 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7381 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
7382 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7383 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
7384 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7385 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7386 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
7387 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7388 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
7389 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7390 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7391 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
7392 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7393 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
7394 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7395 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7396 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
7397 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7398 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
7399 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7400 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7401 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
7402 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7403 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
7404 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7405 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7406 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
7407 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7408 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
7409 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7410 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7411 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f | 7412 | }; |
de390645 | 7413 | |
84940ed8 RC |
7414 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
7415 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
7416 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
0f66d223 | 7417 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7418 | .fgt = FGT_TLBIRVAE1IS, |
84940ed8 RC |
7419 | .writefn = tlbi_aa64_rvae1is_write }, |
7420 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
7421 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
0f66d223 | 7422 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7423 | .fgt = FGT_TLBIRVAAE1IS, |
84940ed8 RC |
7424 | .writefn = tlbi_aa64_rvae1is_write }, |
7425 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
7426 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
0f66d223 | 7427 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7428 | .fgt = FGT_TLBIRVALE1IS, |
84940ed8 RC |
7429 | .writefn = tlbi_aa64_rvae1is_write }, |
7430 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
7431 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
0f66d223 | 7432 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7433 | .fgt = FGT_TLBIRVAALE1IS, |
84940ed8 RC |
7434 | .writefn = tlbi_aa64_rvae1is_write }, |
7435 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
7436 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
fe3ca86c | 7437 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7438 | .fgt = FGT_TLBIRVAE1OS, |
84940ed8 RC |
7439 | .writefn = tlbi_aa64_rvae1is_write }, |
7440 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
7441 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
fe3ca86c | 7442 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7443 | .fgt = FGT_TLBIRVAAE1OS, |
84940ed8 RC |
7444 | .writefn = tlbi_aa64_rvae1is_write }, |
7445 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
7446 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
fe3ca86c | 7447 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7448 | .fgt = FGT_TLBIRVALE1OS, |
84940ed8 RC |
7449 | .writefn = tlbi_aa64_rvae1is_write }, |
7450 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
7451 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
fe3ca86c | 7452 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7453 | .fgt = FGT_TLBIRVAALE1OS, |
84940ed8 RC |
7454 | .writefn = tlbi_aa64_rvae1is_write }, |
7455 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
7456 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
4870f38b | 7457 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7458 | .fgt = FGT_TLBIRVAE1, |
84940ed8 RC |
7459 | .writefn = tlbi_aa64_rvae1_write }, |
7460 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
7461 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
4870f38b | 7462 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7463 | .fgt = FGT_TLBIRVAAE1, |
84940ed8 RC |
7464 | .writefn = tlbi_aa64_rvae1_write }, |
7465 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
7466 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
4870f38b | 7467 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7468 | .fgt = FGT_TLBIRVALE1, |
84940ed8 RC |
7469 | .writefn = tlbi_aa64_rvae1_write }, |
7470 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
7471 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
4870f38b | 7472 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7473 | .fgt = FGT_TLBIRVAALE1, |
84940ed8 RC |
7474 | .writefn = tlbi_aa64_rvae1_write }, |
7475 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
7476 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
575a94af RH |
7477 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7478 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7479 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
7480 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
575a94af RH |
7481 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7482 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7483 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, |
7484 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
696ba377 | 7485 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7486 | .writefn = tlbi_aa64_rvae2is_write }, |
7487 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
7488 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
696ba377 | 7489 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7490 | .writefn = tlbi_aa64_rvae2is_write }, |
7491 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
7492 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
575a94af RH |
7493 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7494 | .writefn = tlbi_aa64_ripas2e1_write }, | |
7495 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
84940ed8 | 7496 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, |
575a94af RH |
7497 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7498 | .writefn = tlbi_aa64_ripas2e1_write }, | |
84940ed8 RC |
7499 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, |
7500 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
696ba377 | 7501 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7502 | .writefn = tlbi_aa64_rvae2is_write }, |
7503 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
7504 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
696ba377 | 7505 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7506 | .writefn = tlbi_aa64_rvae2is_write }, |
7507 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
7508 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
696ba377 | 7509 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7510 | .writefn = tlbi_aa64_rvae2_write }, |
7511 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
7512 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
696ba377 | 7513 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7514 | .writefn = tlbi_aa64_rvae2_write }, |
7515 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
7516 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
7517 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7518 | .writefn = tlbi_aa64_rvae3is_write }, | |
7519 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
7520 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
7521 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7522 | .writefn = tlbi_aa64_rvae3is_write }, | |
7523 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
7524 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
7525 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7526 | .writefn = tlbi_aa64_rvae3is_write }, | |
7527 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
7528 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
7529 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7530 | .writefn = tlbi_aa64_rvae3is_write }, | |
7531 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
7532 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
7533 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7534 | .writefn = tlbi_aa64_rvae3_write }, | |
7535 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
7536 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
7537 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7538 | .writefn = tlbi_aa64_rvae3_write }, | |
84940ed8 RC |
7539 | }; |
7540 | ||
7113d618 RC |
7541 | static const ARMCPRegInfo tlbios_reginfo[] = { |
7542 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
7543 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
fe3ca86c | 7544 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7545 | .fgt = FGT_TLBIVMALLE1OS, |
7113d618 | 7546 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7547 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
7548 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
bf2f0625 | 7549 | .fgt = FGT_TLBIVAE1OS, |
fe3ca86c | 7550 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
b7469ef9 | 7551 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7552 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
7553 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
fe3ca86c | 7554 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7555 | .fgt = FGT_TLBIASIDE1OS, |
7113d618 | 7556 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7557 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
7558 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
fe3ca86c | 7559 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7560 | .fgt = FGT_TLBIVAAE1OS, |
b7469ef9 IH |
7561 | .writefn = tlbi_aa64_vae1is_write }, |
7562 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
7563 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
fe3ca86c | 7564 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7565 | .fgt = FGT_TLBIVALE1OS, |
b7469ef9 IH |
7566 | .writefn = tlbi_aa64_vae1is_write }, |
7567 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
7568 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
fe3ca86c | 7569 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7570 | .fgt = FGT_TLBIVAALE1OS, |
b7469ef9 | 7571 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7572 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
7573 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
696ba377 | 7574 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
7113d618 | 7575 | .writefn = tlbi_aa64_alle2is_write }, |
b7469ef9 IH |
7576 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
7577 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
696ba377 | 7578 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7579 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7580 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
7581 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
7582 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7583 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
7584 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
7585 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
696ba377 | 7586 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7587 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7588 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
7589 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
7590 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7591 | .writefn = tlbi_aa64_alle1is_write }, | |
7592 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7593 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7594 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7595 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7596 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7597 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7598 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7599 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7600 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7601 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7602 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7603 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7604 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7605 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7606 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7607 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7608 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7609 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7610 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7611 | .writefn = tlbi_aa64_vae3is_write }, | |
7612 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7613 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7614 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7615 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7616 | }; |
7617 | ||
de390645 RH |
7618 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7619 | { | |
7620 | Error *err = NULL; | |
7621 | uint64_t ret; | |
7622 | ||
7623 | /* Success sets NZCV = 0000. */ | |
7624 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7625 | ||
7626 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7627 | /* | |
7628 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7629 | * The best we can do is log the reason and return the | |
7630 | * timed-out indication to the guest. There is no reason | |
7631 | * we know to expect this failure to be transitory, so the | |
7632 | * guest may well hang retrying the operation. | |
7633 | */ | |
7634 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7635 | ri->name, error_get_pretty(err)); | |
7636 | error_free(err); | |
7637 | ||
7638 | env->ZF = 0; /* NZCF = 0100 */ | |
7639 | return 0; | |
7640 | } | |
7641 | return ret; | |
7642 | } | |
7643 | ||
7644 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7645 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7646 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7647 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7648 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7649 | .access = PL0_R, .readfn = rndr_readfn }, | |
7650 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7651 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7652 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7653 | .access = PL0_R, .readfn = rndr_readfn }, | |
de390645 | 7654 | }; |
0d57b499 | 7655 | |
0d57b499 BM |
7656 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, |
7657 | uint64_t value) | |
7658 | { | |
7659 | ARMCPU *cpu = env_archcpu(env); | |
7660 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7661 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7662 | uint64_t vaddr_in = (uint64_t) value; | |
7663 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7664 | void *haddr; | |
7665 | int mem_idx = cpu_mmu_index(env, false); | |
7666 | ||
7667 | /* This won't be crossing page boundaries */ | |
7668 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7669 | if (haddr) { | |
cd4a47f9 | 7670 | #ifndef CONFIG_USER_ONLY |
0d57b499 BM |
7671 | |
7672 | ram_addr_t offset; | |
7673 | MemoryRegion *mr; | |
7674 | ||
7675 | /* RCU lock is already being held */ | |
7676 | mr = memory_region_from_host(haddr, &offset); | |
7677 | ||
7678 | if (mr) { | |
4dfe59d1 | 7679 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 | 7680 | } |
cd4a47f9 | 7681 | #endif /*CONFIG_USER_ONLY*/ |
0d57b499 BM |
7682 | } |
7683 | } | |
7684 | ||
7685 | static const ARMCPRegInfo dcpop_reg[] = { | |
7686 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7687 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7688 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7689 | .fgt = FGT_DCCVAP, |
1bed4d2e | 7690 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7691 | }; |
7692 | ||
7693 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7694 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7695 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7696 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7697 | .fgt = FGT_DCCVADP, |
1bed4d2e | 7698 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 | 7699 | }; |
0d57b499 | 7700 | |
4b779ceb RH |
7701 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7702 | bool isread) | |
7703 | { | |
7704 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7705 | return CP_ACCESS_TRAP_EL2; | |
7706 | } | |
7707 | ||
7708 | return CP_ACCESS_OK; | |
7709 | } | |
7710 | ||
7711 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7712 | bool isread) | |
7713 | { | |
7714 | int el = arm_current_el(env); | |
7715 | ||
0da067f2 | 7716 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
7717 | uint64_t hcr = arm_hcr_el2_eff(env); |
7718 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7719 | return CP_ACCESS_TRAP_EL2; | |
7720 | } | |
4b779ceb RH |
7721 | } |
7722 | if (el < 3 && | |
7723 | arm_feature(env, ARM_FEATURE_EL3) && | |
7724 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7725 | return CP_ACCESS_TRAP_EL3; | |
7726 | } | |
7727 | return CP_ACCESS_OK; | |
7728 | } | |
7729 | ||
7730 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7731 | { | |
7732 | return env->pstate & PSTATE_TCO; | |
7733 | } | |
7734 | ||
7735 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7736 | { | |
7737 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7738 | } | |
7739 | ||
7740 | static const ARMCPRegInfo mte_reginfo[] = { | |
7741 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7742 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7743 | .access = PL1_RW, .accessfn = access_mte, | |
7744 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7745 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7746 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7747 | .access = PL1_RW, .accessfn = access_mte, | |
7748 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7749 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7750 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7751 | .access = PL2_RW, .accessfn = access_mte, | |
7752 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7753 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7754 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7755 | .access = PL3_RW, | |
7756 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7757 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7758 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7759 | .access = PL1_RW, .accessfn = access_mte, | |
7760 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7761 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7762 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7763 | .access = PL1_RW, .accessfn = access_mte, | |
7764 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
4b779ceb RH |
7765 | { .name = "TCO", .state = ARM_CP_STATE_AA64, |
7766 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7767 | .type = ARM_CP_NO_RAW, | |
7768 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7769 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7770 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7771 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7772 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7773 | .accessfn = aa64_cacheop_poc_access }, |
7774 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7775 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
dd345653 | 7776 | .fgt = FGT_DCISW, |
5463df16 RH |
7777 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7778 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7779 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7780 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7781 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7782 | .accessfn = aa64_cacheop_poc_access }, |
7783 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7784 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
dd345653 | 7785 | .fgt = FGT_DCISW, |
5463df16 RH |
7786 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7787 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7788 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
dd345653 | 7789 | .fgt = FGT_DCCSW, |
5463df16 RH |
7790 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7791 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7792 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
dd345653 | 7793 | .fgt = FGT_DCCSW, |
5463df16 RH |
7794 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7795 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7796 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
dd345653 | 7797 | .fgt = FGT_DCCISW, |
5463df16 RH |
7798 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7799 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7800 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
dd345653 | 7801 | .fgt = FGT_DCCISW, |
5463df16 | 7802 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
4b779ceb RH |
7803 | }; |
7804 | ||
7805 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7806 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7807 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7808 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
4b779ceb | 7809 | }; |
5463df16 RH |
7810 | |
7811 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7812 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7813 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7814 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7815 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7816 | .accessfn = aa64_cacheop_poc_access }, |
7817 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7818 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7819 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7820 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7821 | .accessfn = aa64_cacheop_poc_access }, |
7822 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7823 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7824 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7825 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7826 | .accessfn = aa64_cacheop_poc_access }, |
7827 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7828 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7829 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7830 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7831 | .accessfn = aa64_cacheop_poc_access }, |
7832 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7833 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7834 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7835 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7836 | .accessfn = aa64_cacheop_poc_access }, |
7837 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7838 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7839 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7840 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7841 | .accessfn = aa64_cacheop_poc_access }, |
7842 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7843 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7844 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7845 | .fgt = FGT_DCCIVAC, |
5463df16 RH |
7846 | .accessfn = aa64_cacheop_poc_access }, |
7847 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7848 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7849 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7850 | .fgt = FGT_DCCIVAC, |
5463df16 | 7851 | .accessfn = aa64_cacheop_poc_access }, |
eb821168 RH |
7852 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7853 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7854 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7855 | #ifndef CONFIG_USER_ONLY | |
7856 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7857 | .accessfn = aa64_zva_access, | |
dd345653 | 7858 | .fgt = FGT_DCZVA, |
eb821168 RH |
7859 | #endif |
7860 | }, | |
7861 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7862 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7863 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7864 | #ifndef CONFIG_USER_ONLY | |
7865 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7866 | .accessfn = aa64_zva_access, | |
dd345653 | 7867 | .fgt = FGT_DCZVA, |
eb821168 RH |
7868 | #endif |
7869 | }, | |
5463df16 RH |
7870 | }; |
7871 | ||
7cb1e618 RH |
7872 | static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, |
7873 | bool isread) | |
7874 | { | |
7875 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7876 | int el = arm_current_el(env); | |
7877 | ||
7878 | if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | |
7879 | if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | |
7880 | if (hcr & HCR_TGE) { | |
7881 | return CP_ACCESS_TRAP_EL2; | |
7882 | } | |
7883 | return CP_ACCESS_TRAP; | |
7884 | } | |
7885 | } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | |
7886 | return CP_ACCESS_TRAP_EL2; | |
7887 | } | |
7888 | if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | |
7889 | return CP_ACCESS_TRAP_EL2; | |
7890 | } | |
7891 | if (el < 3 | |
7892 | && arm_feature(env, ARM_FEATURE_EL3) | |
7893 | && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | |
7894 | return CP_ACCESS_TRAP_EL3; | |
7895 | } | |
7896 | return CP_ACCESS_OK; | |
7897 | } | |
7898 | ||
7899 | static const ARMCPRegInfo scxtnum_reginfo[] = { | |
7900 | { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | |
7901 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | |
7902 | .access = PL0_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7903 | .fgt = FGT_SCXTNUM_EL0, |
7cb1e618 RH |
7904 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, |
7905 | { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | |
7906 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | |
7907 | .access = PL1_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7908 | .fgt = FGT_SCXTNUM_EL1, |
7cb1e618 RH |
7909 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, |
7910 | { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | |
7911 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | |
7912 | .access = PL2_RW, .accessfn = access_scxtnum, | |
7913 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | |
7914 | { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | |
7915 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | |
7916 | .access = PL3_RW, | |
7917 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | |
7918 | }; | |
15126d9c PM |
7919 | |
7920 | static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, | |
7921 | bool isread) | |
7922 | { | |
7923 | if (arm_current_el(env) == 2 && | |
7924 | arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { | |
7925 | return CP_ACCESS_TRAP_EL3; | |
7926 | } | |
7927 | return CP_ACCESS_OK; | |
7928 | } | |
7929 | ||
7930 | static const ARMCPRegInfo fgt_reginfo[] = { | |
7931 | { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
7932 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
7933 | .access = PL2_RW, .accessfn = access_fgt, | |
7934 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) }, | |
7935 | { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
7936 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5, | |
7937 | .access = PL2_RW, .accessfn = access_fgt, | |
7938 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) }, | |
7939 | { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
7940 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4, | |
7941 | .access = PL2_RW, .accessfn = access_fgt, | |
7942 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) }, | |
7943 | { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
7944 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5, | |
7945 | .access = PL2_RW, .accessfn = access_fgt, | |
7946 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) }, | |
7947 | { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64, | |
7948 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6, | |
7949 | .access = PL2_RW, .accessfn = access_fgt, | |
7950 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, | |
7951 | }; | |
7cb1e618 | 7952 | #endif /* TARGET_AARCH64 */ |
967aa94f | 7953 | |
cb570bd3 RH |
7954 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
7955 | bool isread) | |
7956 | { | |
7957 | int el = arm_current_el(env); | |
7958 | ||
7959 | if (el == 0) { | |
7960 | uint64_t sctlr = arm_sctlr(env, el); | |
7961 | if (!(sctlr & SCTLR_EnRCTX)) { | |
7962 | return CP_ACCESS_TRAP; | |
7963 | } | |
7964 | } else if (el == 1) { | |
7965 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7966 | if (hcr & HCR_NV) { | |
7967 | return CP_ACCESS_TRAP_EL2; | |
7968 | } | |
7969 | } | |
7970 | return CP_ACCESS_OK; | |
7971 | } | |
7972 | ||
7973 | static const ARMCPRegInfo predinv_reginfo[] = { | |
7974 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
7975 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 7976 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
7977 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7978 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
7979 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 7980 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
7981 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7982 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
7983 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 7984 | .fgt = FGT_CPPRCTX, |
cb570bd3 RH |
7985 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7986 | /* | |
7987 | * Note the AArch32 opcodes have a different OPC1. | |
7988 | */ | |
7989 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
7990 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 7991 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
7992 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7993 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
7994 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 7995 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
7996 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7997 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
7998 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 7999 | .fgt = FGT_CPPRCTX, |
cb570bd3 | 8000 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
cb570bd3 RH |
8001 | }; |
8002 | ||
957e6155 PM |
8003 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
8004 | { | |
8005 | /* Read the high 32 bits of the current CCSIDR */ | |
8006 | return extract64(ccsidr_read(env, ri), 32, 32); | |
8007 | } | |
8008 | ||
8009 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
8010 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
8011 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
8012 | .access = PL1_R, | |
e2ce5fcd | 8013 | .accessfn = access_tid4, |
957e6155 | 8014 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, |
957e6155 PM |
8015 | }; |
8016 | ||
6a4ef4e5 MZ |
8017 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
8018 | bool isread) | |
8019 | { | |
8020 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
8021 | return CP_ACCESS_TRAP_EL2; | |
8022 | } | |
8023 | ||
8024 | return CP_ACCESS_OK; | |
8025 | } | |
8026 | ||
8027 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
8028 | bool isread) | |
8029 | { | |
8030 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
8031 | return access_aa64_tid3(env, ri, isread); | |
8032 | } | |
8033 | ||
8034 | return CP_ACCESS_OK; | |
8035 | } | |
8036 | ||
f96f3d5f MZ |
8037 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
8038 | bool isread) | |
8039 | { | |
8040 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
8041 | return CP_ACCESS_TRAP_EL2; | |
8042 | } | |
8043 | ||
8044 | return CP_ACCESS_OK; | |
8045 | } | |
8046 | ||
8e228c9e PM |
8047 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
8048 | const ARMCPRegInfo *ri, bool isread) | |
8049 | { | |
8050 | /* | |
8051 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
8052 | * in v7A, not in v8A. | |
8053 | */ | |
8054 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
8055 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
8056 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
8057 | return CP_ACCESS_TRAP_EL2; | |
8058 | } | |
8059 | return CP_ACCESS_OK; | |
8060 | } | |
8061 | ||
f96f3d5f MZ |
8062 | static const ARMCPRegInfo jazelle_regs[] = { |
8063 | { .name = "JIDR", | |
8064 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8065 | .access = PL1_R, .accessfn = access_jazelle, | |
8066 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8067 | { .name = "JOSCR", | |
8068 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8069 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
8070 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
8071 | { .name = "JMCR", | |
8072 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8073 | .accessfn = access_joscr_jmcr, |
f96f3d5f | 8074 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f96f3d5f MZ |
8075 | }; |
8076 | ||
52d18727 RH |
8077 | static const ARMCPRegInfo contextidr_el2 = { |
8078 | .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
8079 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
8080 | .access = PL2_RW, | |
8081 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | |
8082 | }; | |
8083 | ||
e2a1a461 | 8084 | static const ARMCPRegInfo vhe_reginfo[] = { |
ed30da8e RH |
8085 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
8086 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
8087 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
587f8b33 | 8088 | .raw_writefn = raw_write, |
ed30da8e | 8089 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, |
8c94b071 RH |
8090 | #ifndef CONFIG_USER_ONLY |
8091 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
8092 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
8093 | .fieldoffset = | |
8094 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
8095 | .type = ARM_CP_IO, .access = PL2_RW, | |
8096 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
8097 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
8098 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
8099 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
8100 | .resetfn = gt_hv_timer_reset, | |
8101 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
8102 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
8103 | .type = ARM_CP_IO, | |
8104 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
8105 | .access = PL2_RW, | |
8106 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
8107 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
8108 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
8109 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
8110 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8111 | .access = PL2_RW, .accessfn = e2h_access, | |
8112 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
8113 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
8114 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
8115 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
8116 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8117 | .access = PL2_RW, .accessfn = e2h_access, | |
8118 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
8119 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
8120 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8121 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
8122 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8123 | .access = PL2_RW, .accessfn = e2h_access, | |
8124 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
8125 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8126 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
8127 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8128 | .access = PL2_RW, .accessfn = e2h_access, | |
8129 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
8130 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8131 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
8132 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8133 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
8134 | .access = PL2_RW, .accessfn = e2h_access, | |
8135 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
8136 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8137 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
8138 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8139 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
8140 | .access = PL2_RW, .accessfn = e2h_access, | |
8141 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 8142 | #endif |
e2a1a461 RH |
8143 | }; |
8144 | ||
04b07d29 RH |
8145 | #ifndef CONFIG_USER_ONLY |
8146 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
3999d2d2 | 8147 | { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8148 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, |
8149 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8150 | .fgt = FGT_ATS1E1RP, |
1acd00ef | 8151 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
3999d2d2 | 8152 | { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8153 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, |
8154 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8155 | .fgt = FGT_ATS1E1WP, |
1acd00ef | 8156 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
04b07d29 RH |
8157 | }; |
8158 | ||
8159 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
8160 | { .name = "ATS1CPRP", | |
8161 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
8162 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8163 | .writefn = ats_write }, | |
8164 | { .name = "ATS1CPWP", | |
8165 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
8166 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8167 | .writefn = ats_write }, | |
04b07d29 RH |
8168 | }; |
8169 | #endif | |
8170 | ||
f6287c24 PM |
8171 | /* |
8172 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
8173 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
8174 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
8175 | * and mandatorily for ARMv8.2 and up. | |
8176 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
8177 | * implementation is RAZ/WI we can ignore this detail, as we | |
8178 | * do for ACTLR. | |
8179 | */ | |
8180 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
8181 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
8182 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
8183 | .access = PL1_RW, .accessfn = access_tacr, |
8184 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
8185 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
8186 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
8187 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8188 | .resetvalue = 0 }, | |
f6287c24 PM |
8189 | }; |
8190 | ||
2ceb98c0 PM |
8191 | void register_cp_regs_for_features(ARMCPU *cpu) |
8192 | { | |
8193 | /* Register all the coprocessor registers based on feature bits */ | |
8194 | CPUARMState *env = &cpu->env; | |
8195 | if (arm_feature(env, ARM_FEATURE_M)) { | |
8196 | /* M profile has no coprocessor registers */ | |
8197 | return; | |
8198 | } | |
8199 | ||
e9aa6c21 | 8200 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 | 8201 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9b37a28c FR |
8202 | /* |
8203 | * Must go early as it is full of wildcards that may be | |
9449fdf6 PM |
8204 | * overridden by later definitions. |
8205 | */ | |
8206 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
8207 | } | |
8208 | ||
7d57f408 | 8209 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
8210 | /* The ID registers all have impdef reset values */ |
8211 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
8212 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
8213 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
8214 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8215 | .accessfn = access_aa32_tid3, |
8a130a7b | 8216 | .resetvalue = cpu->isar.id_pfr0 }, |
9b37a28c FR |
8217 | /* |
8218 | * ID_PFR1 is not a plain ARM_CP_CONST because we don't know | |
96a8b92e PM |
8219 | * the value of the GIC field until after we define these regs. |
8220 | */ | |
0ff644a7 PM |
8221 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
8222 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 8223 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 8224 | .accessfn = access_aa32_tid3, |
0f150c84 PMD |
8225 | #ifdef CONFIG_USER_ONLY |
8226 | .type = ARM_CP_CONST, | |
8227 | .resetvalue = cpu->isar.id_pfr1, | |
8228 | #else | |
8229 | .type = ARM_CP_NO_RAW, | |
8230 | .accessfn = access_aa32_tid3, | |
96a8b92e | 8231 | .readfn = id_pfr1_read, |
0f150c84 PMD |
8232 | .writefn = arm_cp_write_ignore |
8233 | #endif | |
8234 | }, | |
0ff644a7 PM |
8235 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
8236 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
8237 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8238 | .accessfn = access_aa32_tid3, |
a6179538 | 8239 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
8240 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
8241 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
8242 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8243 | .accessfn = access_aa32_tid3, |
8515a092 | 8244 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
8245 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
8246 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
8247 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8248 | .accessfn = access_aa32_tid3, |
10054016 | 8249 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
8250 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
8251 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
8252 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8253 | .accessfn = access_aa32_tid3, |
10054016 | 8254 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
8255 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
8256 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
8257 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8258 | .accessfn = access_aa32_tid3, |
10054016 | 8259 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
8260 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
8261 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
8262 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8263 | .accessfn = access_aa32_tid3, |
10054016 | 8264 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
8265 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
8266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
8267 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8268 | .accessfn = access_aa32_tid3, |
47576b94 | 8269 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
8270 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
8271 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
8272 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8273 | .accessfn = access_aa32_tid3, |
47576b94 | 8274 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
8275 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
8276 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
8277 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8278 | .accessfn = access_aa32_tid3, |
47576b94 | 8279 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
8280 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
8281 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
8282 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8283 | .accessfn = access_aa32_tid3, |
47576b94 | 8284 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
8285 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
8286 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
8287 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8288 | .accessfn = access_aa32_tid3, |
47576b94 | 8289 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
8290 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
8291 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
8292 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8293 | .accessfn = access_aa32_tid3, |
47576b94 | 8294 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
8295 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
8296 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
8297 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8298 | .accessfn = access_aa32_tid3, |
10054016 | 8299 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 8300 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8301 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
8302 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8303 | .accessfn = access_aa32_tid3, |
47576b94 | 8304 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
8305 | }; |
8306 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
8307 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
8308 | } else { | |
8309 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
8310 | } | |
4d31c596 PM |
8311 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
8312 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
8313 | } | |
5e5cf9e3 | 8314 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 8315 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
8316 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
8317 | } | |
327dd510 AL |
8318 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
8319 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
8320 | } | |
e9aa6c21 | 8321 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 8322 | ARMCPRegInfo clidr = { |
7da845b0 PM |
8323 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
8324 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d | 8325 | .access = PL1_R, .type = ARM_CP_CONST, |
e2ce5fcd | 8326 | .accessfn = access_tid4, |
158c276c | 8327 | .fgt = FGT_CLIDR_EL1, |
630fcd4d | 8328 | .resetvalue = cpu->clidr |
776d4e5c | 8329 | }; |
776d4e5c | 8330 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 8331 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 8332 | define_debug_regs(cpu); |
24183fb6 | 8333 | define_pmu_regs(cpu); |
7d57f408 PM |
8334 | } else { |
8335 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 8336 | } |
b0d2b7d0 | 8337 | if (arm_feature(env, ARM_FEATURE_V8)) { |
dde4d028 PM |
8338 | /* |
8339 | * v8 ID registers, which all have impdef reset values. | |
e20d84c1 PM |
8340 | * Note that within the ID register ranges the unused slots |
8341 | * must all RAZ, not UNDEF; future architecture versions may | |
8342 | * define new registers here. | |
dde4d028 PM |
8343 | * ID registers which are AArch64 views of the AArch32 ID registers |
8344 | * which already existed in v6 and v7 are handled elsewhere, | |
8345 | * in v6_idregs[]. | |
e20d84c1 | 8346 | */ |
dde4d028 | 8347 | int i; |
e60cef86 | 8348 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
8349 | /* |
8350 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
8351 | * emulation because we don't know the right value for the | |
8352 | * GIC field until after we define these regs. | |
96a8b92e | 8353 | */ |
e60cef86 PM |
8354 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
8355 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
8356 | .access = PL1_R, |
8357 | #ifdef CONFIG_USER_ONLY | |
8358 | .type = ARM_CP_CONST, | |
8359 | .resetvalue = cpu->isar.id_aa64pfr0 | |
8360 | #else | |
8361 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 8362 | .accessfn = access_aa64_tid3, |
96a8b92e | 8363 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
8364 | .writefn = arm_cp_write_ignore |
8365 | #endif | |
8366 | }, | |
e60cef86 PM |
8367 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
8368 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
8369 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8370 | .accessfn = access_aa64_tid3, |
47576b94 | 8371 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
8372 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8373 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
8374 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8375 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8376 | .resetvalue = 0 }, |
8377 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8378 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
8379 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8380 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8381 | .resetvalue = 0 }, |
9516d772 | 8382 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8383 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
8384 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8385 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 8386 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
414c54d5 | 8387 | { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8388 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, |
8389 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8390 | .accessfn = access_aa64_tid3, |
414c54d5 | 8391 | .resetvalue = cpu->isar.id_aa64smfr0 }, |
e20d84c1 PM |
8392 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8393 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
8394 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8395 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8396 | .resetvalue = 0 }, |
8397 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8398 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
8399 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8400 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8401 | .resetvalue = 0 }, |
e60cef86 PM |
8402 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
8403 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
8404 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8405 | .accessfn = access_aa64_tid3, |
2a609df8 | 8406 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
8407 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
8408 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
8409 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8410 | .accessfn = access_aa64_tid3, |
2a609df8 | 8411 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
8412 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8413 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
8414 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8415 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8416 | .resetvalue = 0 }, |
8417 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8418 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
8419 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8420 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8421 | .resetvalue = 0 }, |
e60cef86 PM |
8422 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
8423 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
8424 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8425 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
8426 | .resetvalue = cpu->id_aa64afr0 }, |
8427 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
8428 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
8429 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8430 | .accessfn = access_aa64_tid3, |
e60cef86 | 8431 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
8432 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8433 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
8434 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8435 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8436 | .resetvalue = 0 }, |
8437 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8438 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
8439 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8440 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8441 | .resetvalue = 0 }, |
e60cef86 PM |
8442 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
8443 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
8444 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8445 | .accessfn = access_aa64_tid3, |
47576b94 | 8446 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
8447 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
8448 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
8449 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8450 | .accessfn = access_aa64_tid3, |
47576b94 | 8451 | .resetvalue = cpu->isar.id_aa64isar1 }, |
a969fe97 | 8452 | { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8453 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, |
8454 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8455 | .accessfn = access_aa64_tid3, |
a969fe97 | 8456 | .resetvalue = cpu->isar.id_aa64isar2 }, |
e20d84c1 PM |
8457 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8458 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
8459 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8460 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8461 | .resetvalue = 0 }, |
8462 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8463 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
8464 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8465 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8466 | .resetvalue = 0 }, |
8467 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8468 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
8469 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8470 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8471 | .resetvalue = 0 }, |
8472 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8473 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
8474 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8475 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8476 | .resetvalue = 0 }, |
8477 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8478 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
8479 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8480 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8481 | .resetvalue = 0 }, |
e60cef86 PM |
8482 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
8483 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
8484 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8485 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8486 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
8487 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
8488 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
8489 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8490 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8491 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 8492 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8493 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
8494 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8495 | .accessfn = access_aa64_tid3, |
64761e10 | 8496 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
8497 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8498 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
8499 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8500 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8501 | .resetvalue = 0 }, |
8502 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8503 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
8504 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8505 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8506 | .resetvalue = 0 }, |
8507 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8508 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
8509 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8510 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8511 | .resetvalue = 0 }, |
8512 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8513 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
8514 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8515 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8516 | .resetvalue = 0 }, |
8517 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8518 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
8519 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8520 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8521 | .resetvalue = 0 }, |
a50c0f51 PM |
8522 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
8523 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8524 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8525 | .accessfn = access_aa64_tid3, |
47576b94 | 8526 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
8527 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
8528 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8529 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8530 | .accessfn = access_aa64_tid3, |
47576b94 | 8531 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
8532 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
8533 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8534 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8535 | .accessfn = access_aa64_tid3, |
47576b94 | 8536 | .resetvalue = cpu->isar.mvfr2 }, |
dde4d028 PM |
8537 | /* |
8538 | * "0, c0, c3, {0,1,2}" are the encodings corresponding to | |
8539 | * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding | |
8540 | * as RAZ, since it is in the "reserved for future ID | |
8541 | * registers, RAZ" part of the AArch32 encoding space. | |
8542 | */ | |
8543 | { .name = "RES_0_C0_C3_0", .state = ARM_CP_STATE_AA32, | |
8544 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8545 | .access = PL1_R, .type = ARM_CP_CONST, | |
8546 | .accessfn = access_aa64_tid3, | |
8547 | .resetvalue = 0 }, | |
8548 | { .name = "RES_0_C0_C3_1", .state = ARM_CP_STATE_AA32, | |
8549 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8550 | .access = PL1_R, .type = ARM_CP_CONST, | |
8551 | .accessfn = access_aa64_tid3, | |
8552 | .resetvalue = 0 }, | |
8553 | { .name = "RES_0_C0_C3_2", .state = ARM_CP_STATE_AA32, | |
8554 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8555 | .access = PL1_R, .type = ARM_CP_CONST, | |
8556 | .accessfn = access_aa64_tid3, | |
8557 | .resetvalue = 0 }, | |
8558 | /* | |
8559 | * Other encodings in "0, c0, c3, ..." are STATE_BOTH because | |
8560 | * they're also RAZ for AArch64, and in v8 are gradually | |
8561 | * being filled with AArch64-view-of-AArch32-ID-register | |
8562 | * for new ID registers. | |
8563 | */ | |
8564 | { .name = "RES_0_C0_C3_3", .state = ARM_CP_STATE_BOTH, | |
e20d84c1 PM |
8565 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, |
8566 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8567 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8568 | .resetvalue = 0 }, |
1d51bc96 | 8569 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8570 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
8571 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8572 | .accessfn = access_aa64_tid3, |
1d51bc96 | 8573 | .resetvalue = cpu->isar.id_pfr2 }, |
d22c5649 | 8574 | { .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8575 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, |
8576 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8577 | .accessfn = access_aa64_tid3, |
d22c5649 | 8578 | .resetvalue = cpu->isar.id_dfr1 }, |
32957aad | 8579 | { .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8580 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, |
8581 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8582 | .accessfn = access_aa64_tid3, |
32957aad | 8583 | .resetvalue = cpu->isar.id_mmfr5 }, |
dde4d028 | 8584 | { .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8585 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, |
8586 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8587 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8588 | .resetvalue = 0 }, |
4054bfa9 AF |
8589 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
8590 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
8591 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8592 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8593 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
8594 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
8595 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
8596 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8597 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 AF |
8598 | .resetvalue = cpu->pmceid0 }, |
8599 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
8600 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
8601 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8602 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8603 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
8604 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
8605 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
8606 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8607 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 | 8608 | .resetvalue = cpu->pmceid1 }, |
e60cef86 | 8609 | }; |
6c5c0fec | 8610 | #ifdef CONFIG_USER_ONLY |
10b0220e | 8611 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
6c5c0fec | 8612 | { .name = "ID_AA64PFR0_EL1", |
bc6bd20e ZS |
8613 | .exported_bits = R_ID_AA64PFR0_FP_MASK | |
8614 | R_ID_AA64PFR0_ADVSIMD_MASK | | |
8615 | R_ID_AA64PFR0_SVE_MASK | | |
8616 | R_ID_AA64PFR0_DIT_MASK, | |
8617 | .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) | | |
8618 | (0x1u << R_ID_AA64PFR0_EL1_SHIFT) }, | |
6c5c0fec | 8619 | { .name = "ID_AA64PFR1_EL1", |
bc6bd20e ZS |
8620 | .exported_bits = R_ID_AA64PFR1_BT_MASK | |
8621 | R_ID_AA64PFR1_SSBS_MASK | | |
8622 | R_ID_AA64PFR1_MTE_MASK | | |
8623 | R_ID_AA64PFR1_SME_MASK }, | |
d040242e | 8624 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
bc6bd20e ZS |
8625 | .is_glob = true }, |
8626 | { .name = "ID_AA64ZFR0_EL1", | |
8627 | .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK | | |
8628 | R_ID_AA64ZFR0_AES_MASK | | |
8629 | R_ID_AA64ZFR0_BITPERM_MASK | | |
8630 | R_ID_AA64ZFR0_BFLOAT16_MASK | | |
8631 | R_ID_AA64ZFR0_SHA3_MASK | | |
8632 | R_ID_AA64ZFR0_SM4_MASK | | |
8633 | R_ID_AA64ZFR0_I8MM_MASK | | |
8634 | R_ID_AA64ZFR0_F32MM_MASK | | |
8635 | R_ID_AA64ZFR0_F64MM_MASK }, | |
8636 | { .name = "ID_AA64SMFR0_EL1", | |
8637 | .exported_bits = R_ID_AA64SMFR0_F32F32_MASK | | |
5f7b71fb | 8638 | R_ID_AA64SMFR0_BI32I32_MASK | |
bc6bd20e ZS |
8639 | R_ID_AA64SMFR0_B16F32_MASK | |
8640 | R_ID_AA64SMFR0_F16F32_MASK | | |
8641 | R_ID_AA64SMFR0_I8I32_MASK | | |
5f7b71fb PM |
8642 | R_ID_AA64SMFR0_F16F16_MASK | |
8643 | R_ID_AA64SMFR0_B16B16_MASK | | |
8644 | R_ID_AA64SMFR0_I16I32_MASK | | |
bc6bd20e ZS |
8645 | R_ID_AA64SMFR0_F64F64_MASK | |
8646 | R_ID_AA64SMFR0_I16I64_MASK | | |
5f7b71fb | 8647 | R_ID_AA64SMFR0_SMEVER_MASK | |
bc6bd20e | 8648 | R_ID_AA64SMFR0_FA64_MASK }, |
6c5c0fec | 8649 | { .name = "ID_AA64MMFR0_EL1", |
bc6bd20e ZS |
8650 | .exported_bits = R_ID_AA64MMFR0_ECV_MASK, |
8651 | .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) | | |
8652 | (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, | |
8653 | { .name = "ID_AA64MMFR1_EL1", | |
8654 | .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, | |
8655 | { .name = "ID_AA64MMFR2_EL1", | |
8656 | .exported_bits = R_ID_AA64MMFR2_AT_MASK }, | |
d040242e | 8657 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
bc6bd20e | 8658 | .is_glob = true }, |
6c5c0fec | 8659 | { .name = "ID_AA64DFR0_EL1", |
bc6bd20e ZS |
8660 | .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, |
8661 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e | 8662 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
bc6bd20e | 8663 | .is_glob = true }, |
d040242e | 8664 | { .name = "ID_AA64AFR*", |
bc6bd20e | 8665 | .is_glob = true }, |
6c5c0fec | 8666 | { .name = "ID_AA64ISAR0_EL1", |
bc6bd20e ZS |
8667 | .exported_bits = R_ID_AA64ISAR0_AES_MASK | |
8668 | R_ID_AA64ISAR0_SHA1_MASK | | |
8669 | R_ID_AA64ISAR0_SHA2_MASK | | |
8670 | R_ID_AA64ISAR0_CRC32_MASK | | |
8671 | R_ID_AA64ISAR0_ATOMIC_MASK | | |
8672 | R_ID_AA64ISAR0_RDM_MASK | | |
8673 | R_ID_AA64ISAR0_SHA3_MASK | | |
8674 | R_ID_AA64ISAR0_SM3_MASK | | |
8675 | R_ID_AA64ISAR0_SM4_MASK | | |
8676 | R_ID_AA64ISAR0_DP_MASK | | |
8677 | R_ID_AA64ISAR0_FHM_MASK | | |
8678 | R_ID_AA64ISAR0_TS_MASK | | |
8679 | R_ID_AA64ISAR0_RNDR_MASK }, | |
6c5c0fec | 8680 | { .name = "ID_AA64ISAR1_EL1", |
bc6bd20e ZS |
8681 | .exported_bits = R_ID_AA64ISAR1_DPB_MASK | |
8682 | R_ID_AA64ISAR1_APA_MASK | | |
8683 | R_ID_AA64ISAR1_API_MASK | | |
8684 | R_ID_AA64ISAR1_JSCVT_MASK | | |
8685 | R_ID_AA64ISAR1_FCMA_MASK | | |
8686 | R_ID_AA64ISAR1_LRCPC_MASK | | |
8687 | R_ID_AA64ISAR1_GPA_MASK | | |
8688 | R_ID_AA64ISAR1_GPI_MASK | | |
8689 | R_ID_AA64ISAR1_FRINTTS_MASK | | |
8690 | R_ID_AA64ISAR1_SB_MASK | | |
8691 | R_ID_AA64ISAR1_BF16_MASK | | |
8692 | R_ID_AA64ISAR1_DGH_MASK | | |
8693 | R_ID_AA64ISAR1_I8MM_MASK }, | |
8694 | { .name = "ID_AA64ISAR2_EL1", | |
8695 | .exported_bits = R_ID_AA64ISAR2_WFXT_MASK | | |
8696 | R_ID_AA64ISAR2_RPRES_MASK | | |
8697 | R_ID_AA64ISAR2_GPA3_MASK | | |
5f7b71fb PM |
8698 | R_ID_AA64ISAR2_APA3_MASK | |
8699 | R_ID_AA64ISAR2_MOPS_MASK | | |
8700 | R_ID_AA64ISAR2_BC_MASK | | |
8701 | R_ID_AA64ISAR2_RPRFM_MASK | | |
8702 | R_ID_AA64ISAR2_CSSC_MASK }, | |
d040242e | 8703 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
bc6bd20e | 8704 | .is_glob = true }, |
6c5c0fec AB |
8705 | }; |
8706 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
8707 | #endif | |
97198a7d RH |
8708 | /* |
8709 | * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL. | |
8710 | * TODO: For RMR, a write with bit 1 set should do something with | |
8711 | * cpu_reset(). In the meantime, "the bit is strictly a request", | |
8712 | * so we are in spec just ignoring writes. | |
8713 | */ | |
be8e8128 GB |
8714 | if (!arm_feature(env, ARM_FEATURE_EL3) && |
8715 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
97198a7d RH |
8716 | ARMCPRegInfo el1_reset_regs[] = { |
8717 | { .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH, | |
8718 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8719 | .access = PL1_R, | |
8720 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8721 | { .name = "RMR_EL1", .state = ARM_CP_STATE_BOTH, | |
8722 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8723 | .access = PL1_RW, .type = ARM_CP_CONST, | |
8724 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) } | |
be8e8128 | 8725 | }; |
97198a7d | 8726 | define_arm_cp_regs(cpu, el1_reset_regs); |
be8e8128 | 8727 | } |
e60cef86 | 8728 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 | 8729 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
dde4d028 PM |
8730 | |
8731 | for (i = 4; i < 16; i++) { | |
8732 | /* | |
8733 | * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. | |
8734 | * For pre-v8 cores there are RAZ patterns for these in | |
8735 | * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here. | |
8736 | * v8 extends the "must RAZ" part of the ID register space | |
8737 | * to also cover c0, 0, c{8-15}, {0-7}. | |
8738 | * These are STATE_AA32 because in the AArch64 sysreg space | |
8739 | * c4-c7 is where the AArch64 ID registers live (and we've | |
8740 | * already defined those in v8_idregs[]), and c8-c15 are not | |
8741 | * "must RAZ" for AArch64. | |
8742 | */ | |
8743 | g_autofree char *name = g_strdup_printf("RES_0_C0_C%d_X", i); | |
8744 | ARMCPRegInfo v8_aa32_raz_idregs = { | |
8745 | .name = name, | |
8746 | .state = ARM_CP_STATE_AA32, | |
8747 | .cp = 15, .opc1 = 0, .crn = 0, .crm = i, .opc2 = CP_ANY, | |
8748 | .access = PL1_R, .type = ARM_CP_CONST, | |
8749 | .accessfn = access_aa64_tid3, | |
8750 | .resetvalue = 0 }; | |
8751 | define_one_arm_cp_reg(cpu, &v8_aa32_raz_idregs); | |
8752 | } | |
b0d2b7d0 | 8753 | } |
99a90811 RH |
8754 | |
8755 | /* | |
8756 | * Register the base EL2 cpregs. | |
8757 | * Pre v8, these registers are implemented only as part of the | |
8758 | * Virtualization Extensions (EL2 present). Beginning with v8, | |
8759 | * if EL2 is missing but EL3 is enabled, mostly these become | |
8760 | * RES0 from EL3, with some specific exceptions. | |
8761 | */ | |
8762 | if (arm_feature(env, ARM_FEATURE_EL2) | |
8763 | || (arm_feature(env, ARM_FEATURE_EL3) | |
8764 | && arm_feature(env, ARM_FEATURE_V8))) { | |
f0d574d6 | 8765 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
8766 | ARMCPRegInfo vpidr_regs[] = { |
8767 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
8768 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8769 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8770 | .resetvalue = cpu->midr, |
8771 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8772 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, |
731de9e6 EI |
8773 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8774 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8775 | .access = PL2_RW, .resetvalue = cpu->midr, | |
696ba377 | 8776 | .type = ARM_CP_EL3_NO_EL2_C_NZ, |
731de9e6 | 8777 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, |
f0d574d6 EI |
8778 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
8779 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
8780 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8781 | .resetvalue = vmpidr_def, |
8782 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8783 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, |
f0d574d6 EI |
8784 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8785 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
696ba377 RH |
8786 | .access = PL2_RW, .resetvalue = vmpidr_def, |
8787 | .type = ARM_CP_EL3_NO_EL2_C_NZ, | |
f0d574d6 | 8788 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, |
731de9e6 | 8789 | }; |
24526bb9 PM |
8790 | /* |
8791 | * The only field of MDCR_EL2 that has a defined architectural reset | |
8792 | * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
8793 | */ | |
8794 | ARMCPRegInfo mdcr_el2 = { | |
7f4fbfb5 | 8795 | .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO, |
24526bb9 | 8796 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, |
01765386 | 8797 | .writefn = mdcr_el2_write, |
24526bb9 PM |
8798 | .access = PL2_RW, .resetvalue = pmu_num_counters(env), |
8799 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), | |
8800 | }; | |
8801 | define_one_arm_cp_reg(cpu, &mdcr_el2); | |
731de9e6 | 8802 | define_arm_cp_regs(cpu, vpidr_regs); |
4771cd01 | 8803 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
8804 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8805 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
8806 | } | |
e9152ee9 RDC |
8807 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
8808 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
8809 | } | |
97198a7d RH |
8810 | /* |
8811 | * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL. | |
8812 | * See commentary near RMR_EL1. | |
8813 | */ | |
be8e8128 | 8814 | if (!arm_feature(env, ARM_FEATURE_EL3)) { |
97198a7d RH |
8815 | static const ARMCPRegInfo el2_reset_regs[] = { |
8816 | { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
8817 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
8818 | .access = PL2_R, | |
8819 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8820 | { .name = "RVBAR", .type = ARM_CP_ALIAS, | |
8821 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8822 | .access = PL2_R, | |
8823 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8824 | { .name = "RMR_EL2", .state = ARM_CP_STATE_AA64, | |
8825 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 2, | |
8826 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
be8e8128 | 8827 | }; |
97198a7d | 8828 | define_arm_cp_regs(cpu, el2_reset_regs); |
be8e8128 | 8829 | } |
3b685ba7 | 8830 | } |
99a90811 RH |
8831 | |
8832 | /* Register the base EL3 cpregs. */ | |
81547d66 | 8833 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 8834 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
8835 | ARMCPRegInfo el3_regs[] = { |
8836 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
8837 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 | 8838 | .access = PL3_R, |
97198a7d RH |
8839 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }, |
8840 | { .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, | |
8841 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, | |
8842 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
8843 | { .name = "RMR", .state = ARM_CP_STATE_AA32, | |
8844 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8845 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8846 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) }, | |
e24fdd23 PM |
8847 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
8848 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
8849 | .access = PL3_RW, | |
8850 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
8851 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
8852 | .resetvalue = cpu->reset_sctlr }, | |
be8e8128 | 8853 | }; |
e24fdd23 PM |
8854 | |
8855 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 8856 | } |
9b37a28c FR |
8857 | /* |
8858 | * The behaviour of NSACR is sufficiently various that we don't | |
2f027fc5 PM |
8859 | * try to describe it in a single reginfo: |
8860 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
8861 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
8862 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
8863 | * if v7 without EL3, register doesn't exist | |
8864 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8865 | */ | |
8866 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8867 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
10b0220e | 8868 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8869 | .name = "NSACR", .type = ARM_CP_CONST, |
8870 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8871 | .access = PL1_RW, .accessfn = nsacr_access, | |
8872 | .resetvalue = 0xc00 | |
8873 | }; | |
8874 | define_one_arm_cp_reg(cpu, &nsacr); | |
8875 | } else { | |
10b0220e | 8876 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8877 | .name = "NSACR", |
8878 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8879 | .access = PL3_RW | PL1_R, | |
8880 | .resetvalue = 0, | |
8881 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8882 | }; | |
8883 | define_one_arm_cp_reg(cpu, &nsacr); | |
8884 | } | |
8885 | } else { | |
8886 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
10b0220e | 8887 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8888 | .name = "NSACR", .type = ARM_CP_CONST, |
8889 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8890 | .access = PL1_R, | |
8891 | .resetvalue = 0xc00 | |
8892 | }; | |
8893 | define_one_arm_cp_reg(cpu, &nsacr); | |
8894 | } | |
8895 | } | |
8896 | ||
452a0955 | 8897 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8898 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8899 | /* PMSAv6 not implemented */ | |
8900 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8901 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8902 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8903 | } else { | |
8904 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8905 | } | |
18032bec | 8906 | } else { |
8e5d75c9 | 8907 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8908 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8909 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8910 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8911 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8912 | } | |
18032bec | 8913 | } |
c326b979 PM |
8914 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8915 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8916 | } | |
6cc7a3ae PM |
8917 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
8918 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
8919 | } | |
4a501606 PM |
8920 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8921 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
8922 | } | |
c4804214 PM |
8923 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
8924 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
8925 | } | |
8926 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
8927 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
8928 | } | |
8929 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
8930 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
8931 | } | |
18032bec PM |
8932 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
8933 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
8934 | } | |
34f90529 PM |
8935 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
8936 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
8937 | } | |
1047b9d7 PM |
8938 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
8939 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
8940 | } | |
8941 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
8942 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
8943 | } | |
7ac681cf PM |
8944 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8945 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
8946 | } | |
873b73c0 | 8947 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
8948 | define_arm_cp_regs(cpu, jazelle_regs); |
8949 | } | |
9b37a28c FR |
8950 | /* |
8951 | * Slightly awkwardly, the OMAP and StrongARM cores need all of | |
7884849c PM |
8952 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should |
8953 | * be read-only (ie write causes UNDEF exception). | |
8954 | */ | |
8955 | { | |
00a29f3d | 8956 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
9b37a28c FR |
8957 | /* |
8958 | * Pre-v8 MIDR space. | |
00a29f3d | 8959 | * Note that the MIDR isn't a simple constant register because |
7884849c PM |
8960 | * of the TI925 behaviour where writes to another register can |
8961 | * cause the MIDR value to change. | |
97ce8d61 PC |
8962 | * |
8963 | * Unimplemented registers in the c15 0 0 0 space default to | |
8964 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
8965 | * and friends override accordingly. | |
7884849c PM |
8966 | */ |
8967 | { .name = "MIDR", | |
97ce8d61 | 8968 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 8969 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 8970 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 8971 | .readfn = midr_read, |
97ce8d61 PC |
8972 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8973 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
8974 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
8975 | { .name = "DUMMY", | |
8976 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
8977 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8978 | { .name = "DUMMY", | |
8979 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
8980 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8981 | { .name = "DUMMY", | |
8982 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
8983 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8984 | { .name = "DUMMY", | |
8985 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
8986 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8987 | { .name = "DUMMY", | |
8988 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
8989 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7884849c | 8990 | }; |
00a29f3d | 8991 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
8992 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8993 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 | 8994 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
67dd8030 | 8995 | .fgt = FGT_MIDR_EL1, |
731de9e6 EI |
8996 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8997 | .readfn = midr_read }, | |
c7f786ab | 8998 | /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */ |
ac00c79f SF |
8999 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, |
9000 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
9001 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
9002 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
9003 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
9004 | .access = PL1_R, |
9005 | .accessfn = access_aa64_tid1, | |
67dd8030 | 9006 | .fgt = FGT_REVIDR_EL1, |
93fbc983 | 9007 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d | 9008 | }; |
c7f786ab TR |
9009 | ARMCPRegInfo id_v8_midr_alias_cp_reginfo = { |
9010 | .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
9011 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
9012 | .access = PL1_R, .resetvalue = cpu->midr | |
9013 | }; | |
00a29f3d PM |
9014 | ARMCPRegInfo id_cp_reginfo[] = { |
9015 | /* These are common to v8 and pre-v8 */ | |
9016 | { .name = "CTR", | |
9017 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
9018 | .access = PL1_R, .accessfn = ctr_el0_access, |
9019 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
9020 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
9021 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
9022 | .access = PL0_R, .accessfn = ctr_el0_access, | |
b19ed03c | 9023 | .fgt = FGT_CTR_EL0, |
00a29f3d PM |
9024 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
9025 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
9026 | { .name = "TCMTR", | |
9027 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
9028 | .access = PL1_R, |
9029 | .accessfn = access_aa32_tid1, | |
9030 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d | 9031 | }; |
8085ce63 PC |
9032 | /* TLBTR is specific to VMSA */ |
9033 | ARMCPRegInfo id_tlbtr_reginfo = { | |
9034 | .name = "TLBTR", | |
9035 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
9036 | .access = PL1_R, |
9037 | .accessfn = access_aa32_tid1, | |
9038 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 9039 | }; |
3281af81 PC |
9040 | /* MPUIR is specific to PMSA V6+ */ |
9041 | ARMCPRegInfo id_mpuir_reginfo = { | |
9042 | .name = "MPUIR", | |
9043 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
9044 | .access = PL1_R, .type = ARM_CP_CONST, | |
9045 | .resetvalue = cpu->pmsav7_dregion << 8 | |
9046 | }; | |
761c4642 TR |
9047 | /* HMPUIR is specific to PMSA V8 */ |
9048 | ARMCPRegInfo id_hmpuir_reginfo = { | |
9049 | .name = "HMPUIR", | |
9050 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4, | |
9051 | .access = PL2_R, .type = ARM_CP_CONST, | |
9052 | .resetvalue = cpu->pmsav8r_hdregion | |
9053 | }; | |
10b0220e | 9054 | static const ARMCPRegInfo crn0_wi_reginfo = { |
7884849c PM |
9055 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
9056 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
9057 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
9058 | }; | |
6c5c0fec | 9059 | #ifdef CONFIG_USER_ONLY |
10b0220e | 9060 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { |
6c5c0fec | 9061 | { .name = "MIDR_EL1", |
bc6bd20e ZS |
9062 | .exported_bits = R_MIDR_EL1_REVISION_MASK | |
9063 | R_MIDR_EL1_PARTNUM_MASK | | |
9064 | R_MIDR_EL1_ARCHITECTURE_MASK | | |
9065 | R_MIDR_EL1_VARIANT_MASK | | |
9066 | R_MIDR_EL1_IMPLEMENTER_MASK }, | |
9067 | { .name = "REVIDR_EL1" }, | |
6c5c0fec AB |
9068 | }; |
9069 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
9070 | #endif | |
7884849c PM |
9071 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
9072 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5809ac57 | 9073 | size_t i; |
9b37a28c FR |
9074 | /* |
9075 | * Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
9076 | * whole space. Then update the specific ID registers to allow write |
9077 | * access, so that they ignore writes rather than causing them to | |
9078 | * UNDEF. | |
7884849c PM |
9079 | */ |
9080 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
5809ac57 RH |
9081 | for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { |
9082 | id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | |
00a29f3d | 9083 | } |
5809ac57 RH |
9084 | for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { |
9085 | id_cp_reginfo[i].access = PL1_RW; | |
7884849c | 9086 | } |
10006112 | 9087 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 9088 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 9089 | } |
00a29f3d PM |
9090 | if (arm_feature(env, ARM_FEATURE_V8)) { |
9091 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
c7f786ab TR |
9092 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
9093 | define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); | |
9094 | } | |
00a29f3d PM |
9095 | } else { |
9096 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
9097 | } | |
a703eda1 | 9098 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 9099 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 9100 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
761c4642 TR |
9101 | } else if (arm_feature(env, ARM_FEATURE_PMSA) && |
9102 | arm_feature(env, ARM_FEATURE_V8)) { | |
9103 | uint32_t i = 0; | |
9104 | char *tmp_string; | |
9105 | ||
9106 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
9107 | define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); | |
9108 | define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); | |
9109 | ||
9110 | /* Register alias is only valid for first 32 indexes */ | |
9111 | for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { | |
9112 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9113 | uint8_t opc1 = extract32(i, 4, 1); | |
9114 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9115 | ||
9116 | tmp_string = g_strdup_printf("PRBAR%u", i); | |
9117 | ARMCPRegInfo tmp_prbarn_reginfo = { | |
9118 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9119 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9120 | .access = PL1_RW, .resetvalue = 0, | |
9121 | .accessfn = access_tvm_trvm, | |
9122 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9123 | }; | |
9124 | define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); | |
9125 | g_free(tmp_string); | |
9126 | ||
9127 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9128 | tmp_string = g_strdup_printf("PRLAR%u", i); | |
9129 | ARMCPRegInfo tmp_prlarn_reginfo = { | |
9130 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9131 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9132 | .access = PL1_RW, .resetvalue = 0, | |
9133 | .accessfn = access_tvm_trvm, | |
9134 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9135 | }; | |
9136 | define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); | |
9137 | g_free(tmp_string); | |
9138 | } | |
9139 | ||
9140 | /* Register alias is only valid for first 32 indexes */ | |
9141 | for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { | |
9142 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9143 | uint8_t opc1 = 0b100 | extract32(i, 4, 1); | |
9144 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9145 | ||
9146 | tmp_string = g_strdup_printf("HPRBAR%u", i); | |
9147 | ARMCPRegInfo tmp_hprbarn_reginfo = { | |
9148 | .name = tmp_string, | |
9149 | .type = ARM_CP_NO_RAW, | |
9150 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9151 | .access = PL2_RW, .resetvalue = 0, | |
9152 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9153 | }; | |
9154 | define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); | |
9155 | g_free(tmp_string); | |
9156 | ||
9157 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9158 | tmp_string = g_strdup_printf("HPRLAR%u", i); | |
9159 | ARMCPRegInfo tmp_hprlarn_reginfo = { | |
9160 | .name = tmp_string, | |
9161 | .type = ARM_CP_NO_RAW, | |
9162 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9163 | .access = PL2_RW, .resetvalue = 0, | |
9164 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9165 | }; | |
9166 | define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); | |
9167 | g_free(tmp_string); | |
9168 | } | |
3281af81 PC |
9169 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
9170 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 9171 | } |
7884849c PM |
9172 | } |
9173 | ||
97ce8d61 | 9174 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
9175 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
9176 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
9177 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
67dd8030 | 9178 | .fgt = FGT_MPIDR_EL1, |
52264166 | 9179 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
52264166 AB |
9180 | }; |
9181 | #ifdef CONFIG_USER_ONLY | |
10b0220e | 9182 | static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { |
52264166 AB |
9183 | { .name = "MPIDR_EL1", |
9184 | .fixed_bits = 0x0000000080000000 }, | |
52264166 AB |
9185 | }; |
9186 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
9187 | #endif | |
97ce8d61 PC |
9188 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
9189 | } | |
9190 | ||
2771db27 | 9191 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
9192 | ARMCPRegInfo auxcr_reginfo[] = { |
9193 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
9194 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
9195 | .access = PL1_RW, .accessfn = access_tacr, |
9196 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
9197 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
9198 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
9199 | .access = PL2_RW, .type = ARM_CP_CONST, | |
9200 | .resetvalue = 0 }, | |
9201 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
9202 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
9203 | .access = PL3_RW, .type = ARM_CP_CONST, | |
9204 | .resetvalue = 0 }, | |
2771db27 | 9205 | }; |
834a6c69 | 9206 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
9207 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
9208 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 9209 | } |
2771db27 PM |
9210 | } |
9211 | ||
d8ba780b | 9212 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
9213 | /* |
9214 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
9215 | * There are two flavours: | |
9216 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
9217 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
9218 | * 32-bit register visible to AArch32 at a different encoding | |
9219 | * to the "flavour 1" register and with the bits rearranged to | |
9220 | * be able to squash a 64-bit address into the 32-bit view. | |
9221 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
9222 | * in future if we support AArch32-only configs of some of the | |
9223 | * AArch64 cores we might need to add a specific feature flag | |
9224 | * to indicate cores with "flavour 2" CBAR. | |
9225 | */ | |
f318cec6 PM |
9226 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
9227 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
9228 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
9229 | | extract64(cpu->reset_cbar, 32, 12); | |
9230 | ARMCPRegInfo cbar_reginfo[] = { | |
9231 | { .name = "CBAR", | |
9232 | .type = ARM_CP_CONST, | |
d56974af LM |
9233 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
9234 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
9235 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
9236 | .type = ARM_CP_CONST, | |
9237 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 9238 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
9239 | }; |
9240 | /* We don't implement a r/w 64 bit CBAR currently */ | |
9241 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
9242 | define_arm_cp_regs(cpu, cbar_reginfo); | |
9243 | } else { | |
9244 | ARMCPRegInfo cbar = { | |
9245 | .name = "CBAR", | |
9246 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
04215eb1 | 9247 | .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar, |
f318cec6 PM |
9248 | .fieldoffset = offsetof(CPUARMState, |
9249 | cp15.c15_config_base_address) | |
9250 | }; | |
9251 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
9252 | cbar.access = PL1_R; | |
9253 | cbar.fieldoffset = 0; | |
9254 | cbar.type = ARM_CP_CONST; | |
9255 | } | |
9256 | define_one_arm_cp_reg(cpu, &cbar); | |
9257 | } | |
d8ba780b PC |
9258 | } |
9259 | ||
91db4642 | 9260 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
10b0220e | 9261 | static const ARMCPRegInfo vbar_cp_reginfo[] = { |
91db4642 CLG |
9262 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
9263 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
9264 | .access = PL1_RW, .writefn = vbar_write, | |
bd8db7d9 | 9265 | .fgt = FGT_VBAR_EL1, |
91db4642 CLG |
9266 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), |
9267 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
9268 | .resetvalue = 0 }, | |
91db4642 CLG |
9269 | }; |
9270 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
9271 | } | |
9272 | ||
2771db27 PM |
9273 | /* Generic registers whose values depend on the implementation */ |
9274 | { | |
9275 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 9276 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 9277 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 9278 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 9279 | .fgt = FGT_SCTLR_EL1, |
137feaa9 FA |
9280 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
9281 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
9282 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
9283 | .raw_writefn = raw_write, | |
2771db27 PM |
9284 | }; |
9285 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
9b37a28c FR |
9286 | /* |
9287 | * Normally we would always end the TB on an SCTLR write, but Linux | |
2771db27 PM |
9288 | * arch/arm/mach-pxa/sleep.S expects two instructions following |
9289 | * an MMU enable to execute from cache. Imitate this behaviour. | |
9290 | */ | |
9291 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
9292 | } | |
9293 | define_one_arm_cp_reg(cpu, &sctlr); | |
761c4642 TR |
9294 | |
9295 | if (arm_feature(env, ARM_FEATURE_PMSA) && | |
9296 | arm_feature(env, ARM_FEATURE_V8)) { | |
9297 | ARMCPRegInfo vsctlr = { | |
9298 | .name = "VSCTLR", .state = ARM_CP_STATE_AA32, | |
9299 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
9300 | .access = PL2_RW, .resetvalue = 0x0, | |
9301 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr), | |
9302 | }; | |
9303 | define_one_arm_cp_reg(cpu, &vsctlr); | |
9304 | } | |
2771db27 | 9305 | } |
5be5e8ed | 9306 | |
2d7137c1 | 9307 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
9308 | define_arm_cp_regs(cpu, lor_reginfo); |
9309 | } | |
220f508f RH |
9310 | if (cpu_isar_feature(aa64_pan, cpu)) { |
9311 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
9312 | } | |
04b07d29 RH |
9313 | #ifndef CONFIG_USER_ONLY |
9314 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
9315 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
9316 | } | |
9317 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
9318 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
9319 | } | |
9320 | #endif | |
9eeb7a1c RH |
9321 | if (cpu_isar_feature(aa64_uao, cpu)) { |
9322 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
9323 | } | |
2d7137c1 | 9324 | |
dc8b1853 RC |
9325 | if (cpu_isar_feature(aa64_dit, cpu)) { |
9326 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
9327 | } | |
f2f68a78 RC |
9328 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
9329 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
9330 | } | |
58e93b48 RH |
9331 | if (cpu_isar_feature(any_ras, cpu)) { |
9332 | define_arm_cp_regs(cpu, minimal_ras_reginfo); | |
9333 | } | |
dc8b1853 | 9334 | |
52d18727 RH |
9335 | if (cpu_isar_feature(aa64_vh, cpu) || |
9336 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | |
9337 | define_one_arm_cp_reg(cpu, &contextidr_el2); | |
9338 | } | |
e2a1a461 RH |
9339 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
9340 | define_arm_cp_regs(cpu, vhe_reginfo); | |
9341 | } | |
9342 | ||
cd208a1c | 9343 | if (cpu_isar_feature(aa64_sve, cpu)) { |
60360d82 | 9344 | define_arm_cp_regs(cpu, zcr_reginfo); |
5be5e8ed | 9345 | } |
967aa94f | 9346 | |
5814d587 RH |
9347 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
9348 | define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); | |
9349 | } | |
9350 | ||
967aa94f | 9351 | #ifdef TARGET_AARCH64 |
9e5ec745 RH |
9352 | if (cpu_isar_feature(aa64_sme, cpu)) { |
9353 | define_arm_cp_regs(cpu, sme_reginfo); | |
9354 | } | |
967aa94f RH |
9355 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
9356 | define_arm_cp_regs(cpu, pauth_reginfo); | |
9357 | } | |
de390645 RH |
9358 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
9359 | define_arm_cp_regs(cpu, rndr_reginfo); | |
9360 | } | |
84940ed8 RC |
9361 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
9362 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
9363 | } | |
7113d618 RC |
9364 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
9365 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
9366 | } | |
0d57b499 BM |
9367 | /* Data Cache clean instructions up to PoP */ |
9368 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
9369 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
9370 | ||
9371 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
9372 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
9373 | } | |
9374 | } | |
4b779ceb RH |
9375 | |
9376 | /* | |
9377 | * If full MTE is enabled, add all of the system registers. | |
9378 | * If only "instructions available at EL0" are enabled, | |
9379 | * then define only a RAZ/WI version of PSTATE.TCO. | |
9380 | */ | |
9381 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
851ec6eb RH |
9382 | ARMCPRegInfo gmid_reginfo = { |
9383 | .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
9384 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
9385 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
9386 | .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | |
9387 | }; | |
9388 | define_one_arm_cp_reg(cpu, &gmid_reginfo); | |
4b779ceb | 9389 | define_arm_cp_regs(cpu, mte_reginfo); |
5463df16 | 9390 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
9391 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
9392 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 9393 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 9394 | } |
7cb1e618 RH |
9395 | |
9396 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { | |
9397 | define_arm_cp_regs(cpu, scxtnum_reginfo); | |
9398 | } | |
15126d9c PM |
9399 | |
9400 | if (cpu_isar_feature(aa64_fgt, cpu)) { | |
9401 | define_arm_cp_regs(cpu, fgt_reginfo); | |
9402 | } | |
ef1febe7 RH |
9403 | |
9404 | if (cpu_isar_feature(aa64_rme, cpu)) { | |
9405 | define_arm_cp_regs(cpu, rme_reginfo); | |
9406 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
9407 | define_arm_cp_regs(cpu, rme_mte_reginfo); | |
9408 | } | |
9409 | } | |
967aa94f | 9410 | #endif |
cb570bd3 | 9411 | |
22e57073 | 9412 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
9413 | define_arm_cp_regs(cpu, predinv_reginfo); |
9414 | } | |
e2cce18f | 9415 | |
957e6155 PM |
9416 | if (cpu_isar_feature(any_ccidx, cpu)) { |
9417 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
9418 | } | |
9419 | ||
e2cce18f RH |
9420 | #ifndef CONFIG_USER_ONLY |
9421 | /* | |
9422 | * Register redirections and aliases must be done last, | |
9423 | * after the registers from the other extensions have been defined. | |
9424 | */ | |
9425 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
9426 | define_arm_vh_e2h_redirects_aliases(cpu); | |
9427 | } | |
9428 | #endif | |
2ceb98c0 PM |
9429 | } |
9430 | ||
777dc784 PM |
9431 | /* Sort alphabetically by type name, except for "any". */ |
9432 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 9433 | { |
777dc784 PM |
9434 | ObjectClass *class_a = (ObjectClass *)a; |
9435 | ObjectClass *class_b = (ObjectClass *)b; | |
9436 | const char *name_a, *name_b; | |
5adb4839 | 9437 | |
777dc784 PM |
9438 | name_a = object_class_get_name(class_a); |
9439 | name_b = object_class_get_name(class_b); | |
51492fd1 | 9440 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 9441 | return 1; |
51492fd1 | 9442 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
9443 | return -1; |
9444 | } else { | |
9445 | return strcmp(name_a, name_b); | |
5adb4839 PB |
9446 | } |
9447 | } | |
9448 | ||
777dc784 | 9449 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 9450 | { |
777dc784 | 9451 | ObjectClass *oc = data; |
977c33ba | 9452 | CPUClass *cc = CPU_CLASS(oc); |
51492fd1 AF |
9453 | const char *typename; |
9454 | char *name; | |
3371d272 | 9455 | |
51492fd1 AF |
9456 | typename = object_class_get_name(oc); |
9457 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
977c33ba DB |
9458 | if (cc->deprecation_note) { |
9459 | qemu_printf(" %s (deprecated)\n", name); | |
9460 | } else { | |
9461 | qemu_printf(" %s\n", name); | |
9462 | } | |
51492fd1 | 9463 | g_free(name); |
777dc784 PM |
9464 | } |
9465 | ||
0442428a | 9466 | void arm_cpu_list(void) |
777dc784 | 9467 | { |
777dc784 PM |
9468 | GSList *list; |
9469 | ||
9470 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
9471 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
9472 | qemu_printf("Available CPUs:\n"); |
9473 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 9474 | g_slist_free(list); |
40f137e1 PB |
9475 | } |
9476 | ||
1859f8c3 RH |
9477 | /* |
9478 | * Private utility function for define_one_arm_cp_reg_with_opaque(): | |
9479 | * add a single reginfo struct to the hash table. | |
9480 | */ | |
6e6efd61 | 9481 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
cbe64585 RH |
9482 | void *opaque, CPState state, |
9483 | CPSecureState secstate, | |
9c513e78 AB |
9484 | int crm, int opc1, int opc2, |
9485 | const char *name) | |
6e6efd61 | 9486 | { |
696ba377 | 9487 | CPUARMState *env = &cpu->env; |
5860362d | 9488 | uint32_t key; |
c27f5d3a | 9489 | ARMCPRegInfo *r2; |
4c8c4541 RH |
9490 | bool is64 = r->type & ARM_CP_64BIT; |
9491 | bool ns = secstate & ARM_CP_SECSTATE_NS; | |
cac65299 | 9492 | int cp = r->cp; |
c27f5d3a | 9493 | size_t name_len; |
696ba377 | 9494 | bool make_const; |
c27f5d3a | 9495 | |
cac65299 RH |
9496 | switch (state) { |
9497 | case ARM_CP_STATE_AA32: | |
9498 | /* We assume it is a cp15 register if the .cp field is left unset. */ | |
9499 | if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | |
9500 | cp = 15; | |
9501 | } | |
9502 | key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | |
9503 | break; | |
9504 | case ARM_CP_STATE_AA64: | |
9505 | /* | |
9506 | * To allow abbreviation of ARMCPRegInfo definitions, we treat | |
9507 | * cp == 0 as equivalent to the value for "standard guest-visible | |
9508 | * sysreg". STATE_BOTH definitions are also always "standard sysreg" | |
9509 | * in their AArch64 view (the .cp value may be non-zero for the | |
9510 | * benefit of the AArch32 view). | |
9511 | */ | |
9512 | if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | |
9513 | cp = CP_REG_ARM64_SYSREG_CP; | |
9514 | } | |
9515 | key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | |
9516 | break; | |
9517 | default: | |
9518 | g_assert_not_reached(); | |
9519 | } | |
9520 | ||
dc44545b RH |
9521 | /* Overriding of an existing definition must be explicitly requested. */ |
9522 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
9523 | const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | |
9524 | if (oldreg) { | |
9525 | assert(oldreg->type & ARM_CP_OVERRIDE); | |
9526 | } | |
9527 | } | |
9528 | ||
696ba377 RH |
9529 | /* |
9530 | * Eliminate registers that are not present because the EL is missing. | |
9531 | * Doing this here makes it easier to put all registers for a given | |
9532 | * feature into the same ARMCPRegInfo array and define them all at once. | |
9533 | */ | |
9534 | make_const = false; | |
9535 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9536 | /* | |
9537 | * An EL2 register without EL2 but with EL3 is (usually) RES0. | |
9538 | * See rule RJFFP in section D1.1.3 of DDI0487H.a. | |
9539 | */ | |
9540 | int min_el = ctz32(r->access) / 2; | |
9541 | if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | |
9542 | if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | |
9543 | return; | |
9544 | } | |
9545 | make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | |
9546 | } | |
9547 | } else { | |
9548 | CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | |
9549 | ? PL2_RW : PL1_RW); | |
9550 | if ((r->access & max_el) == 0) { | |
9551 | return; | |
9552 | } | |
9553 | } | |
9554 | ||
c27f5d3a RH |
9555 | /* Combine cpreg and name into one allocation. */ |
9556 | name_len = strlen(name) + 1; | |
9557 | r2 = g_malloc(sizeof(*r2) + name_len); | |
9558 | *r2 = *r; | |
9559 | r2->name = memcpy(r2 + 1, name, name_len); | |
3f3c82a5 | 9560 | |
cc946d96 RH |
9561 | /* |
9562 | * Update fields to match the instantiation, overwiting wildcards | |
9563 | * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | |
3f3c82a5 | 9564 | */ |
cc946d96 RH |
9565 | r2->cp = cp; |
9566 | r2->crm = crm; | |
9567 | r2->opc1 = opc1; | |
9568 | r2->opc2 = opc2; | |
9569 | r2->state = state; | |
3f3c82a5 | 9570 | r2->secure = secstate; |
cc946d96 RH |
9571 | if (opaque) { |
9572 | r2->opaque = opaque; | |
9573 | } | |
3f3c82a5 | 9574 | |
696ba377 RH |
9575 | if (make_const) { |
9576 | /* This should not have been a very special register to begin. */ | |
9577 | int old_special = r2->type & ARM_CP_SPECIAL_MASK; | |
9578 | assert(old_special == 0 || old_special == ARM_CP_NOP); | |
1859f8c3 | 9579 | /* |
696ba377 RH |
9580 | * Set the special function to CONST, retaining the other flags. |
9581 | * This is important for e.g. ARM_CP_SVE so that we still | |
9582 | * take the SVE trap if CPTR_EL3.EZ == 0. | |
f5a0a5a5 | 9583 | */ |
696ba377 RH |
9584 | r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; |
9585 | /* | |
9586 | * Usually, these registers become RES0, but there are a few | |
9587 | * special cases like VPIDR_EL2 which have a constant non-zero | |
9588 | * value with writes ignored. | |
9589 | */ | |
9590 | if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | |
9591 | r2->resetvalue = 0; | |
9592 | } | |
9593 | /* | |
9594 | * ARM_CP_CONST has precedence, so removing the callbacks and | |
9595 | * offsets are not strictly necessary, but it is potentially | |
9596 | * less confusing to debug later. | |
9597 | */ | |
9598 | r2->readfn = NULL; | |
9599 | r2->writefn = NULL; | |
9600 | r2->raw_readfn = NULL; | |
9601 | r2->raw_writefn = NULL; | |
9602 | r2->resetfn = NULL; | |
9603 | r2->fieldoffset = 0; | |
9604 | r2->bank_fieldoffsets[0] = 0; | |
9605 | r2->bank_fieldoffsets[1] = 0; | |
9606 | } else { | |
9607 | bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | |
3f3c82a5 | 9608 | |
10748a96 | 9609 | if (isbanked) { |
1859f8c3 | 9610 | /* |
696ba377 RH |
9611 | * Register is banked (using both entries in array). |
9612 | * Overwriting fieldoffset as the array is only used to define | |
9613 | * banked registers but later only fieldoffset is used. | |
3f3c82a5 | 9614 | */ |
696ba377 RH |
9615 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
9616 | } | |
9617 | if (state == ARM_CP_STATE_AA32) { | |
9618 | if (isbanked) { | |
9619 | /* | |
9620 | * If the register is banked then we don't need to migrate or | |
9621 | * reset the 32-bit instance in certain cases: | |
9622 | * | |
9623 | * 1) If the register has both 32-bit and 64-bit instances | |
9624 | * then we can count on the 64-bit instance taking care | |
9625 | * of the non-secure bank. | |
9626 | * 2) If ARMv8 is enabled then we can count on a 64-bit | |
9627 | * version taking care of the secure bank. This requires | |
9628 | * that separate 32 and 64-bit definitions are provided. | |
9629 | */ | |
9630 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
9631 | (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | |
9632 | r2->type |= ARM_CP_ALIAS; | |
9633 | } | |
9634 | } else if ((secstate != r->secure) && !ns) { | |
9635 | /* | |
9636 | * The register is not banked so we only want to allow | |
9637 | * migration of the non-secure instance. | |
9638 | */ | |
7a0e58fa | 9639 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 | 9640 | } |
3f3c82a5 | 9641 | |
696ba377 RH |
9642 | if (HOST_BIG_ENDIAN && |
9643 | r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | |
9644 | r2->fieldoffset += sizeof(uint32_t); | |
9645 | } | |
3f3c82a5 | 9646 | } |
f5a0a5a5 | 9647 | } |
cc946d96 | 9648 | |
1859f8c3 RH |
9649 | /* |
9650 | * By convention, for wildcarded registers only the first | |
6e6efd61 | 9651 | * entry is used for migration; the others are marked as |
7a0e58fa | 9652 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 9653 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 9654 | * never migratable and not even raw-accessible. |
6e6efd61 | 9655 | */ |
696ba377 | 9656 | if (r2->type & ARM_CP_SPECIAL_MASK) { |
7a0e58fa PM |
9657 | r2->type |= ARM_CP_NO_RAW; |
9658 | } | |
9659 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
9660 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
9661 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 9662 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
9663 | } |
9664 | ||
1859f8c3 RH |
9665 | /* |
9666 | * Check that raw accesses are either forbidden or handled. Note that | |
375421cc PM |
9667 | * we can't assert this earlier because the setup of fieldoffset for |
9668 | * banked registers has to be done first. | |
9669 | */ | |
9670 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
9671 | assert(!raw_accessors_invalid(r2)); | |
9672 | } | |
9673 | ||
5860362d | 9674 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); |
6e6efd61 PM |
9675 | } |
9676 | ||
9677 | ||
4b6a83fb PM |
9678 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
9679 | const ARMCPRegInfo *r, void *opaque) | |
9680 | { | |
9b37a28c FR |
9681 | /* |
9682 | * Define implementations of coprocessor registers. | |
4b6a83fb PM |
9683 | * We store these in a hashtable because typically |
9684 | * there are less than 150 registers in a space which | |
9685 | * is 16*16*16*8*8 = 262144 in size. | |
9686 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
9687 | * If a register is defined twice then the second definition is | |
9688 | * used, so this can be used to define some generic registers and | |
9689 | * then override them with implementation specific variations. | |
9690 | * At least one of the original and the second definition should | |
9691 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
9692 | * against accidental use. | |
f5a0a5a5 PM |
9693 | * |
9694 | * The state field defines whether the register is to be | |
9695 | * visible in the AArch32 or AArch64 execution state. If the | |
9696 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
9697 | * reginfo structure for the AArch32 view, which sees the lower | |
9698 | * 32 bits of the 64 bit register. | |
9699 | * | |
9700 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
9701 | * be wildcarded. AArch64 registers are always considered to be 64 | |
9702 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
9703 | * the register, if any. | |
4b6a83fb | 9704 | */ |
d95101d6 | 9705 | int crm, opc1, opc2; |
4b6a83fb PM |
9706 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
9707 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
9708 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
9709 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
9710 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
9711 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
d95101d6 RH |
9712 | CPState state; |
9713 | ||
4b6a83fb PM |
9714 | /* 64 bit registers have only CRm and Opc1 fields */ |
9715 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
9716 | /* op0 only exists in the AArch64 encodings */ |
9717 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
9718 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
9719 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
9720 | /* |
9721 | * This API is only for Arm's system coprocessors (14 and 15) or | |
9722 | * (M-profile or v7A-and-earlier only) for implementation defined | |
9723 | * coprocessors in the range 0..7. Our decode assumes this, since | |
9724 | * 8..13 can be used for other insns including VFP and Neon. See | |
9725 | * valid_cp() in translate.c. Assert here that we haven't tried | |
9726 | * to use an invalid coprocessor number. | |
9727 | */ | |
9728 | switch (r->state) { | |
9729 | case ARM_CP_STATE_BOTH: | |
9730 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
9731 | if (r->cp == 0) { | |
9732 | break; | |
9733 | } | |
9734 | /* fall through */ | |
9735 | case ARM_CP_STATE_AA32: | |
9736 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
9737 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
9738 | assert(r->cp >= 14 && r->cp <= 15); | |
9739 | } else { | |
9740 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
9741 | } | |
9742 | break; | |
9743 | case ARM_CP_STATE_AA64: | |
9744 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
9745 | break; | |
9746 | default: | |
9747 | g_assert_not_reached(); | |
9748 | } | |
9b37a28c FR |
9749 | /* |
9750 | * The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
f5a0a5a5 PM |
9751 | * encodes a minimum access level for the register. We roll this |
9752 | * runtime check into our general permission check code, so check | |
9753 | * here that the reginfo's specified permissions are strict enough | |
9754 | * to encompass the generic architectural permission check. | |
9755 | */ | |
9756 | if (r->state != ARM_CP_STATE_AA32) { | |
39107337 | 9757 | CPAccessRights mask; |
f5a0a5a5 | 9758 | switch (r->opc1) { |
b5bd7440 AB |
9759 | case 0: |
9760 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
9761 | mask = PL0U_R | PL1_RW; | |
9762 | break; | |
9763 | case 1: case 2: | |
f5a0a5a5 PM |
9764 | /* min_EL EL1 */ |
9765 | mask = PL1_RW; | |
9766 | break; | |
9767 | case 3: | |
9768 | /* min_EL EL0 */ | |
9769 | mask = PL0_RW; | |
9770 | break; | |
9771 | case 4: | |
b4ecf60f | 9772 | case 5: |
f5a0a5a5 PM |
9773 | /* min_EL EL2 */ |
9774 | mask = PL2_RW; | |
9775 | break; | |
f5a0a5a5 PM |
9776 | case 6: |
9777 | /* min_EL EL3 */ | |
9778 | mask = PL3_RW; | |
9779 | break; | |
9780 | case 7: | |
9781 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
9782 | mask = PL1_RW; | |
9783 | break; | |
9784 | default: | |
9785 | /* broken reginfo with out-of-range opc1 */ | |
d385a605 | 9786 | g_assert_not_reached(); |
f5a0a5a5 PM |
9787 | } |
9788 | /* assert our permissions are not too lax (stricter is fine) */ | |
9789 | assert((r->access & ~mask) == 0); | |
9790 | } | |
9791 | ||
9b37a28c FR |
9792 | /* |
9793 | * Check that the register definition has enough info to handle | |
4b6a83fb PM |
9794 | * reads and writes if they are permitted. |
9795 | */ | |
87c3f0f2 | 9796 | if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { |
4b6a83fb | 9797 | if (r->access & PL3_R) { |
3f3c82a5 FA |
9798 | assert((r->fieldoffset || |
9799 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9800 | r->readfn); | |
4b6a83fb PM |
9801 | } |
9802 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
9803 | assert((r->fieldoffset || |
9804 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9805 | r->writefn); | |
4b6a83fb PM |
9806 | } |
9807 | } | |
5809ac57 | 9808 | |
4b6a83fb PM |
9809 | for (crm = crmmin; crm <= crmmax; crm++) { |
9810 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
9811 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
9812 | for (state = ARM_CP_STATE_AA32; |
9813 | state <= ARM_CP_STATE_AA64; state++) { | |
9814 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
9815 | continue; | |
9816 | } | |
3f3c82a5 | 9817 | if (state == ARM_CP_STATE_AA32) { |
9b37a28c FR |
9818 | /* |
9819 | * Under AArch32 CP registers can be common | |
3f3c82a5 FA |
9820 | * (same for secure and non-secure world) or banked. |
9821 | */ | |
9c513e78 AB |
9822 | char *name; |
9823 | ||
3f3c82a5 FA |
9824 | switch (r->secure) { |
9825 | case ARM_CP_SECSTATE_S: | |
9826 | case ARM_CP_SECSTATE_NS: | |
9827 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
9828 | r->secure, crm, opc1, opc2, |
9829 | r->name); | |
3f3c82a5 | 9830 | break; |
cbe64585 | 9831 | case ARM_CP_SECSTATE_BOTH: |
9c513e78 | 9832 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
9833 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9834 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
9835 | crm, opc1, opc2, name); |
9836 | g_free(name); | |
3f3c82a5 FA |
9837 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9838 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9839 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9840 | break; |
cbe64585 RH |
9841 | default: |
9842 | g_assert_not_reached(); | |
3f3c82a5 FA |
9843 | } |
9844 | } else { | |
9b37a28c FR |
9845 | /* |
9846 | * AArch64 registers get mapped to non-secure instance | |
9847 | * of AArch32 | |
9848 | */ | |
3f3c82a5 FA |
9849 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9850 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9851 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9852 | } |
f5a0a5a5 | 9853 | } |
4b6a83fb PM |
9854 | } |
9855 | } | |
9856 | } | |
9857 | } | |
9858 | ||
5809ac57 RH |
9859 | /* Define a whole list of registers */ |
9860 | void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | |
9861 | void *opaque, size_t len) | |
4b6a83fb | 9862 | { |
5809ac57 RH |
9863 | size_t i; |
9864 | for (i = 0; i < len; ++i) { | |
9865 | define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | |
4b6a83fb PM |
9866 | } |
9867 | } | |
9868 | ||
6c5c0fec AB |
9869 | /* |
9870 | * Modify ARMCPRegInfo for access from userspace. | |
9871 | * | |
9872 | * This is a data driven modification directed by | |
9873 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
9874 | * user-space cannot alter any values and dynamic values pertaining to | |
9875 | * execution state are hidden from user space view anyway. | |
9876 | */ | |
5809ac57 RH |
9877 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
9878 | const ARMCPRegUserSpaceInfo *mods, | |
9879 | size_t mods_len) | |
6c5c0fec | 9880 | { |
5809ac57 RH |
9881 | for (size_t mi = 0; mi < mods_len; ++mi) { |
9882 | const ARMCPRegUserSpaceInfo *m = mods + mi; | |
d040242e | 9883 | GPatternSpec *pat = NULL; |
5809ac57 | 9884 | |
d040242e AB |
9885 | if (m->is_glob) { |
9886 | pat = g_pattern_spec_new(m->name); | |
9887 | } | |
5809ac57 RH |
9888 | for (size_t ri = 0; ri < regs_len; ++ri) { |
9889 | ARMCPRegInfo *r = regs + ri; | |
9890 | ||
d040242e AB |
9891 | if (pat && g_pattern_match_string(pat, r->name)) { |
9892 | r->type = ARM_CP_CONST; | |
9893 | r->access = PL0U_R; | |
9894 | r->resetvalue = 0; | |
9895 | /* continue */ | |
9896 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
9897 | r->type = ARM_CP_CONST; |
9898 | r->access = PL0U_R; | |
9899 | r->resetvalue &= m->exported_bits; | |
9900 | r->resetvalue |= m->fixed_bits; | |
9901 | break; | |
9902 | } | |
9903 | } | |
d040242e AB |
9904 | if (pat) { |
9905 | g_pattern_spec_free(pat); | |
9906 | } | |
6c5c0fec AB |
9907 | } |
9908 | } | |
9909 | ||
60322b39 | 9910 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 9911 | { |
5860362d | 9912 | return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); |
4b6a83fb PM |
9913 | } |
9914 | ||
c4241c7d PM |
9915 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
9916 | uint64_t value) | |
4b6a83fb PM |
9917 | { |
9918 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
9919 | } |
9920 | ||
c4241c7d | 9921 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
9922 | { |
9923 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
9924 | return 0; |
9925 | } | |
9926 | ||
f5a0a5a5 PM |
9927 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
9928 | { | |
9929 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
9930 | } | |
9931 | ||
af393ffc | 9932 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b | 9933 | { |
9b37a28c FR |
9934 | /* |
9935 | * Return true if it is not valid for us to switch to | |
37064a8b PM |
9936 | * this CPU mode (ie all the UNPREDICTABLE cases in |
9937 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
9938 | */ | |
af393ffc PM |
9939 | |
9940 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
9941 | if (write_type == CPSRWriteByInstr && | |
9942 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
9943 | mode == ARM_CPU_MODE_HYP)) { | |
9944 | return 1; | |
9945 | } | |
9946 | ||
37064a8b PM |
9947 | switch (mode) { |
9948 | case ARM_CPU_MODE_USR: | |
10eacda7 | 9949 | return 0; |
37064a8b PM |
9950 | case ARM_CPU_MODE_SYS: |
9951 | case ARM_CPU_MODE_SVC: | |
9952 | case ARM_CPU_MODE_ABT: | |
9953 | case ARM_CPU_MODE_UND: | |
9954 | case ARM_CPU_MODE_IRQ: | |
9955 | case ARM_CPU_MODE_FIQ: | |
9b37a28c FR |
9956 | /* |
9957 | * Note that we don't implement the IMPDEF NSACR.RFR which in v7 | |
52ff951b PM |
9958 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) |
9959 | */ | |
9b37a28c FR |
9960 | /* |
9961 | * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR | |
10eacda7 PM |
9962 | * and CPS are treated as illegal mode changes. |
9963 | */ | |
9964 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 9965 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 9966 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
9967 | return 1; |
9968 | } | |
37064a8b | 9969 | return 0; |
e6c8fc07 | 9970 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 9971 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 9972 | case ARM_CPU_MODE_MON: |
58ae2d1f | 9973 | return arm_current_el(env) < 3; |
37064a8b PM |
9974 | default: |
9975 | return 1; | |
9976 | } | |
9977 | } | |
9978 | ||
2f4a40e5 AZ |
9979 | uint32_t cpsr_read(CPUARMState *env) |
9980 | { | |
9981 | int ZF; | |
6fbe23d5 PB |
9982 | ZF = (env->ZF == 0); |
9983 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
9984 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
9985 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
9986 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 9987 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
9988 | } |
9989 | ||
50866ba5 PM |
9990 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
9991 | CPSRWriteType write_type) | |
2f4a40e5 | 9992 | { |
6e8801f9 | 9993 | uint32_t changed_daif; |
e784807c PM |
9994 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
9995 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 9996 | |
2f4a40e5 | 9997 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
9998 | env->ZF = (~val) & CPSR_Z; |
9999 | env->NF = val; | |
2f4a40e5 AZ |
10000 | env->CF = (val >> 29) & 1; |
10001 | env->VF = (val << 3) & 0x80000000; | |
10002 | } | |
f927dbda | 10003 | if (mask & CPSR_Q) { |
2f4a40e5 | 10004 | env->QF = ((val & CPSR_Q) != 0); |
f927dbda FR |
10005 | } |
10006 | if (mask & CPSR_T) { | |
2f4a40e5 | 10007 | env->thumb = ((val & CPSR_T) != 0); |
f927dbda | 10008 | } |
2f4a40e5 AZ |
10009 | if (mask & CPSR_IT_0_1) { |
10010 | env->condexec_bits &= ~3; | |
10011 | env->condexec_bits |= (val >> 25) & 3; | |
10012 | } | |
10013 | if (mask & CPSR_IT_2_7) { | |
10014 | env->condexec_bits &= 3; | |
10015 | env->condexec_bits |= (val >> 8) & 0xfc; | |
10016 | } | |
10017 | if (mask & CPSR_GE) { | |
10018 | env->GE = (val >> 16) & 0xf; | |
10019 | } | |
10020 | ||
9b37a28c FR |
10021 | /* |
10022 | * In a V7 implementation that includes the security extensions but does | |
6e8801f9 FA |
10023 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control |
10024 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
10025 | * bits respectively. | |
10026 | * | |
10027 | * In a V8 implementation, it is permitted for privileged software to | |
10028 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
10029 | */ | |
f8c88bbc | 10030 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
10031 | arm_feature(env, ARM_FEATURE_EL3) && |
10032 | !arm_feature(env, ARM_FEATURE_EL2) && | |
10033 | !arm_is_secure(env)) { | |
10034 | ||
10035 | changed_daif = (env->daif ^ val) & mask; | |
10036 | ||
10037 | if (changed_daif & CPSR_A) { | |
9b37a28c FR |
10038 | /* |
10039 | * Check to see if we are allowed to change the masking of async | |
6e8801f9 FA |
10040 | * abort exceptions from a non-secure state. |
10041 | */ | |
10042 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
10043 | qemu_log_mask(LOG_GUEST_ERROR, | |
10044 | "Ignoring attempt to switch CPSR_A flag from " | |
10045 | "non-secure world with SCR.AW bit clear\n"); | |
10046 | mask &= ~CPSR_A; | |
10047 | } | |
10048 | } | |
10049 | ||
10050 | if (changed_daif & CPSR_F) { | |
9b37a28c FR |
10051 | /* |
10052 | * Check to see if we are allowed to change the masking of FIQ | |
6e8801f9 FA |
10053 | * exceptions from a non-secure state. |
10054 | */ | |
10055 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
10056 | qemu_log_mask(LOG_GUEST_ERROR, | |
10057 | "Ignoring attempt to switch CPSR_F flag from " | |
10058 | "non-secure world with SCR.FW bit clear\n"); | |
10059 | mask &= ~CPSR_F; | |
10060 | } | |
10061 | ||
9b37a28c FR |
10062 | /* |
10063 | * Check whether non-maskable FIQ (NMFI) support is enabled. | |
6e8801f9 FA |
10064 | * If this bit is set software is not allowed to mask |
10065 | * FIQs, but is allowed to set CPSR_F to 0. | |
10066 | */ | |
10067 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
10068 | (val & CPSR_F)) { | |
10069 | qemu_log_mask(LOG_GUEST_ERROR, | |
10070 | "Ignoring attempt to enable CPSR_F flag " | |
10071 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
10072 | mask &= ~CPSR_F; | |
10073 | } | |
10074 | } | |
10075 | } | |
10076 | ||
4cc35614 PM |
10077 | env->daif &= ~(CPSR_AIF & mask); |
10078 | env->daif |= val & CPSR_AIF & mask; | |
10079 | ||
f8c88bbc PM |
10080 | if (write_type != CPSRWriteRaw && |
10081 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 | 10082 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9b37a28c FR |
10083 | /* |
10084 | * Note that we can only get here in USR mode if this is a | |
8c4f0eb9 PM |
10085 | * gdb stub write; for this case we follow the architectural |
10086 | * behaviour for guest writes in USR mode of ignoring an attempt | |
10087 | * to switch mode. (Those are caught by translate.c for writes | |
10088 | * triggered by guest instructions.) | |
10089 | */ | |
10090 | mask &= ~CPSR_M; | |
10091 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
9b37a28c FR |
10092 | /* |
10093 | * Attempt to switch to an invalid mode: this is UNPREDICTABLE in | |
81907a58 PM |
10094 | * v7, and has defined behaviour in v8: |
10095 | * + leave CPSR.M untouched | |
10096 | * + allow changes to the other CPSR fields | |
10097 | * + set PSTATE.IL | |
10098 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
10099 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
10100 | */ |
10101 | mask &= ~CPSR_M; | |
81907a58 PM |
10102 | if (write_type != CPSRWriteByGDBStub && |
10103 | arm_feature(env, ARM_FEATURE_V8)) { | |
10104 | mask |= CPSR_IL; | |
10105 | val |= CPSR_IL; | |
10106 | } | |
81e37284 PM |
10107 | qemu_log_mask(LOG_GUEST_ERROR, |
10108 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
10109 | aarch32_mode_name(env->uncached_cpsr), | |
10110 | aarch32_mode_name(val)); | |
37064a8b | 10111 | } else { |
81e37284 PM |
10112 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
10113 | write_type == CPSRWriteExceptionReturn ? | |
10114 | "Exception return from AArch32" : | |
10115 | "AArch32 mode switch from", | |
10116 | aarch32_mode_name(env->uncached_cpsr), | |
10117 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
10118 | switch_mode(env, val & CPSR_M); |
10119 | } | |
2f4a40e5 AZ |
10120 | } |
10121 | mask &= ~CACHED_CPSR_BITS; | |
10122 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
2b77ad4d | 10123 | if (tcg_enabled() && rebuild_hflags) { |
e784807c PM |
10124 | arm_rebuild_hflags(env); |
10125 | } | |
2f4a40e5 AZ |
10126 | } |
10127 | ||
b26eefb6 PB |
10128 | /* Sign/zero extend */ |
10129 | uint32_t HELPER(sxtb16)(uint32_t x) | |
10130 | { | |
10131 | uint32_t res; | |
10132 | res = (uint16_t)(int8_t)x; | |
10133 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
10134 | return res; | |
10135 | } | |
10136 | ||
e5346292 PM |
10137 | static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) |
10138 | { | |
10139 | /* | |
10140 | * Take a division-by-zero exception if necessary; otherwise return | |
10141 | * to get the usual non-trapping division behaviour (result of 0) | |
10142 | */ | |
10143 | if (arm_feature(env, ARM_FEATURE_M) | |
10144 | && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { | |
10145 | raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); | |
10146 | } | |
10147 | } | |
10148 | ||
b26eefb6 PB |
10149 | uint32_t HELPER(uxtb16)(uint32_t x) |
10150 | { | |
10151 | uint32_t res; | |
10152 | res = (uint16_t)(uint8_t)x; | |
10153 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
10154 | return res; | |
10155 | } | |
10156 | ||
e5346292 | 10157 | int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) |
3670669c | 10158 | { |
fc7a5038 | 10159 | if (den == 0) { |
e5346292 | 10160 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
10161 | return 0; |
10162 | } | |
10163 | if (num == INT_MIN && den == -1) { | |
10164 | return INT_MIN; | |
10165 | } | |
3670669c PB |
10166 | return num / den; |
10167 | } | |
10168 | ||
e5346292 | 10169 | uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) |
3670669c | 10170 | { |
fc7a5038 | 10171 | if (den == 0) { |
e5346292 | 10172 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
10173 | return 0; |
10174 | } | |
3670669c PB |
10175 | return num / den; |
10176 | } | |
10177 | ||
10178 | uint32_t HELPER(rbit)(uint32_t x) | |
10179 | { | |
42fedbca | 10180 | return revbit32(x); |
3670669c PB |
10181 | } |
10182 | ||
c47eaf9f | 10183 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 10184 | |
affdb64d | 10185 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 10186 | { |
2fc0cc0e | 10187 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
10188 | |
10189 | if (mode != ARM_CPU_MODE_USR) { | |
10190 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
10191 | } | |
b5ff1b31 FB |
10192 | } |
10193 | ||
012a906b GB |
10194 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10195 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
10196 | { |
10197 | return 1; | |
10198 | } | |
10199 | ||
ce02049d GB |
10200 | void aarch64_sync_64_to_32(CPUARMState *env) |
10201 | { | |
10202 | g_assert_not_reached(); | |
10203 | } | |
10204 | ||
b5ff1b31 FB |
10205 | #else |
10206 | ||
affdb64d | 10207 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
10208 | { |
10209 | int old_mode; | |
10210 | int i; | |
10211 | ||
10212 | old_mode = env->uncached_cpsr & CPSR_M; | |
f927dbda | 10213 | if (mode == old_mode) { |
b5ff1b31 | 10214 | return; |
f927dbda | 10215 | } |
b5ff1b31 FB |
10216 | |
10217 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
04215eb1 FR |
10218 | memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10219 | memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 | 10220 | } else if (mode == ARM_CPU_MODE_FIQ) { |
04215eb1 FR |
10221 | memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10222 | memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 FB |
10223 | } |
10224 | ||
f5206413 | 10225 | i = bank_number(old_mode); |
b5ff1b31 | 10226 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
10227 | env->banked_spsr[i] = env->spsr; |
10228 | ||
f5206413 | 10229 | i = bank_number(mode); |
b5ff1b31 | 10230 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 10231 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
10232 | |
10233 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
10234 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
10235 | } |
10236 | ||
9b37a28c FR |
10237 | /* |
10238 | * Physical Interrupt Target EL Lookup Table | |
0eeb17d6 GB |
10239 | * |
10240 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
10241 | * | |
10242 | * The below multi-dimensional table is used for looking up the target | |
10243 | * exception level given numerous condition criteria. Specifically, the | |
10244 | * target EL is based on SCR and HCR routing controls as well as the | |
10245 | * currently executing EL and secure state. | |
10246 | * | |
10247 | * Dimensions: | |
10248 | * target_el_table[2][2][2][2][2][4] | |
10249 | * | | | | | +--- Current EL | |
10250 | * | | | | +------ Non-secure(0)/Secure(1) | |
10251 | * | | | +--------- HCR mask override | |
10252 | * | | +------------ SCR exec state control | |
10253 | * | +--------------- SCR mask override | |
10254 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
10255 | * | |
10256 | * The table values are as such: | |
10257 | * 0-3 = EL0-EL3 | |
10258 | * -1 = Cannot occur | |
10259 | * | |
10260 | * The ARM ARM target EL table includes entries indicating that an "exception | |
10261 | * is not taken". The two cases where this is applicable are: | |
10262 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
10263 | * routed to EL3. | |
10264 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
10265 | * routed to EL2. | |
10266 | * In these two cases, the below table contain a target of EL1. This value is | |
10267 | * returned as it is expected that the consumer of the table data will check | |
10268 | * for "target EL >= current EL" to ensure the exception is not taken. | |
10269 | * | |
10270 | * SCR HCR | |
10271 | * 64 EA AMO From | |
10272 | * BIT IRQ IMO Non-secure Secure | |
10273 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
10274 | */ | |
82c39f6a | 10275 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
10276 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
10277 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
10278 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
10279 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
10280 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10281 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
10282 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10283 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
10284 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
10285 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
10286 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
10287 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
10288 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
10289 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
10290 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
10291 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
10292 | }; |
10293 | ||
10294 | /* | |
10295 | * Determine the target EL for physical exceptions | |
10296 | */ | |
012a906b GB |
10297 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10298 | uint32_t cur_el, bool secure) | |
0eeb17d6 | 10299 | { |
b77af26e | 10300 | CPUARMState *env = cpu_env(cs); |
f7778444 RH |
10301 | bool rw; |
10302 | bool scr; | |
10303 | bool hcr; | |
0eeb17d6 | 10304 | int target_el; |
2cde031f | 10305 | /* Is the highest EL AArch64? */ |
f7778444 RH |
10306 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
10307 | uint64_t hcr_el2; | |
2cde031f SS |
10308 | |
10309 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
10310 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
10311 | } else { | |
9b37a28c FR |
10312 | /* |
10313 | * Either EL2 is the highest EL (and so the EL2 register width | |
2cde031f SS |
10314 | * is given by is64); or there is no EL2 or EL3, in which case |
10315 | * the value of 'rw' does not affect the table lookup anyway. | |
10316 | */ | |
10317 | rw = is64; | |
10318 | } | |
0eeb17d6 | 10319 | |
f7778444 | 10320 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
10321 | switch (excp_idx) { |
10322 | case EXCP_IRQ: | |
10323 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 10324 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
10325 | break; |
10326 | case EXCP_FIQ: | |
10327 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 10328 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
10329 | break; |
10330 | default: | |
10331 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 10332 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
10333 | break; |
10334 | }; | |
10335 | ||
d1b31428 RH |
10336 | /* |
10337 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
10338 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
10339 | */ | |
10340 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
10341 | ||
0eeb17d6 GB |
10342 | /* Perform a table-lookup for the target EL given the current state */ |
10343 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
10344 | ||
10345 | assert(target_el > 0); | |
10346 | ||
10347 | return target_el; | |
10348 | } | |
10349 | ||
fc6177af | 10350 | void arm_log_exception(CPUState *cs) |
b59f479b | 10351 | { |
fc6177af PM |
10352 | int idx = cs->exception_index; |
10353 | ||
b59f479b PMD |
10354 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
10355 | const char *exc = NULL; | |
10356 | static const char * const excnames[] = { | |
10357 | [EXCP_UDEF] = "Undefined Instruction", | |
10358 | [EXCP_SWI] = "SVC", | |
10359 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
10360 | [EXCP_DATA_ABORT] = "Data Abort", | |
10361 | [EXCP_IRQ] = "IRQ", | |
10362 | [EXCP_FIQ] = "FIQ", | |
10363 | [EXCP_BKPT] = "Breakpoint", | |
10364 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
10365 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
10366 | [EXCP_HVC] = "Hypervisor Call", | |
10367 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
10368 | [EXCP_SMC] = "Secure Monitor Call", | |
10369 | [EXCP_VIRQ] = "Virtual IRQ", | |
10370 | [EXCP_VFIQ] = "Virtual FIQ", | |
10371 | [EXCP_SEMIHOST] = "Semihosting call", | |
10372 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
10373 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
10374 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
10375 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
10376 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
10377 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 10378 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
3c29632f | 10379 | [EXCP_VSERR] = "Virtual SERR", |
11b76fda | 10380 | [EXCP_GPC] = "Granule Protection Check", |
b59f479b PMD |
10381 | }; |
10382 | ||
10383 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
10384 | exc = excnames[idx]; | |
10385 | } | |
10386 | if (!exc) { | |
10387 | exc = "unknown"; | |
10388 | } | |
fc6177af PM |
10389 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
10390 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
10391 | } |
10392 | } | |
10393 | ||
a356dacf | 10394 | /* |
7aab5a8c PMD |
10395 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
10396 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10397 | * execution state. | |
a356dacf | 10398 | */ |
7aab5a8c | 10399 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 10400 | { |
7aab5a8c PMD |
10401 | int i; |
10402 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
10403 | ||
10404 | /* We can blanket copy R[0:7] to X[0:7] */ | |
10405 | for (i = 0; i < 8; i++) { | |
10406 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 10407 | } |
70d74660 | 10408 | |
9a223097 | 10409 | /* |
7aab5a8c PMD |
10410 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
10411 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 10412 | */ |
7aab5a8c PMD |
10413 | if (mode == ARM_CPU_MODE_FIQ) { |
10414 | for (i = 8; i < 13; i++) { | |
10415 | env->xregs[i] = env->usr_regs[i - 8]; | |
10416 | } | |
10417 | } else { | |
10418 | for (i = 8; i < 13; i++) { | |
10419 | env->xregs[i] = env->regs[i]; | |
10420 | } | |
fd592d89 | 10421 | } |
9ee6e8bb | 10422 | |
7aab5a8c PMD |
10423 | /* |
10424 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
10425 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
10426 | * from the mode banked register. | |
10427 | */ | |
10428 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
10429 | env->xregs[13] = env->regs[13]; | |
10430 | env->xregs[14] = env->regs[14]; | |
10431 | } else { | |
10432 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
10433 | /* HYP is an exception in that it is copied from r14 */ | |
10434 | if (mode == ARM_CPU_MODE_HYP) { | |
10435 | env->xregs[14] = env->regs[14]; | |
95695eff | 10436 | } else { |
7aab5a8c | 10437 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 10438 | } |
95695eff PM |
10439 | } |
10440 | ||
7aab5a8c PMD |
10441 | if (mode == ARM_CPU_MODE_HYP) { |
10442 | env->xregs[15] = env->regs[13]; | |
10443 | } else { | |
10444 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
10445 | } |
10446 | ||
7aab5a8c PMD |
10447 | if (mode == ARM_CPU_MODE_IRQ) { |
10448 | env->xregs[16] = env->regs[14]; | |
10449 | env->xregs[17] = env->regs[13]; | |
10450 | } else { | |
10451 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
10452 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
10453 | } | |
95695eff | 10454 | |
7aab5a8c PMD |
10455 | if (mode == ARM_CPU_MODE_SVC) { |
10456 | env->xregs[18] = env->regs[14]; | |
10457 | env->xregs[19] = env->regs[13]; | |
10458 | } else { | |
10459 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
10460 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
10461 | } | |
95695eff | 10462 | |
7aab5a8c PMD |
10463 | if (mode == ARM_CPU_MODE_ABT) { |
10464 | env->xregs[20] = env->regs[14]; | |
10465 | env->xregs[21] = env->regs[13]; | |
10466 | } else { | |
10467 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
10468 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
10469 | } | |
e33cf0f8 | 10470 | |
7aab5a8c PMD |
10471 | if (mode == ARM_CPU_MODE_UND) { |
10472 | env->xregs[22] = env->regs[14]; | |
10473 | env->xregs[23] = env->regs[13]; | |
10474 | } else { | |
10475 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
10476 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
10477 | } |
10478 | ||
10479 | /* | |
7aab5a8c PMD |
10480 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
10481 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
10482 | * FIQ bank for r8-r14. | |
e33cf0f8 | 10483 | */ |
7aab5a8c PMD |
10484 | if (mode == ARM_CPU_MODE_FIQ) { |
10485 | for (i = 24; i < 31; i++) { | |
10486 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
10487 | } | |
10488 | } else { | |
10489 | for (i = 24; i < 29; i++) { | |
10490 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 10491 | } |
7aab5a8c PMD |
10492 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
10493 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 10494 | } |
7aab5a8c PMD |
10495 | |
10496 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
10497 | } |
10498 | ||
9a223097 | 10499 | /* |
7aab5a8c PMD |
10500 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
10501 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10502 | * execution state. | |
de2db7ec | 10503 | */ |
7aab5a8c | 10504 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 10505 | { |
7aab5a8c PMD |
10506 | int i; |
10507 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 10508 | |
7aab5a8c PMD |
10509 | /* We can blanket copy X[0:7] to R[0:7] */ |
10510 | for (i = 0; i < 8; i++) { | |
10511 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 10512 | } |
3f0cddee | 10513 | |
9a223097 | 10514 | /* |
7aab5a8c PMD |
10515 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
10516 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 10517 | */ |
7aab5a8c PMD |
10518 | if (mode == ARM_CPU_MODE_FIQ) { |
10519 | for (i = 8; i < 13; i++) { | |
10520 | env->usr_regs[i - 8] = env->xregs[i]; | |
10521 | } | |
10522 | } else { | |
10523 | for (i = 8; i < 13; i++) { | |
10524 | env->regs[i] = env->xregs[i]; | |
10525 | } | |
fb602cb7 PM |
10526 | } |
10527 | ||
9a223097 | 10528 | /* |
7aab5a8c PMD |
10529 | * Registers r13 & r14 depend on the current mode. |
10530 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
10531 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
10532 | * for the mode. | |
fb602cb7 | 10533 | */ |
7aab5a8c PMD |
10534 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
10535 | env->regs[13] = env->xregs[13]; | |
10536 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 10537 | } else { |
7aab5a8c | 10538 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 10539 | |
7aab5a8c PMD |
10540 | /* |
10541 | * HYP is an exception in that it does not have its own banked r14 but | |
10542 | * shares the USR r14 | |
10543 | */ | |
10544 | if (mode == ARM_CPU_MODE_HYP) { | |
10545 | env->regs[14] = env->xregs[14]; | |
10546 | } else { | |
10547 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
10548 | } | |
10549 | } | |
fb602cb7 | 10550 | |
7aab5a8c PMD |
10551 | if (mode == ARM_CPU_MODE_HYP) { |
10552 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 10553 | } else { |
7aab5a8c | 10554 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 10555 | } |
d02a8698 | 10556 | |
7aab5a8c PMD |
10557 | if (mode == ARM_CPU_MODE_IRQ) { |
10558 | env->regs[14] = env->xregs[16]; | |
10559 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 10560 | } else { |
7aab5a8c PMD |
10561 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
10562 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
10563 | } |
10564 | ||
7aab5a8c PMD |
10565 | if (mode == ARM_CPU_MODE_SVC) { |
10566 | env->regs[14] = env->xregs[18]; | |
10567 | env->regs[13] = env->xregs[19]; | |
10568 | } else { | |
10569 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
10570 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
10571 | } |
10572 | ||
7aab5a8c PMD |
10573 | if (mode == ARM_CPU_MODE_ABT) { |
10574 | env->regs[14] = env->xregs[20]; | |
10575 | env->regs[13] = env->xregs[21]; | |
10576 | } else { | |
10577 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
10578 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
10579 | } |
10580 | ||
10581 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
10582 | env->regs[14] = env->xregs[22]; |
10583 | env->regs[13] = env->xregs[23]; | |
ce02049d | 10584 | } else { |
593cfa2b | 10585 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 10586 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
10587 | } |
10588 | ||
9b37a28c FR |
10589 | /* |
10590 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
ce02049d GB |
10591 | * mode, then we can copy to r8-r14. Otherwise, we copy to the |
10592 | * FIQ bank for r8-r14. | |
10593 | */ | |
10594 | if (mode == ARM_CPU_MODE_FIQ) { | |
10595 | for (i = 24; i < 31; i++) { | |
10596 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
10597 | } | |
10598 | } else { | |
10599 | for (i = 24; i < 29; i++) { | |
10600 | env->fiq_regs[i - 24] = env->xregs[i]; | |
10601 | } | |
10602 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 10603 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
10604 | } |
10605 | ||
10606 | env->regs[15] = env->pc; | |
10607 | } | |
10608 | ||
dea8378b PM |
10609 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
10610 | uint32_t mask, uint32_t offset, | |
10611 | uint32_t newpc) | |
10612 | { | |
4a2696c0 RH |
10613 | int new_el; |
10614 | ||
dea8378b PM |
10615 | /* Change the CPU state so as to actually take the exception. */ |
10616 | switch_mode(env, new_mode); | |
4a2696c0 | 10617 | |
dea8378b PM |
10618 | /* |
10619 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
10620 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
10621 | */ | |
f944a854 | 10622 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
10623 | env->spsr = cpsr_read(env); |
10624 | /* Clear IT bits. */ | |
10625 | env->condexec_bits = 0; | |
10626 | /* Switch to the new mode, and to the correct instruction set. */ | |
10627 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
10628 | |
10629 | /* This must be after mode switching. */ | |
10630 | new_el = arm_current_el(env); | |
10631 | ||
dea8378b PM |
10632 | /* Set new mode endianness */ |
10633 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 10634 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
10635 | env->uncached_cpsr |= CPSR_E; |
10636 | } | |
829f9fd3 PM |
10637 | /* J and IL must always be cleared for exception entry */ |
10638 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
10639 | env->daif |= mask; |
10640 | ||
f2f68a78 RC |
10641 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
10642 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
10643 | env->uncached_cpsr |= CPSR_SSBS; | |
10644 | } else { | |
10645 | env->uncached_cpsr &= ~CPSR_SSBS; | |
10646 | } | |
10647 | } | |
10648 | ||
dea8378b PM |
10649 | if (new_mode == ARM_CPU_MODE_HYP) { |
10650 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
10651 | env->elr_el[2] = env->regs[15]; | |
10652 | } else { | |
4a2696c0 | 10653 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 10654 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
10655 | switch (new_el) { |
10656 | case 3: | |
10657 | if (!arm_is_secure_below_el3(env)) { | |
10658 | /* ... the target is EL3, from non-secure state. */ | |
10659 | env->uncached_cpsr &= ~CPSR_PAN; | |
10660 | break; | |
10661 | } | |
10662 | /* ... the target is EL3, from secure state ... */ | |
10663 | /* fall through */ | |
10664 | case 1: | |
10665 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
10666 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
10667 | env->uncached_cpsr |= CPSR_PAN; | |
10668 | } | |
10669 | break; | |
10670 | } | |
10671 | } | |
dea8378b PM |
10672 | /* |
10673 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
10674 | * and we should just guard the thumb mode on V4 | |
10675 | */ | |
10676 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
10677 | env->thumb = | |
10678 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
10679 | } | |
10680 | env->regs[14] = env->regs[15] + offset; | |
10681 | } | |
10682 | env->regs[15] = newpc; | |
2b77ad4d FR |
10683 | |
10684 | if (tcg_enabled()) { | |
10685 | arm_rebuild_hflags(env); | |
10686 | } | |
dea8378b PM |
10687 | } |
10688 | ||
b9bc21ff PM |
10689 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
10690 | { | |
10691 | /* | |
10692 | * Handle exception entry to Hyp mode; this is sufficiently | |
10693 | * different to entry to other AArch32 modes that we handle it | |
10694 | * separately here. | |
10695 | * | |
10696 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 10697 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
10698 | * The offset applied to the preferred return address is always zero |
10699 | * (see DDI0487C.a section G1.12.3). | |
10700 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
10701 | */ | |
10702 | uint32_t addr, mask; | |
10703 | ARMCPU *cpu = ARM_CPU(cs); | |
10704 | CPUARMState *env = &cpu->env; | |
10705 | ||
10706 | switch (cs->exception_index) { | |
10707 | case EXCP_UDEF: | |
10708 | addr = 0x04; | |
10709 | break; | |
10710 | case EXCP_SWI: | |
2c023d36 | 10711 | addr = 0x08; |
b9bc21ff PM |
10712 | break; |
10713 | case EXCP_BKPT: | |
10714 | /* Fall through to prefetch abort. */ | |
10715 | case EXCP_PREFETCH_ABORT: | |
10716 | env->cp15.ifar_s = env->exception.vaddress; | |
10717 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
10718 | (uint32_t)env->exception.vaddress); | |
10719 | addr = 0x0c; | |
10720 | break; | |
10721 | case EXCP_DATA_ABORT: | |
10722 | env->cp15.dfar_s = env->exception.vaddress; | |
10723 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
10724 | (uint32_t)env->exception.vaddress); | |
10725 | addr = 0x10; | |
10726 | break; | |
10727 | case EXCP_IRQ: | |
10728 | addr = 0x18; | |
10729 | break; | |
10730 | case EXCP_FIQ: | |
10731 | addr = 0x1c; | |
10732 | break; | |
10733 | case EXCP_HVC: | |
10734 | addr = 0x08; | |
10735 | break; | |
10736 | case EXCP_HYP_TRAP: | |
10737 | addr = 0x14; | |
9bbb4ef9 | 10738 | break; |
b9bc21ff PM |
10739 | default: |
10740 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10741 | } | |
10742 | ||
10743 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
10744 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
10745 | /* | |
10746 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
10747 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
10748 | * If this is a v7 CPU, squash the IL bit in those cases. | |
10749 | */ | |
10750 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
10751 | (cs->exception_index == EXCP_DATA_ABORT && | |
10752 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
10753 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
10754 | env->exception.syndrome &= ~ARM_EL_IL; | |
10755 | } | |
10756 | } | |
b9bc21ff PM |
10757 | env->cp15.esr_el[2] = env->exception.syndrome; |
10758 | } | |
10759 | ||
10760 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
10761 | addr = 0x14; | |
10762 | } | |
10763 | ||
10764 | mask = 0; | |
10765 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
10766 | mask |= CPSR_A; | |
10767 | } | |
10768 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
10769 | mask |= CPSR_I; | |
10770 | } | |
10771 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
10772 | mask |= CPSR_F; | |
10773 | } | |
10774 | ||
10775 | addr += env->cp15.hvbar; | |
10776 | ||
10777 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
10778 | } | |
10779 | ||
966f758c | 10780 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 10781 | { |
97a8ea5a AF |
10782 | ARMCPU *cpu = ARM_CPU(cs); |
10783 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
10784 | uint32_t addr; |
10785 | uint32_t mask; | |
10786 | int new_mode; | |
10787 | uint32_t offset; | |
16a906fd | 10788 | uint32_t moe; |
b5ff1b31 | 10789 | |
16a906fd | 10790 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 10791 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
10792 | case EC_BREAKPOINT: |
10793 | case EC_BREAKPOINT_SAME_EL: | |
10794 | moe = 1; | |
10795 | break; | |
10796 | case EC_WATCHPOINT: | |
10797 | case EC_WATCHPOINT_SAME_EL: | |
10798 | moe = 10; | |
10799 | break; | |
10800 | case EC_AA32_BKPT: | |
10801 | moe = 3; | |
10802 | break; | |
10803 | case EC_VECTORCATCH: | |
10804 | moe = 5; | |
10805 | break; | |
10806 | default: | |
10807 | moe = 0; | |
10808 | break; | |
10809 | } | |
10810 | ||
10811 | if (moe) { | |
10812 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
10813 | } | |
10814 | ||
b9bc21ff PM |
10815 | if (env->exception.target_el == 2) { |
10816 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
10817 | return; | |
10818 | } | |
10819 | ||
27103424 | 10820 | switch (cs->exception_index) { |
b5ff1b31 FB |
10821 | case EXCP_UDEF: |
10822 | new_mode = ARM_CPU_MODE_UND; | |
10823 | addr = 0x04; | |
10824 | mask = CPSR_I; | |
f927dbda | 10825 | if (env->thumb) { |
b5ff1b31 | 10826 | offset = 2; |
f927dbda | 10827 | } else { |
b5ff1b31 | 10828 | offset = 4; |
f927dbda | 10829 | } |
b5ff1b31 FB |
10830 | break; |
10831 | case EXCP_SWI: | |
10832 | new_mode = ARM_CPU_MODE_SVC; | |
10833 | addr = 0x08; | |
10834 | mask = CPSR_I; | |
601d70b9 | 10835 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
10836 | offset = 0; |
10837 | break; | |
06c949e6 | 10838 | case EXCP_BKPT: |
9ee6e8bb PB |
10839 | /* Fall through to prefetch abort. */ |
10840 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 10841 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 10842 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 10843 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 10844 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10845 | new_mode = ARM_CPU_MODE_ABT; |
10846 | addr = 0x0c; | |
10847 | mask = CPSR_A | CPSR_I; | |
10848 | offset = 4; | |
10849 | break; | |
10850 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 10851 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 10852 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 10853 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 10854 | env->exception.fsr, |
6cd8a264 | 10855 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10856 | new_mode = ARM_CPU_MODE_ABT; |
10857 | addr = 0x10; | |
10858 | mask = CPSR_A | CPSR_I; | |
10859 | offset = 8; | |
10860 | break; | |
10861 | case EXCP_IRQ: | |
10862 | new_mode = ARM_CPU_MODE_IRQ; | |
10863 | addr = 0x18; | |
10864 | /* Disable IRQ and imprecise data aborts. */ | |
10865 | mask = CPSR_A | CPSR_I; | |
10866 | offset = 4; | |
de38d23b FA |
10867 | if (env->cp15.scr_el3 & SCR_IRQ) { |
10868 | /* IRQ routed to monitor mode */ | |
10869 | new_mode = ARM_CPU_MODE_MON; | |
10870 | mask |= CPSR_F; | |
10871 | } | |
b5ff1b31 FB |
10872 | break; |
10873 | case EXCP_FIQ: | |
10874 | new_mode = ARM_CPU_MODE_FIQ; | |
10875 | addr = 0x1c; | |
10876 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10877 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
10878 | if (env->cp15.scr_el3 & SCR_FIQ) { |
10879 | /* FIQ routed to monitor mode */ | |
10880 | new_mode = ARM_CPU_MODE_MON; | |
10881 | } | |
b5ff1b31 FB |
10882 | offset = 4; |
10883 | break; | |
87a4b270 PM |
10884 | case EXCP_VIRQ: |
10885 | new_mode = ARM_CPU_MODE_IRQ; | |
10886 | addr = 0x18; | |
10887 | /* Disable IRQ and imprecise data aborts. */ | |
10888 | mask = CPSR_A | CPSR_I; | |
10889 | offset = 4; | |
10890 | break; | |
10891 | case EXCP_VFIQ: | |
10892 | new_mode = ARM_CPU_MODE_FIQ; | |
10893 | addr = 0x1c; | |
10894 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10895 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10896 | offset = 4; | |
10897 | break; | |
3c29632f RH |
10898 | case EXCP_VSERR: |
10899 | { | |
10900 | /* | |
10901 | * Note that this is reported as a data abort, but the DFAR | |
10902 | * has an UNKNOWN value. Construct the SError syndrome from | |
10903 | * AET and ExT fields. | |
10904 | */ | |
10905 | ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | |
10906 | ||
10907 | if (extended_addresses_enabled(env)) { | |
10908 | env->exception.fsr = arm_fi_to_lfsc(&fi); | |
10909 | } else { | |
10910 | env->exception.fsr = arm_fi_to_sfsc(&fi); | |
10911 | } | |
10912 | env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | |
10913 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | |
10914 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | |
10915 | env->exception.fsr); | |
10916 | ||
10917 | new_mode = ARM_CPU_MODE_ABT; | |
10918 | addr = 0x10; | |
10919 | mask = CPSR_A | CPSR_I; | |
10920 | offset = 8; | |
10921 | } | |
10922 | break; | |
dbe9d163 FA |
10923 | case EXCP_SMC: |
10924 | new_mode = ARM_CPU_MODE_MON; | |
10925 | addr = 0x08; | |
10926 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10927 | offset = 0; | |
10928 | break; | |
b5ff1b31 | 10929 | default: |
a47dddd7 | 10930 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
10931 | return; /* Never happens. Keep compiler happy. */ |
10932 | } | |
e89e51a1 FA |
10933 | |
10934 | if (new_mode == ARM_CPU_MODE_MON) { | |
10935 | addr += env->cp15.mvbar; | |
137feaa9 | 10936 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 10937 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 10938 | addr += 0xffff0000; |
8641136c | 10939 | } else { |
9b37a28c FR |
10940 | /* |
10941 | * ARM v7 architectures provide a vector base address register to remap | |
8641136c | 10942 | * the interrupt vector table. |
e89e51a1 | 10943 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
10944 | * Note: only bits 31:5 are valid. |
10945 | */ | |
fb6c91ba | 10946 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 10947 | } |
dbe9d163 FA |
10948 | |
10949 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
10950 | env->cp15.scr_el3 &= ~SCR_NS; | |
10951 | } | |
10952 | ||
dea8378b | 10953 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
10954 | } |
10955 | ||
a65dabf7 PM |
10956 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
10957 | { | |
10958 | /* | |
10959 | * Return the register number of the AArch64 view of the AArch32 | |
10960 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
10961 | * be that of the AArch32 mode the exception came from. | |
10962 | */ | |
10963 | int mode = env->uncached_cpsr & CPSR_M; | |
10964 | ||
10965 | switch (aarch32_reg) { | |
10966 | case 0 ... 7: | |
10967 | return aarch32_reg; | |
10968 | case 8 ... 12: | |
10969 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
10970 | case 13: | |
10971 | switch (mode) { | |
10972 | case ARM_CPU_MODE_USR: | |
10973 | case ARM_CPU_MODE_SYS: | |
10974 | return 13; | |
10975 | case ARM_CPU_MODE_HYP: | |
10976 | return 15; | |
10977 | case ARM_CPU_MODE_IRQ: | |
10978 | return 17; | |
10979 | case ARM_CPU_MODE_SVC: | |
10980 | return 19; | |
10981 | case ARM_CPU_MODE_ABT: | |
10982 | return 21; | |
10983 | case ARM_CPU_MODE_UND: | |
10984 | return 23; | |
10985 | case ARM_CPU_MODE_FIQ: | |
10986 | return 29; | |
10987 | default: | |
10988 | g_assert_not_reached(); | |
10989 | } | |
10990 | case 14: | |
10991 | switch (mode) { | |
10992 | case ARM_CPU_MODE_USR: | |
10993 | case ARM_CPU_MODE_SYS: | |
10994 | case ARM_CPU_MODE_HYP: | |
10995 | return 14; | |
10996 | case ARM_CPU_MODE_IRQ: | |
10997 | return 16; | |
10998 | case ARM_CPU_MODE_SVC: | |
10999 | return 18; | |
11000 | case ARM_CPU_MODE_ABT: | |
11001 | return 20; | |
11002 | case ARM_CPU_MODE_UND: | |
11003 | return 22; | |
11004 | case ARM_CPU_MODE_FIQ: | |
11005 | return 30; | |
11006 | default: | |
11007 | g_assert_not_reached(); | |
11008 | } | |
11009 | case 15: | |
11010 | return 31; | |
11011 | default: | |
11012 | g_assert_not_reached(); | |
11013 | } | |
11014 | } | |
11015 | ||
f944a854 RC |
11016 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
11017 | { | |
11018 | uint32_t ret = cpsr_read(env); | |
11019 | ||
11020 | /* Move DIT to the correct location for SPSR_ELx */ | |
11021 | if (ret & CPSR_DIT) { | |
11022 | ret &= ~CPSR_DIT; | |
11023 | ret |= PSTATE_DIT; | |
11024 | } | |
11025 | /* Merge PSTATE.SS into SPSR_ELx */ | |
11026 | ret |= env->pstate & PSTATE_SS; | |
11027 | ||
11028 | return ret; | |
11029 | } | |
11030 | ||
7ac61020 PM |
11031 | static bool syndrome_is_sync_extabt(uint32_t syndrome) |
11032 | { | |
11033 | /* Return true if this syndrome value is a synchronous external abort */ | |
11034 | switch (syn_get_ec(syndrome)) { | |
11035 | case EC_INSNABORT: | |
11036 | case EC_INSNABORT_SAME_EL: | |
11037 | case EC_DATAABORT: | |
11038 | case EC_DATAABORT_SAME_EL: | |
11039 | /* Look at fault status code for all the synchronous ext abort cases */ | |
11040 | switch (syndrome & 0x3f) { | |
11041 | case 0x10: | |
11042 | case 0x13: | |
11043 | case 0x14: | |
11044 | case 0x15: | |
11045 | case 0x16: | |
11046 | case 0x17: | |
11047 | return true; | |
11048 | default: | |
11049 | return false; | |
11050 | } | |
11051 | default: | |
11052 | return false; | |
11053 | } | |
11054 | } | |
11055 | ||
966f758c PM |
11056 | /* Handle exception entry to a target EL which is using AArch64 */ |
11057 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
11058 | { |
11059 | ARMCPU *cpu = ARM_CPU(cs); | |
11060 | CPUARMState *env = &cpu->env; | |
11061 | unsigned int new_el = env->exception.target_el; | |
11062 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
11063 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 11064 | unsigned int old_mode; |
0ab5953b | 11065 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 11066 | int rt; |
0ab5953b | 11067 | |
d55b2a2a CF |
11068 | if (tcg_enabled()) { |
11069 | /* | |
11070 | * Note that new_el can never be 0. If cur_el is 0, then | |
11071 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
11072 | */ | |
11073 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
11074 | } | |
f3a9b694 | 11075 | |
0ab5953b | 11076 | if (cur_el < new_el) { |
9b37a28c FR |
11077 | /* |
11078 | * Entry vector offset depends on whether the implemented EL | |
3d6f7617 PM |
11079 | * immediately lower than the target level is using AArch32 or AArch64 |
11080 | */ | |
11081 | bool is_aa64; | |
cb092fbb | 11082 | uint64_t hcr; |
3d6f7617 PM |
11083 | |
11084 | switch (new_el) { | |
11085 | case 3: | |
11086 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
11087 | break; | |
11088 | case 2: | |
cb092fbb RH |
11089 | hcr = arm_hcr_el2_eff(env); |
11090 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
11091 | is_aa64 = (hcr & HCR_RW) != 0; | |
11092 | break; | |
11093 | } | |
11094 | /* fall through */ | |
3d6f7617 PM |
11095 | case 1: |
11096 | is_aa64 = is_a64(env); | |
11097 | break; | |
11098 | default: | |
11099 | g_assert_not_reached(); | |
11100 | } | |
11101 | ||
11102 | if (is_aa64) { | |
f3a9b694 PM |
11103 | addr += 0x400; |
11104 | } else { | |
11105 | addr += 0x600; | |
11106 | } | |
11107 | } else if (pstate_read(env) & PSTATE_SP) { | |
11108 | addr += 0x200; | |
11109 | } | |
11110 | ||
f3a9b694 | 11111 | switch (cs->exception_index) { |
11b76fda RH |
11112 | case EXCP_GPC: |
11113 | qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", | |
11114 | env->cp15.mfar_el3); | |
11115 | /* fall through */ | |
f3a9b694 PM |
11116 | case EXCP_PREFETCH_ABORT: |
11117 | case EXCP_DATA_ABORT: | |
7ac61020 PM |
11118 | /* |
11119 | * FEAT_DoubleFault allows synchronous external aborts taken to EL3 | |
11120 | * to be taken to the SError vector entrypoint. | |
11121 | */ | |
11122 | if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && | |
11123 | syndrome_is_sync_extabt(env->exception.syndrome)) { | |
11124 | addr += 0x180; | |
11125 | } | |
f3a9b694 PM |
11126 | env->cp15.far_el[new_el] = env->exception.vaddress; |
11127 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
11128 | env->cp15.far_el[new_el]); | |
11129 | /* fall through */ | |
11130 | case EXCP_BKPT: | |
11131 | case EXCP_UDEF: | |
11132 | case EXCP_SWI: | |
11133 | case EXCP_HVC: | |
11134 | case EXCP_HYP_TRAP: | |
11135 | case EXCP_SMC: | |
a65dabf7 PM |
11136 | switch (syn_get_ec(env->exception.syndrome)) { |
11137 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
11138 | /* |
11139 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
11140 | * TA and coproc fields which are only exposed if the exception | |
11141 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
11142 | * AArch64 format syndrome. | |
11143 | */ | |
11144 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
11145 | break; |
11146 | case EC_CP14RTTRAP: | |
11147 | case EC_CP15RTTRAP: | |
11148 | case EC_CP14DTTRAP: | |
11149 | /* | |
11150 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
11151 | * the raw register field from the insn; when taking this to | |
11152 | * AArch64 we must convert it to the AArch64 view of the register | |
11153 | * number. Notice that we read a 4-bit AArch32 register number and | |
11154 | * write back a 5-bit AArch64 one. | |
11155 | */ | |
11156 | rt = extract32(env->exception.syndrome, 5, 4); | |
11157 | rt = aarch64_regnum(env, rt); | |
11158 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11159 | 5, 5, rt); | |
11160 | break; | |
11161 | case EC_CP15RRTTRAP: | |
11162 | case EC_CP14RRTTRAP: | |
11163 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
11164 | rt = extract32(env->exception.syndrome, 5, 4); | |
11165 | rt = aarch64_regnum(env, rt); | |
11166 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11167 | 5, 5, rt); | |
11168 | rt = extract32(env->exception.syndrome, 10, 4); | |
11169 | rt = aarch64_regnum(env, rt); | |
11170 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11171 | 10, 5, rt); | |
11172 | break; | |
4be42f40 | 11173 | } |
f3a9b694 PM |
11174 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
11175 | break; | |
11176 | case EXCP_IRQ: | |
11177 | case EXCP_VIRQ: | |
11178 | addr += 0x80; | |
11179 | break; | |
11180 | case EXCP_FIQ: | |
11181 | case EXCP_VFIQ: | |
11182 | addr += 0x100; | |
11183 | break; | |
3c29632f RH |
11184 | case EXCP_VSERR: |
11185 | addr += 0x180; | |
11186 | /* Construct the SError syndrome from IDS and ISS fields. */ | |
11187 | env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | |
11188 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
11189 | break; | |
f3a9b694 PM |
11190 | default: |
11191 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
11192 | } | |
11193 | ||
11194 | if (is_a64(env)) { | |
4a2696c0 | 11195 | old_mode = pstate_read(env); |
f3a9b694 PM |
11196 | aarch64_save_sp(env, arm_current_el(env)); |
11197 | env->elr_el[new_el] = env->pc; | |
11198 | } else { | |
f944a854 | 11199 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
11200 | env->elr_el[new_el] = env->regs[15]; |
11201 | ||
11202 | aarch64_sync_32_to_64(env); | |
11203 | ||
11204 | env->condexec_bits = 0; | |
11205 | } | |
4a2696c0 RH |
11206 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
11207 | ||
f3a9b694 PM |
11208 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
11209 | env->elr_el[new_el]); | |
11210 | ||
4a2696c0 RH |
11211 | if (cpu_isar_feature(aa64_pan, cpu)) { |
11212 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
11213 | new_mode |= old_mode & PSTATE_PAN; | |
11214 | switch (new_el) { | |
11215 | case 2: | |
11216 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
11217 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
11218 | != (HCR_E2H | HCR_TGE)) { | |
11219 | break; | |
11220 | } | |
11221 | /* fall through */ | |
11222 | case 1: | |
11223 | /* ... the target is EL1 ... */ | |
11224 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
11225 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
11226 | new_mode |= PSTATE_PAN; | |
11227 | } | |
11228 | break; | |
11229 | } | |
11230 | } | |
34669338 RH |
11231 | if (cpu_isar_feature(aa64_mte, cpu)) { |
11232 | new_mode |= PSTATE_TCO; | |
11233 | } | |
4a2696c0 | 11234 | |
f2f68a78 RC |
11235 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
11236 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
11237 | new_mode |= PSTATE_SSBS; | |
11238 | } else { | |
11239 | new_mode &= ~PSTATE_SSBS; | |
11240 | } | |
11241 | } | |
11242 | ||
f3a9b694 | 11243 | pstate_write(env, PSTATE_DAIF | new_mode); |
53221552 | 11244 | env->aarch64 = true; |
f3a9b694 | 11245 | aarch64_restore_sp(env, new_el); |
2b77ad4d FR |
11246 | |
11247 | if (tcg_enabled()) { | |
11248 | helper_rebuild_hflags_a64(env, new_el); | |
11249 | } | |
f3a9b694 PM |
11250 | |
11251 | env->pc = addr; | |
11252 | ||
11253 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
11254 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
11255 | } |
11256 | ||
ed6e6ba9 AB |
11257 | /* |
11258 | * Do semihosting call and set the appropriate return value. All the | |
11259 | * permission and validity checks have been done at translate time. | |
11260 | * | |
11261 | * We only see semihosting exceptions in TCG only as they are not | |
11262 | * trapped to the hypervisor in KVM. | |
11263 | */ | |
91f78c58 | 11264 | #ifdef CONFIG_TCG |
a06e3a68 | 11265 | static void tcg_handle_semihosting(CPUState *cs) |
ed6e6ba9 | 11266 | { |
904c04de PM |
11267 | ARMCPU *cpu = ARM_CPU(cs); |
11268 | CPUARMState *env = &cpu->env; | |
11269 | ||
11270 | if (is_a64(env)) { | |
ed6e6ba9 AB |
11271 | qemu_log_mask(CPU_LOG_INT, |
11272 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
11273 | env->xregs[0]); | |
ed3a06b1 | 11274 | do_common_semihosting(cs); |
4ff5ef9e | 11275 | env->pc += 4; |
904c04de | 11276 | } else { |
904c04de PM |
11277 | qemu_log_mask(CPU_LOG_INT, |
11278 | "...handling as semihosting call 0x%x\n", | |
11279 | env->regs[0]); | |
ed3a06b1 | 11280 | do_common_semihosting(cs); |
4ff5ef9e | 11281 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
11282 | } |
11283 | } | |
ed6e6ba9 | 11284 | #endif |
904c04de | 11285 | |
9b37a28c FR |
11286 | /* |
11287 | * Handle a CPU exception for A and R profile CPUs. | |
966f758c PM |
11288 | * Do any appropriate logging, handle PSCI calls, and then hand off |
11289 | * to the AArch64-entry or AArch32-entry function depending on the | |
11290 | * target exception level's register width. | |
853bfef4 CF |
11291 | * |
11292 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
11293 | * and KVM to re-inject guest debug exceptions, and to | |
11294 | * inject a Synchronous-External-Abort. | |
966f758c PM |
11295 | */ |
11296 | void arm_cpu_do_interrupt(CPUState *cs) | |
11297 | { | |
11298 | ARMCPU *cpu = ARM_CPU(cs); | |
11299 | CPUARMState *env = &cpu->env; | |
11300 | unsigned int new_el = env->exception.target_el; | |
11301 | ||
531c60a9 | 11302 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 11303 | |
fc6177af | 11304 | arm_log_exception(cs); |
966f758c PM |
11305 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
11306 | new_el); | |
11307 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
11308 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 11309 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 11310 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
11311 | env->exception.syndrome); |
11312 | } | |
11313 | ||
0c1aaa66 | 11314 | if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { |
966f758c PM |
11315 | arm_handle_psci_call(cpu); |
11316 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
11317 | return; | |
11318 | } | |
11319 | ||
ed6e6ba9 AB |
11320 | /* |
11321 | * Semihosting semantics depend on the register width of the code | |
11322 | * that caused the exception, not the target exception level, so | |
11323 | * must be handled here. | |
966f758c | 11324 | */ |
ed6e6ba9 AB |
11325 | #ifdef CONFIG_TCG |
11326 | if (cs->exception_index == EXCP_SEMIHOST) { | |
a06e3a68 | 11327 | tcg_handle_semihosting(cs); |
904c04de PM |
11328 | return; |
11329 | } | |
ed6e6ba9 | 11330 | #endif |
904c04de | 11331 | |
9b37a28c FR |
11332 | /* |
11333 | * Hooks may change global state so BQL should be held, also the | |
b5c53d1b AL |
11334 | * BQL needs to be held for any modification of |
11335 | * cs->interrupt_request. | |
11336 | */ | |
11337 | g_assert(qemu_mutex_iothread_locked()); | |
11338 | ||
11339 | arm_call_pre_el_change_hook(cpu); | |
11340 | ||
904c04de PM |
11341 | assert(!excp_is_internal(cs->exception_index)); |
11342 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
11343 | arm_cpu_do_interrupt_aarch64(cs); |
11344 | } else { | |
11345 | arm_cpu_do_interrupt_aarch32(cs); | |
11346 | } | |
f3a9b694 | 11347 | |
bd7d00fc PM |
11348 | arm_call_el_change_hook(cpu); |
11349 | ||
f3a9b694 PM |
11350 | if (!kvm_enabled()) { |
11351 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
11352 | } | |
11353 | } | |
c47eaf9f | 11354 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 11355 | |
aaec1432 RH |
11356 | uint64_t arm_sctlr(CPUARMState *env, int el) |
11357 | { | |
11358 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
11359 | if (el == 0) { | |
11360 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
d902ae75 | 11361 | el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; |
aaec1432 RH |
11362 | } |
11363 | return env->cp15.sctlr_el[el]; | |
11364 | } | |
c47eaf9f | 11365 | |
8ae08860 | 11366 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11367 | { |
11368 | if (regime_has_2_ranges(mmu_idx)) { | |
11369 | return extract64(tcr, 37, 2); | |
edc05dd4 | 11370 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11371 | return 0; /* VTCR_EL2 */ |
11372 | } else { | |
3e270f67 RH |
11373 | /* Replicate the single TBI bit so we always have 2 bits. */ |
11374 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
11375 | } |
11376 | } | |
11377 | ||
8ae08860 | 11378 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11379 | { |
11380 | if (regime_has_2_ranges(mmu_idx)) { | |
11381 | return extract64(tcr, 51, 2); | |
edc05dd4 | 11382 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11383 | return 0; /* VTCR_EL2 */ |
11384 | } else { | |
3e270f67 RH |
11385 | /* Replicate the single TBID bit so we always have 2 bits. */ |
11386 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
11387 | } |
11388 | } | |
11389 | ||
671efad1 | 11390 | int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
81ae05fa RH |
11391 | { |
11392 | if (regime_has_2_ranges(mmu_idx)) { | |
11393 | return extract64(tcr, 57, 2); | |
11394 | } else { | |
11395 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
11396 | return extract32(tcr, 30, 1) * 3; | |
11397 | } | |
11398 | } | |
11399 | ||
104f703d PM |
11400 | static ARMGranuleSize tg0_to_gran_size(int tg) |
11401 | { | |
11402 | switch (tg) { | |
11403 | case 0: | |
11404 | return Gran4K; | |
11405 | case 1: | |
11406 | return Gran64K; | |
11407 | case 2: | |
11408 | return Gran16K; | |
11409 | default: | |
11410 | return GranInvalid; | |
11411 | } | |
11412 | } | |
11413 | ||
11414 | static ARMGranuleSize tg1_to_gran_size(int tg) | |
11415 | { | |
11416 | switch (tg) { | |
11417 | case 1: | |
11418 | return Gran16K; | |
11419 | case 2: | |
11420 | return Gran4K; | |
11421 | case 3: | |
11422 | return Gran64K; | |
11423 | default: | |
11424 | return GranInvalid; | |
11425 | } | |
11426 | } | |
11427 | ||
11428 | static inline bool have4k(ARMCPU *cpu, bool stage2) | |
11429 | { | |
11430 | return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu) | |
11431 | : cpu_isar_feature(aa64_tgran4, cpu); | |
11432 | } | |
11433 | ||
11434 | static inline bool have16k(ARMCPU *cpu, bool stage2) | |
11435 | { | |
11436 | return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu) | |
11437 | : cpu_isar_feature(aa64_tgran16, cpu); | |
11438 | } | |
11439 | ||
11440 | static inline bool have64k(ARMCPU *cpu, bool stage2) | |
11441 | { | |
11442 | return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu) | |
11443 | : cpu_isar_feature(aa64_tgran64, cpu); | |
11444 | } | |
11445 | ||
11446 | static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, | |
11447 | bool stage2) | |
11448 | { | |
11449 | switch (gran) { | |
11450 | case Gran4K: | |
11451 | if (have4k(cpu, stage2)) { | |
11452 | return gran; | |
11453 | } | |
11454 | break; | |
11455 | case Gran16K: | |
11456 | if (have16k(cpu, stage2)) { | |
11457 | return gran; | |
11458 | } | |
11459 | break; | |
11460 | case Gran64K: | |
11461 | if (have64k(cpu, stage2)) { | |
11462 | return gran; | |
11463 | } | |
11464 | break; | |
11465 | case GranInvalid: | |
11466 | break; | |
11467 | } | |
11468 | /* | |
11469 | * If the guest selects a granule size that isn't implemented, | |
11470 | * the architecture requires that we behave as if it selected one | |
11471 | * that is (with an IMPDEF choice of which one to pick). We choose | |
11472 | * to implement the smallest supported granule size. | |
11473 | */ | |
11474 | if (have4k(cpu, stage2)) { | |
11475 | return Gran4K; | |
11476 | } | |
11477 | if (have16k(cpu, stage2)) { | |
11478 | return Gran16K; | |
11479 | } | |
11480 | assert(have64k(cpu, stage2)); | |
11481 | return Gran64K; | |
11482 | } | |
11483 | ||
b830a5ee | 11484 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
478dccbb PM |
11485 | ARMMMUIdx mmu_idx, bool data, |
11486 | bool el1_is_aa32) | |
ba97be9f | 11487 | { |
c1547bba | 11488 | uint64_t tcr = regime_tcr(env, mmu_idx); |
89739227 | 11489 | bool epd, hpd, tsz_oob, ds, ha, hd; |
ef56c242 | 11490 | int select, tsz, tbi, max_tsz, min_tsz, ps, sh; |
104f703d | 11491 | ARMGranuleSize gran; |
ef56c242 | 11492 | ARMCPU *cpu = env_archcpu(env); |
edc05dd4 | 11493 | bool stage2 = regime_is_stage2(mmu_idx); |
ba97be9f | 11494 | |
339370b9 | 11495 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 11496 | select = 0; |
ba97be9f | 11497 | tsz = extract32(tcr, 0, 6); |
104f703d PM |
11498 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
11499 | if (stage2) { | |
ba97be9f | 11500 | /* VTCR_EL2 */ |
b830a5ee | 11501 | hpd = false; |
ba97be9f | 11502 | } else { |
ba97be9f RH |
11503 | hpd = extract32(tcr, 24, 1); |
11504 | } | |
11505 | epd = false; | |
ef56c242 | 11506 | sh = extract32(tcr, 12, 2); |
f4ecc015 | 11507 | ps = extract32(tcr, 16, 3); |
89739227 RH |
11508 | ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11509 | hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11510 | ds = extract64(tcr, 32, 1); |
ba97be9f | 11511 | } else { |
e4c93e44 PM |
11512 | bool e0pd; |
11513 | ||
71d18164 RH |
11514 | /* |
11515 | * Bit 55 is always between the two regions, and is canonical for | |
11516 | * determining if address tagging is enabled. | |
11517 | */ | |
11518 | select = extract64(va, 55, 1); | |
11519 | if (!select) { | |
11520 | tsz = extract32(tcr, 0, 6); | |
104f703d | 11521 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
71d18164 | 11522 | epd = extract32(tcr, 7, 1); |
ef56c242 | 11523 | sh = extract32(tcr, 12, 2); |
71d18164 | 11524 | hpd = extract64(tcr, 41, 1); |
e4c93e44 | 11525 | e0pd = extract64(tcr, 55, 1); |
71d18164 | 11526 | } else { |
71d18164 | 11527 | tsz = extract32(tcr, 16, 6); |
104f703d | 11528 | gran = tg1_to_gran_size(extract32(tcr, 30, 2)); |
71d18164 | 11529 | epd = extract32(tcr, 23, 1); |
ef56c242 | 11530 | sh = extract32(tcr, 28, 2); |
71d18164 | 11531 | hpd = extract64(tcr, 42, 1); |
e4c93e44 | 11532 | e0pd = extract64(tcr, 56, 1); |
71d18164 | 11533 | } |
f4ecc015 | 11534 | ps = extract64(tcr, 32, 3); |
89739227 RH |
11535 | ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11536 | hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11537 | ds = extract64(tcr, 59, 1); |
e4c93e44 PM |
11538 | |
11539 | if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && | |
11540 | regime_is_user(env, mmu_idx)) { | |
11541 | epd = true; | |
11542 | } | |
ba97be9f | 11543 | } |
c36c65ea | 11544 | |
104f703d | 11545 | gran = sanitize_gran_size(cpu, gran, stage2); |
104f703d | 11546 | |
ef56c242 | 11547 | if (cpu_isar_feature(aa64_st, cpu)) { |
3c003f70 | 11548 | max_tsz = 48 - (gran == Gran64K); |
c36c65ea RDC |
11549 | } else { |
11550 | max_tsz = 39; | |
11551 | } | |
0af312b6 | 11552 | |
ef56c242 RH |
11553 | /* |
11554 | * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | |
11555 | * adjust the effective value of DS, as documented. | |
11556 | */ | |
0af312b6 | 11557 | min_tsz = 16; |
3c003f70 | 11558 | if (gran == Gran64K) { |
ef56c242 RH |
11559 | if (cpu_isar_feature(aa64_lva, cpu)) { |
11560 | min_tsz = 12; | |
11561 | } | |
11562 | ds = false; | |
11563 | } else if (ds) { | |
edc05dd4 | 11564 | if (regime_is_stage2(mmu_idx)) { |
3c003f70 | 11565 | if (gran == Gran16K) { |
ef56c242 RH |
11566 | ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); |
11567 | } else { | |
11568 | ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | |
11569 | } | |
edc05dd4 | 11570 | } else { |
3c003f70 | 11571 | if (gran == Gran16K) { |
ef56c242 RH |
11572 | ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); |
11573 | } else { | |
11574 | ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | |
11575 | } | |
ef56c242 RH |
11576 | } |
11577 | if (ds) { | |
0af312b6 RH |
11578 | min_tsz = 12; |
11579 | } | |
11580 | } | |
c36c65ea | 11581 | |
478dccbb PM |
11582 | if (stage2 && el1_is_aa32) { |
11583 | /* | |
11584 | * For AArch32 EL1 the min txsz (and thus max IPA size) requirements | |
11585 | * are loosened: a configured IPA of 40 bits is permitted even if | |
11586 | * the implemented PA is less than that (and so a 40 bit IPA would | |
11587 | * fault for an AArch64 EL1). See R_DTLMN. | |
11588 | */ | |
11589 | min_tsz = MIN(min_tsz, 24); | |
11590 | } | |
11591 | ||
ebf93ce7 RH |
11592 | if (tsz > max_tsz) { |
11593 | tsz = max_tsz; | |
11594 | tsz_oob = true; | |
11595 | } else if (tsz < min_tsz) { | |
11596 | tsz = min_tsz; | |
11597 | tsz_oob = true; | |
11598 | } else { | |
11599 | tsz_oob = false; | |
11600 | } | |
ba97be9f | 11601 | |
b830a5ee RH |
11602 | /* Present TBI as a composite with TBID. */ |
11603 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
11604 | if (!data) { | |
11605 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
11606 | } | |
11607 | tbi = (tbi >> select) & 1; | |
11608 | ||
ba97be9f RH |
11609 | return (ARMVAParameters) { |
11610 | .tsz = tsz, | |
f4ecc015 | 11611 | .ps = ps, |
ef56c242 | 11612 | .sh = sh, |
ba97be9f RH |
11613 | .select = select, |
11614 | .tbi = tbi, | |
11615 | .epd = epd, | |
11616 | .hpd = hpd, | |
ebf93ce7 | 11617 | .tsz_oob = tsz_oob, |
ef56c242 | 11618 | .ds = ds, |
89739227 RH |
11619 | .ha = ha, |
11620 | .hd = ha && hd, | |
3c003f70 | 11621 | .gran = gran, |
ba97be9f RH |
11622 | }; |
11623 | } | |
11624 | ||
9b37a28c FR |
11625 | /* |
11626 | * Note that signed overflow is undefined in C. The following routines are | |
11627 | * careful to use unsigned types where modulo arithmetic is required. | |
11628 | * Failure to do so _will_ break on newer gcc. | |
11629 | */ | |
6ddbc6e4 PB |
11630 | |
11631 | /* Signed saturating arithmetic. */ | |
11632 | ||
1654b2d6 | 11633 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
11634 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
11635 | { | |
11636 | uint16_t res; | |
11637 | ||
11638 | res = a + b; | |
11639 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
f927dbda | 11640 | if (a & 0x8000) { |
6ddbc6e4 | 11641 | res = 0x8000; |
f927dbda | 11642 | } else { |
6ddbc6e4 | 11643 | res = 0x7fff; |
f927dbda | 11644 | } |
6ddbc6e4 PB |
11645 | } |
11646 | return res; | |
11647 | } | |
11648 | ||
1654b2d6 | 11649 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
11650 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
11651 | { | |
11652 | uint8_t res; | |
11653 | ||
11654 | res = a + b; | |
11655 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
f927dbda | 11656 | if (a & 0x80) { |
6ddbc6e4 | 11657 | res = 0x80; |
f927dbda | 11658 | } else { |
6ddbc6e4 | 11659 | res = 0x7f; |
f927dbda | 11660 | } |
6ddbc6e4 PB |
11661 | } |
11662 | return res; | |
11663 | } | |
11664 | ||
1654b2d6 | 11665 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11666 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
11667 | { | |
11668 | uint16_t res; | |
11669 | ||
11670 | res = a - b; | |
11671 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
f927dbda | 11672 | if (a & 0x8000) { |
6ddbc6e4 | 11673 | res = 0x8000; |
f927dbda | 11674 | } else { |
6ddbc6e4 | 11675 | res = 0x7fff; |
f927dbda | 11676 | } |
6ddbc6e4 PB |
11677 | } |
11678 | return res; | |
11679 | } | |
11680 | ||
1654b2d6 | 11681 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11682 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
11683 | { | |
11684 | uint8_t res; | |
11685 | ||
11686 | res = a - b; | |
11687 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
f927dbda | 11688 | if (a & 0x80) { |
6ddbc6e4 | 11689 | res = 0x80; |
f927dbda | 11690 | } else { |
6ddbc6e4 | 11691 | res = 0x7f; |
f927dbda | 11692 | } |
6ddbc6e4 PB |
11693 | } |
11694 | return res; | |
11695 | } | |
11696 | ||
11697 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
11698 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
11699 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
11700 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
11701 | #define PFX q | |
11702 | ||
11703 | #include "op_addsub.h" | |
11704 | ||
11705 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 11706 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
11707 | { |
11708 | uint16_t res; | |
11709 | res = a + b; | |
f927dbda | 11710 | if (res < a) { |
6ddbc6e4 | 11711 | res = 0xffff; |
f927dbda | 11712 | } |
6ddbc6e4 PB |
11713 | return res; |
11714 | } | |
11715 | ||
460a09c1 | 11716 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 11717 | { |
f927dbda | 11718 | if (a > b) { |
6ddbc6e4 | 11719 | return a - b; |
f927dbda | 11720 | } else { |
6ddbc6e4 | 11721 | return 0; |
f927dbda | 11722 | } |
6ddbc6e4 PB |
11723 | } |
11724 | ||
11725 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
11726 | { | |
11727 | uint8_t res; | |
11728 | res = a + b; | |
f927dbda | 11729 | if (res < a) { |
6ddbc6e4 | 11730 | res = 0xff; |
f927dbda | 11731 | } |
6ddbc6e4 PB |
11732 | return res; |
11733 | } | |
11734 | ||
11735 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
11736 | { | |
f927dbda | 11737 | if (a > b) { |
6ddbc6e4 | 11738 | return a - b; |
f927dbda | 11739 | } else { |
6ddbc6e4 | 11740 | return 0; |
f927dbda | 11741 | } |
6ddbc6e4 PB |
11742 | } |
11743 | ||
11744 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
11745 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
11746 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
11747 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
11748 | #define PFX uq | |
11749 | ||
11750 | #include "op_addsub.h" | |
11751 | ||
11752 | /* Signed modulo arithmetic. */ | |
11753 | #define SARITH16(a, b, n, op) do { \ | |
11754 | int32_t sum; \ | |
db6e2e65 | 11755 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
11756 | RESULT(sum, n, 16); \ |
11757 | if (sum >= 0) \ | |
11758 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11759 | } while (0) |
6ddbc6e4 PB |
11760 | |
11761 | #define SARITH8(a, b, n, op) do { \ | |
11762 | int32_t sum; \ | |
db6e2e65 | 11763 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
11764 | RESULT(sum, n, 8); \ |
11765 | if (sum >= 0) \ | |
11766 | ge |= 1 << n; \ | |
04215eb1 | 11767 | } while (0) |
6ddbc6e4 PB |
11768 | |
11769 | ||
11770 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
11771 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
11772 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
11773 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
11774 | #define PFX s | |
11775 | #define ARITH_GE | |
11776 | ||
11777 | #include "op_addsub.h" | |
11778 | ||
11779 | /* Unsigned modulo arithmetic. */ | |
11780 | #define ADD16(a, b, n) do { \ | |
11781 | uint32_t sum; \ | |
11782 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
11783 | RESULT(sum, n, 16); \ | |
a87aa10b | 11784 | if ((sum >> 16) == 1) \ |
6ddbc6e4 | 11785 | ge |= 3 << (n * 2); \ |
04215eb1 | 11786 | } while (0) |
6ddbc6e4 PB |
11787 | |
11788 | #define ADD8(a, b, n) do { \ | |
11789 | uint32_t sum; \ | |
11790 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
11791 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
11792 | if ((sum >> 8) == 1) \ |
11793 | ge |= 1 << n; \ | |
04215eb1 | 11794 | } while (0) |
6ddbc6e4 PB |
11795 | |
11796 | #define SUB16(a, b, n) do { \ | |
11797 | uint32_t sum; \ | |
11798 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
11799 | RESULT(sum, n, 16); \ | |
11800 | if ((sum >> 16) == 0) \ | |
11801 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11802 | } while (0) |
6ddbc6e4 PB |
11803 | |
11804 | #define SUB8(a, b, n) do { \ | |
11805 | uint32_t sum; \ | |
11806 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
11807 | RESULT(sum, n, 8); \ | |
11808 | if ((sum >> 8) == 0) \ | |
a87aa10b | 11809 | ge |= 1 << n; \ |
04215eb1 | 11810 | } while (0) |
6ddbc6e4 PB |
11811 | |
11812 | #define PFX u | |
11813 | #define ARITH_GE | |
11814 | ||
11815 | #include "op_addsub.h" | |
11816 | ||
11817 | /* Halved signed arithmetic. */ | |
11818 | #define ADD16(a, b, n) \ | |
11819 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11820 | #define SUB16(a, b, n) \ | |
11821 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11822 | #define ADD8(a, b, n) \ | |
11823 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11824 | #define SUB8(a, b, n) \ | |
11825 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11826 | #define PFX sh | |
11827 | ||
11828 | #include "op_addsub.h" | |
11829 | ||
11830 | /* Halved unsigned arithmetic. */ | |
11831 | #define ADD16(a, b, n) \ | |
11832 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11833 | #define SUB16(a, b, n) \ | |
11834 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11835 | #define ADD8(a, b, n) \ | |
11836 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11837 | #define SUB8(a, b, n) \ | |
11838 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11839 | #define PFX uh | |
11840 | ||
11841 | #include "op_addsub.h" | |
11842 | ||
11843 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
11844 | { | |
f927dbda | 11845 | if (a > b) { |
6ddbc6e4 | 11846 | return a - b; |
f927dbda | 11847 | } else { |
6ddbc6e4 | 11848 | return b - a; |
f927dbda | 11849 | } |
6ddbc6e4 PB |
11850 | } |
11851 | ||
11852 | /* Unsigned sum of absolute byte differences. */ | |
11853 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
11854 | { | |
11855 | uint32_t sum; | |
11856 | sum = do_usad(a, b); | |
11857 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 11858 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
11859 | sum += do_usad(a >> 24, b >> 24); |
11860 | return sum; | |
11861 | } | |
11862 | ||
11863 | /* For ARMv6 SEL instruction. */ | |
11864 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
11865 | { | |
11866 | uint32_t mask; | |
11867 | ||
11868 | mask = 0; | |
f927dbda | 11869 | if (flags & 1) { |
6ddbc6e4 | 11870 | mask |= 0xff; |
f927dbda FR |
11871 | } |
11872 | if (flags & 2) { | |
6ddbc6e4 | 11873 | mask |= 0xff00; |
f927dbda FR |
11874 | } |
11875 | if (flags & 4) { | |
6ddbc6e4 | 11876 | mask |= 0xff0000; |
f927dbda FR |
11877 | } |
11878 | if (flags & 8) { | |
6ddbc6e4 | 11879 | mask |= 0xff000000; |
f927dbda | 11880 | } |
6ddbc6e4 PB |
11881 | return (a & mask) | (b & ~mask); |
11882 | } | |
11883 | ||
9b37a28c FR |
11884 | /* |
11885 | * CRC helpers. | |
aa633469 PM |
11886 | * The upper bytes of val (above the number specified by 'bytes') must have |
11887 | * been zeroed out by the caller. | |
11888 | */ | |
eb0ecd5a WN |
11889 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
11890 | { | |
11891 | uint8_t buf[4]; | |
11892 | ||
aa633469 | 11893 | stl_le_p(buf, val); |
eb0ecd5a WN |
11894 | |
11895 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
11896 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
11897 | } | |
11898 | ||
11899 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
11900 | { | |
11901 | uint8_t buf[4]; | |
11902 | ||
aa633469 | 11903 | stl_le_p(buf, val); |
eb0ecd5a WN |
11904 | |
11905 | /* Linux crc32c converts the output to one's complement. */ | |
11906 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
11907 | } | |
a9e01311 | 11908 | |
9b37a28c FR |
11909 | /* |
11910 | * Return the exception level to which FP-disabled exceptions should | |
a9e01311 RH |
11911 | * be taken, or 0 if FP is enabled. |
11912 | */ | |
ced31551 | 11913 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 11914 | { |
55faa212 | 11915 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
11916 | uint64_t hcr_el2; |
11917 | ||
9b37a28c FR |
11918 | /* |
11919 | * CPACR and the CPTR registers don't exist before v6, so FP is | |
a9e01311 RH |
11920 | * always accessible |
11921 | */ | |
11922 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
11923 | return 0; | |
11924 | } | |
11925 | ||
d87513c0 PM |
11926 | if (arm_feature(env, ARM_FEATURE_M)) { |
11927 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
11928 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
11929 | return 1; | |
11930 | } | |
11931 | ||
11932 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
11933 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
11934 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
11935 | return 3; | |
11936 | } | |
11937 | } | |
11938 | ||
11939 | return 0; | |
11940 | } | |
11941 | ||
d5a6fa2d RH |
11942 | hcr_el2 = arm_hcr_el2_eff(env); |
11943 | ||
9b37a28c FR |
11944 | /* |
11945 | * The CPACR controls traps to EL1, or PL1 if we're 32 bit: | |
a9e01311 RH |
11946 | * 0, 2 : trap EL0 and EL1/PL1 accesses |
11947 | * 1 : trap only EL0 accesses | |
11948 | * 3 : trap no accesses | |
c2ddb7cf | 11949 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 11950 | */ |
d5a6fa2d | 11951 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
fab8ad39 | 11952 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); |
c2ddb7cf RH |
11953 | |
11954 | switch (fpen) { | |
02e1de14 RH |
11955 | case 1: |
11956 | if (cur_el != 0) { | |
11957 | break; | |
11958 | } | |
11959 | /* fall through */ | |
c2ddb7cf RH |
11960 | case 0: |
11961 | case 2: | |
02e1de14 RH |
11962 | /* Trap from Secure PL0 or PL1 to Secure PL1. */ |
11963 | if (!arm_el_is_aa64(env, 3) | |
11964 | && (cur_el == 3 || arm_is_secure_below_el3(env))) { | |
a9e01311 RH |
11965 | return 3; |
11966 | } | |
02e1de14 | 11967 | if (cur_el <= 1) { |
c2ddb7cf RH |
11968 | return 1; |
11969 | } | |
11970 | break; | |
a9e01311 | 11971 | } |
a9e01311 RH |
11972 | } |
11973 | ||
fc1120a7 PM |
11974 | /* |
11975 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
11976 | * to control non-secure access to the FPU. It doesn't have any | |
11977 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
11978 | */ | |
11979 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
11980 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
11981 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
11982 | /* FP insns act as UNDEF */ | |
11983 | return cur_el == 2 ? 2 : 1; | |
11984 | } | |
11985 | } | |
11986 | ||
d5a6fa2d RH |
11987 | /* |
11988 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
11989 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 11990 | */ |
d5a6fa2d RH |
11991 | if (cur_el <= 2) { |
11992 | if (hcr_el2 & HCR_E2H) { | |
fab8ad39 | 11993 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { |
d5a6fa2d RH |
11994 | case 1: |
11995 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
11996 | break; | |
11997 | } | |
11998 | /* fall through */ | |
11999 | case 0: | |
12000 | case 2: | |
12001 | return 2; | |
12002 | } | |
12003 | } else if (arm_is_el2_enabled(env)) { | |
fab8ad39 | 12004 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { |
d5a6fa2d RH |
12005 | return 2; |
12006 | } | |
12007 | } | |
a9e01311 RH |
12008 | } |
12009 | ||
12010 | /* CPTR_EL3 : present in v8 */ | |
fab8ad39 | 12011 | if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { |
a9e01311 RH |
12012 | /* Trap all FP ops to EL3 */ |
12013 | return 3; | |
12014 | } | |
55faa212 | 12015 | #endif |
a9e01311 RH |
12016 | return 0; |
12017 | } | |
12018 | ||
b9f6033c RH |
12019 | /* Return the exception level we're running at if this is our mmu_idx */ |
12020 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
12021 | { | |
12022 | if (mmu_idx & ARM_MMU_IDX_M) { | |
12023 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
12024 | } | |
12025 | ||
12026 | switch (mmu_idx) { | |
12027 | case ARMMMUIdx_E10_0: | |
12028 | case ARMMMUIdx_E20_0: | |
b9f6033c RH |
12029 | return 0; |
12030 | case ARMMMUIdx_E10_1: | |
452ef8cb | 12031 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c RH |
12032 | return 1; |
12033 | case ARMMMUIdx_E2: | |
12034 | case ARMMMUIdx_E20_2: | |
452ef8cb | 12035 | case ARMMMUIdx_E20_2_PAN: |
b9f6033c | 12036 | return 2; |
d902ae75 | 12037 | case ARMMMUIdx_E3: |
b9f6033c RH |
12038 | return 3; |
12039 | default: | |
12040 | g_assert_not_reached(); | |
12041 | } | |
12042 | } | |
12043 | ||
7aab5a8c | 12044 | #ifndef CONFIG_TCG |
65e4655c RH |
12045 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
12046 | { | |
7aab5a8c | 12047 | g_assert_not_reached(); |
65e4655c | 12048 | } |
7aab5a8c | 12049 | #endif |
65e4655c | 12050 | |
6f2d9d74 TK |
12051 | static bool arm_pan_enabled(CPUARMState *env) |
12052 | { | |
12053 | if (is_a64(env)) { | |
12054 | return env->pstate & PSTATE_PAN; | |
12055 | } else { | |
12056 | return env->uncached_cpsr & CPSR_PAN; | |
12057 | } | |
12058 | } | |
12059 | ||
164690b2 | 12060 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 12061 | { |
b6ad6062 RDC |
12062 | ARMMMUIdx idx; |
12063 | uint64_t hcr; | |
12064 | ||
65e4655c | 12065 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 12066 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
12067 | } |
12068 | ||
6003d980 | 12069 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
12070 | switch (el) { |
12071 | case 0: | |
b6ad6062 RDC |
12072 | hcr = arm_hcr_el2_eff(env); |
12073 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
12074 | idx = ARMMMUIdx_E20_0; | |
12075 | } else { | |
12076 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 12077 | } |
b6ad6062 | 12078 | break; |
b9f6033c | 12079 | case 1: |
6f2d9d74 | 12080 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12081 | idx = ARMMMUIdx_E10_1_PAN; |
12082 | } else { | |
12083 | idx = ARMMMUIdx_E10_1; | |
66412260 | 12084 | } |
b6ad6062 | 12085 | break; |
b9f6033c | 12086 | case 2: |
6003d980 | 12087 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 12088 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
6f2d9d74 | 12089 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12090 | idx = ARMMMUIdx_E20_2_PAN; |
12091 | } else { | |
12092 | idx = ARMMMUIdx_E20_2; | |
66412260 | 12093 | } |
b6ad6062 RDC |
12094 | } else { |
12095 | idx = ARMMMUIdx_E2; | |
6003d980 | 12096 | } |
b6ad6062 | 12097 | break; |
b9f6033c | 12098 | case 3: |
d902ae75 | 12099 | return ARMMMUIdx_E3; |
b9f6033c RH |
12100 | default: |
12101 | g_assert_not_reached(); | |
65e4655c | 12102 | } |
b6ad6062 | 12103 | |
b6ad6062 | 12104 | return idx; |
50494a27 RH |
12105 | } |
12106 | ||
164690b2 RH |
12107 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
12108 | { | |
12109 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
12110 | } | |
12111 | ||
26702213 PM |
12112 | static bool mve_no_pred(CPUARMState *env) |
12113 | { | |
12114 | /* | |
12115 | * Return true if there is definitely no predication of MVE | |
12116 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
12117 | * isn't any predication is OK; generated code will just be | |
12118 | * a little worse.) | |
12119 | * If the CPU does not implement MVE then this TB flag is always 0. | |
12120 | * | |
12121 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
12122 | * logic in gen_update_fp_context() needs to be updated to match. | |
12123 | * | |
12124 | * We do not include the effect of the ECI bits here -- they are | |
12125 | * tracked in other TB flags. This simplifies the logic for | |
12126 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
12127 | * and thus need to end the TB?". | |
12128 | */ | |
12129 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
12130 | return false; | |
12131 | } | |
12132 | if (env->v7m.vpr) { | |
12133 | return false; | |
12134 | } | |
12135 | if (env->v7m.ltpsize < 4) { | |
12136 | return false; | |
12137 | } | |
12138 | return true; | |
12139 | } | |
12140 | ||
bb5de525 AJ |
12141 | void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, |
12142 | uint64_t *cs_base, uint32_t *pflags) | |
d4d7503a | 12143 | { |
3902bfc6 | 12144 | CPUARMTBFlags flags; |
d4d7503a | 12145 | |
0ee8b24a | 12146 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 12147 | flags = env->hflags; |
3d74e2e9 | 12148 | |
a729a46b | 12149 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 12150 | *pc = env->pc; |
d4d7503a | 12151 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 12152 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 12153 | } |
a9e01311 RH |
12154 | } else { |
12155 | *pc = env->regs[15]; | |
6e33ced5 RH |
12156 | |
12157 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
12158 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
12159 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
12160 | != env->v7m.secure) { | |
a729a46b | 12161 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
12162 | } |
12163 | ||
12164 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
12165 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
12166 | (env->v7m.secure && | |
12167 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
12168 | /* | |
12169 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
12170 | * active FP context; we must create a new FP context before | |
12171 | * executing any FP insn. | |
12172 | */ | |
a729a46b | 12173 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
12174 | } |
12175 | ||
12176 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
12177 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 12178 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 12179 | } |
26702213 PM |
12180 | |
12181 | if (mve_no_pred(env)) { | |
12182 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
12183 | } | |
6e33ced5 | 12184 | } else { |
bbad7c62 RH |
12185 | /* |
12186 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
12187 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
12188 | */ | |
12189 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 12190 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 12191 | } else { |
a729a46b RH |
12192 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
12193 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 12194 | } |
0a54d68e | 12195 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 12196 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 12197 | } |
6e33ced5 RH |
12198 | } |
12199 | ||
a729a46b RH |
12200 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
12201 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 12202 | } |
a9e01311 | 12203 | |
60e12c37 RH |
12204 | /* |
12205 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
12206 | * states defined in the ARM ARM for software singlestep: |
12207 | * SS_ACTIVE PSTATE.SS State | |
12208 | * 0 x Inactive (the TB flag for SS is always 0) | |
12209 | * 1 0 Active-pending | |
12210 | * 1 1 Active-not-pending | |
ae6eb1e9 | 12211 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 12212 | */ |
a729a46b RH |
12213 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
12214 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 12215 | } |
a9e01311 | 12216 | |
3902bfc6 | 12217 | *pflags = flags.flags; |
a378206a | 12218 | *cs_base = flags.flags2; |
a9e01311 | 12219 | } |
0ab5953b RH |
12220 | |
12221 | #ifdef TARGET_AARCH64 | |
12222 | /* | |
12223 | * The manual says that when SVE is enabled and VQ is widened the | |
12224 | * implementation is allowed to zero the previously inaccessible | |
12225 | * portion of the registers. The corollary to that is that when | |
12226 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
12227 | * the now inaccessible portion of the registers. | |
12228 | * | |
12229 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
12230 | * Which means that some operations on predicate registers themselves | |
12231 | * may operate on full uint64_t or even unrolled across the maximum | |
12232 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
12233 | * may well be cheaper than conditionals to restrict the operation | |
12234 | * to the relevant portion of a uint16_t[16]. | |
12235 | */ | |
12236 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
12237 | { | |
12238 | int i, j; | |
12239 | uint64_t pmask; | |
12240 | ||
12241 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 12242 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
12243 | |
12244 | /* Zap the high bits of the zregs. */ | |
12245 | for (i = 0; i < 32; i++) { | |
12246 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
12247 | } | |
12248 | ||
12249 | /* Zap the high bits of the pregs and ffr. */ | |
12250 | pmask = 0; | |
12251 | if (vq & 3) { | |
12252 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
12253 | } | |
12254 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
12255 | for (i = 0; i < 17; ++i) { | |
12256 | env->vfp.pregs[i].p[j] &= pmask; | |
12257 | } | |
12258 | pmask = 0; | |
12259 | } | |
12260 | } | |
12261 | ||
6a775fd6 RH |
12262 | static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) |
12263 | { | |
12264 | int exc_el; | |
12265 | ||
12266 | if (sm) { | |
12267 | exc_el = sme_exception_el(env, el); | |
12268 | } else { | |
12269 | exc_el = sve_exception_el(env, el); | |
12270 | } | |
12271 | if (exc_el) { | |
12272 | return 0; /* disabled */ | |
12273 | } | |
12274 | return sve_vqm1_for_el_sm(env, el, sm); | |
12275 | } | |
12276 | ||
0ab5953b RH |
12277 | /* |
12278 | * Notice a change in SVE vector size when changing EL. | |
12279 | */ | |
9a05f7b6 RH |
12280 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
12281 | int new_el, bool el0_a64) | |
0ab5953b | 12282 | { |
2fc0cc0e | 12283 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 12284 | int old_len, new_len; |
6a775fd6 | 12285 | bool old_a64, new_a64, sm; |
0ab5953b RH |
12286 | |
12287 | /* Nothing to do if no SVE. */ | |
cd208a1c | 12288 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
12289 | return; |
12290 | } | |
12291 | ||
12292 | /* Nothing to do if FP is disabled in either EL. */ | |
12293 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
12294 | return; | |
12295 | } | |
12296 | ||
04fbce76 RH |
12297 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
12298 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | |
12299 | ||
12300 | /* | |
12301 | * Both AArch64.TakeException and AArch64.ExceptionReturn | |
12302 | * invoke ResetSVEState when taking an exception from, or | |
12303 | * returning to, AArch32 state when PSTATE.SM is enabled. | |
12304 | */ | |
6a775fd6 RH |
12305 | sm = FIELD_EX64(env->svcr, SVCR, SM); |
12306 | if (old_a64 != new_a64 && sm) { | |
04fbce76 RH |
12307 | arm_reset_sve_state(env); |
12308 | return; | |
12309 | } | |
12310 | ||
0ab5953b RH |
12311 | /* |
12312 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
12313 | * at ELx, or not available because the EL is in AArch32 state, then | |
12314 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
12315 | * has an effective value of 0". | |
12316 | * | |
12317 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
12318 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
12319 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
12320 | * we already have the correct register contents when encountering the | |
12321 | * vq0->vq0 transition between EL0->EL1. | |
12322 | */ | |
6a775fd6 RH |
12323 | old_len = new_len = 0; |
12324 | if (old_a64) { | |
12325 | old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm); | |
12326 | } | |
12327 | if (new_a64) { | |
12328 | new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm); | |
12329 | } | |
0ab5953b RH |
12330 | |
12331 | /* When changing vector length, clear inaccessible state. */ | |
12332 | if (new_len < old_len) { | |
12333 | aarch64_sve_narrow_vq(env, new_len + 1); | |
12334 | } | |
12335 | } | |
12336 | #endif | |
5d28ac0c RH |
12337 | |
12338 | #ifndef CONFIG_USER_ONLY | |
12339 | ARMSecuritySpace arm_security_space(CPUARMState *env) | |
12340 | { | |
12341 | if (arm_feature(env, ARM_FEATURE_M)) { | |
12342 | return arm_secure_to_space(env->v7m.secure); | |
12343 | } | |
12344 | ||
12345 | /* | |
12346 | * If EL3 is not supported then the secure state is implementation | |
12347 | * defined, in which case QEMU defaults to non-secure. | |
12348 | */ | |
12349 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12350 | return ARMSS_NonSecure; | |
12351 | } | |
12352 | ||
12353 | /* Check for AArch64 EL3 or AArch32 Mon. */ | |
12354 | if (is_a64(env)) { | |
12355 | if (extract32(env->pstate, 2, 2) == 3) { | |
12356 | if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { | |
12357 | return ARMSS_Root; | |
12358 | } else { | |
12359 | return ARMSS_Secure; | |
12360 | } | |
12361 | } | |
12362 | } else { | |
12363 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
12364 | return ARMSS_Secure; | |
12365 | } | |
12366 | } | |
12367 | ||
12368 | return arm_security_space_below_el3(env); | |
12369 | } | |
12370 | ||
12371 | ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) | |
12372 | { | |
12373 | assert(!arm_feature(env, ARM_FEATURE_M)); | |
12374 | ||
12375 | /* | |
12376 | * If EL3 is not supported then the secure state is implementation | |
12377 | * defined, in which case QEMU defaults to non-secure. | |
12378 | */ | |
12379 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12380 | return ARMSS_NonSecure; | |
12381 | } | |
12382 | ||
12383 | /* | |
12384 | * Note NSE cannot be set without RME, and NSE & !NS is Reserved. | |
12385 | * Ignoring NSE when !NS retains consistency without having to | |
12386 | * modify other predicates. | |
12387 | */ | |
12388 | if (!(env->cp15.scr_el3 & SCR_NS)) { | |
12389 | return ARMSS_Secure; | |
12390 | } else if (env->cp15.scr_el3 & SCR_NSE) { | |
12391 | return ARMSS_Realm; | |
12392 | } else { | |
12393 | return ARMSS_NonSecure; | |
12394 | } | |
12395 | } | |
12396 | #endif /* !CONFIG_USER_ONLY */ |