[mirror_qemu.git] / target / cris / helper.c

/*
 *  CRIS helper routines.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "mmu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"


//#define CRIS_HELPER_DEBUG


#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if defined(CONFIG_USER_ONLY)

void cris_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;

    cs->exception_index = -1;
    env->pregs[PR_ERP] = env->pc;
}

void crisv10_cpu_do_interrupt(CPUState *cs)
{
    cris_cpu_do_interrupt(cs);
}

int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
                              int mmu_idx)
{
    CRISCPU *cpu = CRIS_CPU(cs);

    cs->exception_index = 0xaa;
    cpu->env.pregs[PR_EDA] = address;
    cpu_dump_state(cs, stderr, fprintf, 0);
    return 1;
}

#else /* !CONFIG_USER_ONLY */


static void cris_shift_ccs(CPUCRISState *env)
{
    uint32_t ccs;
    /* Apply the ccs shift.  */
    ccs = env->pregs[PR_CCS];
    ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
    env->pregs[PR_CCS] = ccs;
}

int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
                              int mmu_idx)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    struct cris_mmu_result res;
    int prot, miss;
    int r = -1;
    target_ulong phy;

    qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
            __func__, address, env->pc, rw);
    miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
                              rw, mmu_idx, 0);
    if (miss) {
        if (cs->exception_index == EXCP_BUSFAULT) {
            cpu_abort(cs,
                      "CRIS: Illegal recursive bus fault."
                      "addr=%" VADDR_PRIx " rw=%d\n",
                      address, rw);
        }

        env->pregs[PR_EDA] = address;
        cs->exception_index = EXCP_BUSFAULT;
        env->fault_vector = res.bf_vec;
        r = 1;
    } else {
        /*
         * Mask off the cache selection bit. The ETRAX busses do not
         * see the top bit.
         */
        phy = res.phy & ~0x80000000;
        prot = res.prot;
        tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
                     prot, mmu_idx, TARGET_PAGE_SIZE);
        r = 0;
    }
    if (r > 0) {
        qemu_log_mask(CPU_LOG_MMU,
                "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
                " pc=%x\n", __func__, r, cs->interrupt_request, address,
                res.phy, res.bf_vec, env->pc);
    }
    return r;
}

void crisv10_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          cs->exception_index,
          cs->interrupt_request);

    if (env->dslot) {
        /* CRISv10 never takes interrupts while in a delay-slot.  */
        cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
    }

    assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
    switch (cs->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are genereated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V10;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        cpu_abort(cs, "Unhandled busfault");
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Now that we are in kernel mode, load the handlers address.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
    env->locked_irq = 1;
    env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */

    qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
                  __func__, env->pc, ex_vec,
                  env->pregs[PR_CCS],
                  env->pregs[PR_PID],
                  env->pregs[PR_ERP]);
}

void cris_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          cs->exception_index,
          cs->interrupt_request);

    switch (cs->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are genereated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V32;
        env->pregs[PR_NRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        ex_vec = env->fault_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    /* Fill in the IDX field.  */
    env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;

    if (env->dslot) {
        D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
              " ERP=%x pid=%x ccs=%x cc=%d %x\n",
              ex_vec, env->pc, env->dslot,
              env->regs[R_SP],
              env->pregs[PR_ERP], env->pregs[PR_PID],
              env->pregs[PR_CCS],
              env->cc_op, env->cc_mask);
        /* We loose the btarget, btaken state here so rexec the
           branch.  */
        env->pregs[PR_ERP] -= env->dslot;
        /* Exception starts with dslot cleared.  */
        env->dslot = 0;
    }

    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Apply the CRIS CCS shift. Clears U if set.  */
    cris_shift_ccs(env);

    /* Now that we are in kernel mode, load the handlers address.
       This load may not fault, real hw leaves that behaviour as
       undefined.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);

    /* Clear the excption_index to avoid spurios hw_aborts for recursive
       bus faults.  */
    cs->exception_index = -1;

    D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
          __func__, env->pc, ex_vec,
          env->pregs[PR_CCS],
          env->pregs[PR_PID],
          env->pregs[PR_ERP]);
}

hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    uint32_t phy = addr;
    struct cris_mmu_result res;
    int miss;

    miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
    /* If D TLB misses, try I TLB.  */
    if (miss) {
        miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
    }

    if (!miss) {
        phy = res.phy;
    }
    D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
    return phy;
}
#endif

bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    CPUClass *cc = CPU_GET_CLASS(cs);
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    bool ret = false;

    if (interrupt_request & CPU_INTERRUPT_HARD
        && (env->pregs[PR_CCS] & I_FLAG)
        && !env->locked_irq) {
        cs->exception_index = EXCP_IRQ;
        cc->do_interrupt(cs);
        ret = true;
    }
    if (interrupt_request & CPU_INTERRUPT_NMI) {
        unsigned int m_flag_archval;
        if (env->pregs[PR_VR] < 32) {
            m_flag_archval = M_FLAG_V10;
        } else {
            m_flag_archval = M_FLAG_V32;
        }
        if ((env->pregs[PR_CCS] & m_flag_archval)) {
            cs->exception_index = EXCP_NMI;
            cc->do_interrupt(cs);
            ret = true;
        }
    }

    return ret;
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
23b0d7df	21	#include "qemu/osdep.h"
81fdc5f8 TS	22	#include "cpu.h"
81fdc5f8 TS	23	#include "mmu.h"
1de7afc9	24	#include "qemu/host-utils.h"
63c91552	25	#include "exec/exec-all.h"
f08b6170	26	#include "exec/cpu_ldst.h"
81fdc5f8	27
d12d51d5 AL	28
	29	//#define CRIS_HELPER_DEBUG
	30
	31
	32	#ifdef CRIS_HELPER_DEBUG
	33	#define D(x) x
3f668b6c	34	#define D_LOG(...) qemu_log(__VA_ARGS__)
d12d51d5	35	#else
e62b5b13	36	#define D(x)
d12d51d5 AL	37	#define D_LOG(...) do { } while (0)
d12d51d5 AL	38	#endif
e62b5b13	39
81fdc5f8 TS	40	#if defined(CONFIG_USER_ONLY)
81fdc5f8 TS	41
97a8ea5a	42	void cris_cpu_do_interrupt(CPUState *cs)
81fdc5f8	43	{
97a8ea5a AF	44	CRISCPU *cpu = CRIS_CPU(cs);
	45	CPUCRISState *env = &cpu->env;
	46
27103424	47	cs->exception_index = -1;
21317bc2	48	env->pregs[PR_ERP] = env->pc;
81fdc5f8 TS	49	}
81fdc5f8 TS	50
b21bfeea AF	51	void crisv10_cpu_do_interrupt(CPUState *cs)
	52	{
	53	cris_cpu_do_interrupt(cs);
	54	}
	55
98670d47	56	int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
97b348e7	57	int mmu_idx)
81fdc5f8	58	{
7510454e	59	CRISCPU *cpu = CRIS_CPU(cs);
878096ee	60
27103424	61	cs->exception_index = 0xaa;
7510454e AF	62	cpu->env.pregs[PR_EDA] = address;
7510454e AF	63	cpu_dump_state(cs, stderr, fprintf, 0);
21317bc2	64	return 1;
81fdc5f8 TS	65	}
81fdc5f8 TS	66
81fdc5f8 TS	67	#else /* !CONFIG_USER_ONLY */
81fdc5f8 TS	68
e62b5b13	69
a1170bfd	70	static void cris_shift_ccs(CPUCRISState *env)
e62b5b13	71	{
21317bc2 AF	72	uint32_t ccs;
	73	/* Apply the ccs shift. */
	74	ccs = env->pregs[PR_CCS];
	75	ccs = ((ccs & 0xc0000000) \| ((ccs << 12) >> 2)) & ~0x3ff;
	76	env->pregs[PR_CCS] = ccs;
e62b5b13 EI	77	}
e62b5b13 EI	78
98670d47	79	int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
21317bc2	80	int mmu_idx)
81fdc5f8	81	{
7510454e AF	82	CRISCPU *cpu = CRIS_CPU(cs);
7510454e AF	83	CPUCRISState *env = &cpu->env;
21317bc2 AF	84	struct cris_mmu_result res;
	85	int prot, miss;
	86	int r = -1;
	87	target_ulong phy;
	88
339aaf5b AP	89	qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
339aaf5b AP	90	__func__, address, env->pc, rw);
21317bc2 AF	91	miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
	92	rw, mmu_idx, 0);
	93	if (miss) {
27103424	94	if (cs->exception_index == EXCP_BUSFAULT) {
a47dddd7	95	cpu_abort(cs,
21317bc2	96	"CRIS: Illegal recursive bus fault."
7510454e	97	"addr=%" VADDR_PRIx " rw=%d\n",
21317bc2 AF	98	address, rw);
	99	}
	100
	101	env->pregs[PR_EDA] = address;
27103424	102	cs->exception_index = EXCP_BUSFAULT;
21317bc2 AF	103	env->fault_vector = res.bf_vec;
	104	r = 1;
	105	} else {
	106	/*
	107	* Mask off the cache selection bit. The ETRAX busses do not
	108	* see the top bit.
	109	*/
	110	phy = res.phy & ~0x80000000;
	111	prot = res.prot;
0c591eb0	112	tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
21317bc2 AF	113	prot, mmu_idx, TARGET_PAGE_SIZE);
	114	r = 0;
	115	}
	116	if (r > 0) {
339aaf5b AP	117	qemu_log_mask(CPU_LOG_MMU,
	118	"%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
	119	" pc=%x\n", __func__, r, cs->interrupt_request, address,
	120	res.phy, res.bf_vec, env->pc);
21317bc2 AF	121	}
21317bc2 AF	122	return r;
81fdc5f8 TS	123	}
81fdc5f8 TS	124
b21bfeea	125	void crisv10_cpu_do_interrupt(CPUState *cs)
7a977356	126	{
b21bfeea AF	127	CRISCPU *cpu = CRIS_CPU(cs);
b21bfeea AF	128	CPUCRISState *env = &cpu->env;
21317bc2 AF	129	int ex_vec = -1;
	130
	131	D_LOG("exception index=%d interrupt_req=%d\n",
27103424	132	cs->exception_index,
259186a7	133	cs->interrupt_request);
21317bc2	134
d66433ff EI	135	if (env->dslot) {
d66433ff EI	136	/* CRISv10 never takes interrupts while in a delay-slot. */
a47dddd7	137	cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
d66433ff EI	138	}
d66433ff EI	139
21317bc2	140	assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
27103424	141	switch (cs->exception_index) {
21317bc2 AF	142	case EXCP_BREAK:
	143	/* These exceptions are genereated by the core itself.
	144	ERP should point to the insn following the brk. */
	145	ex_vec = env->trap_vector;
	146	env->pregs[PRV10_BRP] = env->pc;
	147	break;
	148
	149	case EXCP_NMI:
	150	/* NMI is hardwired to vector zero. */
	151	ex_vec = 0;
	152	env->pregs[PR_CCS] &= ~M_FLAG_V10;
	153	env->pregs[PRV10_BRP] = env->pc;
	154	break;
	155
	156	case EXCP_BUSFAULT:
a47dddd7	157	cpu_abort(cs, "Unhandled busfault");
21317bc2 AF	158	break;
	159
	160	default:
	161	/* The interrupt controller gives us the vector. */
	162	ex_vec = env->interrupt_vector;
	163	/* Normal interrupts are taken between
	164	TB's. env->pc is valid here. */
	165	env->pregs[PR_ERP] = env->pc;
	166	break;
	167	}
	168
	169	if (env->pregs[PR_CCS] & U_FLAG) {
	170	/* Swap stack pointers. */
	171	env->pregs[PR_USP] = env->regs[R_SP];
	172	env->regs[R_SP] = env->ksp;
	173	}
	174
	175	/* Now that we are in kernel mode, load the handlers address. */
	176	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	177	env->locked_irq = 1;
	178	env->pregs[PR_CCS] \|= F_FLAG_V10; /* set F. */
	179
	180	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	181	__func__, env->pc, ex_vec,
	182	env->pregs[PR_CCS],
	183	env->pregs[PR_PID],
	184	env->pregs[PR_ERP]);
7a977356 EI	185	}
7a977356 EI	186
97a8ea5a	187	void cris_cpu_do_interrupt(CPUState *cs)
81fdc5f8	188	{
97a8ea5a AF	189	CRISCPU *cpu = CRIS_CPU(cs);
97a8ea5a AF	190	CPUCRISState *env = &cpu->env;
21317bc2 AF	191	int ex_vec = -1;
21317bc2 AF	192
21317bc2	193	D_LOG("exception index=%d interrupt_req=%d\n",
27103424	194	cs->exception_index,
259186a7	195	cs->interrupt_request);
21317bc2	196
27103424	197	switch (cs->exception_index) {
21317bc2 AF	198	case EXCP_BREAK:
	199	/* These exceptions are genereated by the core itself.
	200	ERP should point to the insn following the brk. */
	201	ex_vec = env->trap_vector;
	202	env->pregs[PR_ERP] = env->pc;
	203	break;
	204
	205	case EXCP_NMI:
	206	/* NMI is hardwired to vector zero. */
	207	ex_vec = 0;
	208	env->pregs[PR_CCS] &= ~M_FLAG_V32;
	209	env->pregs[PR_NRP] = env->pc;
	210	break;
	211
	212	case EXCP_BUSFAULT:
	213	ex_vec = env->fault_vector;
	214	env->pregs[PR_ERP] = env->pc;
	215	break;
	216
	217	default:
	218	/* The interrupt controller gives us the vector. */
	219	ex_vec = env->interrupt_vector;
	220	/* Normal interrupts are taken between
	221	TB's. env->pc is valid here. */
	222	env->pregs[PR_ERP] = env->pc;
	223	break;
	224	}
	225
	226	/* Fill in the IDX field. */
	227	env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
	228
	229	if (env->dslot) {
	230	D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
	231	" ERP=%x pid=%x ccs=%x cc=%d %x\n",
	232	ex_vec, env->pc, env->dslot,
	233	env->regs[R_SP],
	234	env->pregs[PR_ERP], env->pregs[PR_PID],
	235	env->pregs[PR_CCS],
	236	env->cc_op, env->cc_mask);
	237	/* We loose the btarget, btaken state here so rexec the
	238	branch. */
	239	env->pregs[PR_ERP] -= env->dslot;
	240	/* Exception starts with dslot cleared. */
	241	env->dslot = 0;
	242	}
7d37435b	243
21317bc2 AF	244	if (env->pregs[PR_CCS] & U_FLAG) {
	245	/* Swap stack pointers. */
	246	env->pregs[PR_USP] = env->regs[R_SP];
	247	env->regs[R_SP] = env->ksp;
	248	}
	249
	250	/* Apply the CRIS CCS shift. Clears U if set. */
	251	cris_shift_ccs(env);
	252
	253	/* Now that we are in kernel mode, load the handlers address.
	254	This load may not fault, real hw leaves that behaviour as
	255	undefined. */
	256	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	257
	258	/* Clear the excption_index to avoid spurios hw_aborts for recursive
	259	bus faults. */
27103424	260	cs->exception_index = -1;
21317bc2 AF	261
	262	D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	263	__func__, env->pc, ex_vec,
	264	env->pregs[PR_CCS],
	265	env->pregs[PR_PID],
	266	env->pregs[PR_ERP]);
81fdc5f8 TS	267	}
81fdc5f8 TS	268
00b941e5	269	hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
81fdc5f8	270	{
00b941e5	271	CRISCPU *cpu = CRIS_CPU(cs);
21317bc2 AF	272	uint32_t phy = addr;
	273	struct cris_mmu_result res;
	274	int miss;
	275
00b941e5	276	miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
21317bc2 AF	277	/* If D TLB misses, try I TLB. */
21317bc2 AF	278	if (miss) {
00b941e5	279	miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
21317bc2 AF	280	}
	281
	282	if (!miss) {
	283	phy = res.phy;
	284	}
	285	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
	286	return phy;
81fdc5f8 TS	287	}
81fdc5f8 TS	288	#endif
5a1f7f44 RH	289
	290	bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	291	{
	292	CPUClass *cc = CPU_GET_CLASS(cs);
	293	CRISCPU *cpu = CRIS_CPU(cs);
	294	CPUCRISState *env = &cpu->env;
	295	bool ret = false;
	296
	297	if (interrupt_request & CPU_INTERRUPT_HARD
	298	&& (env->pregs[PR_CCS] & I_FLAG)
	299	&& !env->locked_irq) {
	300	cs->exception_index = EXCP_IRQ;
	301	cc->do_interrupt(cs);
	302	ret = true;
	303	}
	304	if (interrupt_request & CPU_INTERRUPT_NMI) {
	305	unsigned int m_flag_archval;
	306	if (env->pregs[PR_VR] < 32) {
	307	m_flag_archval = M_FLAG_V10;
	308	} else {
	309	m_flag_archval = M_FLAG_V32;
	310	}
	311	if ((env->pregs[PR_CCS] & m_flag_archval)) {
	312	cs->exception_index = EXCP_NMI;
	313	cc->do_interrupt(cs);
	314	ret = true;
	315	}
	316	}
	317
	318	return ret;
	319	}