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ed69e831 CF |
1 | /* |
2 | * i386 TCG cpu class initialization | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
ed69e831 | 22 | #include "helper-tcg.h" |
f5cc5a5c CF |
23 | #include "qemu/accel.h" |
24 | #include "hw/core/accel-cpu.h" | |
ed69e831 | 25 | |
222f3e6f | 26 | #include "tcg-cpu.h" |
ed69e831 CF |
27 | |
28 | /* Frob eflags into and out of the CPU temporary format. */ | |
29 | ||
30 | static void x86_cpu_exec_enter(CPUState *cs) | |
31 | { | |
32 | X86CPU *cpu = X86_CPU(cs); | |
33 | CPUX86State *env = &cpu->env; | |
34 | ||
35 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
36 | env->df = 1 - (2 * ((env->eflags >> 10) & 1)); | |
37 | CC_OP = CC_OP_EFLAGS; | |
38 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
39 | } | |
40 | ||
41 | static void x86_cpu_exec_exit(CPUState *cs) | |
42 | { | |
43 | X86CPU *cpu = X86_CPU(cs); | |
44 | CPUX86State *env = &cpu->env; | |
45 | ||
46 | env->eflags = cpu_compute_eflags(env); | |
47 | } | |
48 | ||
04a37d4c RH |
49 | static void x86_cpu_synchronize_from_tb(CPUState *cs, |
50 | const TranslationBlock *tb) | |
ed69e831 | 51 | { |
2e3afe8e AJ |
52 | /* The instruction pointer is always up to date with CF_PCREL. */ |
53 | if (!(tb_cflags(tb) & CF_PCREL)) { | |
b77af26e | 54 | CPUX86State *env = cpu_env(cs); |
34a39c24 | 55 | env->eip = tb->pc - tb->cs_base; |
e3a79e0e | 56 | } |
ed69e831 CF |
57 | } |
58 | ||
434382e6 RH |
59 | static void x86_restore_state_to_opc(CPUState *cs, |
60 | const TranslationBlock *tb, | |
61 | const uint64_t *data) | |
62 | { | |
63 | X86CPU *cpu = X86_CPU(cs); | |
64 | CPUX86State *env = &cpu->env; | |
65 | int cc_op = data[1]; | |
66 | ||
2e3afe8e | 67 | if (tb_cflags(tb) & CF_PCREL) { |
434382e6 RH |
68 | env->eip = (env->eip & TARGET_PAGE_MASK) | data[0]; |
69 | } else { | |
70 | env->eip = data[0] - tb->cs_base; | |
71 | } | |
72 | if (cc_op != CC_OP_DYNAMIC) { | |
73 | env->cc_op = cc_op; | |
74 | } | |
75 | } | |
76 | ||
7b9810ea RH |
77 | #ifndef CONFIG_USER_ONLY |
78 | static bool x86_debug_check_breakpoint(CPUState *cs) | |
79 | { | |
80 | X86CPU *cpu = X86_CPU(cs); | |
81 | CPUX86State *env = &cpu->env; | |
82 | ||
83 | /* RF disables all architectural breakpoints. */ | |
84 | return !(env->eflags & RF_MASK); | |
85 | } | |
86 | #endif | |
87 | ||
78271684 CF |
88 | #include "hw/core/tcg-cpu-ops.h" |
89 | ||
11906557 | 90 | static const struct TCGCPUOps x86_tcg_ops = { |
78271684 CF |
91 | .initialize = tcg_x86_init, |
92 | .synchronize_from_tb = x86_cpu_synchronize_from_tb, | |
434382e6 | 93 | .restore_state_to_opc = x86_restore_state_to_opc, |
78271684 CF |
94 | .cpu_exec_enter = x86_cpu_exec_enter, |
95 | .cpu_exec_exit = x86_cpu_exec_exit, | |
12096421 PMD |
96 | #ifdef CONFIG_USER_ONLY |
97 | .fake_user_interrupt = x86_cpu_do_interrupt, | |
f74bd157 | 98 | .record_sigsegv = x86_cpu_record_sigsegv, |
958e1dd1 | 99 | .record_sigbus = x86_cpu_record_sigbus, |
12096421 | 100 | #else |
f74bd157 | 101 | .tlb_fill = x86_cpu_tlb_fill, |
12096421 | 102 | .do_interrupt = x86_cpu_do_interrupt, |
60466472 | 103 | .cpu_exec_interrupt = x86_cpu_exec_interrupt, |
958e1dd1 | 104 | .do_unaligned_access = x86_cpu_do_unaligned_access, |
78271684 | 105 | .debug_excp_handler = breakpoint_handler, |
7b9810ea | 106 | .debug_check_breakpoint = x86_debug_check_breakpoint, |
78271684 CF |
107 | #endif /* !CONFIG_USER_ONLY */ |
108 | }; | |
109 | ||
cc3f2be6 | 110 | static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) |
ed69e831 | 111 | { |
cc3f2be6 | 112 | /* for x86, all cpus use the same set of operations */ |
78271684 | 113 | cc->tcg_ops = &x86_tcg_ops; |
ed69e831 | 114 | } |
f5cc5a5c | 115 | |
cc3f2be6 CF |
116 | static void tcg_cpu_class_init(CPUClass *cc) |
117 | { | |
118 | cc->init_accel_cpu = tcg_cpu_init_ops; | |
119 | } | |
120 | ||
fea45008 DE |
121 | static void tcg_cpu_xsave_init(void) |
122 | { | |
123 | #define XO(bit, field) \ | |
124 | x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field); | |
125 | ||
126 | XO(XSTATE_FP_BIT, legacy); | |
127 | XO(XSTATE_SSE_BIT, legacy); | |
128 | XO(XSTATE_YMM_BIT, avx_state); | |
129 | XO(XSTATE_BNDREGS_BIT, bndreg_state); | |
130 | XO(XSTATE_BNDCSR_BIT, bndcsr_state); | |
131 | XO(XSTATE_OPMASK_BIT, opmask_state); | |
132 | XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state); | |
133 | XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state); | |
134 | XO(XSTATE_PKRU_BIT, pkru_state); | |
135 | ||
136 | #undef XO | |
137 | } | |
138 | ||
f5cc5a5c | 139 | /* |
5b8978d8 CF |
140 | * TCG-specific defaults that override cpudef models when using TCG. |
141 | * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. | |
f5cc5a5c CF |
142 | */ |
143 | static PropValue tcg_default_props[] = { | |
144 | { "vme", "off" }, | |
145 | { NULL, NULL }, | |
146 | }; | |
147 | ||
148 | static void tcg_cpu_instance_init(CPUState *cs) | |
149 | { | |
150 | X86CPU *cpu = X86_CPU(cs); | |
5b8978d8 CF |
151 | X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); |
152 | ||
153 | if (xcc->model) { | |
154 | /* Special cases not set in the X86CPUDefinition structs: */ | |
155 | x86_cpu_apply_props(cpu, tcg_default_props); | |
156 | } | |
fea45008 DE |
157 | |
158 | tcg_cpu_xsave_init(); | |
f5cc5a5c CF |
159 | } |
160 | ||
161 | static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) | |
162 | { | |
163 | AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); | |
164 | ||
222f3e6f | 165 | #ifndef CONFIG_USER_ONLY |
6294e502 | 166 | acc->cpu_target_realize = tcg_cpu_realizefn; |
222f3e6f PB |
167 | #endif /* CONFIG_USER_ONLY */ |
168 | ||
f5cc5a5c CF |
169 | acc->cpu_class_init = tcg_cpu_class_init; |
170 | acc->cpu_instance_init = tcg_cpu_instance_init; | |
171 | } | |
172 | static const TypeInfo tcg_cpu_accel_type_info = { | |
173 | .name = ACCEL_CPU_NAME("tcg"), | |
174 | ||
175 | .parent = TYPE_ACCEL_CPU, | |
176 | .class_init = tcg_cpu_accel_class_init, | |
177 | .abstract = true, | |
178 | }; | |
179 | static void tcg_cpu_accel_register_types(void) | |
180 | { | |
181 | type_register_static(&tcg_cpu_accel_type_info); | |
182 | } | |
183 | type_init(tcg_cpu_accel_register_types); |