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228021f0 SG |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * QEMU LoongArch CPU | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | ||
8 | #include "qemu/osdep.h" | |
9 | #include "qemu/log.h" | |
10 | #include "qemu/qemu-print.h" | |
11 | #include "qapi/error.h" | |
12 | #include "qemu/module.h" | |
13 | #include "sysemu/qtest.h" | |
09b07f28 | 14 | #include "exec/cpu_ldst.h" |
228021f0 | 15 | #include "exec/exec-all.h" |
228021f0 SG |
16 | #include "cpu.h" |
17 | #include "internals.h" | |
18 | #include "fpu/softfloat-helpers.h" | |
398cecb9 | 19 | #include "cpu-csr.h" |
f84a2aac | 20 | #include "sysemu/reset.h" |
e83cf1c1 | 21 | #include "tcg/tcg.h" |
008a3b16 | 22 | #include "vec.h" |
228021f0 SG |
23 | |
24 | const char * const regnames[32] = { | |
25 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
26 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
27 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
28 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
29 | }; | |
30 | ||
31 | const char * const fregnames[32] = { | |
32 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
33 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
34 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
35 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
36 | }; | |
37 | ||
38 | static const char * const excp_names[] = { | |
39 | [EXCCODE_INT] = "Interrupt", | |
40 | [EXCCODE_PIL] = "Page invalid exception for load", | |
41 | [EXCCODE_PIS] = "Page invalid exception for store", | |
42 | [EXCCODE_PIF] = "Page invalid exception for fetch", | |
43 | [EXCCODE_PME] = "Page modified exception", | |
44 | [EXCCODE_PNR] = "Page Not Readable exception", | |
45 | [EXCCODE_PNX] = "Page Not Executable exception", | |
46 | [EXCCODE_PPI] = "Page Privilege error", | |
47 | [EXCCODE_ADEF] = "Address error for instruction fetch", | |
48 | [EXCCODE_ADEM] = "Address error for Memory access", | |
49 | [EXCCODE_SYS] = "Syscall", | |
50 | [EXCCODE_BRK] = "Break", | |
51 | [EXCCODE_INE] = "Instruction Non-Existent", | |
52 | [EXCCODE_IPE] = "Instruction privilege error", | |
2419978c | 53 | [EXCCODE_FPD] = "Floating Point Disabled", |
228021f0 SG |
54 | [EXCCODE_FPE] = "Floating Point Exception", |
55 | [EXCCODE_DBP] = "Debug breakpoint", | |
7fe7eea6 | 56 | [EXCCODE_BCE] = "Bound Check Exception", |
a3f3db5c | 57 | [EXCCODE_SXD] = "128 bit vector instructions Disable exception", |
b8f1bdf3 | 58 | [EXCCODE_ASXD] = "256 bit vector instructions Disable exception", |
228021f0 SG |
59 | }; |
60 | ||
61 | const char *loongarch_exception_name(int32_t exception) | |
62 | { | |
63 | assert(excp_names[exception]); | |
64 | return excp_names[exception]; | |
65 | } | |
66 | ||
67 | void G_NORETURN do_raise_exception(CPULoongArchState *env, | |
68 | uint32_t exception, | |
69 | uintptr_t pc) | |
70 | { | |
71 | CPUState *cs = env_cpu(env); | |
72 | ||
73 | qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", | |
74 | __func__, | |
75 | exception, | |
76 | loongarch_exception_name(exception)); | |
77 | cs->exception_index = exception; | |
78 | ||
79 | cpu_loop_exit_restore(cs, pc); | |
80 | } | |
81 | ||
82 | static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) | |
83 | { | |
84 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
85 | CPULoongArchState *env = &cpu->env; | |
86 | ||
2f6478ff | 87 | set_pc(env, value); |
228021f0 SG |
88 | } |
89 | ||
e4fdf9df RH |
90 | static vaddr loongarch_cpu_get_pc(CPUState *cs) |
91 | { | |
92 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
93 | CPULoongArchState *env = &cpu->env; | |
94 | ||
95 | return env->pc; | |
96 | } | |
97 | ||
0093b9a5 | 98 | #ifndef CONFIG_USER_ONLY |
a8a506c3 XY |
99 | #include "hw/loongarch/virt.h" |
100 | ||
f757a2cd XY |
101 | void loongarch_cpu_set_irq(void *opaque, int irq, int level) |
102 | { | |
103 | LoongArchCPU *cpu = opaque; | |
104 | CPULoongArchState *env = &cpu->env; | |
105 | CPUState *cs = CPU(cpu); | |
106 | ||
107 | if (irq < 0 || irq >= N_IRQS) { | |
108 | return; | |
109 | } | |
110 | ||
111 | env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); | |
112 | ||
113 | if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { | |
114 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
115 | } else { | |
116 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
117 | } | |
118 | } | |
119 | ||
120 | static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) | |
121 | { | |
122 | bool ret = 0; | |
123 | ||
124 | ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && | |
125 | !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
130 | /* Check if there is pending and not masked out interrupt */ | |
131 | static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) | |
132 | { | |
133 | uint32_t pending; | |
134 | uint32_t status; | |
f757a2cd XY |
135 | |
136 | pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); | |
137 | status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); | |
138 | ||
66997c42 | 139 | return (pending & status) != 0; |
f757a2cd XY |
140 | } |
141 | ||
142 | static void loongarch_cpu_do_interrupt(CPUState *cs) | |
143 | { | |
144 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
145 | CPULoongArchState *env = &cpu->env; | |
146 | bool update_badinstr = 1; | |
147 | int cause = -1; | |
148 | const char *name; | |
149 | bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); | |
150 | uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); | |
151 | ||
152 | if (cs->exception_index != EXCCODE_INT) { | |
153 | if (cs->exception_index < 0 || | |
e4ad16f4 | 154 | cs->exception_index >= ARRAY_SIZE(excp_names)) { |
f757a2cd XY |
155 | name = "unknown"; |
156 | } else { | |
157 | name = excp_names[cs->exception_index]; | |
158 | } | |
159 | ||
160 | qemu_log_mask(CPU_LOG_INT, | |
161 | "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
162 | " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, | |
163 | env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); | |
164 | } | |
165 | ||
166 | switch (cs->exception_index) { | |
167 | case EXCCODE_DBP: | |
168 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); | |
169 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); | |
170 | goto set_DERA; | |
171 | set_DERA: | |
172 | env->CSR_DERA = env->pc; | |
173 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); | |
2f6478ff | 174 | set_pc(env, env->CSR_EENTRY + 0x480); |
f757a2cd XY |
175 | break; |
176 | case EXCCODE_INT: | |
177 | if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { | |
178 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); | |
179 | goto set_DERA; | |
180 | } | |
181 | QEMU_FALLTHROUGH; | |
182 | case EXCCODE_PIF: | |
8752b130 | 183 | case EXCCODE_ADEF: |
f757a2cd XY |
184 | cause = cs->exception_index; |
185 | update_badinstr = 0; | |
186 | break; | |
f757a2cd XY |
187 | case EXCCODE_SYS: |
188 | case EXCCODE_BRK: | |
7d552f0e SG |
189 | case EXCCODE_INE: |
190 | case EXCCODE_IPE: | |
2419978c | 191 | case EXCCODE_FPD: |
7d552f0e | 192 | case EXCCODE_FPE: |
a3f3db5c | 193 | case EXCCODE_SXD: |
b8f1bdf3 | 194 | case EXCCODE_ASXD: |
7d552f0e SG |
195 | env->CSR_BADV = env->pc; |
196 | QEMU_FALLTHROUGH; | |
2e2ca3c8 | 197 | case EXCCODE_BCE: |
7d552f0e | 198 | case EXCCODE_ADEM: |
f757a2cd XY |
199 | case EXCCODE_PIL: |
200 | case EXCCODE_PIS: | |
201 | case EXCCODE_PME: | |
202 | case EXCCODE_PNR: | |
203 | case EXCCODE_PNX: | |
204 | case EXCCODE_PPI: | |
f757a2cd XY |
205 | cause = cs->exception_index; |
206 | break; | |
207 | default: | |
e4ad16f4 XY |
208 | qemu_log("Error: exception(%d) has not been supported\n", |
209 | cs->exception_index); | |
f757a2cd XY |
210 | abort(); |
211 | } | |
212 | ||
213 | if (update_badinstr) { | |
214 | env->CSR_BADI = cpu_ldl_code(env, env->pc); | |
215 | } | |
216 | ||
217 | /* Save PLV and IE */ | |
218 | if (tlbfill) { | |
219 | env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, | |
220 | FIELD_EX64(env->CSR_CRMD, | |
221 | CSR_CRMD, PLV)); | |
222 | env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, | |
223 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); | |
224 | /* set the DA mode */ | |
225 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); | |
226 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); | |
227 | env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, | |
228 | PC, (env->pc >> 2)); | |
229 | } else { | |
a6b129c8 SG |
230 | env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, |
231 | EXCODE_MCODE(cause)); | |
232 | env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, | |
233 | EXCODE_SUBCODE(cause)); | |
f757a2cd XY |
234 | env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, |
235 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); | |
236 | env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, | |
237 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); | |
238 | env->CSR_ERA = env->pc; | |
239 | } | |
240 | ||
241 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); | |
242 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); | |
243 | ||
46233676 XY |
244 | if (vec_size) { |
245 | vec_size = (1 << vec_size) * 4; | |
246 | } | |
247 | ||
f757a2cd XY |
248 | if (cs->exception_index == EXCCODE_INT) { |
249 | /* Interrupt */ | |
250 | uint32_t vector = 0; | |
251 | uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); | |
252 | pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); | |
253 | ||
254 | /* Find the highest-priority interrupt. */ | |
255 | vector = 31 - clz32(pending); | |
2f6478ff JC |
256 | set_pc(env, env->CSR_EENTRY + \ |
257 | (EXCCODE_EXTERNAL_INT + vector) * vec_size); | |
f757a2cd XY |
258 | qemu_log_mask(CPU_LOG_INT, |
259 | "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
260 | " cause %d\n" " A " TARGET_FMT_lx " D " | |
261 | TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" | |
262 | TARGET_FMT_lx "\n", | |
263 | __func__, env->pc, env->CSR_ERA, | |
264 | cause, env->CSR_BADV, env->CSR_DERA, vector, | |
265 | env->CSR_ECFG, env->CSR_ESTAT); | |
266 | } else { | |
267 | if (tlbfill) { | |
2f6478ff | 268 | set_pc(env, env->CSR_TLBRENTRY); |
f757a2cd | 269 | } else { |
2f6478ff | 270 | set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); |
f757a2cd XY |
271 | } |
272 | qemu_log_mask(CPU_LOG_INT, | |
273 | "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
274 | " cause %d%s\n, ESTAT " TARGET_FMT_lx | |
275 | " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx | |
276 | "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu | |
277 | " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, | |
278 | tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, | |
279 | cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, | |
280 | env->CSR_ECFG, | |
281 | tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, | |
282 | env->CSR_BADI, env->gpr[11], cs->cpu_index, | |
283 | env->CSR_ASID); | |
284 | } | |
285 | cs->exception_index = -1; | |
286 | } | |
287 | ||
288 | static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
289 | vaddr addr, unsigned size, | |
290 | MMUAccessType access_type, | |
291 | int mmu_idx, MemTxAttrs attrs, | |
292 | MemTxResult response, | |
293 | uintptr_t retaddr) | |
294 | { | |
295 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
296 | CPULoongArchState *env = &cpu->env; | |
297 | ||
298 | if (access_type == MMU_INST_FETCH) { | |
299 | do_raise_exception(env, EXCCODE_ADEF, retaddr); | |
300 | } else { | |
301 | do_raise_exception(env, EXCCODE_ADEM, retaddr); | |
302 | } | |
303 | } | |
304 | ||
305 | static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
306 | { | |
307 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
308 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
309 | CPULoongArchState *env = &cpu->env; | |
310 | ||
311 | if (cpu_loongarch_hw_interrupts_enabled(env) && | |
312 | cpu_loongarch_hw_interrupts_pending(env)) { | |
313 | /* Raise it */ | |
314 | cs->exception_index = EXCCODE_INT; | |
315 | loongarch_cpu_do_interrupt(cs); | |
316 | return true; | |
317 | } | |
318 | } | |
319 | return false; | |
320 | } | |
0093b9a5 | 321 | #endif |
f757a2cd | 322 | |
228021f0 SG |
323 | #ifdef CONFIG_TCG |
324 | static void loongarch_cpu_synchronize_from_tb(CPUState *cs, | |
325 | const TranslationBlock *tb) | |
326 | { | |
327 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
328 | CPULoongArchState *env = &cpu->env; | |
329 | ||
e83cf1c1 | 330 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
2f6478ff | 331 | set_pc(env, tb->pc); |
228021f0 | 332 | } |
ab27940f RH |
333 | |
334 | static void loongarch_restore_state_to_opc(CPUState *cs, | |
335 | const TranslationBlock *tb, | |
336 | const uint64_t *data) | |
337 | { | |
338 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
339 | CPULoongArchState *env = &cpu->env; | |
340 | ||
2f6478ff | 341 | set_pc(env, data[0]); |
ab27940f | 342 | } |
228021f0 SG |
343 | #endif /* CONFIG_TCG */ |
344 | ||
f757a2cd XY |
345 | static bool loongarch_cpu_has_work(CPUState *cs) |
346 | { | |
0093b9a5 SG |
347 | #ifdef CONFIG_USER_ONLY |
348 | return true; | |
349 | #else | |
f757a2cd XY |
350 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); |
351 | CPULoongArchState *env = &cpu->env; | |
352 | bool has_work = false; | |
353 | ||
354 | if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
355 | cpu_loongarch_hw_interrupts_pending(env)) { | |
356 | has_work = true; | |
357 | } | |
358 | ||
359 | return has_work; | |
0093b9a5 | 360 | #endif |
f757a2cd XY |
361 | } |
362 | ||
228021f0 SG |
363 | static void loongarch_la464_initfn(Object *obj) |
364 | { | |
365 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | |
366 | CPULoongArchState *env = &cpu->env; | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < 21; i++) { | |
370 | env->cpucfg[i] = 0x0; | |
371 | } | |
372 | ||
fda3f15b | 373 | cpu->dtb_compatible = "loongarch,Loongson-3A5000"; |
228021f0 SG |
374 | env->cpucfg[0] = 0x14c010; /* PRID */ |
375 | ||
376 | uint32_t data = 0; | |
377 | data = FIELD_DP32(data, CPUCFG1, ARCH, 2); | |
378 | data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); | |
379 | data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); | |
380 | data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); | |
381 | data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); | |
382 | data = FIELD_DP32(data, CPUCFG1, UAL, 1); | |
383 | data = FIELD_DP32(data, CPUCFG1, RI, 1); | |
384 | data = FIELD_DP32(data, CPUCFG1, EP, 1); | |
385 | data = FIELD_DP32(data, CPUCFG1, RPLV, 1); | |
386 | data = FIELD_DP32(data, CPUCFG1, HP, 1); | |
387 | data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); | |
388 | env->cpucfg[1] = data; | |
389 | ||
390 | data = 0; | |
391 | data = FIELD_DP32(data, CPUCFG2, FP, 1); | |
392 | data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); | |
393 | data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); | |
394 | data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); | |
c6c2fec4 | 395 | data = FIELD_DP32(data, CPUCFG2, LSX, 1), |
2cd81e37 | 396 | data = FIELD_DP32(data, CPUCFG2, LASX, 1), |
228021f0 SG |
397 | data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); |
398 | data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); | |
0b360727 | 399 | data = FIELD_DP32(data, CPUCFG2, LSPW, 1); |
228021f0 SG |
400 | data = FIELD_DP32(data, CPUCFG2, LAM, 1); |
401 | env->cpucfg[2] = data; | |
402 | ||
403 | env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ | |
404 | ||
405 | data = 0; | |
406 | data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); | |
407 | data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); | |
408 | env->cpucfg[5] = data; | |
409 | ||
410 | data = 0; | |
411 | data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); | |
412 | data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); | |
413 | data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); | |
414 | data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); | |
415 | data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); | |
416 | data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); | |
417 | data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); | |
418 | data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); | |
419 | env->cpucfg[16] = data; | |
420 | ||
421 | data = 0; | |
422 | data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); | |
423 | data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); | |
424 | data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); | |
425 | env->cpucfg[17] = data; | |
426 | ||
427 | data = 0; | |
428 | data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); | |
429 | data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); | |
430 | data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); | |
431 | env->cpucfg[18] = data; | |
432 | ||
433 | data = 0; | |
434 | data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); | |
435 | data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); | |
436 | data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); | |
437 | env->cpucfg[19] = data; | |
438 | ||
439 | data = 0; | |
440 | data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); | |
441 | data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); | |
fa90456f | 442 | data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); |
228021f0 | 443 | env->cpucfg[20] = data; |
398cecb9 XY |
444 | |
445 | env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); | |
228021f0 SG |
446 | } |
447 | ||
bb8710cf JC |
448 | static void loongarch_la132_initfn(Object *obj) |
449 | { | |
450 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | |
451 | CPULoongArchState *env = &cpu->env; | |
452 | ||
453 | int i; | |
454 | ||
455 | for (i = 0; i < 21; i++) { | |
456 | env->cpucfg[i] = 0x0; | |
457 | } | |
458 | ||
459 | cpu->dtb_compatible = "loongarch,Loongson-1C103"; | |
460 | env->cpucfg[0] = 0x148042; /* PRID */ | |
461 | ||
462 | uint32_t data = 0; | |
463 | data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ | |
464 | data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); | |
465 | data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); | |
466 | data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ | |
467 | data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ | |
468 | data = FIELD_DP32(data, CPUCFG1, UAL, 1); | |
469 | data = FIELD_DP32(data, CPUCFG1, RI, 0); | |
470 | data = FIELD_DP32(data, CPUCFG1, EP, 0); | |
471 | data = FIELD_DP32(data, CPUCFG1, RPLV, 0); | |
472 | data = FIELD_DP32(data, CPUCFG1, HP, 1); | |
473 | data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); | |
474 | env->cpucfg[1] = data; | |
475 | } | |
476 | ||
228021f0 SG |
477 | static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) |
478 | { | |
479 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); | |
480 | ||
481 | qemu_printf("%s\n", typename); | |
482 | } | |
483 | ||
484 | void loongarch_cpu_list(void) | |
485 | { | |
486 | GSList *list; | |
487 | list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); | |
488 | g_slist_foreach(list, loongarch_cpu_list_entry, NULL); | |
489 | g_slist_free(list); | |
490 | } | |
491 | ||
f78b49ae | 492 | static void loongarch_cpu_reset_hold(Object *obj) |
228021f0 | 493 | { |
f78b49ae | 494 | CPUState *cs = CPU(obj); |
228021f0 SG |
495 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); |
496 | LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); | |
497 | CPULoongArchState *env = &cpu->env; | |
498 | ||
f78b49ae PM |
499 | if (lacc->parent_phases.hold) { |
500 | lacc->parent_phases.hold(obj); | |
501 | } | |
228021f0 SG |
502 | |
503 | env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; | |
504 | env->fcsr0 = 0x0; | |
505 | ||
398cecb9 XY |
506 | int n; |
507 | /* Set csr registers value after reset */ | |
508 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); | |
509 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); | |
510 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); | |
511 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); | |
512 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); | |
513 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); | |
514 | ||
515 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); | |
516 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); | |
517 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); | |
518 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); | |
519 | ||
520 | env->CSR_MISC = 0; | |
521 | ||
522 | env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); | |
523 | env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); | |
524 | ||
525 | env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); | |
526 | env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); | |
527 | env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); | |
528 | env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); | |
529 | env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); | |
530 | env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); | |
531 | ||
532 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); | |
533 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); | |
534 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); | |
535 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); | |
536 | ||
537 | for (n = 0; n < 4; n++) { | |
538 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); | |
539 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); | |
540 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); | |
541 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); | |
542 | } | |
543 | ||
0093b9a5 | 544 | #ifndef CONFIG_USER_ONLY |
f757a2cd | 545 | env->pc = 0x1c000000; |
3517fb72 | 546 | memset(env->tlb, 0, sizeof(env->tlb)); |
0093b9a5 | 547 | #endif |
f757a2cd | 548 | |
d578ca6c | 549 | restore_fp_status(env); |
228021f0 SG |
550 | cs->exception_index = -1; |
551 | } | |
552 | ||
553 | static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
554 | { | |
555 | info->print_insn = print_insn_loongarch; | |
556 | } | |
557 | ||
558 | static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) | |
559 | { | |
560 | CPUState *cs = CPU(dev); | |
561 | LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); | |
562 | Error *local_err = NULL; | |
563 | ||
564 | cpu_exec_realizefn(cs, &local_err); | |
565 | if (local_err != NULL) { | |
566 | error_propagate(errp, local_err); | |
567 | return; | |
568 | } | |
569 | ||
ca61e750 XY |
570 | loongarch_cpu_register_gdb_regs_for_features(cs); |
571 | ||
228021f0 SG |
572 | cpu_reset(cs); |
573 | qemu_init_vcpu(cs); | |
574 | ||
575 | lacc->parent_realize(dev, errp); | |
576 | } | |
577 | ||
0093b9a5 | 578 | #ifndef CONFIG_USER_ONLY |
f84a2aac XY |
579 | static void loongarch_qemu_write(void *opaque, hwaddr addr, |
580 | uint64_t val, unsigned size) | |
581 | { | |
3da4004c PMD |
582 | qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", |
583 | __func__, addr); | |
f84a2aac XY |
584 | } |
585 | ||
586 | static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) | |
587 | { | |
588 | switch (addr) { | |
c77432d0 SG |
589 | case VERSION_REG: |
590 | return 0x11ULL; | |
f84a2aac XY |
591 | case FEATURE_REG: |
592 | return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | | |
593 | 1ULL << IOCSRF_CSRIPI; | |
594 | case VENDOR_REG: | |
595 | return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ | |
596 | case CPUNAME_REG: | |
597 | return 0x303030354133ULL; /* "3A5000" */ | |
598 | case MISC_FUNC_REG: | |
599 | return 1ULL << IOCSRM_EXTIOI_EN; | |
600 | } | |
601 | return 0ULL; | |
602 | } | |
603 | ||
604 | static const MemoryRegionOps loongarch_qemu_ops = { | |
605 | .read = loongarch_qemu_read, | |
606 | .write = loongarch_qemu_write, | |
607 | .endianness = DEVICE_LITTLE_ENDIAN, | |
608 | .valid = { | |
609 | .min_access_size = 4, | |
610 | .max_access_size = 8, | |
611 | }, | |
612 | .impl = { | |
613 | .min_access_size = 8, | |
614 | .max_access_size = 8, | |
615 | }, | |
616 | }; | |
0093b9a5 | 617 | #endif |
f84a2aac | 618 | |
228021f0 SG |
619 | static void loongarch_cpu_init(Object *obj) |
620 | { | |
621 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | |
622 | ||
623 | cpu_set_cpustate_pointers(cpu); | |
0093b9a5 SG |
624 | |
625 | #ifndef CONFIG_USER_ONLY | |
626 | CPULoongArchState *env = &cpu->env; | |
f757a2cd | 627 | qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); |
dd615fa4 XY |
628 | timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, |
629 | &loongarch_constant_timer_cb, cpu); | |
f84a2aac XY |
630 | memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, |
631 | env, "iocsr", UINT64_MAX); | |
632 | address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); | |
633 | memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, | |
634 | NULL, "iocsr_misc", 0x428); | |
635 | memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); | |
0093b9a5 | 636 | #endif |
228021f0 SG |
637 | } |
638 | ||
639 | static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) | |
640 | { | |
641 | ObjectClass *oc; | |
228021f0 | 642 | |
c254f7af XY |
643 | oc = object_class_by_name(cpu_model); |
644 | if (!oc) { | |
e83cf1c1 | 645 | g_autofree char *typename |
c254f7af XY |
646 | = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); |
647 | oc = object_class_by_name(typename); | |
648 | if (!oc) { | |
649 | return NULL; | |
650 | } | |
651 | } | |
652 | ||
653 | if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) | |
654 | && !object_class_is_abstract(oc)) { | |
655 | return oc; | |
656 | } | |
657 | return NULL; | |
228021f0 SG |
658 | } |
659 | ||
660 | void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
661 | { | |
662 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
663 | CPULoongArchState *env = &cpu->env; | |
664 | int i; | |
665 | ||
666 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | |
667 | qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, | |
668 | get_float_exception_flags(&env->fp_status)); | |
669 | ||
670 | /* gpr */ | |
671 | for (i = 0; i < 32; i++) { | |
672 | if ((i & 3) == 0) { | |
673 | qemu_fprintf(f, " GPR%02d:", i); | |
674 | } | |
675 | qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); | |
676 | if ((i & 3) == 3) { | |
677 | qemu_fprintf(f, "\n"); | |
678 | } | |
679 | } | |
680 | ||
7e1c521e XY |
681 | qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); |
682 | qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); | |
683 | qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); | |
684 | qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); | |
685 | qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); | |
686 | qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); | |
687 | qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); | |
688 | qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); | |
689 | qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," | |
690 | " PRCFG3=%016" PRIx64 "\n", | |
691 | env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); | |
692 | qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); | |
693 | qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); | |
694 | qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); | |
695 | ||
228021f0 SG |
696 | /* fpr */ |
697 | if (flags & CPU_DUMP_FPU) { | |
698 | for (i = 0; i < 32; i++) { | |
16f5396c | 699 | qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); |
228021f0 SG |
700 | if ((i & 3) == 3) { |
701 | qemu_fprintf(f, "\n"); | |
702 | } | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
707 | #ifdef CONFIG_TCG | |
708 | #include "hw/core/tcg-cpu-ops.h" | |
709 | ||
710 | static struct TCGCPUOps loongarch_tcg_ops = { | |
711 | .initialize = loongarch_translate_init, | |
712 | .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, | |
ab27940f | 713 | .restore_state_to_opc = loongarch_restore_state_to_opc, |
7e1c521e | 714 | |
0093b9a5 | 715 | #ifndef CONFIG_USER_ONLY |
7e1c521e | 716 | .tlb_fill = loongarch_cpu_tlb_fill, |
f757a2cd XY |
717 | .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, |
718 | .do_interrupt = loongarch_cpu_do_interrupt, | |
719 | .do_transaction_failed = loongarch_cpu_do_transaction_failed, | |
0093b9a5 | 720 | #endif |
228021f0 SG |
721 | }; |
722 | #endif /* CONFIG_TCG */ | |
723 | ||
0093b9a5 | 724 | #ifndef CONFIG_USER_ONLY |
7e1c521e XY |
725 | #include "hw/core/sysemu-cpu-ops.h" |
726 | ||
727 | static const struct SysemuCPUOps loongarch_sysemu_ops = { | |
728 | .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, | |
729 | }; | |
14f21f67 BM |
730 | |
731 | static int64_t loongarch_cpu_get_arch_id(CPUState *cs) | |
732 | { | |
733 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
734 | ||
735 | return cpu->phy_id; | |
736 | } | |
0093b9a5 | 737 | #endif |
7e1c521e | 738 | |
228021f0 SG |
739 | static void loongarch_cpu_class_init(ObjectClass *c, void *data) |
740 | { | |
741 | LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); | |
742 | CPUClass *cc = CPU_CLASS(c); | |
743 | DeviceClass *dc = DEVICE_CLASS(c); | |
f78b49ae | 744 | ResettableClass *rc = RESETTABLE_CLASS(c); |
228021f0 SG |
745 | |
746 | device_class_set_parent_realize(dc, loongarch_cpu_realizefn, | |
747 | &lacc->parent_realize); | |
f78b49ae PM |
748 | resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, |
749 | &lacc->parent_phases); | |
228021f0 SG |
750 | |
751 | cc->class_by_name = loongarch_cpu_class_by_name; | |
f757a2cd | 752 | cc->has_work = loongarch_cpu_has_work; |
228021f0 SG |
753 | cc->dump_state = loongarch_cpu_dump_state; |
754 | cc->set_pc = loongarch_cpu_set_pc; | |
e4fdf9df | 755 | cc->get_pc = loongarch_cpu_get_pc; |
0093b9a5 | 756 | #ifndef CONFIG_USER_ONLY |
14f21f67 | 757 | cc->get_arch_id = loongarch_cpu_get_arch_id; |
67ebd42a | 758 | dc->vmsd = &vmstate_loongarch_cpu; |
7e1c521e | 759 | cc->sysemu_ops = &loongarch_sysemu_ops; |
0093b9a5 | 760 | #endif |
228021f0 | 761 | cc->disas_set_info = loongarch_cpu_disas_set_info; |
ca61e750 XY |
762 | cc->gdb_read_register = loongarch_cpu_gdb_read_register; |
763 | cc->gdb_write_register = loongarch_cpu_gdb_write_register; | |
ca61e750 XY |
764 | cc->gdb_stop_before_watchpoint = true; |
765 | ||
228021f0 SG |
766 | #ifdef CONFIG_TCG |
767 | cc->tcg_ops = &loongarch_tcg_ops; | |
768 | #endif | |
769 | } | |
770 | ||
ebda3036 JC |
771 | static gchar *loongarch32_gdb_arch_name(CPUState *cs) |
772 | { | |
773 | return g_strdup("loongarch32"); | |
774 | } | |
775 | ||
6cbba3e9 JC |
776 | static void loongarch32_cpu_class_init(ObjectClass *c, void *data) |
777 | { | |
ebda3036 JC |
778 | CPUClass *cc = CPU_CLASS(c); |
779 | ||
780 | cc->gdb_num_core_regs = 35; | |
781 | cc->gdb_core_xml_file = "loongarch-base32.xml"; | |
782 | cc->gdb_arch_name = loongarch32_gdb_arch_name; | |
6cbba3e9 JC |
783 | } |
784 | ||
e389358e PMD |
785 | static gchar *loongarch64_gdb_arch_name(CPUState *cs) |
786 | { | |
787 | return g_strdup("loongarch64"); | |
788 | } | |
789 | ||
790 | static void loongarch64_cpu_class_init(ObjectClass *c, void *data) | |
791 | { | |
792 | CPUClass *cc = CPU_CLASS(c); | |
793 | ||
794 | cc->gdb_num_core_regs = 35; | |
795 | cc->gdb_core_xml_file = "loongarch-base64.xml"; | |
796 | cc->gdb_arch_name = loongarch64_gdb_arch_name; | |
797 | } | |
798 | ||
146f2354 | 799 | #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ |
228021f0 | 800 | { \ |
146f2354 | 801 | .parent = TYPE_LOONGARCH##size##_CPU, \ |
228021f0 SG |
802 | .instance_init = initfn, \ |
803 | .name = LOONGARCH_CPU_TYPE_NAME(model), \ | |
804 | } | |
805 | ||
806 | static const TypeInfo loongarch_cpu_type_infos[] = { | |
807 | { | |
808 | .name = TYPE_LOONGARCH_CPU, | |
809 | .parent = TYPE_CPU, | |
810 | .instance_size = sizeof(LoongArchCPU), | |
811 | .instance_init = loongarch_cpu_init, | |
812 | ||
813 | .abstract = true, | |
814 | .class_size = sizeof(LoongArchCPUClass), | |
815 | .class_init = loongarch_cpu_class_init, | |
816 | }, | |
6cbba3e9 JC |
817 | { |
818 | .name = TYPE_LOONGARCH32_CPU, | |
819 | .parent = TYPE_LOONGARCH_CPU, | |
820 | ||
821 | .abstract = true, | |
822 | .class_init = loongarch32_cpu_class_init, | |
823 | }, | |
146f2354 PMD |
824 | { |
825 | .name = TYPE_LOONGARCH64_CPU, | |
826 | .parent = TYPE_LOONGARCH_CPU, | |
827 | ||
828 | .abstract = true, | |
e389358e | 829 | .class_init = loongarch64_cpu_class_init, |
146f2354 PMD |
830 | }, |
831 | DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), | |
bb8710cf | 832 | DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), |
228021f0 SG |
833 | }; |
834 | ||
835 | DEFINE_TYPES(loongarch_cpu_type_infos) |