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Commit | Line | Data |
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228021f0 SG |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * QEMU LoongArch CPU | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | ||
8 | #include "qemu/osdep.h" | |
9 | #include "qemu/log.h" | |
10 | #include "qemu/qemu-print.h" | |
11 | #include "qapi/error.h" | |
12 | #include "qemu/module.h" | |
13 | #include "sysemu/qtest.h" | |
14 | #include "exec/exec-all.h" | |
228021f0 SG |
15 | #include "cpu.h" |
16 | #include "internals.h" | |
17 | #include "fpu/softfloat-helpers.h" | |
398cecb9 | 18 | #include "cpu-csr.h" |
f84a2aac | 19 | #include "sysemu/reset.h" |
228021f0 SG |
20 | |
21 | const char * const regnames[32] = { | |
22 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
23 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
24 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
25 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
26 | }; | |
27 | ||
28 | const char * const fregnames[32] = { | |
29 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
30 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
31 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
32 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
33 | }; | |
34 | ||
35 | static const char * const excp_names[] = { | |
36 | [EXCCODE_INT] = "Interrupt", | |
37 | [EXCCODE_PIL] = "Page invalid exception for load", | |
38 | [EXCCODE_PIS] = "Page invalid exception for store", | |
39 | [EXCCODE_PIF] = "Page invalid exception for fetch", | |
40 | [EXCCODE_PME] = "Page modified exception", | |
41 | [EXCCODE_PNR] = "Page Not Readable exception", | |
42 | [EXCCODE_PNX] = "Page Not Executable exception", | |
43 | [EXCCODE_PPI] = "Page Privilege error", | |
44 | [EXCCODE_ADEF] = "Address error for instruction fetch", | |
45 | [EXCCODE_ADEM] = "Address error for Memory access", | |
46 | [EXCCODE_SYS] = "Syscall", | |
47 | [EXCCODE_BRK] = "Break", | |
48 | [EXCCODE_INE] = "Instruction Non-Existent", | |
49 | [EXCCODE_IPE] = "Instruction privilege error", | |
2419978c | 50 | [EXCCODE_FPD] = "Floating Point Disabled", |
228021f0 SG |
51 | [EXCCODE_FPE] = "Floating Point Exception", |
52 | [EXCCODE_DBP] = "Debug breakpoint", | |
7fe7eea6 | 53 | [EXCCODE_BCE] = "Bound Check Exception", |
228021f0 SG |
54 | }; |
55 | ||
56 | const char *loongarch_exception_name(int32_t exception) | |
57 | { | |
58 | assert(excp_names[exception]); | |
59 | return excp_names[exception]; | |
60 | } | |
61 | ||
62 | void G_NORETURN do_raise_exception(CPULoongArchState *env, | |
63 | uint32_t exception, | |
64 | uintptr_t pc) | |
65 | { | |
66 | CPUState *cs = env_cpu(env); | |
67 | ||
68 | qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", | |
69 | __func__, | |
70 | exception, | |
71 | loongarch_exception_name(exception)); | |
72 | cs->exception_index = exception; | |
73 | ||
74 | cpu_loop_exit_restore(cs, pc); | |
75 | } | |
76 | ||
77 | static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) | |
78 | { | |
79 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
80 | CPULoongArchState *env = &cpu->env; | |
81 | ||
82 | env->pc = value; | |
83 | } | |
84 | ||
e4fdf9df RH |
85 | static vaddr loongarch_cpu_get_pc(CPUState *cs) |
86 | { | |
87 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
88 | CPULoongArchState *env = &cpu->env; | |
89 | ||
90 | return env->pc; | |
91 | } | |
92 | ||
0093b9a5 | 93 | #ifndef CONFIG_USER_ONLY |
a8a506c3 XY |
94 | #include "hw/loongarch/virt.h" |
95 | ||
f757a2cd XY |
96 | void loongarch_cpu_set_irq(void *opaque, int irq, int level) |
97 | { | |
98 | LoongArchCPU *cpu = opaque; | |
99 | CPULoongArchState *env = &cpu->env; | |
100 | CPUState *cs = CPU(cpu); | |
101 | ||
102 | if (irq < 0 || irq >= N_IRQS) { | |
103 | return; | |
104 | } | |
105 | ||
106 | env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); | |
107 | ||
108 | if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { | |
109 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
110 | } else { | |
111 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
112 | } | |
113 | } | |
114 | ||
115 | static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) | |
116 | { | |
117 | bool ret = 0; | |
118 | ||
119 | ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && | |
120 | !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); | |
121 | ||
122 | return ret; | |
123 | } | |
124 | ||
125 | /* Check if there is pending and not masked out interrupt */ | |
126 | static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) | |
127 | { | |
128 | uint32_t pending; | |
129 | uint32_t status; | |
f757a2cd XY |
130 | |
131 | pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); | |
132 | status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); | |
133 | ||
66997c42 | 134 | return (pending & status) != 0; |
f757a2cd XY |
135 | } |
136 | ||
137 | static void loongarch_cpu_do_interrupt(CPUState *cs) | |
138 | { | |
139 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
140 | CPULoongArchState *env = &cpu->env; | |
141 | bool update_badinstr = 1; | |
142 | int cause = -1; | |
143 | const char *name; | |
144 | bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); | |
145 | uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); | |
146 | ||
147 | if (cs->exception_index != EXCCODE_INT) { | |
148 | if (cs->exception_index < 0 || | |
e4ad16f4 | 149 | cs->exception_index >= ARRAY_SIZE(excp_names)) { |
f757a2cd XY |
150 | name = "unknown"; |
151 | } else { | |
152 | name = excp_names[cs->exception_index]; | |
153 | } | |
154 | ||
155 | qemu_log_mask(CPU_LOG_INT, | |
156 | "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
157 | " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, | |
158 | env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); | |
159 | } | |
160 | ||
161 | switch (cs->exception_index) { | |
162 | case EXCCODE_DBP: | |
163 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); | |
164 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); | |
165 | goto set_DERA; | |
166 | set_DERA: | |
167 | env->CSR_DERA = env->pc; | |
168 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); | |
169 | env->pc = env->CSR_EENTRY + 0x480; | |
170 | break; | |
171 | case EXCCODE_INT: | |
172 | if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { | |
173 | env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); | |
174 | goto set_DERA; | |
175 | } | |
176 | QEMU_FALLTHROUGH; | |
177 | case EXCCODE_PIF: | |
8752b130 | 178 | case EXCCODE_ADEF: |
f757a2cd XY |
179 | cause = cs->exception_index; |
180 | update_badinstr = 0; | |
181 | break; | |
f757a2cd XY |
182 | case EXCCODE_SYS: |
183 | case EXCCODE_BRK: | |
7d552f0e SG |
184 | case EXCCODE_INE: |
185 | case EXCCODE_IPE: | |
2419978c | 186 | case EXCCODE_FPD: |
7d552f0e | 187 | case EXCCODE_FPE: |
7fe7eea6 | 188 | case EXCCODE_BCE: |
7d552f0e SG |
189 | env->CSR_BADV = env->pc; |
190 | QEMU_FALLTHROUGH; | |
191 | case EXCCODE_ADEM: | |
f757a2cd XY |
192 | case EXCCODE_PIL: |
193 | case EXCCODE_PIS: | |
194 | case EXCCODE_PME: | |
195 | case EXCCODE_PNR: | |
196 | case EXCCODE_PNX: | |
197 | case EXCCODE_PPI: | |
f757a2cd XY |
198 | cause = cs->exception_index; |
199 | break; | |
200 | default: | |
e4ad16f4 XY |
201 | qemu_log("Error: exception(%d) has not been supported\n", |
202 | cs->exception_index); | |
f757a2cd XY |
203 | abort(); |
204 | } | |
205 | ||
206 | if (update_badinstr) { | |
207 | env->CSR_BADI = cpu_ldl_code(env, env->pc); | |
208 | } | |
209 | ||
210 | /* Save PLV and IE */ | |
211 | if (tlbfill) { | |
212 | env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, | |
213 | FIELD_EX64(env->CSR_CRMD, | |
214 | CSR_CRMD, PLV)); | |
215 | env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, | |
216 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); | |
217 | /* set the DA mode */ | |
218 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); | |
219 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); | |
220 | env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, | |
221 | PC, (env->pc >> 2)); | |
222 | } else { | |
a6b129c8 SG |
223 | env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, |
224 | EXCODE_MCODE(cause)); | |
225 | env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, | |
226 | EXCODE_SUBCODE(cause)); | |
f757a2cd XY |
227 | env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, |
228 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); | |
229 | env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, | |
230 | FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); | |
231 | env->CSR_ERA = env->pc; | |
232 | } | |
233 | ||
234 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); | |
235 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); | |
236 | ||
46233676 XY |
237 | if (vec_size) { |
238 | vec_size = (1 << vec_size) * 4; | |
239 | } | |
240 | ||
f757a2cd XY |
241 | if (cs->exception_index == EXCCODE_INT) { |
242 | /* Interrupt */ | |
243 | uint32_t vector = 0; | |
244 | uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); | |
245 | pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); | |
246 | ||
247 | /* Find the highest-priority interrupt. */ | |
248 | vector = 31 - clz32(pending); | |
249 | env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; | |
250 | qemu_log_mask(CPU_LOG_INT, | |
251 | "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
252 | " cause %d\n" " A " TARGET_FMT_lx " D " | |
253 | TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" | |
254 | TARGET_FMT_lx "\n", | |
255 | __func__, env->pc, env->CSR_ERA, | |
256 | cause, env->CSR_BADV, env->CSR_DERA, vector, | |
257 | env->CSR_ECFG, env->CSR_ESTAT); | |
258 | } else { | |
259 | if (tlbfill) { | |
260 | env->pc = env->CSR_TLBRENTRY; | |
261 | } else { | |
262 | env->pc = env->CSR_EENTRY; | |
a6b129c8 | 263 | env->pc += EXCODE_MCODE(cause) * vec_size; |
f757a2cd XY |
264 | } |
265 | qemu_log_mask(CPU_LOG_INT, | |
266 | "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx | |
267 | " cause %d%s\n, ESTAT " TARGET_FMT_lx | |
268 | " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx | |
269 | "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu | |
270 | " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, | |
271 | tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, | |
272 | cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, | |
273 | env->CSR_ECFG, | |
274 | tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, | |
275 | env->CSR_BADI, env->gpr[11], cs->cpu_index, | |
276 | env->CSR_ASID); | |
277 | } | |
278 | cs->exception_index = -1; | |
279 | } | |
280 | ||
281 | static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
282 | vaddr addr, unsigned size, | |
283 | MMUAccessType access_type, | |
284 | int mmu_idx, MemTxAttrs attrs, | |
285 | MemTxResult response, | |
286 | uintptr_t retaddr) | |
287 | { | |
288 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
289 | CPULoongArchState *env = &cpu->env; | |
290 | ||
291 | if (access_type == MMU_INST_FETCH) { | |
292 | do_raise_exception(env, EXCCODE_ADEF, retaddr); | |
293 | } else { | |
294 | do_raise_exception(env, EXCCODE_ADEM, retaddr); | |
295 | } | |
296 | } | |
297 | ||
298 | static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
299 | { | |
300 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
301 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
302 | CPULoongArchState *env = &cpu->env; | |
303 | ||
304 | if (cpu_loongarch_hw_interrupts_enabled(env) && | |
305 | cpu_loongarch_hw_interrupts_pending(env)) { | |
306 | /* Raise it */ | |
307 | cs->exception_index = EXCCODE_INT; | |
308 | loongarch_cpu_do_interrupt(cs); | |
309 | return true; | |
310 | } | |
311 | } | |
312 | return false; | |
313 | } | |
0093b9a5 | 314 | #endif |
f757a2cd | 315 | |
228021f0 SG |
316 | #ifdef CONFIG_TCG |
317 | static void loongarch_cpu_synchronize_from_tb(CPUState *cs, | |
318 | const TranslationBlock *tb) | |
319 | { | |
320 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
321 | CPULoongArchState *env = &cpu->env; | |
322 | ||
fbf59aad | 323 | env->pc = tb_pc(tb); |
228021f0 | 324 | } |
ab27940f RH |
325 | |
326 | static void loongarch_restore_state_to_opc(CPUState *cs, | |
327 | const TranslationBlock *tb, | |
328 | const uint64_t *data) | |
329 | { | |
330 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
331 | CPULoongArchState *env = &cpu->env; | |
332 | ||
333 | env->pc = data[0]; | |
334 | } | |
228021f0 SG |
335 | #endif /* CONFIG_TCG */ |
336 | ||
f757a2cd XY |
337 | static bool loongarch_cpu_has_work(CPUState *cs) |
338 | { | |
0093b9a5 SG |
339 | #ifdef CONFIG_USER_ONLY |
340 | return true; | |
341 | #else | |
f757a2cd XY |
342 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); |
343 | CPULoongArchState *env = &cpu->env; | |
344 | bool has_work = false; | |
345 | ||
346 | if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
347 | cpu_loongarch_hw_interrupts_pending(env)) { | |
348 | has_work = true; | |
349 | } | |
350 | ||
351 | return has_work; | |
0093b9a5 | 352 | #endif |
f757a2cd XY |
353 | } |
354 | ||
228021f0 SG |
355 | static void loongarch_la464_initfn(Object *obj) |
356 | { | |
357 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | |
358 | CPULoongArchState *env = &cpu->env; | |
359 | int i; | |
360 | ||
361 | for (i = 0; i < 21; i++) { | |
362 | env->cpucfg[i] = 0x0; | |
363 | } | |
364 | ||
fda3f15b | 365 | cpu->dtb_compatible = "loongarch,Loongson-3A5000"; |
228021f0 SG |
366 | env->cpucfg[0] = 0x14c010; /* PRID */ |
367 | ||
368 | uint32_t data = 0; | |
369 | data = FIELD_DP32(data, CPUCFG1, ARCH, 2); | |
370 | data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); | |
371 | data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); | |
372 | data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); | |
373 | data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); | |
374 | data = FIELD_DP32(data, CPUCFG1, UAL, 1); | |
375 | data = FIELD_DP32(data, CPUCFG1, RI, 1); | |
376 | data = FIELD_DP32(data, CPUCFG1, EP, 1); | |
377 | data = FIELD_DP32(data, CPUCFG1, RPLV, 1); | |
378 | data = FIELD_DP32(data, CPUCFG1, HP, 1); | |
379 | data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); | |
380 | env->cpucfg[1] = data; | |
381 | ||
382 | data = 0; | |
383 | data = FIELD_DP32(data, CPUCFG2, FP, 1); | |
384 | data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); | |
385 | data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); | |
386 | data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); | |
387 | data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); | |
388 | data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); | |
389 | data = FIELD_DP32(data, CPUCFG2, LAM, 1); | |
390 | env->cpucfg[2] = data; | |
391 | ||
392 | env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ | |
393 | ||
394 | data = 0; | |
395 | data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); | |
396 | data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); | |
397 | env->cpucfg[5] = data; | |
398 | ||
399 | data = 0; | |
400 | data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); | |
401 | data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); | |
402 | data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); | |
403 | data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); | |
404 | data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); | |
405 | data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); | |
406 | data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); | |
407 | data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); | |
408 | env->cpucfg[16] = data; | |
409 | ||
410 | data = 0; | |
411 | data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); | |
412 | data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); | |
413 | data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); | |
414 | env->cpucfg[17] = data; | |
415 | ||
416 | data = 0; | |
417 | data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); | |
418 | data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); | |
419 | data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); | |
420 | env->cpucfg[18] = data; | |
421 | ||
422 | data = 0; | |
423 | data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); | |
424 | data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); | |
425 | data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); | |
426 | env->cpucfg[19] = data; | |
427 | ||
428 | data = 0; | |
429 | data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); | |
430 | data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); | |
fa90456f | 431 | data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); |
228021f0 | 432 | env->cpucfg[20] = data; |
398cecb9 XY |
433 | |
434 | env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); | |
228021f0 SG |
435 | } |
436 | ||
437 | static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) | |
438 | { | |
439 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); | |
440 | ||
441 | qemu_printf("%s\n", typename); | |
442 | } | |
443 | ||
444 | void loongarch_cpu_list(void) | |
445 | { | |
446 | GSList *list; | |
447 | list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); | |
448 | g_slist_foreach(list, loongarch_cpu_list_entry, NULL); | |
449 | g_slist_free(list); | |
450 | } | |
451 | ||
f78b49ae | 452 | static void loongarch_cpu_reset_hold(Object *obj) |
228021f0 | 453 | { |
f78b49ae | 454 | CPUState *cs = CPU(obj); |
228021f0 SG |
455 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); |
456 | LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); | |
457 | CPULoongArchState *env = &cpu->env; | |
458 | ||
f78b49ae PM |
459 | if (lacc->parent_phases.hold) { |
460 | lacc->parent_phases.hold(obj); | |
461 | } | |
228021f0 SG |
462 | |
463 | env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; | |
464 | env->fcsr0 = 0x0; | |
465 | ||
398cecb9 XY |
466 | int n; |
467 | /* Set csr registers value after reset */ | |
468 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); | |
469 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); | |
470 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); | |
471 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); | |
472 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); | |
473 | env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); | |
474 | ||
475 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); | |
476 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); | |
477 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); | |
478 | env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); | |
479 | ||
480 | env->CSR_MISC = 0; | |
481 | ||
482 | env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); | |
483 | env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); | |
484 | ||
485 | env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); | |
486 | env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); | |
487 | env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); | |
488 | env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); | |
489 | env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); | |
490 | env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); | |
491 | ||
492 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); | |
493 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); | |
494 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); | |
495 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); | |
496 | ||
497 | for (n = 0; n < 4; n++) { | |
498 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); | |
499 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); | |
500 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); | |
501 | env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); | |
502 | } | |
503 | ||
0093b9a5 | 504 | #ifndef CONFIG_USER_ONLY |
f757a2cd | 505 | env->pc = 0x1c000000; |
3517fb72 | 506 | memset(env->tlb, 0, sizeof(env->tlb)); |
0093b9a5 | 507 | #endif |
f757a2cd | 508 | |
d578ca6c | 509 | restore_fp_status(env); |
228021f0 SG |
510 | cs->exception_index = -1; |
511 | } | |
512 | ||
513 | static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
514 | { | |
515 | info->print_insn = print_insn_loongarch; | |
516 | } | |
517 | ||
518 | static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) | |
519 | { | |
520 | CPUState *cs = CPU(dev); | |
521 | LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); | |
522 | Error *local_err = NULL; | |
523 | ||
524 | cpu_exec_realizefn(cs, &local_err); | |
525 | if (local_err != NULL) { | |
526 | error_propagate(errp, local_err); | |
527 | return; | |
528 | } | |
529 | ||
ca61e750 XY |
530 | loongarch_cpu_register_gdb_regs_for_features(cs); |
531 | ||
228021f0 SG |
532 | cpu_reset(cs); |
533 | qemu_init_vcpu(cs); | |
534 | ||
535 | lacc->parent_realize(dev, errp); | |
536 | } | |
537 | ||
0093b9a5 | 538 | #ifndef CONFIG_USER_ONLY |
f84a2aac XY |
539 | static void loongarch_qemu_write(void *opaque, hwaddr addr, |
540 | uint64_t val, unsigned size) | |
541 | { | |
542 | } | |
543 | ||
544 | static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) | |
545 | { | |
546 | switch (addr) { | |
547 | case FEATURE_REG: | |
548 | return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | | |
549 | 1ULL << IOCSRF_CSRIPI; | |
550 | case VENDOR_REG: | |
551 | return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ | |
552 | case CPUNAME_REG: | |
553 | return 0x303030354133ULL; /* "3A5000" */ | |
554 | case MISC_FUNC_REG: | |
555 | return 1ULL << IOCSRM_EXTIOI_EN; | |
556 | } | |
557 | return 0ULL; | |
558 | } | |
559 | ||
560 | static const MemoryRegionOps loongarch_qemu_ops = { | |
561 | .read = loongarch_qemu_read, | |
562 | .write = loongarch_qemu_write, | |
563 | .endianness = DEVICE_LITTLE_ENDIAN, | |
564 | .valid = { | |
565 | .min_access_size = 4, | |
566 | .max_access_size = 8, | |
567 | }, | |
568 | .impl = { | |
569 | .min_access_size = 8, | |
570 | .max_access_size = 8, | |
571 | }, | |
572 | }; | |
0093b9a5 | 573 | #endif |
f84a2aac | 574 | |
228021f0 SG |
575 | static void loongarch_cpu_init(Object *obj) |
576 | { | |
577 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | |
578 | ||
579 | cpu_set_cpustate_pointers(cpu); | |
0093b9a5 SG |
580 | |
581 | #ifndef CONFIG_USER_ONLY | |
582 | CPULoongArchState *env = &cpu->env; | |
f757a2cd | 583 | qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); |
dd615fa4 XY |
584 | timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, |
585 | &loongarch_constant_timer_cb, cpu); | |
f84a2aac XY |
586 | memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, |
587 | env, "iocsr", UINT64_MAX); | |
588 | address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); | |
589 | memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, | |
590 | NULL, "iocsr_misc", 0x428); | |
591 | memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); | |
0093b9a5 | 592 | #endif |
228021f0 SG |
593 | } |
594 | ||
595 | static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) | |
596 | { | |
597 | ObjectClass *oc; | |
228021f0 | 598 | |
c254f7af XY |
599 | oc = object_class_by_name(cpu_model); |
600 | if (!oc) { | |
601 | g_autofree char *typename | |
602 | = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); | |
603 | oc = object_class_by_name(typename); | |
604 | if (!oc) { | |
605 | return NULL; | |
606 | } | |
607 | } | |
608 | ||
609 | if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) | |
610 | && !object_class_is_abstract(oc)) { | |
611 | return oc; | |
612 | } | |
613 | return NULL; | |
228021f0 SG |
614 | } |
615 | ||
616 | void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
617 | { | |
618 | LoongArchCPU *cpu = LOONGARCH_CPU(cs); | |
619 | CPULoongArchState *env = &cpu->env; | |
620 | int i; | |
621 | ||
622 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | |
623 | qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, | |
624 | get_float_exception_flags(&env->fp_status)); | |
625 | ||
626 | /* gpr */ | |
627 | for (i = 0; i < 32; i++) { | |
628 | if ((i & 3) == 0) { | |
629 | qemu_fprintf(f, " GPR%02d:", i); | |
630 | } | |
631 | qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); | |
632 | if ((i & 3) == 3) { | |
633 | qemu_fprintf(f, "\n"); | |
634 | } | |
635 | } | |
636 | ||
7e1c521e XY |
637 | qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); |
638 | qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); | |
639 | qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); | |
640 | qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); | |
641 | qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); | |
642 | qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); | |
643 | qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); | |
644 | qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); | |
645 | qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," | |
646 | " PRCFG3=%016" PRIx64 "\n", | |
647 | env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); | |
648 | qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); | |
649 | qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); | |
650 | qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); | |
651 | ||
228021f0 SG |
652 | /* fpr */ |
653 | if (flags & CPU_DUMP_FPU) { | |
654 | for (i = 0; i < 32; i++) { | |
655 | qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); | |
656 | if ((i & 3) == 3) { | |
657 | qemu_fprintf(f, "\n"); | |
658 | } | |
659 | } | |
660 | } | |
661 | } | |
662 | ||
663 | #ifdef CONFIG_TCG | |
664 | #include "hw/core/tcg-cpu-ops.h" | |
665 | ||
666 | static struct TCGCPUOps loongarch_tcg_ops = { | |
667 | .initialize = loongarch_translate_init, | |
668 | .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, | |
ab27940f | 669 | .restore_state_to_opc = loongarch_restore_state_to_opc, |
7e1c521e | 670 | |
0093b9a5 | 671 | #ifndef CONFIG_USER_ONLY |
7e1c521e | 672 | .tlb_fill = loongarch_cpu_tlb_fill, |
f757a2cd XY |
673 | .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, |
674 | .do_interrupt = loongarch_cpu_do_interrupt, | |
675 | .do_transaction_failed = loongarch_cpu_do_transaction_failed, | |
0093b9a5 | 676 | #endif |
228021f0 SG |
677 | }; |
678 | #endif /* CONFIG_TCG */ | |
679 | ||
0093b9a5 | 680 | #ifndef CONFIG_USER_ONLY |
7e1c521e XY |
681 | #include "hw/core/sysemu-cpu-ops.h" |
682 | ||
683 | static const struct SysemuCPUOps loongarch_sysemu_ops = { | |
684 | .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, | |
685 | }; | |
0093b9a5 | 686 | #endif |
7e1c521e | 687 | |
cd8ef0ed SG |
688 | static gchar *loongarch_gdb_arch_name(CPUState *cs) |
689 | { | |
690 | return g_strdup("loongarch64"); | |
691 | } | |
692 | ||
228021f0 SG |
693 | static void loongarch_cpu_class_init(ObjectClass *c, void *data) |
694 | { | |
695 | LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); | |
696 | CPUClass *cc = CPU_CLASS(c); | |
697 | DeviceClass *dc = DEVICE_CLASS(c); | |
f78b49ae | 698 | ResettableClass *rc = RESETTABLE_CLASS(c); |
228021f0 SG |
699 | |
700 | device_class_set_parent_realize(dc, loongarch_cpu_realizefn, | |
701 | &lacc->parent_realize); | |
f78b49ae PM |
702 | resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, |
703 | &lacc->parent_phases); | |
228021f0 SG |
704 | |
705 | cc->class_by_name = loongarch_cpu_class_by_name; | |
f757a2cd | 706 | cc->has_work = loongarch_cpu_has_work; |
228021f0 SG |
707 | cc->dump_state = loongarch_cpu_dump_state; |
708 | cc->set_pc = loongarch_cpu_set_pc; | |
e4fdf9df | 709 | cc->get_pc = loongarch_cpu_get_pc; |
0093b9a5 | 710 | #ifndef CONFIG_USER_ONLY |
67ebd42a | 711 | dc->vmsd = &vmstate_loongarch_cpu; |
7e1c521e | 712 | cc->sysemu_ops = &loongarch_sysemu_ops; |
0093b9a5 | 713 | #endif |
228021f0 | 714 | cc->disas_set_info = loongarch_cpu_disas_set_info; |
ca61e750 XY |
715 | cc->gdb_read_register = loongarch_cpu_gdb_read_register; |
716 | cc->gdb_write_register = loongarch_cpu_gdb_write_register; | |
717 | cc->disas_set_info = loongarch_cpu_disas_set_info; | |
1fe8ac35 | 718 | cc->gdb_num_core_regs = 35; |
ca61e750 XY |
719 | cc->gdb_core_xml_file = "loongarch-base64.xml"; |
720 | cc->gdb_stop_before_watchpoint = true; | |
cd8ef0ed | 721 | cc->gdb_arch_name = loongarch_gdb_arch_name; |
ca61e750 | 722 | |
228021f0 SG |
723 | #ifdef CONFIG_TCG |
724 | cc->tcg_ops = &loongarch_tcg_ops; | |
725 | #endif | |
726 | } | |
727 | ||
728 | #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ | |
729 | { \ | |
730 | .parent = TYPE_LOONGARCH_CPU, \ | |
731 | .instance_init = initfn, \ | |
732 | .name = LOONGARCH_CPU_TYPE_NAME(model), \ | |
733 | } | |
734 | ||
735 | static const TypeInfo loongarch_cpu_type_infos[] = { | |
736 | { | |
737 | .name = TYPE_LOONGARCH_CPU, | |
738 | .parent = TYPE_CPU, | |
739 | .instance_size = sizeof(LoongArchCPU), | |
740 | .instance_init = loongarch_cpu_init, | |
741 | ||
742 | .abstract = true, | |
743 | .class_size = sizeof(LoongArchCPUClass), | |
744 | .class_init = loongarch_cpu_class_init, | |
745 | }, | |
746 | DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), | |
747 | }; | |
748 | ||
749 | DEFINE_TYPES(loongarch_cpu_type_infos) |