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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
22 | #include "tcg-op.h" | |
23 | #include "disas/disas.h" | |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
35 | static TCGv cpu_gpr[32], cpu_pc; | |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ | |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
55c2a12c | 47 | uint32_t opcode; |
83a71719 | 48 | uint32_t mstatus_fs; |
db9f3fd6 | 49 | uint32_t misa; |
55c2a12c | 50 | uint32_t mem_idx; |
55c2a12c MC |
51 | /* Remember the rounding mode encoded in the previous fp instruction, |
52 | which we have already installed into env->fp_status. Or -1 for | |
53 | no previous fp instruction. Note that we exit the TB when writing | |
54 | to any system register, which includes CSR_FRM, so we do not have | |
55 | to reset this known value. */ | |
56 | int frm; | |
57 | } DisasContext; | |
58 | ||
bce8a342 | 59 | #ifdef TARGET_RISCV64 |
55c2a12c MC |
60 | /* convert riscv funct3 to qemu memop for load/store */ |
61 | static const int tcg_memop_lookup[8] = { | |
62 | [0 ... 7] = -1, | |
63 | [0] = MO_SB, | |
64 | [1] = MO_TESW, | |
65 | [2] = MO_TESL, | |
66 | [4] = MO_UB, | |
67 | [5] = MO_TEUW, | |
68 | #ifdef TARGET_RISCV64 | |
69 | [3] = MO_TEQ, | |
70 | [6] = MO_TEUL, | |
71 | #endif | |
72 | }; | |
bce8a342 | 73 | #endif |
55c2a12c MC |
74 | |
75 | #ifdef TARGET_RISCV64 | |
76 | #define CASE_OP_32_64(X) case X: case glue(X, W) | |
77 | #else | |
78 | #define CASE_OP_32_64(X) case X | |
79 | #endif | |
80 | ||
db9f3fd6 MC |
81 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
82 | { | |
83 | return ctx->misa & ext; | |
84 | } | |
85 | ||
55c2a12c MC |
86 | static void generate_exception(DisasContext *ctx, int excp) |
87 | { | |
0114db1c | 88 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
89 | TCGv_i32 helper_tmp = tcg_const_i32(excp); |
90 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
91 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 92 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
93 | } |
94 | ||
95 | static void generate_exception_mbadaddr(DisasContext *ctx, int excp) | |
96 | { | |
0114db1c | 97 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
98 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
99 | TCGv_i32 helper_tmp = tcg_const_i32(excp); | |
100 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
101 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 102 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
103 | } |
104 | ||
105 | static void gen_exception_debug(void) | |
106 | { | |
107 | TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); | |
108 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
109 | tcg_temp_free_i32(helper_tmp); | |
110 | } | |
111 | ||
6e2716d8 FC |
112 | /* Wrapper around tcg_gen_exit_tb that handles single stepping */ |
113 | static void exit_tb(DisasContext *ctx) | |
114 | { | |
115 | if (ctx->base.singlestep_enabled) { | |
116 | gen_exception_debug(); | |
117 | } else { | |
118 | tcg_gen_exit_tb(NULL, 0); | |
119 | } | |
120 | } | |
121 | ||
122 | /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | |
123 | static void lookup_and_goto_ptr(DisasContext *ctx) | |
124 | { | |
125 | if (ctx->base.singlestep_enabled) { | |
126 | gen_exception_debug(); | |
127 | } else { | |
128 | tcg_gen_lookup_and_goto_ptr(); | |
129 | } | |
130 | } | |
131 | ||
55c2a12c MC |
132 | static void gen_exception_illegal(DisasContext *ctx) |
133 | { | |
134 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
135 | } | |
136 | ||
137 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
138 | { | |
139 | generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); | |
140 | } | |
141 | ||
142 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
143 | { | |
0114db1c | 144 | if (unlikely(ctx->base.singlestep_enabled)) { |
55c2a12c MC |
145 | return false; |
146 | } | |
147 | ||
148 | #ifndef CONFIG_USER_ONLY | |
0114db1c | 149 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
55c2a12c MC |
150 | #else |
151 | return true; | |
152 | #endif | |
153 | } | |
154 | ||
155 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
156 | { | |
157 | if (use_goto_tb(ctx, dest)) { | |
158 | /* chaining is only allowed when the jump is to the same page */ | |
159 | tcg_gen_goto_tb(n); | |
160 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 FC |
161 | |
162 | /* No need to check for single stepping here as use_goto_tb() will | |
163 | * return false in case of single stepping. | |
164 | */ | |
07ea28b4 | 165 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
166 | } else { |
167 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 | 168 | lookup_and_goto_ptr(ctx); |
55c2a12c MC |
169 | } |
170 | } | |
171 | ||
172 | /* Wrapper for getting reg values - need to check of reg is zero since | |
173 | * cpu_gpr[0] is not actually allocated | |
174 | */ | |
175 | static inline void gen_get_gpr(TCGv t, int reg_num) | |
176 | { | |
177 | if (reg_num == 0) { | |
178 | tcg_gen_movi_tl(t, 0); | |
179 | } else { | |
180 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
181 | } | |
182 | } | |
183 | ||
184 | /* Wrapper for setting reg values - need to check of reg is zero since | |
185 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
186 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
187 | * $zero | |
188 | */ | |
189 | static inline void gen_set_gpr(int reg_num_dst, TCGv t) | |
190 | { | |
191 | if (reg_num_dst != 0) { | |
192 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
193 | } | |
194 | } | |
195 | ||
196 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
197 | { | |
198 | TCGv rl = tcg_temp_new(); | |
199 | TCGv rh = tcg_temp_new(); | |
200 | ||
201 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
202 | /* fix up for one negative */ | |
203 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
204 | tcg_gen_and_tl(rl, rl, arg2); | |
205 | tcg_gen_sub_tl(ret, rh, rl); | |
206 | ||
207 | tcg_temp_free(rl); | |
208 | tcg_temp_free(rh); | |
209 | } | |
210 | ||
12887016 | 211 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 212 | { |
12887016 BK |
213 | TCGv cond1, cond2, zeroreg, resultopt1; |
214 | /* | |
215 | * Handle by altering args to tcg_gen_div to produce req'd results: | |
216 | * For overflow: want source1 in source1 and 1 in source2 | |
217 | * For div by zero: want -1 in source1 and 1 in source2 -> -1 result | |
218 | */ | |
219 | cond1 = tcg_temp_new(); | |
220 | cond2 = tcg_temp_new(); | |
221 | zeroreg = tcg_const_tl(0); | |
222 | resultopt1 = tcg_temp_new(); | |
223 | ||
224 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
225 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); | |
226 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
227 | ((target_ulong)1) << (TARGET_LONG_BITS - 1)); | |
228 | tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ | |
229 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ | |
230 | /* if div by zero, set source1 to -1, otherwise don't change */ | |
231 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, | |
232 | resultopt1); | |
233 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
234 | tcg_gen_or_tl(cond1, cond1, cond2); | |
235 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
236 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
237 | resultopt1); | |
238 | tcg_gen_div_tl(ret, source1, source2); | |
239 | ||
240 | tcg_temp_free(cond1); | |
241 | tcg_temp_free(cond2); | |
242 | tcg_temp_free(zeroreg); | |
243 | tcg_temp_free(resultopt1); | |
244 | } | |
55c2a12c | 245 | |
12887016 BK |
246 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
247 | { | |
248 | TCGv cond1, zeroreg, resultopt1; | |
249 | cond1 = tcg_temp_new(); | |
250 | ||
251 | zeroreg = tcg_const_tl(0); | |
252 | resultopt1 = tcg_temp_new(); | |
253 | ||
254 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
255 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
256 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, | |
257 | resultopt1); | |
258 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
259 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
260 | resultopt1); | |
261 | tcg_gen_divu_tl(ret, source1, source2); | |
262 | ||
263 | tcg_temp_free(cond1); | |
264 | tcg_temp_free(zeroreg); | |
265 | tcg_temp_free(resultopt1); | |
266 | } | |
55c2a12c | 267 | |
12887016 BK |
268 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
269 | { | |
270 | TCGv cond1, cond2, zeroreg, resultopt1; | |
271 | ||
272 | cond1 = tcg_temp_new(); | |
273 | cond2 = tcg_temp_new(); | |
274 | zeroreg = tcg_const_tl(0); | |
275 | resultopt1 = tcg_temp_new(); | |
276 | ||
277 | tcg_gen_movi_tl(resultopt1, 1L); | |
278 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); | |
279 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
280 | (target_ulong)1 << (TARGET_LONG_BITS - 1)); | |
281 | tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ | |
282 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ | |
283 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
284 | tcg_gen_or_tl(cond2, cond1, cond2); | |
285 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, | |
286 | resultopt1); | |
287 | tcg_gen_rem_tl(resultopt1, source1, source2); | |
288 | /* if div by zero, just return the original dividend */ | |
289 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
290 | source1); | |
291 | ||
292 | tcg_temp_free(cond1); | |
293 | tcg_temp_free(cond2); | |
294 | tcg_temp_free(zeroreg); | |
295 | tcg_temp_free(resultopt1); | |
296 | } | |
55c2a12c | 297 | |
12887016 BK |
298 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
299 | { | |
300 | TCGv cond1, zeroreg, resultopt1; | |
301 | cond1 = tcg_temp_new(); | |
302 | zeroreg = tcg_const_tl(0); | |
303 | resultopt1 = tcg_temp_new(); | |
304 | ||
305 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
306 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
307 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
308 | resultopt1); | |
309 | tcg_gen_remu_tl(resultopt1, source1, source2); | |
310 | /* if div by zero, just return the original dividend */ | |
311 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
312 | source1); | |
313 | ||
314 | tcg_temp_free(cond1); | |
315 | tcg_temp_free(zeroreg); | |
316 | tcg_temp_free(resultopt1); | |
55c2a12c MC |
317 | } |
318 | ||
db9f3fd6 | 319 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
320 | { |
321 | target_ulong next_pc; | |
322 | ||
323 | /* check misaligned: */ | |
0114db1c | 324 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 325 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
326 | if ((next_pc & 0x3) != 0) { |
327 | gen_exception_inst_addr_mis(ctx); | |
328 | return; | |
329 | } | |
330 | } | |
331 | if (rd != 0) { | |
0114db1c | 332 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
333 | } |
334 | ||
0114db1c EC |
335 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
336 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
337 | } |
338 | ||
98898b20 BK |
339 | #ifdef TARGET_RISCV64 |
340 | static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, | |
55c2a12c MC |
341 | target_long imm) |
342 | { | |
343 | TCGv t0 = tcg_temp_new(); | |
344 | TCGv t1 = tcg_temp_new(); | |
345 | gen_get_gpr(t0, rs1); | |
346 | tcg_gen_addi_tl(t0, t0, imm); | |
347 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
348 | ||
349 | if (memop < 0) { | |
350 | gen_exception_illegal(ctx); | |
351 | return; | |
352 | } | |
353 | ||
354 | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); | |
355 | gen_set_gpr(rd, t1); | |
356 | tcg_temp_free(t0); | |
357 | tcg_temp_free(t1); | |
358 | } | |
359 | ||
bce8a342 | 360 | static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, |
55c2a12c MC |
361 | target_long imm) |
362 | { | |
363 | TCGv t0 = tcg_temp_new(); | |
364 | TCGv dat = tcg_temp_new(); | |
365 | gen_get_gpr(t0, rs1); | |
366 | tcg_gen_addi_tl(t0, t0, imm); | |
367 | gen_get_gpr(dat, rs2); | |
368 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
369 | ||
370 | if (memop < 0) { | |
371 | gen_exception_illegal(ctx); | |
372 | return; | |
373 | } | |
374 | ||
375 | tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); | |
376 | tcg_temp_free(t0); | |
377 | tcg_temp_free(dat); | |
378 | } | |
bce8a342 | 379 | #endif |
55c2a12c | 380 | |
533b8f88 RH |
381 | #ifndef CONFIG_USER_ONLY |
382 | /* The states of mstatus_fs are: | |
383 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
384 | * We will have already diagnosed disabled state, | |
385 | * and need to turn initial/clean into dirty. | |
386 | */ | |
387 | static void mark_fs_dirty(DisasContext *ctx) | |
388 | { | |
389 | TCGv tmp; | |
390 | if (ctx->mstatus_fs == MSTATUS_FS) { | |
391 | return; | |
392 | } | |
393 | /* Remember the state change for the rest of the TB. */ | |
394 | ctx->mstatus_fs = MSTATUS_FS; | |
395 | ||
396 | tmp = tcg_temp_new(); | |
397 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
398 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); | |
399 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
400 | tcg_temp_free(tmp); | |
401 | } | |
402 | #else | |
403 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
404 | #endif | |
405 | ||
97b0be81 | 406 | #if !defined(TARGET_RISCV64) |
55c2a12c MC |
407 | static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, |
408 | int rs1, target_long imm) | |
409 | { | |
410 | TCGv t0; | |
411 | ||
83a71719 | 412 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
413 | gen_exception_illegal(ctx); |
414 | return; | |
415 | } | |
416 | ||
417 | t0 = tcg_temp_new(); | |
418 | gen_get_gpr(t0, rs1); | |
419 | tcg_gen_addi_tl(t0, t0, imm); | |
420 | ||
421 | switch (opc) { | |
422 | case OPC_RISC_FLW: | |
d77c3401 MC |
423 | if (!has_ext(ctx, RVF)) { |
424 | goto do_illegal; | |
425 | } | |
55c2a12c MC |
426 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); |
427 | /* RISC-V requires NaN-boxing of narrower width floating point values */ | |
428 | tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); | |
429 | break; | |
430 | case OPC_RISC_FLD: | |
d77c3401 MC |
431 | if (!has_ext(ctx, RVD)) { |
432 | goto do_illegal; | |
433 | } | |
55c2a12c MC |
434 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); |
435 | break; | |
d77c3401 | 436 | do_illegal: |
55c2a12c MC |
437 | default: |
438 | gen_exception_illegal(ctx); | |
439 | break; | |
440 | } | |
441 | tcg_temp_free(t0); | |
533b8f88 RH |
442 | |
443 | mark_fs_dirty(ctx); | |
55c2a12c MC |
444 | } |
445 | ||
446 | static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, | |
447 | int rs2, target_long imm) | |
448 | { | |
449 | TCGv t0; | |
450 | ||
83a71719 | 451 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
452 | gen_exception_illegal(ctx); |
453 | return; | |
454 | } | |
455 | ||
456 | t0 = tcg_temp_new(); | |
457 | gen_get_gpr(t0, rs1); | |
458 | tcg_gen_addi_tl(t0, t0, imm); | |
459 | ||
460 | switch (opc) { | |
461 | case OPC_RISC_FSW: | |
d77c3401 MC |
462 | if (!has_ext(ctx, RVF)) { |
463 | goto do_illegal; | |
464 | } | |
55c2a12c MC |
465 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); |
466 | break; | |
467 | case OPC_RISC_FSD: | |
d77c3401 MC |
468 | if (!has_ext(ctx, RVD)) { |
469 | goto do_illegal; | |
470 | } | |
55c2a12c MC |
471 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); |
472 | break; | |
d77c3401 | 473 | do_illegal: |
55c2a12c MC |
474 | default: |
475 | gen_exception_illegal(ctx); | |
476 | break; | |
477 | } | |
478 | ||
479 | tcg_temp_free(t0); | |
480 | } | |
97b0be81 | 481 | #endif |
55c2a12c | 482 | |
55c2a12c MC |
483 | static void gen_set_rm(DisasContext *ctx, int rm) |
484 | { | |
485 | TCGv_i32 t0; | |
486 | ||
487 | if (ctx->frm == rm) { | |
488 | return; | |
489 | } | |
490 | ctx->frm = rm; | |
491 | t0 = tcg_const_i32(rm); | |
492 | gen_helper_set_rounding_mode(cpu_env, t0); | |
493 | tcg_temp_free_i32(t0); | |
494 | } | |
495 | ||
55c2a12c MC |
496 | static void decode_RV32_64C0(DisasContext *ctx) |
497 | { | |
498 | uint8_t funct3 = extract32(ctx->opcode, 13, 3); | |
499 | uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode); | |
500 | uint8_t rs1s = GET_C_RS1S(ctx->opcode); | |
501 | ||
502 | switch (funct3) { | |
55c2a12c MC |
503 | case 3: |
504 | #if defined(TARGET_RISCV64) | |
505 | /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ | |
98898b20 | 506 | gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, |
55c2a12c MC |
507 | GET_C_LD_IMM(ctx->opcode)); |
508 | #else | |
509 | /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ | |
510 | gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, | |
511 | GET_C_LW_IMM(ctx->opcode)); | |
512 | #endif | |
513 | break; | |
55c2a12c MC |
514 | case 7: |
515 | #if defined(TARGET_RISCV64) | |
516 | /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ | |
bce8a342 | 517 | gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, |
55c2a12c MC |
518 | GET_C_LD_IMM(ctx->opcode)); |
519 | #else | |
520 | /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ | |
521 | gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, | |
522 | GET_C_LW_IMM(ctx->opcode)); | |
523 | #endif | |
524 | break; | |
525 | } | |
526 | } | |
527 | ||
db9f3fd6 | 528 | static void decode_RV32_64C(DisasContext *ctx) |
55c2a12c MC |
529 | { |
530 | uint8_t op = extract32(ctx->opcode, 0, 2); | |
531 | ||
532 | switch (op) { | |
533 | case 0: | |
534 | decode_RV32_64C0(ctx); | |
535 | break; | |
55c2a12c MC |
536 | } |
537 | } | |
538 | ||
2a53cff4 | 539 | #define EX_SH(amount) \ |
451e4ffd | 540 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
541 | { \ |
542 | return imm << amount; \ | |
543 | } | |
3cca75a6 | 544 | EX_SH(1) |
e98d9140 BK |
545 | EX_SH(2) |
546 | EX_SH(3) | |
07b001c6 | 547 | EX_SH(4) |
2a53cff4 BK |
548 | EX_SH(12) |
549 | ||
d2e2c1e4 BK |
550 | #define REQUIRE_EXT(ctx, ext) do { \ |
551 | if (!has_ext(ctx, ext)) { \ | |
552 | return false; \ | |
553 | } \ | |
554 | } while (0) | |
555 | ||
451e4ffd | 556 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
557 | { |
558 | return 8 + reg; | |
559 | } | |
560 | ||
6cafec92 RH |
561 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
562 | { | |
563 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
564 | return imm ? imm : 64; | |
565 | } | |
566 | ||
2a53cff4 BK |
567 | /* Include the auto-generated decoder for 32 bit insn */ |
568 | #include "decode_insn32.inc.c" | |
7a50d3e2 BK |
569 | |
570 | static bool gen_arith_imm(DisasContext *ctx, arg_i *a, | |
571 | void(*func)(TCGv, TCGv, TCGv)) | |
572 | { | |
573 | TCGv source1, source2; | |
574 | source1 = tcg_temp_new(); | |
575 | source2 = tcg_temp_new(); | |
576 | ||
577 | gen_get_gpr(source1, a->rs1); | |
578 | tcg_gen_movi_tl(source2, a->imm); | |
579 | ||
580 | (*func)(source1, source1, source2); | |
581 | ||
582 | gen_set_gpr(a->rd, source1); | |
583 | tcg_temp_free(source1); | |
584 | tcg_temp_free(source2); | |
585 | return true; | |
586 | } | |
587 | ||
588 | #ifdef TARGET_RISCV64 | |
589 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) | |
590 | { | |
591 | tcg_gen_add_tl(ret, arg1, arg2); | |
592 | tcg_gen_ext32s_tl(ret, ret); | |
593 | } | |
f2ab1728 BK |
594 | |
595 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
596 | { | |
597 | tcg_gen_sub_tl(ret, arg1, arg2); | |
598 | tcg_gen_ext32s_tl(ret, ret); | |
599 | } | |
600 | ||
12887016 BK |
601 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
602 | { | |
603 | tcg_gen_mul_tl(ret, arg1, arg2); | |
604 | tcg_gen_ext32s_tl(ret, ret); | |
605 | } | |
606 | ||
607 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
608 | void(*func)(TCGv, TCGv, TCGv)) | |
609 | { | |
610 | TCGv source1, source2; | |
611 | source1 = tcg_temp_new(); | |
612 | source2 = tcg_temp_new(); | |
613 | ||
614 | gen_get_gpr(source1, a->rs1); | |
615 | gen_get_gpr(source2, a->rs2); | |
616 | tcg_gen_ext32s_tl(source1, source1); | |
617 | tcg_gen_ext32s_tl(source2, source2); | |
618 | ||
619 | (*func)(source1, source1, source2); | |
620 | ||
621 | tcg_gen_ext32s_tl(source1, source1); | |
622 | gen_set_gpr(a->rd, source1); | |
623 | tcg_temp_free(source1); | |
624 | tcg_temp_free(source2); | |
625 | return true; | |
626 | } | |
627 | ||
f17e02cd PD |
628 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
629 | void(*func)(TCGv, TCGv, TCGv)) | |
630 | { | |
631 | TCGv source1, source2; | |
632 | source1 = tcg_temp_new(); | |
633 | source2 = tcg_temp_new(); | |
634 | ||
635 | gen_get_gpr(source1, a->rs1); | |
636 | gen_get_gpr(source2, a->rs2); | |
637 | tcg_gen_ext32u_tl(source1, source1); | |
638 | tcg_gen_ext32u_tl(source2, source2); | |
639 | ||
640 | (*func)(source1, source1, source2); | |
641 | ||
642 | tcg_gen_ext32s_tl(source1, source1); | |
643 | gen_set_gpr(a->rd, source1); | |
644 | tcg_temp_free(source1); | |
645 | tcg_temp_free(source2); | |
646 | return true; | |
647 | } | |
648 | ||
7a50d3e2 BK |
649 | #endif |
650 | ||
8dc9e8a8 BK |
651 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
652 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
653 | { |
654 | TCGv source1, source2; | |
655 | source1 = tcg_temp_new(); | |
656 | source2 = tcg_temp_new(); | |
657 | ||
658 | gen_get_gpr(source1, a->rs1); | |
659 | gen_get_gpr(source2, a->rs2); | |
660 | ||
661 | (*func)(source1, source1, source2); | |
662 | ||
663 | gen_set_gpr(a->rd, source1); | |
664 | tcg_temp_free(source1); | |
665 | tcg_temp_free(source2); | |
666 | return true; | |
667 | } | |
668 | ||
34446e84 BK |
669 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
670 | void(*func)(TCGv, TCGv, TCGv)) | |
671 | { | |
672 | TCGv source1 = tcg_temp_new(); | |
673 | TCGv source2 = tcg_temp_new(); | |
674 | ||
675 | gen_get_gpr(source1, a->rs1); | |
676 | gen_get_gpr(source2, a->rs2); | |
677 | ||
678 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
679 | (*func)(source1, source1, source2); | |
680 | ||
681 | gen_set_gpr(a->rd, source1); | |
682 | tcg_temp_free(source1); | |
683 | tcg_temp_free(source2); | |
684 | return true; | |
685 | } | |
686 | ||
2a53cff4 BK |
687 | /* Include insn module translation function */ |
688 | #include "insn_trans/trans_rvi.inc.c" | |
d2e2c1e4 | 689 | #include "insn_trans/trans_rvm.inc.c" |
3b77c289 | 690 | #include "insn_trans/trans_rva.inc.c" |
6f0e74ff | 691 | #include "insn_trans/trans_rvf.inc.c" |
97f8b493 | 692 | #include "insn_trans/trans_rvd.inc.c" |
4ba79c47 | 693 | #include "insn_trans/trans_privileged.inc.c" |
2a53cff4 | 694 | |
e7617997 RH |
695 | /* |
696 | * Auto-generated decoder. | |
697 | * Note that the 16-bit decoder reuses some of the trans_* functions | |
698 | * initially declared by the 32-bit decoder, which results in duplicate | |
699 | * declaration warnings. Suppress them. | |
700 | */ | |
701 | #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE | |
702 | # pragma GCC diagnostic push | |
703 | # pragma GCC diagnostic ignored "-Wredundant-decls" | |
704 | # ifdef __clang__ | |
705 | # pragma GCC diagnostic ignored "-Wtypedef-redefinition" | |
706 | # endif | |
707 | #endif | |
708 | ||
e98d9140 BK |
709 | #include "decode_insn16.inc.c" |
710 | #include "insn_trans/trans_rvc.inc.c" | |
711 | ||
e7617997 RH |
712 | #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE |
713 | # pragma GCC diagnostic pop | |
714 | #endif | |
715 | ||
db9f3fd6 | 716 | static void decode_opc(DisasContext *ctx) |
55c2a12c MC |
717 | { |
718 | /* check for compressed insn */ | |
719 | if (extract32(ctx->opcode, 0, 2) != 3) { | |
db9f3fd6 | 720 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
721 | gen_exception_illegal(ctx); |
722 | } else { | |
0114db1c | 723 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
e98d9140 BK |
724 | if (!decode_insn16(ctx, ctx->opcode)) { |
725 | /* fall back to old decoder */ | |
726 | decode_RV32_64C(ctx); | |
727 | } | |
55c2a12c MC |
728 | } |
729 | } else { | |
0114db1c | 730 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
2a53cff4 | 731 | if (!decode_insn32(ctx, ctx->opcode)) { |
25e6ca30 | 732 | gen_exception_illegal(ctx); |
2a53cff4 | 733 | } |
55c2a12c MC |
734 | } |
735 | } | |
736 | ||
5b4f1d2d | 737 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 738 | { |
5b4f1d2d | 739 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 740 | CPURISCVState *env = cs->env_ptr; |
55c2a12c | 741 | |
5b4f1d2d | 742 | ctx->pc_succ_insn = ctx->base.pc_first; |
5b4f1d2d | 743 | ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; |
83a71719 | 744 | ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; |
d75377bf | 745 | ctx->priv_ver = env->priv_ver; |
db9f3fd6 | 746 | ctx->misa = env->misa; |
5b4f1d2d EC |
747 | ctx->frm = -1; /* unknown rounding mode */ |
748 | } | |
55c2a12c | 749 | |
5b4f1d2d EC |
750 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
751 | { | |
752 | } | |
55c2a12c | 753 | |
5b4f1d2d EC |
754 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
755 | { | |
756 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
757 | ||
758 | tcg_gen_insn_start(ctx->base.pc_next); | |
759 | } | |
760 | ||
761 | static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, | |
762 | const CPUBreakpoint *bp) | |
763 | { | |
764 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
765 | ||
766 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | |
767 | ctx->base.is_jmp = DISAS_NORETURN; | |
768 | gen_exception_debug(); | |
769 | /* The address covered by the breakpoint must be included in | |
770 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
771 | properly cleared -- thus we increment the PC here so that | |
772 | the logic setting tb->size below does the right thing. */ | |
773 | ctx->base.pc_next += 4; | |
774 | return true; | |
775 | } | |
776 | ||
5b4f1d2d EC |
777 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
778 | { | |
779 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
780 | CPURISCVState *env = cpu->env_ptr; | |
55c2a12c | 781 | |
5b4f1d2d | 782 | ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); |
db9f3fd6 | 783 | decode_opc(ctx); |
5b4f1d2d EC |
784 | ctx->base.pc_next = ctx->pc_succ_insn; |
785 | ||
786 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
787 | target_ulong page_start; | |
788 | ||
789 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
790 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
791 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 792 | } |
55c2a12c | 793 | } |
5b4f1d2d EC |
794 | } |
795 | ||
796 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
797 | { | |
798 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
799 | ||
800 | switch (ctx->base.is_jmp) { | |
b2e32021 | 801 | case DISAS_TOO_MANY: |
ccf08e40 | 802 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 803 | break; |
b2e32021 | 804 | case DISAS_NORETURN: |
55c2a12c | 805 | break; |
b2e32021 EC |
806 | default: |
807 | g_assert_not_reached(); | |
55c2a12c | 808 | } |
5b4f1d2d EC |
809 | } |
810 | ||
811 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
812 | { | |
813 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
814 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); | |
815 | } | |
816 | ||
817 | static const TranslatorOps riscv_tr_ops = { | |
818 | .init_disas_context = riscv_tr_init_disas_context, | |
819 | .tb_start = riscv_tr_tb_start, | |
820 | .insn_start = riscv_tr_insn_start, | |
821 | .breakpoint_check = riscv_tr_breakpoint_check, | |
822 | .translate_insn = riscv_tr_translate_insn, | |
823 | .tb_stop = riscv_tr_tb_stop, | |
824 | .disas_log = riscv_tr_disas_log, | |
825 | }; | |
826 | ||
8b86d6d2 | 827 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
828 | { |
829 | DisasContext ctx; | |
830 | ||
8b86d6d2 | 831 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
832 | } |
833 | ||
834 | void riscv_translate_init(void) | |
835 | { | |
836 | int i; | |
837 | ||
838 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
839 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
840 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
841 | cpu_gpr[0] = NULL; | |
842 | ||
843 | for (i = 1; i < 32; i++) { | |
844 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
845 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
846 | } | |
847 | ||
848 | for (i = 0; i < 32; i++) { | |
849 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
850 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
851 | } | |
852 | ||
853 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
854 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), | |
855 | "load_res"); | |
856 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
857 | "load_val"); | |
858 | } |