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Commit | Line | Data |
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d0fb9657 | 1 | # See docs/devel/tracing.rst for syntax documentation. |
1cba9b29 | 2 | |
500016e5 | 3 | # mmu_helper.c |
8908eb1a VSO |
4 | mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at 0x%"PRIx64" context 0x%"PRIx64" mmu_idx=%d tl=%d" |
5 | mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at 0x%"PRIx64" context 0x%"PRIx64" mmu_idx=%d tl=%d" | |
6 | mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at 0x%"PRIx64" context 0x%"PRIx64 | |
7 | mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at 0x%"PRIx64" context 0x%"PRIx64 | |
8 | mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at 0x%"PRIx64" context 0x%"PRIx64 | |
9 | mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64 | |
10 | mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64 | |
11 | mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64 | |
1cba9b29 | 12 | |
10fb1340 PMD |
13 | # int32_helper.c |
14 | sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" | |
15 | sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" | |
16 | ||
500016e5 | 17 | # int64_helper.c |
8908eb1a VSO |
18 | int_helper_set_softint(uint32_t softint) "new 0x%08x" |
19 | int_helper_clear_softint(uint32_t softint) "new 0x%08x" | |
20 | int_helper_write_softint(uint32_t softint) "new 0x%08x" | |
10fb1340 PMD |
21 | sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" |
22 | sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" | |
23 | sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" | |
24 | sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" | |
1cba9b29 | 25 | |
500016e5 | 26 | # win_helper.c |
8908eb1a VSO |
27 | win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x" |
28 | win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x" | |
29 | win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=0x%x (unchanged)" | |
30 | win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=0x%x new=0x%x" | |
1cba9b29 DB |
31 | win_helper_done(uint32_t tl) "tl=%d" |
32 | win_helper_retry(uint32_t tl) "tl=%d" |