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25ebd80f AF |
1 | /* |
2 | * QEMU Alpha CPU | |
3 | * | |
9444006f | 4 | * Copyright (c) 2007 Jocelyn Mayer |
25ebd80f AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
3993c6bd | 22 | #include "cpu.h" |
25ebd80f AF |
23 | #include "qemu-common.h" |
24 | ||
25 | ||
bd1b2828 | 26 | static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) |
0c28246f | 27 | { |
bd1b2828 AF |
28 | AlphaCPU *cpu = ALPHA_CPU(dev); |
29 | AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); | |
0c28246f AF |
30 | |
31 | qemu_init_vcpu(&cpu->env); | |
bd1b2828 AF |
32 | |
33 | acc->parent_realize(dev, errp); | |
0c28246f AF |
34 | } |
35 | ||
494342b3 AF |
36 | /* Sort alphabetically by type name. */ |
37 | static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b) | |
38 | { | |
39 | ObjectClass *class_a = (ObjectClass *)a; | |
40 | ObjectClass *class_b = (ObjectClass *)b; | |
41 | const char *name_a, *name_b; | |
42 | ||
43 | name_a = object_class_get_name(class_a); | |
44 | name_b = object_class_get_name(class_b); | |
45 | return strcmp(name_a, name_b); | |
46 | } | |
47 | ||
48 | static void alpha_cpu_list_entry(gpointer data, gpointer user_data) | |
49 | { | |
50 | ObjectClass *oc = data; | |
92a31361 | 51 | CPUListState *s = user_data; |
494342b3 AF |
52 | |
53 | (*s->cpu_fprintf)(s->file, " %s\n", | |
54 | object_class_get_name(oc)); | |
55 | } | |
56 | ||
57 | void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
58 | { | |
92a31361 | 59 | CPUListState s = { |
494342b3 AF |
60 | .file = f, |
61 | .cpu_fprintf = cpu_fprintf, | |
62 | }; | |
63 | GSList *list; | |
64 | ||
65 | list = object_class_get_list(TYPE_ALPHA_CPU, false); | |
66 | list = g_slist_sort(list, alpha_cpu_list_compare); | |
67 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
68 | g_slist_foreach(list, alpha_cpu_list_entry, &s); | |
69 | g_slist_free(list); | |
70 | } | |
71 | ||
0c28246f AF |
72 | /* Models */ |
73 | ||
74 | #define TYPE(model) model "-" TYPE_ALPHA_CPU | |
75 | ||
76 | typedef struct AlphaCPUAlias { | |
77 | const char *alias; | |
78 | const char *typename; | |
79 | } AlphaCPUAlias; | |
80 | ||
81 | static const AlphaCPUAlias alpha_cpu_aliases[] = { | |
82 | { "21064", TYPE("ev4") }, | |
83 | { "21164", TYPE("ev5") }, | |
84 | { "21164a", TYPE("ev56") }, | |
85 | { "21164pc", TYPE("pca56") }, | |
86 | { "21264", TYPE("ev6") }, | |
87 | { "21264a", TYPE("ev67") }, | |
88 | }; | |
89 | ||
90 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) | |
91 | { | |
92 | ObjectClass *oc = NULL; | |
93 | char *typename; | |
94 | int i; | |
95 | ||
96 | if (cpu_model == NULL) { | |
97 | return NULL; | |
98 | } | |
99 | ||
100 | oc = object_class_by_name(cpu_model); | |
a120c287 AF |
101 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && |
102 | !object_class_is_abstract(oc)) { | |
0c28246f AF |
103 | return oc; |
104 | } | |
105 | ||
106 | for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { | |
107 | if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { | |
108 | oc = object_class_by_name(alpha_cpu_aliases[i].typename); | |
a120c287 | 109 | assert(oc != NULL && !object_class_is_abstract(oc)); |
0c28246f AF |
110 | return oc; |
111 | } | |
112 | } | |
113 | ||
114 | typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model); | |
115 | oc = object_class_by_name(typename); | |
116 | g_free(typename); | |
a120c287 AF |
117 | if (oc != NULL && object_class_is_abstract(oc)) { |
118 | oc = NULL; | |
119 | } | |
0c28246f AF |
120 | return oc; |
121 | } | |
122 | ||
123 | AlphaCPU *cpu_alpha_init(const char *cpu_model) | |
124 | { | |
125 | AlphaCPU *cpu; | |
126 | CPUAlphaState *env; | |
127 | ObjectClass *cpu_class; | |
128 | ||
129 | cpu_class = alpha_cpu_class_by_name(cpu_model); | |
130 | if (cpu_class == NULL) { | |
131 | /* Default to ev67; no reason not to emulate insns by default. */ | |
132 | cpu_class = object_class_by_name(TYPE("ev67")); | |
133 | } | |
134 | cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class))); | |
135 | env = &cpu->env; | |
136 | ||
137 | env->cpu_model_str = cpu_model; | |
138 | ||
bd1b2828 AF |
139 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
140 | ||
0c28246f AF |
141 | return cpu; |
142 | } | |
143 | ||
144 | static void ev4_cpu_initfn(Object *obj) | |
145 | { | |
146 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
147 | CPUAlphaState *env = &cpu->env; | |
148 | ||
149 | env->implver = IMPLVER_2106x; | |
150 | } | |
151 | ||
152 | static const TypeInfo ev4_cpu_type_info = { | |
153 | .name = TYPE("ev4"), | |
154 | .parent = TYPE_ALPHA_CPU, | |
155 | .instance_init = ev4_cpu_initfn, | |
156 | }; | |
157 | ||
158 | static void ev5_cpu_initfn(Object *obj) | |
159 | { | |
160 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
161 | CPUAlphaState *env = &cpu->env; | |
162 | ||
163 | env->implver = IMPLVER_21164; | |
164 | } | |
165 | ||
166 | static const TypeInfo ev5_cpu_type_info = { | |
167 | .name = TYPE("ev5"), | |
168 | .parent = TYPE_ALPHA_CPU, | |
169 | .instance_init = ev5_cpu_initfn, | |
170 | }; | |
171 | ||
172 | static void ev56_cpu_initfn(Object *obj) | |
173 | { | |
174 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
175 | CPUAlphaState *env = &cpu->env; | |
176 | ||
177 | env->amask |= AMASK_BWX; | |
178 | } | |
179 | ||
180 | static const TypeInfo ev56_cpu_type_info = { | |
181 | .name = TYPE("ev56"), | |
182 | .parent = TYPE("ev5"), | |
183 | .instance_init = ev56_cpu_initfn, | |
184 | }; | |
185 | ||
186 | static void pca56_cpu_initfn(Object *obj) | |
187 | { | |
188 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
189 | CPUAlphaState *env = &cpu->env; | |
190 | ||
191 | env->amask |= AMASK_MVI; | |
192 | } | |
193 | ||
194 | static const TypeInfo pca56_cpu_type_info = { | |
195 | .name = TYPE("pca56"), | |
196 | .parent = TYPE("ev56"), | |
197 | .instance_init = pca56_cpu_initfn, | |
198 | }; | |
199 | ||
200 | static void ev6_cpu_initfn(Object *obj) | |
201 | { | |
202 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
203 | CPUAlphaState *env = &cpu->env; | |
204 | ||
205 | env->implver = IMPLVER_21264; | |
206 | env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; | |
207 | } | |
208 | ||
209 | static const TypeInfo ev6_cpu_type_info = { | |
210 | .name = TYPE("ev6"), | |
211 | .parent = TYPE_ALPHA_CPU, | |
212 | .instance_init = ev6_cpu_initfn, | |
213 | }; | |
214 | ||
215 | static void ev67_cpu_initfn(Object *obj) | |
216 | { | |
217 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
218 | CPUAlphaState *env = &cpu->env; | |
219 | ||
220 | env->amask |= AMASK_CIX | AMASK_PREFETCH; | |
221 | } | |
222 | ||
223 | static const TypeInfo ev67_cpu_type_info = { | |
224 | .name = TYPE("ev67"), | |
225 | .parent = TYPE("ev6"), | |
226 | .instance_init = ev67_cpu_initfn, | |
227 | }; | |
228 | ||
229 | static const TypeInfo ev68_cpu_type_info = { | |
230 | .name = TYPE("ev68"), | |
231 | .parent = TYPE("ev67"), | |
232 | }; | |
233 | ||
9444006f AF |
234 | static void alpha_cpu_initfn(Object *obj) |
235 | { | |
c05efcb1 | 236 | CPUState *cs = CPU(obj); |
9444006f AF |
237 | AlphaCPU *cpu = ALPHA_CPU(obj); |
238 | CPUAlphaState *env = &cpu->env; | |
239 | ||
c05efcb1 | 240 | cs->env_ptr = env; |
9444006f AF |
241 | cpu_exec_init(env); |
242 | tlb_flush(env, 1); | |
243 | ||
0c28246f AF |
244 | alpha_translate_init(); |
245 | ||
9444006f AF |
246 | #if defined(CONFIG_USER_ONLY) |
247 | env->ps = PS_USER_MODE; | |
248 | cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | |
249 | | FPCR_UNFD | FPCR_INED | FPCR_DNOD | |
250 | | FPCR_DYN_NORMAL)); | |
251 | #endif | |
252 | env->lock_addr = -1; | |
253 | env->fen = 1; | |
254 | } | |
255 | ||
2b8c2754 AF |
256 | static void alpha_cpu_class_init(ObjectClass *oc, void *data) |
257 | { | |
bd1b2828 | 258 | DeviceClass *dc = DEVICE_CLASS(oc); |
2b8c2754 | 259 | CPUClass *cc = CPU_CLASS(oc); |
bd1b2828 AF |
260 | AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); |
261 | ||
262 | acc->parent_realize = dc->realize; | |
263 | dc->realize = alpha_cpu_realizefn; | |
2b8c2754 AF |
264 | |
265 | cc->class_by_name = alpha_cpu_class_by_name; | |
266 | } | |
267 | ||
25ebd80f AF |
268 | static const TypeInfo alpha_cpu_type_info = { |
269 | .name = TYPE_ALPHA_CPU, | |
270 | .parent = TYPE_CPU, | |
271 | .instance_size = sizeof(AlphaCPU), | |
9444006f | 272 | .instance_init = alpha_cpu_initfn, |
0c28246f | 273 | .abstract = true, |
25ebd80f | 274 | .class_size = sizeof(AlphaCPUClass), |
2b8c2754 | 275 | .class_init = alpha_cpu_class_init, |
25ebd80f AF |
276 | }; |
277 | ||
278 | static void alpha_cpu_register_types(void) | |
279 | { | |
280 | type_register_static(&alpha_cpu_type_info); | |
0c28246f AF |
281 | type_register_static(&ev4_cpu_type_info); |
282 | type_register_static(&ev5_cpu_type_info); | |
283 | type_register_static(&ev56_cpu_type_info); | |
284 | type_register_static(&pca56_cpu_type_info); | |
285 | type_register_static(&ev6_cpu_type_info); | |
286 | type_register_static(&ev67_cpu_type_info); | |
287 | type_register_static(&ev68_cpu_type_info); | |
25ebd80f AF |
288 | } |
289 | ||
290 | type_init(alpha_cpu_register_types) |