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4c9649a9 JM |
1 | /* |
2 | * Alpha emulation cpu definitions for qemu. | |
5fafdf24 | 3 | * |
4c9649a9 JM |
4 | * Copyright (c) 2007 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4c9649a9 JM |
18 | */ |
19 | ||
20 | #if !defined (__CPU_ALPHA_H__) | |
21 | #define __CPU_ALPHA_H__ | |
22 | ||
23 | #include "config.h" | |
24 | ||
25 | #define TARGET_LONG_BITS 64 | |
26 | ||
c2764719 PB |
27 | #define CPUState struct CPUAlphaState |
28 | ||
4c9649a9 JM |
29 | #include "cpu-defs.h" |
30 | ||
4c9649a9 JM |
31 | #include <setjmp.h> |
32 | ||
33 | #include "softfloat.h" | |
34 | ||
4c9649a9 JM |
35 | #define TARGET_HAS_ICE 1 |
36 | ||
f071b4d3 | 37 | #define ELF_MACHINE EM_ALPHA |
4c9649a9 JM |
38 | |
39 | #define ICACHE_LINE_SIZE 32 | |
40 | #define DCACHE_LINE_SIZE 32 | |
41 | ||
b09d9d46 | 42 | #define TARGET_PAGE_BITS 13 |
4c9649a9 | 43 | |
52705890 RH |
44 | /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ |
45 | #define TARGET_PHYS_ADDR_SPACE_BITS 44 | |
46 | #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) | |
4c9649a9 JM |
47 | |
48 | /* Alpha major type */ | |
49 | enum { | |
50 | ALPHA_EV3 = 1, | |
51 | ALPHA_EV4 = 2, | |
52 | ALPHA_SIM = 3, | |
53 | ALPHA_LCA = 4, | |
54 | ALPHA_EV5 = 5, /* 21164 */ | |
55 | ALPHA_EV45 = 6, /* 21064A */ | |
56 | ALPHA_EV56 = 7, /* 21164A */ | |
57 | }; | |
58 | ||
59 | /* EV4 minor type */ | |
60 | enum { | |
61 | ALPHA_EV4_2 = 0, | |
62 | ALPHA_EV4_3 = 1, | |
63 | }; | |
64 | ||
65 | /* LCA minor type */ | |
66 | enum { | |
67 | ALPHA_LCA_1 = 1, /* 21066 */ | |
68 | ALPHA_LCA_2 = 2, /* 20166 */ | |
69 | ALPHA_LCA_3 = 3, /* 21068 */ | |
70 | ALPHA_LCA_4 = 4, /* 21068 */ | |
71 | ALPHA_LCA_5 = 5, /* 21066A */ | |
72 | ALPHA_LCA_6 = 6, /* 21068A */ | |
73 | }; | |
74 | ||
75 | /* EV5 minor type */ | |
76 | enum { | |
77 | ALPHA_EV5_1 = 1, /* Rev BA, CA */ | |
78 | ALPHA_EV5_2 = 2, /* Rev DA, EA */ | |
79 | ALPHA_EV5_3 = 3, /* Pass 3 */ | |
80 | ALPHA_EV5_4 = 4, /* Pass 3.2 */ | |
81 | ALPHA_EV5_5 = 5, /* Pass 4 */ | |
82 | }; | |
83 | ||
84 | /* EV45 minor type */ | |
85 | enum { | |
86 | ALPHA_EV45_1 = 1, /* Pass 1 */ | |
87 | ALPHA_EV45_2 = 2, /* Pass 1.1 */ | |
88 | ALPHA_EV45_3 = 3, /* Pass 2 */ | |
89 | }; | |
90 | ||
91 | /* EV56 minor type */ | |
92 | enum { | |
93 | ALPHA_EV56_1 = 1, /* Pass 1 */ | |
94 | ALPHA_EV56_2 = 2, /* Pass 2 */ | |
95 | }; | |
96 | ||
97 | enum { | |
98 | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ | |
99 | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ | |
100 | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ | |
101 | IMPLVER_21364 = 3, /* EV7 & EV79 */ | |
102 | }; | |
103 | ||
104 | enum { | |
105 | AMASK_BWX = 0x00000001, | |
106 | AMASK_FIX = 0x00000002, | |
107 | AMASK_CIX = 0x00000004, | |
108 | AMASK_MVI = 0x00000100, | |
109 | AMASK_TRAP = 0x00000200, | |
110 | AMASK_PREFETCH = 0x00001000, | |
111 | }; | |
112 | ||
113 | enum { | |
114 | VAX_ROUND_NORMAL = 0, | |
115 | VAX_ROUND_CHOPPED, | |
116 | }; | |
117 | ||
118 | enum { | |
119 | IEEE_ROUND_NORMAL = 0, | |
120 | IEEE_ROUND_DYNAMIC, | |
121 | IEEE_ROUND_PLUS, | |
122 | IEEE_ROUND_MINUS, | |
123 | IEEE_ROUND_CHOPPED, | |
124 | }; | |
125 | ||
126 | /* IEEE floating-point operations encoding */ | |
127 | /* Trap mode */ | |
128 | enum { | |
129 | FP_TRAP_I = 0x0, | |
130 | FP_TRAP_U = 0x1, | |
131 | FP_TRAP_S = 0x4, | |
132 | FP_TRAP_SU = 0x5, | |
133 | FP_TRAP_SUI = 0x7, | |
134 | }; | |
135 | ||
136 | /* Rounding mode */ | |
137 | enum { | |
138 | FP_ROUND_CHOPPED = 0x0, | |
139 | FP_ROUND_MINUS = 0x1, | |
140 | FP_ROUND_NORMAL = 0x2, | |
141 | FP_ROUND_DYNAMIC = 0x3, | |
142 | }; | |
143 | ||
ba0e276d RH |
144 | /* FPCR bits */ |
145 | #define FPCR_SUM (1ULL << 63) | |
146 | #define FPCR_INED (1ULL << 62) | |
147 | #define FPCR_UNFD (1ULL << 61) | |
148 | #define FPCR_UNDZ (1ULL << 60) | |
149 | #define FPCR_DYN_SHIFT 58 | |
8443effb RH |
150 | #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT) |
151 | #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT) | |
152 | #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT) | |
153 | #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT) | |
ba0e276d RH |
154 | #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT) |
155 | #define FPCR_IOV (1ULL << 57) | |
156 | #define FPCR_INE (1ULL << 56) | |
157 | #define FPCR_UNF (1ULL << 55) | |
158 | #define FPCR_OVF (1ULL << 54) | |
159 | #define FPCR_DZE (1ULL << 53) | |
160 | #define FPCR_INV (1ULL << 52) | |
161 | #define FPCR_OVFD (1ULL << 51) | |
162 | #define FPCR_DZED (1ULL << 50) | |
163 | #define FPCR_INVD (1ULL << 49) | |
164 | #define FPCR_DNZ (1ULL << 48) | |
165 | #define FPCR_DNOD (1ULL << 47) | |
166 | #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ | |
167 | | FPCR_OVF | FPCR_DZE | FPCR_INV) | |
168 | ||
169 | /* The silly software trap enables implemented by the kernel emulation. | |
170 | These are more or less architecturally required, since the real hardware | |
171 | has read-as-zero bits in the FPCR when the features aren't implemented. | |
172 | For the purposes of QEMU, we pretend the FPCR can hold everything. */ | |
173 | #define SWCR_TRAP_ENABLE_INV (1ULL << 1) | |
174 | #define SWCR_TRAP_ENABLE_DZE (1ULL << 2) | |
175 | #define SWCR_TRAP_ENABLE_OVF (1ULL << 3) | |
176 | #define SWCR_TRAP_ENABLE_UNF (1ULL << 4) | |
177 | #define SWCR_TRAP_ENABLE_INE (1ULL << 5) | |
178 | #define SWCR_TRAP_ENABLE_DNO (1ULL << 6) | |
179 | #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1)) | |
180 | ||
181 | #define SWCR_MAP_DMZ (1ULL << 12) | |
182 | #define SWCR_MAP_UMZ (1ULL << 13) | |
183 | #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ) | |
184 | ||
185 | #define SWCR_STATUS_INV (1ULL << 17) | |
186 | #define SWCR_STATUS_DZE (1ULL << 18) | |
187 | #define SWCR_STATUS_OVF (1ULL << 19) | |
188 | #define SWCR_STATUS_UNF (1ULL << 20) | |
189 | #define SWCR_STATUS_INE (1ULL << 21) | |
190 | #define SWCR_STATUS_DNO (1ULL << 22) | |
191 | #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17)) | |
192 | ||
193 | #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) | |
194 | ||
8417845e RH |
195 | /* MMU modes definitions */ |
196 | ||
197 | /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. | |
198 | The Unix PALcode only exposes the kernel and user modes; presumably | |
199 | executive and supervisor are used by VMS. | |
200 | ||
201 | PALcode itself uses physical mode for code and kernel mode for data; | |
202 | there are PALmode instructions that can access data via physical mode | |
203 | or via an os-installed "alternate mode", which is one of the 4 above. | |
204 | ||
205 | QEMU does not currently properly distinguish between code/data when | |
206 | looking up addresses. To avoid having to address this issue, our | |
207 | emulated PALcode will cheat and use the KSEG mapping for its code+data | |
208 | rather than physical addresses. | |
209 | ||
210 | Moreover, we're only emulating Unix PALcode, and not attempting VMS. | |
211 | ||
212 | All of which allows us to drop all but kernel and user modes. | |
213 | Elide the unused MMU modes to save space. */ | |
4c9649a9 | 214 | |
8417845e RH |
215 | #define NB_MMU_MODES 2 |
216 | ||
217 | #define MMU_MODE0_SUFFIX _kernel | |
218 | #define MMU_MODE1_SUFFIX _user | |
219 | #define MMU_KERNEL_IDX 0 | |
220 | #define MMU_USER_IDX 1 | |
221 | ||
222 | typedef struct CPUAlphaState CPUAlphaState; | |
6ebbf390 | 223 | |
4c9649a9 JM |
224 | struct CPUAlphaState { |
225 | uint64_t ir[31]; | |
8443effb | 226 | float64 fir[31]; |
4c9649a9 | 227 | uint64_t pc; |
4c9649a9 | 228 | uint64_t unique; |
6910b8f6 RH |
229 | uint64_t lock_addr; |
230 | uint64_t lock_st_addr; | |
231 | uint64_t lock_value; | |
8443effb RH |
232 | float_status fp_status; |
233 | /* The following fields make up the FPCR, but in FP_STATUS format. */ | |
234 | uint8_t fpcr_exc_status; | |
235 | uint8_t fpcr_exc_mask; | |
236 | uint8_t fpcr_dyn_round; | |
237 | uint8_t fpcr_flush_to_zero; | |
238 | uint8_t fpcr_dnz; | |
239 | uint8_t fpcr_dnod; | |
240 | uint8_t fpcr_undz; | |
241 | ||
129d8aa5 RH |
242 | /* The Internal Processor Registers. Some of these we assume always |
243 | exist for use in user-mode. */ | |
244 | uint8_t ps; | |
8443effb | 245 | uint8_t intr_flag; |
129d8aa5 RH |
246 | uint8_t pal_mode; |
247 | ||
248 | /* These pass data from the exception logic in the translator and | |
249 | helpers to the OS entry point. This is used for both system | |
250 | emulation and user-mode. */ | |
251 | uint64_t trap_arg0; | |
252 | uint64_t trap_arg1; | |
253 | uint64_t trap_arg2; | |
4c9649a9 | 254 | |
bf9525e9 JM |
255 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
256 | /* temporary fixed-point registers | |
257 | * used to emulate 64 bits target on 32 bits hosts | |
5fafdf24 | 258 | */ |
04acd307 | 259 | target_ulong t0, t1; |
bf9525e9 | 260 | #endif |
4c9649a9 JM |
261 | |
262 | /* Those resources are used only in Qemu core */ | |
263 | CPU_COMMON | |
264 | ||
4c9649a9 | 265 | int error_code; |
4c9649a9 JM |
266 | |
267 | uint32_t features; | |
268 | uint32_t amask; | |
269 | int implver; | |
4c9649a9 JM |
270 | }; |
271 | ||
9467d44c TS |
272 | #define cpu_init cpu_alpha_init |
273 | #define cpu_exec cpu_alpha_exec | |
274 | #define cpu_gen_code cpu_alpha_gen_code | |
275 | #define cpu_signal_handler cpu_alpha_signal_handler | |
276 | ||
6ebbf390 JM |
277 | static inline int cpu_mmu_index (CPUState *env) |
278 | { | |
8417845e | 279 | return (env->ps >> 3) & 1; |
6ebbf390 JM |
280 | } |
281 | ||
4c9649a9 JM |
282 | #include "cpu-all.h" |
283 | ||
284 | enum { | |
285 | FEATURE_ASN = 0x00000001, | |
286 | FEATURE_SPS = 0x00000002, | |
287 | FEATURE_VIRBND = 0x00000004, | |
288 | FEATURE_TBCHK = 0x00000008, | |
289 | }; | |
290 | ||
291 | enum { | |
07b6c13b RH |
292 | EXCP_RESET, |
293 | EXCP_MCHK, | |
294 | EXCP_SMP_INTERRUPT, | |
295 | EXCP_CLK_INTERRUPT, | |
296 | EXCP_DEV_INTERRUPT, | |
297 | EXCP_MMFAULT, | |
298 | EXCP_UNALIGN, | |
299 | EXCP_OPCDEC, | |
300 | EXCP_ARITH, | |
301 | EXCP_FEN, | |
302 | EXCP_CALL_PAL, | |
303 | /* For Usermode emulation. */ | |
304 | EXCP_STL_C, | |
305 | EXCP_STQ_C, | |
4c9649a9 JM |
306 | }; |
307 | ||
308 | /* Arithmetic exception */ | |
866be65d RH |
309 | #define EXC_M_IOV (1<<16) /* Integer Overflow */ |
310 | #define EXC_M_INE (1<<15) /* Inexact result */ | |
311 | #define EXC_M_UNF (1<<14) /* Underflow */ | |
312 | #define EXC_M_FOV (1<<13) /* Overflow */ | |
313 | #define EXC_M_DZE (1<<12) /* Division by zero */ | |
314 | #define EXC_M_INV (1<<11) /* Invalid operation */ | |
315 | #define EXC_M_SWC (1<<10) /* Software completion */ | |
4c9649a9 | 316 | |
4c9649a9 JM |
317 | enum { |
318 | IR_V0 = 0, | |
319 | IR_T0 = 1, | |
320 | IR_T1 = 2, | |
321 | IR_T2 = 3, | |
322 | IR_T3 = 4, | |
323 | IR_T4 = 5, | |
324 | IR_T5 = 6, | |
325 | IR_T6 = 7, | |
326 | IR_T7 = 8, | |
327 | IR_S0 = 9, | |
328 | IR_S1 = 10, | |
329 | IR_S2 = 11, | |
330 | IR_S3 = 12, | |
331 | IR_S4 = 13, | |
332 | IR_S5 = 14, | |
333 | IR_S6 = 15, | |
a4b388ff | 334 | IR_FP = IR_S6, |
4c9649a9 JM |
335 | IR_A0 = 16, |
336 | IR_A1 = 17, | |
337 | IR_A2 = 18, | |
338 | IR_A3 = 19, | |
339 | IR_A4 = 20, | |
340 | IR_A5 = 21, | |
341 | IR_T8 = 22, | |
342 | IR_T9 = 23, | |
343 | IR_T10 = 24, | |
344 | IR_T11 = 25, | |
345 | IR_RA = 26, | |
346 | IR_T12 = 27, | |
a4b388ff | 347 | IR_PV = IR_T12, |
4c9649a9 JM |
348 | IR_AT = 28, |
349 | IR_GP = 29, | |
350 | IR_SP = 30, | |
351 | IR_ZERO = 31, | |
352 | }; | |
353 | ||
aaed909a | 354 | CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
e96efcfc JM |
355 | int cpu_alpha_exec(CPUAlphaState *s); |
356 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
357 | signal handlers to inform the virtual CPU of exceptions. non zero | |
358 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 359 | int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
e96efcfc | 360 | void *puc); |
95870356 AJ |
361 | int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, |
362 | int mmu_idx, int is_softmmu); | |
0b5c1ce8 | 363 | #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault |
95870356 AJ |
364 | void do_interrupt (CPUState *env); |
365 | ||
ba0e276d RH |
366 | uint64_t cpu_alpha_load_fpcr (CPUState *env); |
367 | void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); | |
4c9649a9 | 368 | |
6b917547 AL |
369 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
370 | target_ulong *cs_base, int *flags) | |
371 | { | |
372 | *pc = env->pc; | |
373 | *cs_base = 0; | |
374 | *flags = env->ps; | |
375 | } | |
376 | ||
a4b388ff RH |
377 | #if defined(CONFIG_USER_ONLY) |
378 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
379 | { | |
380 | if (newsp) { | |
381 | env->ir[IR_SP] = newsp; | |
382 | } | |
383 | env->ir[IR_V0] = 0; | |
384 | env->ir[IR_A3] = 0; | |
385 | } | |
386 | ||
387 | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) | |
388 | { | |
389 | env->unique = newtls; | |
390 | } | |
391 | #endif | |
392 | ||
4c9649a9 | 393 | #endif /* !defined (__CPU_ALPHA_H__) */ |