[qemu.git] / target-alpha / cpu.h

/*
 *  Alpha emulation cpu definitions for qemu.
 *
 *  Copyright (c) 2007 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#if !defined (__CPU_ALPHA_H__)
#define __CPU_ALPHA_H__

#include "config.h"
#include "qemu-common.h"

#define TARGET_LONG_BITS 64

#define CPUArchState struct CPUAlphaState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define ELF_MACHINE     EM_ALPHA

#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32

#define TARGET_PAGE_BITS 13

/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
#define TARGET_PHYS_ADDR_SPACE_BITS	44
#define TARGET_VIRT_ADDR_SPACE_BITS	(30 + TARGET_PAGE_BITS)

/* Alpha major type */
enum {
    ALPHA_EV3  = 1,
    ALPHA_EV4  = 2,
    ALPHA_SIM  = 3,
    ALPHA_LCA  = 4,
    ALPHA_EV5  = 5, /* 21164 */
    ALPHA_EV45 = 6, /* 21064A */
    ALPHA_EV56 = 7, /* 21164A */
};

/* EV4 minor type */
enum {
    ALPHA_EV4_2 = 0,
    ALPHA_EV4_3 = 1,
};

/* LCA minor type */
enum {
    ALPHA_LCA_1 = 1, /* 21066 */
    ALPHA_LCA_2 = 2, /* 20166 */
    ALPHA_LCA_3 = 3, /* 21068 */
    ALPHA_LCA_4 = 4, /* 21068 */
    ALPHA_LCA_5 = 5, /* 21066A */
    ALPHA_LCA_6 = 6, /* 21068A */
};

/* EV5 minor type */
enum {
    ALPHA_EV5_1 = 1, /* Rev BA, CA */
    ALPHA_EV5_2 = 2, /* Rev DA, EA */
    ALPHA_EV5_3 = 3, /* Pass 3 */
    ALPHA_EV5_4 = 4, /* Pass 3.2 */
    ALPHA_EV5_5 = 5, /* Pass 4 */
};

/* EV45 minor type */
enum {
    ALPHA_EV45_1 = 1, /* Pass 1 */
    ALPHA_EV45_2 = 2, /* Pass 1.1 */
    ALPHA_EV45_3 = 3, /* Pass 2 */
};

/* EV56 minor type */
enum {
    ALPHA_EV56_1 = 1, /* Pass 1 */
    ALPHA_EV56_2 = 2, /* Pass 2 */
};

enum {
    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
    IMPLVER_21364 = 3, /* EV7 & EV79 */
};

enum {
    AMASK_BWX      = 0x00000001,
    AMASK_FIX      = 0x00000002,
    AMASK_CIX      = 0x00000004,
    AMASK_MVI      = 0x00000100,
    AMASK_TRAP     = 0x00000200,
    AMASK_PREFETCH = 0x00001000,
};

enum {
    VAX_ROUND_NORMAL = 0,
    VAX_ROUND_CHOPPED,
};

enum {
    IEEE_ROUND_NORMAL = 0,
    IEEE_ROUND_DYNAMIC,
    IEEE_ROUND_PLUS,
    IEEE_ROUND_MINUS,
    IEEE_ROUND_CHOPPED,
};

/* IEEE floating-point operations encoding */
/* Trap mode */
enum {
    FP_TRAP_I   = 0x0,
    FP_TRAP_U   = 0x1,
    FP_TRAP_S  = 0x4,
    FP_TRAP_SU  = 0x5,
    FP_TRAP_SUI = 0x7,
};

/* Rounding mode */
enum {
    FP_ROUND_CHOPPED = 0x0,
    FP_ROUND_MINUS   = 0x1,
    FP_ROUND_NORMAL  = 0x2,
    FP_ROUND_DYNAMIC = 0x3,
};

/* FPCR bits */
#define FPCR_SUM		(1ULL << 63)
#define FPCR_INED		(1ULL << 62)
#define FPCR_UNFD		(1ULL << 61)
#define FPCR_UNDZ		(1ULL << 60)
#define FPCR_DYN_SHIFT		58
#define FPCR_DYN_CHOPPED	(0ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MINUS		(1ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_NORMAL		(2ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_PLUS		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MASK		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_IOV		(1ULL << 57)
#define FPCR_INE		(1ULL << 56)
#define FPCR_UNF		(1ULL << 55)
#define FPCR_OVF		(1ULL << 54)
#define FPCR_DZE		(1ULL << 53)
#define FPCR_INV		(1ULL << 52)
#define FPCR_OVFD		(1ULL << 51)
#define FPCR_DZED		(1ULL << 50)
#define FPCR_INVD		(1ULL << 49)
#define FPCR_DNZ		(1ULL << 48)
#define FPCR_DNOD		(1ULL << 47)
#define FPCR_STATUS_MASK	(FPCR_IOV | FPCR_INE | FPCR_UNF \
				 | FPCR_OVF | FPCR_DZE | FPCR_INV)

/* The silly software trap enables implemented by the kernel emulation.
   These are more or less architecturally required, since the real hardware
   has read-as-zero bits in the FPCR when the features aren't implemented.
   For the purposes of QEMU, we pretend the FPCR can hold everything.  */
#define SWCR_TRAP_ENABLE_INV	(1ULL << 1)
#define SWCR_TRAP_ENABLE_DZE	(1ULL << 2)
#define SWCR_TRAP_ENABLE_OVF	(1ULL << 3)
#define SWCR_TRAP_ENABLE_UNF	(1ULL << 4)
#define SWCR_TRAP_ENABLE_INE	(1ULL << 5)
#define SWCR_TRAP_ENABLE_DNO	(1ULL << 6)
#define SWCR_TRAP_ENABLE_MASK	((1ULL << 7) - (1ULL << 1))

#define SWCR_MAP_DMZ		(1ULL << 12)
#define SWCR_MAP_UMZ		(1ULL << 13)
#define SWCR_MAP_MASK		(SWCR_MAP_DMZ | SWCR_MAP_UMZ)

#define SWCR_STATUS_INV		(1ULL << 17)
#define SWCR_STATUS_DZE		(1ULL << 18)
#define SWCR_STATUS_OVF		(1ULL << 19)
#define SWCR_STATUS_UNF		(1ULL << 20)
#define SWCR_STATUS_INE		(1ULL << 21)
#define SWCR_STATUS_DNO		(1ULL << 22)
#define SWCR_STATUS_MASK	((1ULL << 23) - (1ULL << 17))

#define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)

/* MMU modes definitions */

/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
   The Unix PALcode only exposes the kernel and user modes; presumably
   executive and supervisor are used by VMS.

   PALcode itself uses physical mode for code and kernel mode for data;
   there are PALmode instructions that can access data via physical mode
   or via an os-installed "alternate mode", which is one of the 4 above.

   QEMU does not currently properly distinguish between code/data when
   looking up addresses.  To avoid having to address this issue, our
   emulated PALcode will cheat and use the KSEG mapping for its code+data
   rather than physical addresses.

   Moreover, we're only emulating Unix PALcode, and not attempting VMS.

   All of which allows us to drop all but kernel and user modes.
   Elide the unused MMU modes to save space.  */

#define NB_MMU_MODES 2

#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX   0
#define MMU_USER_IDX     1

typedef struct CPUAlphaState CPUAlphaState;

struct CPUAlphaState {
    uint64_t ir[31];
    float64 fir[31];
    uint64_t pc;
    uint64_t unique;
    uint64_t lock_addr;
    uint64_t lock_st_addr;
    uint64_t lock_value;
    float_status fp_status;
    /* The following fields make up the FPCR, but in FP_STATUS format.  */
    uint8_t fpcr_exc_status;
    uint8_t fpcr_exc_mask;
    uint8_t fpcr_dyn_round;
    uint8_t fpcr_flush_to_zero;
    uint8_t fpcr_dnod;
    uint8_t fpcr_undz;

    /* The Internal Processor Registers.  Some of these we assume always
       exist for use in user-mode.  */
    uint8_t ps;
    uint8_t intr_flag;
    uint8_t pal_mode;
    uint8_t fen;

    uint32_t pcc_ofs;

    /* These pass data from the exception logic in the translator and
       helpers to the OS entry point.  This is used for both system
       emulation and user-mode.  */
    uint64_t trap_arg0;
    uint64_t trap_arg1;
    uint64_t trap_arg2;

#if !defined(CONFIG_USER_ONLY)
    /* The internal data required by our emulation of the Unix PALcode.  */
    uint64_t exc_addr;
    uint64_t palbr;
    uint64_t ptbr;
    uint64_t vptptr;
    uint64_t sysval;
    uint64_t usp;
    uint64_t shadow[8];
    uint64_t scratch[24];
#endif

    /* This alarm doesn't exist in real hardware; we wish it did.  */
    struct QEMUTimer *alarm_timer;
    uint64_t alarm_expire;

#if TARGET_LONG_BITS > HOST_LONG_BITS
    /* temporary fixed-point registers
     * used to emulate 64 bits target on 32 bits hosts
     */
    target_ulong t0, t1;
#endif

    /* Those resources are used only in QEMU core */
    CPU_COMMON

    int error_code;

    uint32_t features;
    uint32_t amask;
    int implver;
};

#define cpu_init cpu_alpha_init
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler

#include "cpu-all.h"
#include "cpu-qom.h"

enum {
    FEATURE_ASN    = 0x00000001,
    FEATURE_SPS    = 0x00000002,
    FEATURE_VIRBND = 0x00000004,
    FEATURE_TBCHK  = 0x00000008,
};

enum {
    EXCP_RESET,
    EXCP_MCHK,
    EXCP_SMP_INTERRUPT,
    EXCP_CLK_INTERRUPT,
    EXCP_DEV_INTERRUPT,
    EXCP_MMFAULT,
    EXCP_UNALIGN,
    EXCP_OPCDEC,
    EXCP_ARITH,
    EXCP_FEN,
    EXCP_CALL_PAL,
    /* For Usermode emulation.  */
    EXCP_STL_C,
    EXCP_STQ_C,
};

/* Alpha-specific interrupt pending bits.  */
#define CPU_INTERRUPT_TIMER	CPU_INTERRUPT_TGT_EXT_0
#define CPU_INTERRUPT_SMP	CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_MCHK	CPU_INTERRUPT_TGT_EXT_2

/* OSF/1 Page table bits.  */
enum {
    PTE_VALID = 0x0001,
    PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
    PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
    PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
    PTE_ASM   = 0x0010,
    PTE_KRE   = 0x0100,
    PTE_URE   = 0x0200,
    PTE_KWE   = 0x1000,
    PTE_UWE   = 0x2000
};

/* Hardware interrupt (entInt) constants.  */
enum {
    INT_K_IP,
    INT_K_CLK,
    INT_K_MCHK,
    INT_K_DEV,
    INT_K_PERF,
};

/* Memory management (entMM) constants.  */
enum {
    MM_K_TNV,
    MM_K_ACV,
    MM_K_FOR,
    MM_K_FOE,
    MM_K_FOW
};

/* Arithmetic exception (entArith) constants.  */
enum {
    EXC_M_SWC = 1,      /* Software completion */
    EXC_M_INV = 2,      /* Invalid operation */
    EXC_M_DZE = 4,      /* Division by zero */
    EXC_M_FOV = 8,      /* Overflow */
    EXC_M_UNF = 16,     /* Underflow */
    EXC_M_INE = 32,     /* Inexact result */
    EXC_M_IOV = 64      /* Integer Overflow */
};

/* Processor status constants.  */
enum {
    /* Low 3 bits are interrupt mask level.  */
    PS_INT_MASK = 7,

    /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
       The Unix PALcode only uses bit 4.  */
    PS_USER_MODE = 8
};

static inline int cpu_mmu_index(CPUAlphaState *env)
{
    if (env->pal_mode) {
        return MMU_KERNEL_IDX;
    } else if (env->ps & PS_USER_MODE) {
        return MMU_USER_IDX;
    } else {
        return MMU_KERNEL_IDX;
    }
}

enum {
    IR_V0   = 0,
    IR_T0   = 1,
    IR_T1   = 2,
    IR_T2   = 3,
    IR_T3   = 4,
    IR_T4   = 5,
    IR_T5   = 6,
    IR_T6   = 7,
    IR_T7   = 8,
    IR_S0   = 9,
    IR_S1   = 10,
    IR_S2   = 11,
    IR_S3   = 12,
    IR_S4   = 13,
    IR_S5   = 14,
    IR_S6   = 15,
    IR_FP   = IR_S6,
    IR_A0   = 16,
    IR_A1   = 17,
    IR_A2   = 18,
    IR_A3   = 19,
    IR_A4   = 20,
    IR_A5   = 21,
    IR_T8   = 22,
    IR_T9   = 23,
    IR_T10  = 24,
    IR_T11  = 25,
    IR_RA   = 26,
    IR_T12  = 27,
    IR_PV   = IR_T12,
    IR_AT   = 28,
    IR_GP   = 29,
    IR_SP   = 30,
    IR_ZERO = 31,
};

CPUAlphaState * cpu_alpha_init (const char *cpu_model);
int cpu_alpha_exec(CPUAlphaState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
                             void *puc);
int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
                                int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
void do_interrupt (CPUAlphaState *env);
void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);

uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUAlphaState *env);
QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
                                         target_phys_addr_t addr, int is_write,
                                         int is_exec, int unused, int size);
#endif

/* Bits in TB->FLAGS that control how translation is processed.  */
enum {
    TB_FLAGS_PAL_MODE = 1,
    TB_FLAGS_FEN = 2,
    TB_FLAGS_USER_MODE = 8,

    TB_FLAGS_AMASK_SHIFT = 4,
    TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};

static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *pflags)
{
    int flags = 0;

    *pc = env->pc;
    *cs_base = 0;

    if (env->pal_mode) {
        flags = TB_FLAGS_PAL_MODE;
    } else {
        flags = env->ps & PS_USER_MODE;
    }
    if (env->fen) {
        flags |= TB_FLAGS_FEN;
    }
    flags |= env->amask << TB_FLAGS_AMASK_SHIFT;

    *pflags = flags;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
{
    if (newsp) {
        env->ir[IR_SP] = newsp;
    }
    env->ir[IR_V0] = 0;
    env->ir[IR_A3] = 0;
}

static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
{
    env->unique = newtls;
}
#endif

static inline bool cpu_has_work(CPUAlphaState *env)
{
    /* Here we are checking to see if the CPU should wake up from HALT.
       We will have gotten into this state only for WTINT from PALmode.  */
    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
       asleep even if (some) interrupts have been asserted.  For now,
       assume that if a CPU really wants to stay asleep, it will mask
       interrupts at the chipset level, which will prevent these bits
       from being set in the first place.  */
    return env->interrupt_request & (CPU_INTERRUPT_HARD
                                     | CPU_INTERRUPT_TIMER
                                     | CPU_INTERRUPT_SMP
                                     | CPU_INTERRUPT_MCHK);
}

#include "exec-all.h"

static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif /* !defined (__CPU_ALPHA_H__) */
Commit	Line	Data
4c9649a9 JM	1	/*
4c9649a9 JM	2	* Alpha emulation cpu definitions for qemu.
5fafdf24	3	*
4c9649a9 JM	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4c9649a9 JM	18	*/
	19
	20	#if !defined (__CPU_ALPHA_H__)
	21	#define __CPU_ALPHA_H__
	22
	23	#include "config.h"
2c976297	24	#include "qemu-common.h"
4c9649a9 JM	25
	26	#define TARGET_LONG_BITS 64
	27
9349b4f9	28	#define CPUArchState struct CPUAlphaState
c2764719	29
4c9649a9 JM	30	#include "cpu-defs.h"
4c9649a9 JM	31
4c9649a9 JM	32	#include "softfloat.h"
4c9649a9 JM	33
4c9649a9 JM	34	#define TARGET_HAS_ICE 1
4c9649a9 JM	35
f071b4d3	36	#define ELF_MACHINE EM_ALPHA
4c9649a9 JM	37
	38	#define ICACHE_LINE_SIZE 32
	39	#define DCACHE_LINE_SIZE 32
	40
b09d9d46	41	#define TARGET_PAGE_BITS 13
4c9649a9	42
52705890 RH	43	/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
	44	#define TARGET_PHYS_ADDR_SPACE_BITS 44
	45	#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
4c9649a9 JM	46
	47	/* Alpha major type */
	48	enum {
	49	ALPHA_EV3 = 1,
	50	ALPHA_EV4 = 2,
	51	ALPHA_SIM = 3,
	52	ALPHA_LCA = 4,
	53	ALPHA_EV5 = 5, /* 21164 */
	54	ALPHA_EV45 = 6, /* 21064A */
	55	ALPHA_EV56 = 7, /* 21164A */
	56	};
	57
	58	/* EV4 minor type */
	59	enum {
	60	ALPHA_EV4_2 = 0,
	61	ALPHA_EV4_3 = 1,
	62	};
	63
	64	/* LCA minor type */
	65	enum {
	66	ALPHA_LCA_1 = 1, /* 21066 */
	67	ALPHA_LCA_2 = 2, /* 20166 */
	68	ALPHA_LCA_3 = 3, /* 21068 */
	69	ALPHA_LCA_4 = 4, /* 21068 */
	70	ALPHA_LCA_5 = 5, /* 21066A */
	71	ALPHA_LCA_6 = 6, /* 21068A */
	72	};
	73
	74	/* EV5 minor type */
	75	enum {
	76	ALPHA_EV5_1 = 1, /* Rev BA, CA */
	77	ALPHA_EV5_2 = 2, /* Rev DA, EA */
	78	ALPHA_EV5_3 = 3, /* Pass 3 */
	79	ALPHA_EV5_4 = 4, /* Pass 3.2 */
	80	ALPHA_EV5_5 = 5, /* Pass 4 */
	81	};
	82
	83	/* EV45 minor type */
	84	enum {
	85	ALPHA_EV45_1 = 1, /* Pass 1 */
	86	ALPHA_EV45_2 = 2, /* Pass 1.1 */
	87	ALPHA_EV45_3 = 3, /* Pass 2 */
	88	};
	89
	90	/* EV56 minor type */
	91	enum {
	92	ALPHA_EV56_1 = 1, /* Pass 1 */
	93	ALPHA_EV56_2 = 2, /* Pass 2 */
	94	};
	95
	96	enum {
	97	IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
	98	IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
	99	IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
	100	IMPLVER_21364 = 3, /* EV7 & EV79 */
	101	};
	102
	103	enum {
	104	AMASK_BWX = 0x00000001,
	105	AMASK_FIX = 0x00000002,
	106	AMASK_CIX = 0x00000004,
	107	AMASK_MVI = 0x00000100,
	108	AMASK_TRAP = 0x00000200,
	109	AMASK_PREFETCH = 0x00001000,
110	};
111
112	enum {
113	VAX_ROUND_NORMAL = 0,
114	VAX_ROUND_CHOPPED,
115	};
116
117	enum {
118	IEEE_ROUND_NORMAL = 0,
119	IEEE_ROUND_DYNAMIC,
120	IEEE_ROUND_PLUS,
121	IEEE_ROUND_MINUS,
122	IEEE_ROUND_CHOPPED,
123	};
124
125	/* IEEE floating-point operations encoding */
126	/* Trap mode */
127	enum {
128	FP_TRAP_I = 0x0,
129	FP_TRAP_U = 0x1,
130	FP_TRAP_S = 0x4,
131	FP_TRAP_SU = 0x5,
132	FP_TRAP_SUI = 0x7,
133	};
134
135	/* Rounding mode */
136	enum {
137	FP_ROUND_CHOPPED = 0x0,
138	FP_ROUND_MINUS = 0x1,
139	FP_ROUND_NORMAL = 0x2,
140	FP_ROUND_DYNAMIC = 0x3,
141	};
142
ba0e276d RH	143	/* FPCR bits */
	144	#define FPCR_SUM (1ULL << 63)
	145	#define FPCR_INED (1ULL << 62)
	146	#define FPCR_UNFD (1ULL << 61)
	147	#define FPCR_UNDZ (1ULL << 60)
	148	#define FPCR_DYN_SHIFT 58
8443effb RH	149	#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
	150	#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
	151	#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
	152	#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
ba0e276d RH	153	#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
	154	#define FPCR_IOV (1ULL << 57)
	155	#define FPCR_INE (1ULL << 56)
	156	#define FPCR_UNF (1ULL << 55)
	157	#define FPCR_OVF (1ULL << 54)
	158	#define FPCR_DZE (1ULL << 53)
	159	#define FPCR_INV (1ULL << 52)
	160	#define FPCR_OVFD (1ULL << 51)
	161	#define FPCR_DZED (1ULL << 50)
	162	#define FPCR_INVD (1ULL << 49)
	163	#define FPCR_DNZ (1ULL << 48)
	164	#define FPCR_DNOD (1ULL << 47)
	165	#define FPCR_STATUS_MASK (FPCR_IOV \| FPCR_INE \| FPCR_UNF \
	166	\| FPCR_OVF \| FPCR_DZE \| FPCR_INV)
	167
	168	/* The silly software trap enables implemented by the kernel emulation.
	169	These are more or less architecturally required, since the real hardware
	170	has read-as-zero bits in the FPCR when the features aren't implemented.
	171	For the purposes of QEMU, we pretend the FPCR can hold everything. */
	172	#define SWCR_TRAP_ENABLE_INV (1ULL << 1)
	173	#define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
	174	#define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
	175	#define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
	176	#define SWCR_TRAP_ENABLE_INE (1ULL << 5)
	177	#define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
	178	#define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
	179
	180	#define SWCR_MAP_DMZ (1ULL << 12)
	181	#define SWCR_MAP_UMZ (1ULL << 13)
	182	#define SWCR_MAP_MASK (SWCR_MAP_DMZ \| SWCR_MAP_UMZ)
	183
	184	#define SWCR_STATUS_INV (1ULL << 17)
	185	#define SWCR_STATUS_DZE (1ULL << 18)
	186	#define SWCR_STATUS_OVF (1ULL << 19)
	187	#define SWCR_STATUS_UNF (1ULL << 20)
	188	#define SWCR_STATUS_INE (1ULL << 21)
	189	#define SWCR_STATUS_DNO (1ULL << 22)
	190	#define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
	191
	192	#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK \| SWCR_MAP_MASK \| SWCR_STATUS_MASK)
	193
8417845e RH	194	/* MMU modes definitions */
	195
	196	/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
	197	The Unix PALcode only exposes the kernel and user modes; presumably
	198	executive and supervisor are used by VMS.
	199
	200	PALcode itself uses physical mode for code and kernel mode for data;
	201	there are PALmode instructions that can access data via physical mode
	202	or via an os-installed "alternate mode", which is one of the 4 above.
	203
	204	QEMU does not currently properly distinguish between code/data when
	205	looking up addresses. To avoid having to address this issue, our
	206	emulated PALcode will cheat and use the KSEG mapping for its code+data
	207	rather than physical addresses.
	208
	209	Moreover, we're only emulating Unix PALcode, and not attempting VMS.
	210
	211	All of which allows us to drop all but kernel and user modes.
	212	Elide the unused MMU modes to save space. */
4c9649a9	213
8417845e RH	214	#define NB_MMU_MODES 2
	215
	216	#define MMU_MODE0_SUFFIX _kernel
	217	#define MMU_MODE1_SUFFIX _user
	218	#define MMU_KERNEL_IDX 0
	219	#define MMU_USER_IDX 1
	220
	221	typedef struct CPUAlphaState CPUAlphaState;
6ebbf390	222
4c9649a9 JM	223	struct CPUAlphaState {
4c9649a9 JM	224	uint64_t ir[31];
8443effb	225	float64 fir[31];
4c9649a9	226	uint64_t pc;
4c9649a9	227	uint64_t unique;
6910b8f6 RH	228	uint64_t lock_addr;
	229	uint64_t lock_st_addr;
	230	uint64_t lock_value;
8443effb RH	231	float_status fp_status;
	232	/* The following fields make up the FPCR, but in FP_STATUS format. */
	233	uint8_t fpcr_exc_status;
	234	uint8_t fpcr_exc_mask;
	235	uint8_t fpcr_dyn_round;
	236	uint8_t fpcr_flush_to_zero;
8443effb RH	237	uint8_t fpcr_dnod;
	238	uint8_t fpcr_undz;
	239
129d8aa5 RH	240	/* The Internal Processor Registers. Some of these we assume always
	241	exist for use in user-mode. */
	242	uint8_t ps;
8443effb	243	uint8_t intr_flag;
129d8aa5	244	uint8_t pal_mode;
26b46094 RH	245	uint8_t fen;
	246
	247	uint32_t pcc_ofs;
129d8aa5 RH	248
	249	/* These pass data from the exception logic in the translator and
	250	helpers to the OS entry point. This is used for both system
	251	emulation and user-mode. */
	252	uint64_t trap_arg0;
	253	uint64_t trap_arg1;
	254	uint64_t trap_arg2;
4c9649a9	255
26b46094 RH	256	#if !defined(CONFIG_USER_ONLY)
	257	/* The internal data required by our emulation of the Unix PALcode. */
	258	uint64_t exc_addr;
	259	uint64_t palbr;
	260	uint64_t ptbr;
	261	uint64_t vptptr;
	262	uint64_t sysval;
	263	uint64_t usp;
	264	uint64_t shadow[8];
	265	uint64_t scratch[24];
	266	#endif
	267
c781cf96 RH	268	/* This alarm doesn't exist in real hardware; we wish it did. */
	269	struct QEMUTimer *alarm_timer;
	270	uint64_t alarm_expire;
	271
bf9525e9 JM	272	#if TARGET_LONG_BITS > HOST_LONG_BITS
	273	/* temporary fixed-point registers
	274	* used to emulate 64 bits target on 32 bits hosts
5fafdf24	275	*/
04acd307	276	target_ulong t0, t1;
bf9525e9	277	#endif
4c9649a9	278
5cbdb3a3	279	/* Those resources are used only in QEMU core */
4c9649a9 JM	280	CPU_COMMON
4c9649a9 JM	281
4c9649a9	282	int error_code;
4c9649a9 JM	283
	284	uint32_t features;
	285	uint32_t amask;
	286	int implver;
4c9649a9 JM	287	};
4c9649a9 JM	288
9467d44c TS	289	#define cpu_init cpu_alpha_init
	290	#define cpu_exec cpu_alpha_exec
	291	#define cpu_gen_code cpu_alpha_gen_code
	292	#define cpu_signal_handler cpu_alpha_signal_handler
	293
4c9649a9	294	#include "cpu-all.h"
25ebd80f	295	#include "cpu-qom.h"
4c9649a9 JM	296
	297	enum {
	298	FEATURE_ASN = 0x00000001,
	299	FEATURE_SPS = 0x00000002,
	300	FEATURE_VIRBND = 0x00000004,
	301	FEATURE_TBCHK = 0x00000008,
	302	};
	303
	304	enum {
07b6c13b RH	305	EXCP_RESET,
	306	EXCP_MCHK,
	307	EXCP_SMP_INTERRUPT,
	308	EXCP_CLK_INTERRUPT,
	309	EXCP_DEV_INTERRUPT,
	310	EXCP_MMFAULT,
	311	EXCP_UNALIGN,
	312	EXCP_OPCDEC,
	313	EXCP_ARITH,
	314	EXCP_FEN,
	315	EXCP_CALL_PAL,
	316	/* For Usermode emulation. */
	317	EXCP_STL_C,
	318	EXCP_STQ_C,
4c9649a9 JM	319	};
4c9649a9 JM	320
6a80e088 RH	321	/* Alpha-specific interrupt pending bits. */
	322	#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
	323	#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
	324	#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
	325
a3b9af16 RH	326	/* OSF/1 Page table bits. */
	327	enum {
	328	PTE_VALID = 0x0001,
	329	PTE_FOR = 0x0002, /* used for page protection (fault on read) */
	330	PTE_FOW = 0x0004, /* used for page protection (fault on write) */
	331	PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
	332	PTE_ASM = 0x0010,
	333	PTE_KRE = 0x0100,
	334	PTE_URE = 0x0200,
	335	PTE_KWE = 0x1000,
	336	PTE_UWE = 0x2000
	337	};
	338
ea879fc7 RH	339	/* Hardware interrupt (entInt) constants. */
	340	enum {
	341	INT_K_IP,
	342	INT_K_CLK,
	343	INT_K_MCHK,
	344	INT_K_DEV,
	345	INT_K_PERF,
	346	};
	347
	348	/* Memory management (entMM) constants. */
	349	enum {
	350	MM_K_TNV,
	351	MM_K_ACV,
	352	MM_K_FOR,
	353	MM_K_FOE,
	354	MM_K_FOW
	355	};
	356
	357	/* Arithmetic exception (entArith) constants. */
	358	enum {
	359	EXC_M_SWC = 1, /* Software completion */
	360	EXC_M_INV = 2, /* Invalid operation */
	361	EXC_M_DZE = 4, /* Division by zero */
	362	EXC_M_FOV = 8, /* Overflow */
	363	EXC_M_UNF = 16, /* Underflow */
	364	EXC_M_INE = 32, /* Inexact result */
	365	EXC_M_IOV = 64 /* Integer Overflow */
	366	};
	367
	368	/* Processor status constants. */
	369	enum {
	370	/* Low 3 bits are interrupt mask level. */
	371	PS_INT_MASK = 7,
	372
	373	/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
	374	The Unix PALcode only uses bit 4. */
	375	PS_USER_MODE = 8
	376	};
	377
4d5712f1	378	static inline int cpu_mmu_index(CPUAlphaState *env)
ea879fc7	379	{
bba9bdce RH	380	if (env->pal_mode) {
	381	return MMU_KERNEL_IDX;
	382	} else if (env->ps & PS_USER_MODE) {
	383	return MMU_USER_IDX;
	384	} else {
	385	return MMU_KERNEL_IDX;
	386	}
ea879fc7	387	}
4c9649a9	388
4c9649a9 JM	389	enum {
	390	IR_V0 = 0,
	391	IR_T0 = 1,
	392	IR_T1 = 2,
	393	IR_T2 = 3,
	394	IR_T3 = 4,
	395	IR_T4 = 5,
	396	IR_T5 = 6,
	397	IR_T6 = 7,
	398	IR_T7 = 8,
	399	IR_S0 = 9,
	400	IR_S1 = 10,
	401	IR_S2 = 11,
	402	IR_S3 = 12,
	403	IR_S4 = 13,
	404	IR_S5 = 14,
	405	IR_S6 = 15,
a4b388ff	406	IR_FP = IR_S6,
4c9649a9 JM	407	IR_A0 = 16,
	408	IR_A1 = 17,
	409	IR_A2 = 18,
	410	IR_A3 = 19,
	411	IR_A4 = 20,
	412	IR_A5 = 21,
	413	IR_T8 = 22,
	414	IR_T9 = 23,
	415	IR_T10 = 24,
	416	IR_T11 = 25,
	417	IR_RA = 26,
	418	IR_T12 = 27,
a4b388ff	419	IR_PV = IR_T12,
4c9649a9 JM	420	IR_AT = 28,
	421	IR_GP = 29,
	422	IR_SP = 30,
	423	IR_ZERO = 31,
	424	};
	425
aaed909a	426	CPUAlphaState * cpu_alpha_init (const char *cpu_model);
e96efcfc JM	427	int cpu_alpha_exec(CPUAlphaState *s);
	428	/* you can call this signal handler from your SIGBUS and SIGSEGV
	429	signal handlers to inform the virtual CPU of exceptions. non zero
	430	is returned if the signal was handled by the virtual CPU. */
5fafdf24	431	int cpu_alpha_signal_handler(int host_signum, void *pinfo,
e96efcfc	432	void *puc);
4d5712f1	433	int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
97b348e7	434	int mmu_idx);
0b5c1ce8	435	#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
4d5712f1	436	void do_interrupt (CPUAlphaState *env);
20503968 BS	437	void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
	438	void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
	439	void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
95870356	440
4d5712f1 AF	441	uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
4d5712f1 AF	442	void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
5b450407	443	#ifndef CONFIG_USER_ONLY
4d5712f1 AF	444	void swap_shadow_regs(CPUAlphaState *env);
4d5712f1 AF	445	QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
b14ef7c9 BS	446	target_phys_addr_t addr, int is_write,
b14ef7c9 BS	447	int is_exec, int unused, int size);
5b450407	448	#endif
4c9649a9	449
a18ad893 RH	450	/* Bits in TB->FLAGS that control how translation is processed. */
	451	enum {
	452	TB_FLAGS_PAL_MODE = 1,
	453	TB_FLAGS_FEN = 2,
	454	TB_FLAGS_USER_MODE = 8,
	455
	456	TB_FLAGS_AMASK_SHIFT = 4,
	457	TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
	458	TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
	459	TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
	460	TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
	461	TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
	462	TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
	463	};
	464
4d5712f1	465	static inline void cpu_get_tb_cpu_state(CPUAlphaState env, target_ulong pc,
a18ad893	466	target_ulong cs_base, int pflags)
6b917547	467	{
a18ad893 RH	468	int flags = 0;
a18ad893 RH	469
6b917547 AL	470	*pc = env->pc;
6b917547 AL	471	*cs_base = 0;
a18ad893 RH	472
	473	if (env->pal_mode) {
	474	flags = TB_FLAGS_PAL_MODE;
	475	} else {
	476	flags = env->ps & PS_USER_MODE;
	477	}
	478	if (env->fen) {
	479	flags \|= TB_FLAGS_FEN;
	480	}
	481	flags \|= env->amask << TB_FLAGS_AMASK_SHIFT;
	482
	483	*pflags = flags;
6b917547 AL	484	}
6b917547 AL	485
a4b388ff	486	#if defined(CONFIG_USER_ONLY)
4d5712f1	487	static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
a4b388ff RH	488	{
	489	if (newsp) {
	490	env->ir[IR_SP] = newsp;
	491	}
	492	env->ir[IR_V0] = 0;
	493	env->ir[IR_A3] = 0;
	494	}
	495
4d5712f1	496	static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
a4b388ff RH	497	{
	498	env->unique = newtls;
	499	}
	500	#endif
	501
4d5712f1	502	static inline bool cpu_has_work(CPUAlphaState *env)
f081c76c BS	503	{
	504	/* Here we are checking to see if the CPU should wake up from HALT.
	505	We will have gotten into this state only for WTINT from PALmode. */
	506	/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
	507	asleep even if (some) interrupts have been asserted. For now,
	508	assume that if a CPU really wants to stay asleep, it will mask
	509	interrupts at the chipset level, which will prevent these bits
	510	from being set in the first place. */
	511	return env->interrupt_request & (CPU_INTERRUPT_HARD
	512	\| CPU_INTERRUPT_TIMER
	513	\| CPU_INTERRUPT_SMP
	514	\| CPU_INTERRUPT_MCHK);
	515	}
	516
	517	#include "exec-all.h"
	518
4d5712f1	519	static inline void cpu_pc_from_tb(CPUAlphaState env, TranslationBlock tb)
f081c76c BS	520	{
	521	env->pc = tb->pc;
	522	}
	523
4c9649a9	524	#endif /* !defined (__CPU_ALPHA_H__) */