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alpha: directly access ir registers
[qemu.git] / target-alpha / translate.c
CommitLineData
4c9649a9
JM		 1/*
2 * Alpha emulation cpu translation for qemu.
5fafdf24 3 *
4c9649a9
JM		 4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <stdint.h>
22#include <stdlib.h>
23#include <stdio.h>
24
25#include "cpu.h"
26#include "exec-all.h"
27#include "disas.h"
496cb5b9 28#include "helper.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
4c9649a9
JM		 31
32#define DO_SINGLE_STEP
33#define GENERATE_NOP
34#define ALPHA_DEBUG_DISAS
35#define DO_TB_FLUSH
36
37typedef struct DisasContext DisasContext;
38struct DisasContext {
39 uint64_t pc;
40 int mem_idx;
41#if !defined (CONFIG_USER_ONLY)
42 int pal_mode;
43#endif
44 uint32_t amask;
45};
46
3761035f 47/* global register indexes */
b2437bf2 48static TCGv cpu_env;
496cb5b9
AJ		 49static TCGv cpu_ir[31];
50static TCGv cpu_pc;
51
3761035f
AJ		 52/* dyngen register indexes */
53static TCGv cpu_T[3];
54
55/* register names */
496cb5b9 56static char cpu_reg_names[5*31];
2e70f6ef
PB		 57
58#include "gen-icount.h"
59
a5f1b965 60static void alpha_translate_init(void)
2e70f6ef 61{
496cb5b9
AJ		 62 int i;
63 char *p;
2e70f6ef 64 static int done_init = 0;
496cb5b9 65
2e70f6ef
PB		 66 if (done_init)
67 return;
496cb5b9 68
2e70f6ef 69 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
496cb5b9 70
3761035f
AJ		 71#if TARGET_LONG_BITS > HOST_LONG_BITS
72 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
73 offsetof(CPUState, t0), "T0");
74 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
75 offsetof(CPUState, t1), "T1");
76 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
77 offsetof(CPUState, t2), "T2");
78#else
79 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
80 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
81 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");
82#endif
83
496cb5b9
AJ		 84 p = cpu_reg_names;
85 for (i = 0; i < 31; i++) {
86 sprintf(p, "ir%d", i);
87 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
88 offsetof(CPUState, ir[i]), p);
89 p += 4;
90 }
91
92 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
93 offsetof(CPUState, pc), "pc");
94
95 /* register helpers */
96#undef DEF_HELPER
97#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
98#include "helper.h"
99
2e70f6ef
PB		 100 done_init = 1;
101}
102
f071b4d3 103static always_inline void gen_op_nop (void)
4c9649a9
JM		 104{
105#if defined(GENERATE_NOP)
106 gen_op_no_op();
107#endif
108}
109
110#define GEN32(func, NAME) \
111static GenOpFunc *NAME ## _table [32] = { \
112NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
113NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
114NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
115NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
116NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
117NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
118NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
119NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
120}; \
f071b4d3 121static always_inline void func (int n) \
4c9649a9
JM		 122{ \
123 NAME ## _table[n](); \
124}
125
126/* IR moves */
127/* Special hacks for ir31 */
4c9649a9 128#define gen_op_cmov_ir31 gen_op_nop
4c9649a9
JM		 129GEN32(gen_op_cmov_ir, gen_op_cmov_ir);
130
4c9649a9
JM		 131/* FIR moves */
132/* Special hacks for fir31 */
133#define gen_op_load_FT0_fir31 gen_op_reset_FT0
134#define gen_op_load_FT1_fir31 gen_op_reset_FT1
135#define gen_op_load_FT2_fir31 gen_op_reset_FT2
136#define gen_op_store_FT0_fir31 gen_op_nop
137#define gen_op_store_FT1_fir31 gen_op_nop
138#define gen_op_store_FT2_fir31 gen_op_nop
139#define gen_op_cmov_fir31 gen_op_nop
140GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
141GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
142GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
143GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
144GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
145GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
146GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
147
f071b4d3 148static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 149{
150 switch (Tn) {
151 case 0:
152 gen_op_load_FT0_fir(firn);
153 break;
154 case 1:
155 gen_op_load_FT1_fir(firn);
156 break;
157 case 2:
158 gen_op_load_FT2_fir(firn);
159 break;
160 }
161}
162
f071b4d3 163static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 164{
165 switch (Tn) {
166 case 0:
167 gen_op_store_FT0_fir(firn);
168 break;
169 case 1:
170 gen_op_store_FT1_fir(firn);
171 break;
172 case 2:
173 gen_op_store_FT2_fir(firn);
174 break;
175 }
176}
177
178/* Memory moves */
179#if defined(CONFIG_USER_ONLY)
180#define OP_LD_TABLE(width) \
181static GenOpFunc *gen_op_ld##width[] = { \
182 &gen_op_ld##width##_raw, \
183}
184#define OP_ST_TABLE(width) \
185static GenOpFunc *gen_op_st##width[] = { \
186 &gen_op_st##width##_raw, \
187}
188#else
189#define OP_LD_TABLE(width) \
190static GenOpFunc *gen_op_ld##width[] = { \
191 &gen_op_ld##width##_kernel, \
bb6f6792
JM		 192 &gen_op_ld##width##_executive, \
193 &gen_op_ld##width##_supervisor, \
194 &gen_op_ld##width##_user, \
4c9649a9
JM		 195}
196#define OP_ST_TABLE(width) \
197static GenOpFunc *gen_op_st##width[] = { \
198 &gen_op_st##width##_kernel, \
bb6f6792
JM		 199 &gen_op_st##width##_executive, \
200 &gen_op_st##width##_supervisor, \
201 &gen_op_st##width##_user, \
4c9649a9
JM		 202}
203#endif
204
205#define GEN_LD(width) \
206OP_LD_TABLE(width); \
f071b4d3 207static always_inline void gen_ld##width (DisasContext *ctx) \
4c9649a9
JM		 208{ \
209 (*gen_op_ld##width[ctx->mem_idx])(); \
210}
211
212#define GEN_ST(width) \
213OP_ST_TABLE(width); \
f071b4d3 214static always_inline void gen_st##width (DisasContext *ctx) \
4c9649a9
JM		 215{ \
216 (*gen_op_st##width[ctx->mem_idx])(); \
217}
218
219GEN_LD(bu);
220GEN_ST(b);
221GEN_LD(wu);
222GEN_ST(w);
223GEN_LD(l);
224GEN_ST(l);
225GEN_LD(q);
226GEN_ST(q);
227GEN_LD(q_u);
228GEN_ST(q_u);
229GEN_LD(l_l);
230GEN_ST(l_c);
231GEN_LD(q_l);
232GEN_ST(q_c);
233
08ab123c 234#if 0 /* currently unused */
4c9649a9
JM		 235GEN_LD(f);
236GEN_ST(f);
237GEN_LD(g);
238GEN_ST(g);
08ab123c 239#endif /* 0 */
4c9649a9
JM		 240GEN_LD(s);
241GEN_ST(s);
242GEN_LD(t);
243GEN_ST(t);
244
f071b4d3 245static always_inline void _gen_op_bcond (DisasContext *ctx)
4c9649a9
JM		 246{
247#if 0 // Qemu does not know how to do this...
248 gen_op_bcond(ctx->pc);
249#else
250 gen_op_bcond(ctx->pc >> 32, ctx->pc);
251#endif
252}
253
f071b4d3
JM		 254static always_inline void gen_excp (DisasContext *ctx,
255 int exception, int error_code)
4c9649a9 256{
496cb5b9 257 tcg_gen_movi_i64(cpu_pc, ctx->pc);
4c9649a9
JM		 258 gen_op_excp(exception, error_code);
259}
260
f071b4d3 261static always_inline void gen_invalid (DisasContext *ctx)
4c9649a9
JM		 262{
263 gen_excp(ctx, EXCP_OPCDEC, 0);
264}
265
f071b4d3
JM		 266static always_inline void gen_load_mem (DisasContext *ctx,
267 void (*gen_load_op)(DisasContext *ctx),
268 int ra, int rb, int32_t disp16,
269 int clear)
4c9649a9
JM		 270{
271 if (ra == 31 && disp16 == 0) {
272 /* UNOP */
273 gen_op_nop();
274 } else {
3761035f
AJ		 275 if (rb != 31)
276 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
277 else
278 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 279 if (disp16 != 0) {
3761035f 280 tcg_gen_movi_i64(cpu_T[1], disp16);
4c9649a9
JM		 281 gen_op_addq();
282 }
283 if (clear)
284 gen_op_n7();
285 (*gen_load_op)(ctx);
3761035f
AJ		 286 if (ra != 31)
287 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 288 }
289}
290
f071b4d3
JM		 291static always_inline void gen_store_mem (DisasContext *ctx,
292 void (*gen_store_op)(DisasContext *ctx),
293 int ra, int rb, int32_t disp16,
294 int clear)
4c9649a9 295{
3761035f
AJ		 296 if (rb != 31)
297 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
298 else
299 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 300 if (disp16 != 0) {
3761035f 301 tcg_gen_movi_i64(cpu_T[1], disp16);
4c9649a9
JM		 302 gen_op_addq();
303 }
304 if (clear)
305 gen_op_n7();
3761035f
AJ		 306 if (ra != 31)
307 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
308 else
309 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 310 (*gen_store_op)(ctx);
311}
312
f071b4d3
JM		 313static always_inline void gen_load_fmem (DisasContext *ctx,
314 void (*gen_load_fop)(DisasContext *ctx),
315 int ra, int rb, int32_t disp16)
4c9649a9 316{
3761035f
AJ		 317 if (rb != 31)
318 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
319 else
320 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 321 if (disp16 != 0) {
3761035f 322 tcg_gen_movi_i64(cpu_T[1], disp16);
4c9649a9
JM		 323 gen_op_addq();
324 }
325 (*gen_load_fop)(ctx);
326 gen_store_fir(ctx, ra, 1);
327}
328
f071b4d3
JM		 329static always_inline void gen_store_fmem (DisasContext *ctx,
330 void (*gen_store_fop)(DisasContext *ctx),
331 int ra, int rb, int32_t disp16)
4c9649a9 332{
3761035f
AJ		 333 if (rb != 31)
334 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
335 else
336 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 337 if (disp16 != 0) {
3761035f 338 tcg_gen_movi_i64(cpu_T[1], disp16);
4c9649a9
JM		 339 gen_op_addq();
340 }
341 gen_load_fir(ctx, ra, 1);
342 (*gen_store_fop)(ctx);
343}
344
f071b4d3
JM		 345static always_inline void gen_bcond (DisasContext *ctx,
346 void (*gen_test_op)(void),
347 int ra, int32_t disp16)
4c9649a9
JM		 348{
349 if (disp16 != 0) {
3761035f
AJ		 350 tcg_gen_movi_i64(cpu_T[0], ctx->pc);
351 tcg_gen_movi_i64(cpu_T[1], disp16 << 2);
4c9649a9
JM		 352 gen_op_addq1();
353 } else {
3761035f 354 tcg_gen_movi_i64(cpu_T[1], ctx->pc);
4c9649a9 355 }
3761035f
AJ		 356 if (ra != 31)
357 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
358 else
359 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 360 (*gen_test_op)();
361 _gen_op_bcond(ctx);
362}
363
f071b4d3
JM		 364static always_inline void gen_fbcond (DisasContext *ctx,
365 void (*gen_test_op)(void),
366 int ra, int32_t disp16)
4c9649a9
JM		 367{
368 if (disp16 != 0) {
3761035f
AJ		 369 tcg_gen_movi_i64(cpu_T[0], ctx->pc);
370 tcg_gen_movi_i64(cpu_T[1], disp16 << 2);
4c9649a9
JM		 371 gen_op_addq1();
372 } else {
3761035f 373 tcg_gen_movi_i64(cpu_T[1], ctx->pc);
4c9649a9
JM		 374 }
375 gen_load_fir(ctx, ra, 0);
376 (*gen_test_op)();
377 _gen_op_bcond(ctx);
378}
379
f071b4d3
JM		 380static always_inline void gen_arith2 (DisasContext *ctx,
381 void (*gen_arith_op)(void),
382 int rb, int rc, int islit, int8_t lit)
4c9649a9
JM		 383{
384 if (islit)
3761035f
AJ		 385 tcg_gen_movi_i64(cpu_T[0], lit);
386 else if (rb != 31)
387 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
4c9649a9 388 else
3761035f 389 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 390 (*gen_arith_op)();
3761035f
AJ		 391 if (rc != 31)
392 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
4c9649a9
JM		 393}
394
f071b4d3
JM		 395static always_inline void gen_arith3 (DisasContext *ctx,
396 void (*gen_arith_op)(void),
397 int ra, int rb, int rc,
398 int islit, int8_t lit)
4c9649a9 399{
3761035f
AJ		 400 if (ra != 31)
401 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
402 else
403 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 404 if (islit)
3761035f
AJ		 405 tcg_gen_movi_i64(cpu_T[1], lit);
406 else if (rb != 31)
407 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
4c9649a9 408 else
3761035f 409 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9 410 (*gen_arith_op)();
3761035f
AJ		 411 if (rc != 31)
412 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
4c9649a9
JM		 413}
414
f071b4d3
JM		 415static always_inline void gen_cmov (DisasContext *ctx,
416 void (*gen_test_op)(void),
417 int ra, int rb, int rc,
418 int islit, int8_t lit)
4c9649a9 419{
3761035f
AJ		 420 if (ra != 31)
421 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
422 else
423 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9 424 if (islit)
3761035f
AJ		 425 tcg_gen_movi_i64(cpu_T[0], lit);
426 else if (rb != 31)
427 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
4c9649a9 428 else
3761035f 429 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 430 (*gen_test_op)();
431 gen_op_cmov_ir(rc);
432}
433
f071b4d3
JM		 434static always_inline void gen_farith2 (DisasContext *ctx,
435 void (*gen_arith_fop)(void),
436 int rb, int rc)
4c9649a9
JM		 437{
438 gen_load_fir(ctx, rb, 0);
439 (*gen_arith_fop)();
440 gen_store_fir(ctx, rc, 0);
441}
442
f071b4d3
JM		 443static always_inline void gen_farith3 (DisasContext *ctx,
444 void (*gen_arith_fop)(void),
445 int ra, int rb, int rc)
4c9649a9
JM		 446{
447 gen_load_fir(ctx, ra, 0);
448 gen_load_fir(ctx, rb, 1);
449 (*gen_arith_fop)();
450 gen_store_fir(ctx, rc, 0);
451}
452
f071b4d3
JM		 453static always_inline void gen_fcmov (DisasContext *ctx,
454 void (*gen_test_fop)(void),
455 int ra, int rb, int rc)
4c9649a9
JM		 456{
457 gen_load_fir(ctx, ra, 0);
458 gen_load_fir(ctx, rb, 1);
459 (*gen_test_fop)();
460 gen_op_cmov_fir(rc);
461}
462
f071b4d3
JM		 463static always_inline void gen_fti (DisasContext *ctx,
464 void (*gen_move_fop)(void),
465 int ra, int rc)
4c9649a9
JM		 466{
467 gen_load_fir(ctx, rc, 0);
468 (*gen_move_fop)();
3761035f
AJ		 469 if (ra != 31)
470 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 471}
472
f071b4d3
JM		 473static always_inline void gen_itf (DisasContext *ctx,
474 void (*gen_move_fop)(void),
475 int ra, int rc)
4c9649a9 476{
3761035f
AJ		 477 if (ra != 31)
478 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
479 else
480 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 481 (*gen_move_fop)();
482 gen_store_fir(ctx, rc, 0);
483}
484
f071b4d3 485static always_inline void gen_s4addl (void)
4c9649a9
JM		 486{
487 gen_op_s4();
488 gen_op_addl();
5fafdf24 489}
4c9649a9 490
f071b4d3 491static always_inline void gen_s4subl (void)
4c9649a9
JM		 492{
493 gen_op_s4();
494 gen_op_subl();
5fafdf24 495}
4c9649a9 496
f071b4d3 497static always_inline void gen_s8addl (void)
4c9649a9
JM		 498{
499 gen_op_s8();
500 gen_op_addl();
5fafdf24 501}
4c9649a9 502
f071b4d3 503static always_inline void gen_s8subl (void)
4c9649a9
JM		 504{
505 gen_op_s8();
506 gen_op_subl();
5fafdf24 507}
4c9649a9 508
f071b4d3 509static always_inline void gen_s4addq (void)
4c9649a9
JM		 510{
511 gen_op_s4();
512 gen_op_addq();
5fafdf24 513}
4c9649a9 514
f071b4d3 515static always_inline void gen_s4subq (void)
4c9649a9
JM		 516{
517 gen_op_s4();
518 gen_op_subq();
5fafdf24 519}
4c9649a9 520
f071b4d3 521static always_inline void gen_s8addq (void)
4c9649a9
JM		 522{
523 gen_op_s8();
524 gen_op_addq();
5fafdf24 525}
4c9649a9 526
f071b4d3 527static always_inline void gen_s8subq (void)
4c9649a9
JM		 528{
529 gen_op_s8();
530 gen_op_subq();
5fafdf24 531}
4c9649a9 532
f071b4d3 533static always_inline void gen_amask (void)
4c9649a9
JM		 534{
535 gen_op_load_amask();
536 gen_op_bic();
537}
538
f071b4d3 539static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
4c9649a9
JM		 540{
541 uint32_t palcode;
542 int32_t disp21, disp16, disp12;
543 uint16_t fn11, fn16;
544 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
545 int8_t lit;
546 int ret;
547
548 /* Decode all instruction fields */
549 opc = insn >> 26;
550 ra = (insn >> 21) & 0x1F;
551 rb = (insn >> 16) & 0x1F;
552 rc = insn & 0x1F;
553 sbz = (insn >> 13) & 0x07;
554 islit = (insn >> 12) & 1;
555 lit = (insn >> 13) & 0xFF;
556 palcode = insn & 0x03FFFFFF;
557 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
558 disp16 = (int16_t)(insn & 0x0000FFFF);
559 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
560 fn16 = insn & 0x0000FFFF;
561 fn11 = (insn >> 5) & 0x000007FF;
562 fpfn = fn11 & 0x3F;
563 fn7 = (insn >> 5) & 0x0000007F;
564 fn2 = (insn >> 5) & 0x00000003;
565 ret = 0;
566#if defined ALPHA_DEBUG_DISAS
567 if (logfile != NULL) {
568 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
569 opc, ra, rb, rc, disp16);
570 }
571#endif
572 switch (opc) {
573 case 0x00:
574 /* CALL_PAL */
575 if (palcode >= 0x80 && palcode < 0xC0) {
576 /* Unprivileged PAL call */
577 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
578#if !defined (CONFIG_USER_ONLY)
579 } else if (palcode < 0x40) {
580 /* Privileged PAL code */
581 if (ctx->mem_idx & 1)
582 goto invalid_opc;
583 else
584 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
585#endif
586 } else {
587 /* Invalid PAL call */
588 goto invalid_opc;
589 }
590 ret = 3;
591 break;
592 case 0x01:
593 /* OPC01 */
594 goto invalid_opc;
595 case 0x02:
596 /* OPC02 */
597 goto invalid_opc;
598 case 0x03:
599 /* OPC03 */
600 goto invalid_opc;
601 case 0x04:
602 /* OPC04 */
603 goto invalid_opc;
604 case 0x05:
605 /* OPC05 */
606 goto invalid_opc;
607 case 0x06:
608 /* OPC06 */
609 goto invalid_opc;
610 case 0x07:
611 /* OPC07 */
612 goto invalid_opc;
613 case 0x08:
614 /* LDA */
3761035f 615 if (ra != 31) {
496cb5b9 616 if (rb != 31)
3761035f
AJ		 617 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
618 else
619 tcg_gen_movi_i64(cpu_ir[ra], disp16);
496cb5b9 620 }
4c9649a9
JM		 621 break;
622 case 0x09:
623 /* LDAH */
3761035f 624 if (ra != 31) {
496cb5b9 625 if (rb != 31)
3761035f
AJ		 626 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
627 else
628 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
496cb5b9 629 }
4c9649a9
JM		 630 break;
631 case 0x0A:
632 /* LDBU */
633 if (!(ctx->amask & AMASK_BWX))
634 goto invalid_opc;
635 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
636 break;
637 case 0x0B:
638 /* LDQ_U */
639 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
640 break;
641 case 0x0C:
642 /* LDWU */
643 if (!(ctx->amask & AMASK_BWX))
644 goto invalid_opc;
645 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
646 break;
647 case 0x0D:
648 /* STW */
649 if (!(ctx->amask & AMASK_BWX))
650 goto invalid_opc;
651 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
652 break;
653 case 0x0E:
654 /* STB */
655 if (!(ctx->amask & AMASK_BWX))
656 goto invalid_opc;
657 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
658 break;
659 case 0x0F:
660 /* STQ_U */
661 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
662 break;
663 case 0x10:
664 switch (fn7) {
665 case 0x00:
666 /* ADDL */
667 gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit);
668 break;
669 case 0x02:
670 /* S4ADDL */
671 gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit);
672 break;
673 case 0x09:
674 /* SUBL */
675 gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit);
676 break;
677 case 0x0B:
678 /* S4SUBL */
679 gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit);
680 break;
681 case 0x0F:
682 /* CMPBGE */
683 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
684 break;
685 case 0x12:
686 /* S8ADDL */
687 gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit);
688 break;
689 case 0x1B:
690 /* S8SUBL */
691 gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit);
692 break;
693 case 0x1D:
694 /* CMPULT */
695 gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
696 break;
697 case 0x20:
698 /* ADDQ */
699 gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit);
700 break;
701 case 0x22:
702 /* S4ADDQ */
703 gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit);
704 break;
705 case 0x29:
706 /* SUBQ */
707 gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit);
708 break;
709 case 0x2B:
710 /* S4SUBQ */
711 gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit);
712 break;
713 case 0x2D:
714 /* CMPEQ */
715 gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
716 break;
717 case 0x32:
718 /* S8ADDQ */
719 gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit);
720 break;
721 case 0x3B:
722 /* S8SUBQ */
723 gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit);
724 break;
725 case 0x3D:
726 /* CMPULE */
727 gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
728 break;
729 case 0x40:
730 /* ADDL/V */
731 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
732 break;
733 case 0x49:
734 /* SUBL/V */
735 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
736 break;
737 case 0x4D:
738 /* CMPLT */
739 gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
740 break;
741 case 0x60:
742 /* ADDQ/V */
743 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
744 break;
745 case 0x69:
746 /* SUBQ/V */
747 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
748 break;
749 case 0x6D:
750 /* CMPLE */
751 gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
752 break;
753 default:
754 goto invalid_opc;
755 }
756 break;
757 case 0x11:
758 switch (fn7) {
759 case 0x00:
760 /* AND */
761 gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit);
762 break;
763 case 0x08:
764 /* BIC */
765 gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit);
766 break;
767 case 0x14:
768 /* CMOVLBS */
769 gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit);
770 break;
771 case 0x16:
772 /* CMOVLBC */
773 gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit);
774 break;
775 case 0x20:
776 /* BIS */
777 if (ra == rb || ra == 31 || rb == 31) {
778 if (ra == 31 && rc == 31) {
779 /* NOP */
780 gen_op_nop();
781 } else {
782 /* MOV */
3761035f
AJ		 783 if (rc != 31) {
784 if (rb != 31)
785 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
786 else
787 tcg_gen_movi_i64(cpu_ir[rc], 0);
788 }
4c9649a9
JM		 789 }
790 } else {
791 gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit);
792 }
793 break;
794 case 0x24:
795 /* CMOVEQ */
796 gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit);
797 break;
798 case 0x26:
799 /* CMOVNE */
800 gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit);
801 break;
802 case 0x28:
803 /* ORNOT */
804 gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit);
805 break;
806 case 0x40:
807 /* XOR */
808 gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit);
809 break;
810 case 0x44:
811 /* CMOVLT */
812 gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit);
813 break;
814 case 0x46:
815 /* CMOVGE */
816 gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit);
817 break;
818 case 0x48:
819 /* EQV */
820 gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit);
821 break;
822 case 0x61:
823 /* AMASK */
824 gen_arith2(ctx, &gen_amask, rb, rc, islit, lit);
825 break;
826 case 0x64:
827 /* CMOVLE */
828 gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit);
829 break;
830 case 0x66:
831 /* CMOVGT */
832 gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit);
833 break;
834 case 0x6C:
835 /* IMPLVER */
836 gen_op_load_implver();
3761035f
AJ		 837 if (rc != 31)
838 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
4c9649a9
JM		 839 break;
840 default:
841 goto invalid_opc;
842 }
843 break;
844 case 0x12:
845 switch (fn7) {
846 case 0x02:
847 /* MSKBL */
848 gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit);
849 break;
850 case 0x06:
851 /* EXTBL */
852 gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit);
853 break;
854 case 0x0B:
855 /* INSBL */
856 gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit);
857 break;
858 case 0x12:
859 /* MSKWL */
860 gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit);
861 break;
862 case 0x16:
863 /* EXTWL */
864 gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit);
865 break;
866 case 0x1B:
867 /* INSWL */
868 gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit);
869 break;
870 case 0x22:
871 /* MSKLL */
872 gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit);
873 break;
874 case 0x26:
875 /* EXTLL */
876 gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit);
877 break;
878 case 0x2B:
879 /* INSLL */
880 gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit);
881 break;
882 case 0x30:
883 /* ZAP */
884 gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit);
885 break;
886 case 0x31:
887 /* ZAPNOT */
888 gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit);
889 break;
890 case 0x32:
891 /* MSKQL */
892 gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit);
893 break;
894 case 0x34:
895 /* SRL */
896 gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit);
897 break;
898 case 0x36:
899 /* EXTQL */
900 gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit);
901 break;
902 case 0x39:
903 /* SLL */
904 gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit);
905 break;
906 case 0x3B:
907 /* INSQL */
908 gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit);
909 break;
910 case 0x3C:
911 /* SRA */
912 gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit);
913 break;
914 case 0x52:
915 /* MSKWH */
916 gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit);
917 break;
918 case 0x57:
919 /* INSWH */
920 gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit);
921 break;
922 case 0x5A:
923 /* EXTWH */
924 gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit);
925 break;
926 case 0x62:
927 /* MSKLH */
928 gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit);
929 break;
930 case 0x67:
931 /* INSLH */
932 gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit);
933 break;
934 case 0x6A:
935 /* EXTLH */
936 gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit);
937 break;
938 case 0x72:
939 /* MSKQH */
940 gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit);
941 break;
942 case 0x77:
943 /* INSQH */
944 gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit);
945 break;
946 case 0x7A:
947 /* EXTQH */
948 gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit);
949 break;
950 default:
951 goto invalid_opc;
952 }
953 break;
954 case 0x13:
955 switch (fn7) {
956 case 0x00:
957 /* MULL */
958 gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit);
959 break;
960 case 0x20:
961 /* MULQ */
962 gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit);
963 break;
964 case 0x30:
965 /* UMULH */
966 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
967 break;
968 case 0x40:
969 /* MULL/V */
970 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
971 break;
972 case 0x60:
973 /* MULQ/V */
974 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
975 break;
976 default:
977 goto invalid_opc;
978 }
979 break;
980 case 0x14:
981 switch (fpfn) { /* f11 & 0x3F */
982 case 0x04:
983 /* ITOFS */
984 if (!(ctx->amask & AMASK_FIX))
985 goto invalid_opc;
986 gen_itf(ctx, &gen_op_itofs, ra, rc);
987 break;
988 case 0x0A:
989 /* SQRTF */
990 if (!(ctx->amask & AMASK_FIX))
991 goto invalid_opc;
992 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
993 break;
994 case 0x0B:
995 /* SQRTS */
996 if (!(ctx->amask & AMASK_FIX))
997 goto invalid_opc;
998 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
999 break;
1000 case 0x14:
1001 /* ITOFF */
1002 if (!(ctx->amask & AMASK_FIX))
1003 goto invalid_opc;
1004#if 0 // TODO
1005 gen_itf(ctx, &gen_op_itoff, ra, rc);
1006#else
1007 goto invalid_opc;
1008#endif
1009 break;
1010 case 0x24:
1011 /* ITOFT */
1012 if (!(ctx->amask & AMASK_FIX))
1013 goto invalid_opc;
1014 gen_itf(ctx, &gen_op_itoft, ra, rc);
1015 break;
1016 case 0x2A:
1017 /* SQRTG */
1018 if (!(ctx->amask & AMASK_FIX))
1019 goto invalid_opc;
1020 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1021 break;
1022 case 0x02B:
1023 /* SQRTT */
1024 if (!(ctx->amask & AMASK_FIX))
1025 goto invalid_opc;
1026 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1027 break;
1028 default:
1029 goto invalid_opc;
1030 }
1031 break;
1032 case 0x15:
1033 /* VAX floating point */
1034 /* XXX: rounding mode and trap are ignored (!) */
1035 switch (fpfn) { /* f11 & 0x3F */
1036 case 0x00:
1037 /* ADDF */
1038 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1039 break;
1040 case 0x01:
1041 /* SUBF */
1042 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1043 break;
1044 case 0x02:
1045 /* MULF */
1046 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1047 break;
1048 case 0x03:
1049 /* DIVF */
1050 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1051 break;
1052 case 0x1E:
1053 /* CVTDG */
1054#if 0 // TODO
1055 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1056#else
1057 goto invalid_opc;
1058#endif
1059 break;
1060 case 0x20:
1061 /* ADDG */
1062 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1063 break;
1064 case 0x21:
1065 /* SUBG */
1066 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1067 break;
1068 case 0x22:
1069 /* MULG */
1070 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1071 break;
1072 case 0x23:
1073 /* DIVG */
1074 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1075 break;
1076 case 0x25:
1077 /* CMPGEQ */
1078 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1079 break;
1080 case 0x26:
1081 /* CMPGLT */
1082 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1083 break;
1084 case 0x27:
1085 /* CMPGLE */
1086 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1087 break;
1088 case 0x2C:
1089 /* CVTGF */
1090 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1091 break;
1092 case 0x2D:
1093 /* CVTGD */
1094#if 0 // TODO
1095 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1096#else
1097 goto invalid_opc;
1098#endif
1099 break;
1100 case 0x2F:
1101 /* CVTGQ */
1102 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1103 break;
1104 case 0x3C:
1105 /* CVTQF */
1106 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1107 break;
1108 case 0x3E:
1109 /* CVTQG */
1110 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1111 break;
1112 default:
1113 goto invalid_opc;
1114 }
1115 break;
1116 case 0x16:
1117 /* IEEE floating-point */
1118 /* XXX: rounding mode and traps are ignored (!) */
1119 switch (fpfn) { /* f11 & 0x3F */
1120 case 0x00:
1121 /* ADDS */
1122 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1123 break;
1124 case 0x01:
1125 /* SUBS */
1126 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1127 break;
1128 case 0x02:
1129 /* MULS */
1130 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1131 break;
1132 case 0x03:
1133 /* DIVS */
1134 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1135 break;
1136 case 0x20:
1137 /* ADDT */
1138 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1139 break;
1140 case 0x21:
1141 /* SUBT */
1142 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1143 break;
1144 case 0x22:
1145 /* MULT */
1146 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1147 break;
1148 case 0x23:
1149 /* DIVT */
1150 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1151 break;
1152 case 0x24:
1153 /* CMPTUN */
1154 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1155 break;
1156 case 0x25:
1157 /* CMPTEQ */
1158 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1159 break;
1160 case 0x26:
1161 /* CMPTLT */
1162 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1163 break;
1164 case 0x27:
1165 /* CMPTLE */
1166 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1167 break;
1168 case 0x2C:
1169 /* XXX: incorrect */
1170 if (fn11 == 0x2AC) {
1171 /* CVTST */
1172 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1173 } else {
1174 /* CVTTS */
1175 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1176 }
1177 break;
1178 case 0x2F:
1179 /* CVTTQ */
1180 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1181 break;
1182 case 0x3C:
1183 /* CVTQS */
1184 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1185 break;
1186 case 0x3E:
1187 /* CVTQT */
1188 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1189 break;
1190 default:
1191 goto invalid_opc;
1192 }
1193 break;
1194 case 0x17:
1195 switch (fn11) {
1196 case 0x010:
1197 /* CVTLQ */
1198 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1199 break;
1200 case 0x020:
1201 /* CPYS */
1202 if (ra == rb) {
1203 if (ra == 31 && rc == 31) {
1204 /* FNOP */
1205 gen_op_nop();
1206 } else {
1207 /* FMOV */
1208 gen_load_fir(ctx, rb, 0);
1209 gen_store_fir(ctx, rc, 0);
1210 }
1211 } else {
1212 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1213 }
1214 break;
1215 case 0x021:
1216 /* CPYSN */
1217 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1218 break;
1219 case 0x022:
1220 /* CPYSE */
1221 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1222 break;
1223 case 0x024:
1224 /* MT_FPCR */
1225 gen_load_fir(ctx, ra, 0);
1226 gen_op_store_fpcr();
1227 break;
1228 case 0x025:
1229 /* MF_FPCR */
1230 gen_op_load_fpcr();
1231 gen_store_fir(ctx, ra, 0);
1232 break;
1233 case 0x02A:
1234 /* FCMOVEQ */
1235 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1236 break;
1237 case 0x02B:
1238 /* FCMOVNE */
1239 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1240 break;
1241 case 0x02C:
1242 /* FCMOVLT */
1243 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1244 break;
1245 case 0x02D:
1246 /* FCMOVGE */
1247 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1248 break;
1249 case 0x02E:
1250 /* FCMOVLE */
1251 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1252 break;
1253 case 0x02F:
1254 /* FCMOVGT */
1255 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1256 break;
1257 case 0x030:
1258 /* CVTQL */
1259 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1260 break;
1261 case 0x130:
1262 /* CVTQL/V */
1263 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1264 break;
1265 case 0x530:
1266 /* CVTQL/SV */
1267 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1268 break;
1269 default:
1270 goto invalid_opc;
1271 }
1272 break;
1273 case 0x18:
1274 switch ((uint16_t)disp16) {
1275 case 0x0000:
1276 /* TRAPB */
1277 /* No-op. Just exit from the current tb */
1278 ret = 2;
1279 break;
1280 case 0x0400:
1281 /* EXCB */
1282 /* No-op. Just exit from the current tb */
1283 ret = 2;
1284 break;
1285 case 0x4000:
1286 /* MB */
1287 /* No-op */
1288 break;
1289 case 0x4400:
1290 /* WMB */
1291 /* No-op */
1292 break;
1293 case 0x8000:
1294 /* FETCH */
1295 /* No-op */
1296 break;
1297 case 0xA000:
1298 /* FETCH_M */
1299 /* No-op */
1300 break;
1301 case 0xC000:
1302 /* RPCC */
1303 gen_op_load_pcc();
3761035f
AJ		 1304 if (ra != 31)
1305 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1306 break;
1307 case 0xE000:
1308 /* RC */
1309 gen_op_load_irf();
3761035f
AJ		 1310 if (ra != 31)
1311 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1312 gen_op_clear_irf();
1313 break;
1314 case 0xE800:
1315 /* ECB */
1316 /* XXX: TODO: evict tb cache at address rb */
1317#if 0
1318 ret = 2;
1319#else
1320 goto invalid_opc;
1321#endif
1322 break;
1323 case 0xF000:
1324 /* RS */
1325 gen_op_load_irf();
3761035f
AJ		 1326 if (ra != 31)
1327 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1328 gen_op_set_irf();
1329 break;
1330 case 0xF800:
1331 /* WH64 */
1332 /* No-op */
1333 break;
1334 default:
1335 goto invalid_opc;
1336 }
1337 break;
1338 case 0x19:
1339 /* HW_MFPR (PALcode) */
1340#if defined (CONFIG_USER_ONLY)
1341 goto invalid_opc;
1342#else
1343 if (!ctx->pal_mode)
1344 goto invalid_opc;
1345 gen_op_mfpr(insn & 0xFF);
3761035f
AJ		 1346 if (ra != 31)
1347 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1348 break;
1349#endif
1350 case 0x1A:
3761035f
AJ		 1351 if (ra != 31)
1352 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1353 if (rb != 31)
1354 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1355 else
1356 tcg_gen_movi_i64(cpu_pc, 0);
4c9649a9
JM		 1357 /* Those four jumps only differ by the branch prediction hint */
1358 switch (fn2) {
1359 case 0x0:
1360 /* JMP */
1361 break;
1362 case 0x1:
1363 /* JSR */
1364 break;
1365 case 0x2:
1366 /* RET */
1367 break;
1368 case 0x3:
1369 /* JSR_COROUTINE */
1370 break;
1371 }
1372 ret = 1;
1373 break;
1374 case 0x1B:
1375 /* HW_LD (PALcode) */
1376#if defined (CONFIG_USER_ONLY)
1377 goto invalid_opc;
1378#else
1379 if (!ctx->pal_mode)
1380 goto invalid_opc;
3761035f
AJ		 1381 if (rb != 31)
1382 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1383 else
1384 tcg_gen_movi_i64(cpu_T[0], 0);
1385 tcg_gen_movi_i64(cpu_T[1], disp12);
4c9649a9
JM		 1386 gen_op_addq();
1387 switch ((insn >> 12) & 0xF) {
1388 case 0x0:
1389 /* Longword physical access */
1390 gen_op_ldl_raw();
1391 break;
1392 case 0x1:
1393 /* Quadword physical access */
1394 gen_op_ldq_raw();
1395 break;
1396 case 0x2:
1397 /* Longword physical access with lock */
1398 gen_op_ldl_l_raw();
1399 break;
1400 case 0x3:
1401 /* Quadword physical access with lock */
1402 gen_op_ldq_l_raw();
1403 break;
1404 case 0x4:
1405 /* Longword virtual PTE fetch */
1406 gen_op_ldl_kernel();
1407 break;
1408 case 0x5:
1409 /* Quadword virtual PTE fetch */
1410 gen_op_ldq_kernel();
1411 break;
1412 case 0x6:
1413 /* Invalid */
1414 goto invalid_opc;
1415 case 0x7:
1416 /* Invalid */
1417 goto invalid_opc;
1418 case 0x8:
1419 /* Longword virtual access */
1420 gen_op_ld_phys_to_virt();
1421 gen_op_ldl_raw();
1422 break;
1423 case 0x9:
1424 /* Quadword virtual access */
1425 gen_op_ld_phys_to_virt();
1426 gen_op_ldq_raw();
1427 break;
1428 case 0xA:
1429 /* Longword virtual access with protection check */
1430 gen_ldl(ctx);
1431 break;
1432 case 0xB:
1433 /* Quadword virtual access with protection check */
1434 gen_ldq(ctx);
1435 break;
1436 case 0xC:
1437 /* Longword virtual access with altenate access mode */
1438 gen_op_set_alt_mode();
1439 gen_op_ld_phys_to_virt();
1440 gen_op_ldl_raw();
1441 gen_op_restore_mode();
1442 break;
1443 case 0xD:
1444 /* Quadword virtual access with altenate access mode */
1445 gen_op_set_alt_mode();
1446 gen_op_ld_phys_to_virt();
1447 gen_op_ldq_raw();
1448 gen_op_restore_mode();
1449 break;
1450 case 0xE:
1451 /* Longword virtual access with alternate access mode and
1452 * protection checks
1453 */
1454 gen_op_set_alt_mode();
1455 gen_op_ldl_data();
1456 gen_op_restore_mode();
1457 break;
1458 case 0xF:
1459 /* Quadword virtual access with alternate access mode and
1460 * protection checks
1461 */
1462 gen_op_set_alt_mode();
1463 gen_op_ldq_data();
1464 gen_op_restore_mode();
1465 break;
1466 }
3761035f
AJ		 1467 if (ra != 31)
1468 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 1469 break;
1470#endif
1471 case 0x1C:
1472 switch (fn7) {
1473 case 0x00:
1474 /* SEXTB */
1475 if (!(ctx->amask & AMASK_BWX))
1476 goto invalid_opc;
1477 gen_arith2(ctx, &gen_op_sextb, rb, rc, islit, lit);
1478 break;
1479 case 0x01:
1480 /* SEXTW */
1481 if (!(ctx->amask & AMASK_BWX))
1482 goto invalid_opc;
1483 gen_arith2(ctx, &gen_op_sextw, rb, rc, islit, lit);
1484 break;
1485 case 0x30:
1486 /* CTPOP */
1487 if (!(ctx->amask & AMASK_CIX))
1488 goto invalid_opc;
1489 gen_arith2(ctx, &gen_op_ctpop, rb, rc, 0, 0);
1490 break;
1491 case 0x31:
1492 /* PERR */
1493 if (!(ctx->amask & AMASK_MVI))
1494 goto invalid_opc;
1495 /* XXX: TODO */
1496 goto invalid_opc;
1497 break;
1498 case 0x32:
1499 /* CTLZ */
1500 if (!(ctx->amask & AMASK_CIX))
1501 goto invalid_opc;
1502 gen_arith2(ctx, &gen_op_ctlz, rb, rc, 0, 0);
1503 break;
1504 case 0x33:
1505 /* CTTZ */
1506 if (!(ctx->amask & AMASK_CIX))
1507 goto invalid_opc;
1508 gen_arith2(ctx, &gen_op_cttz, rb, rc, 0, 0);
1509 break;
1510 case 0x34:
1511 /* UNPKBW */
1512 if (!(ctx->amask & AMASK_MVI))
1513 goto invalid_opc;
1514 /* XXX: TODO */
1515 goto invalid_opc;
1516 break;
1517 case 0x35:
1518 /* UNPKWL */
1519 if (!(ctx->amask & AMASK_MVI))
1520 goto invalid_opc;
1521 /* XXX: TODO */
1522 goto invalid_opc;
1523 break;
1524 case 0x36:
1525 /* PKWB */
1526 if (!(ctx->amask & AMASK_MVI))
1527 goto invalid_opc;
1528 /* XXX: TODO */
1529 goto invalid_opc;
1530 break;
1531 case 0x37:
1532 /* PKLB */
1533 if (!(ctx->amask & AMASK_MVI))
1534 goto invalid_opc;
1535 /* XXX: TODO */
1536 goto invalid_opc;
1537 break;
1538 case 0x38:
1539 /* MINSB8 */
1540 if (!(ctx->amask & AMASK_MVI))
1541 goto invalid_opc;
1542 /* XXX: TODO */
1543 goto invalid_opc;
1544 break;
1545 case 0x39:
1546 /* MINSW4 */
1547 if (!(ctx->amask & AMASK_MVI))
1548 goto invalid_opc;
1549 /* XXX: TODO */
1550 goto invalid_opc;
1551 break;
1552 case 0x3A:
1553 /* MINUB8 */
1554 if (!(ctx->amask & AMASK_MVI))
1555 goto invalid_opc;
1556 /* XXX: TODO */
1557 goto invalid_opc;
1558 break;
1559 case 0x3B:
1560 /* MINUW4 */
1561 if (!(ctx->amask & AMASK_MVI))
1562 goto invalid_opc;
1563 /* XXX: TODO */
1564 goto invalid_opc;
1565 break;
1566 case 0x3C:
1567 /* MAXUB8 */
1568 if (!(ctx->amask & AMASK_MVI))
1569 goto invalid_opc;
1570 /* XXX: TODO */
1571 goto invalid_opc;
1572 break;
1573 case 0x3D:
1574 /* MAXUW4 */
1575 if (!(ctx->amask & AMASK_MVI))
1576 goto invalid_opc;
1577 /* XXX: TODO */
1578 goto invalid_opc;
1579 break;
1580 case 0x3E:
1581 /* MAXSB8 */
1582 if (!(ctx->amask & AMASK_MVI))
1583 goto invalid_opc;
1584 /* XXX: TODO */
1585 goto invalid_opc;
1586 break;
1587 case 0x3F:
1588 /* MAXSW4 */
1589 if (!(ctx->amask & AMASK_MVI))
1590 goto invalid_opc;
1591 /* XXX: TODO */
1592 goto invalid_opc;
1593 break;
1594 case 0x70:
1595 /* FTOIT */
1596 if (!(ctx->amask & AMASK_FIX))
1597 goto invalid_opc;
1598 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1599 break;
1600 case 0x78:
1601 /* FTOIS */
1602 if (!(ctx->amask & AMASK_FIX))
1603 goto invalid_opc;
1604 gen_fti(ctx, &gen_op_ftois, ra, rb);
1605 break;
1606 default:
1607 goto invalid_opc;
1608 }
1609 break;
1610 case 0x1D:
1611 /* HW_MTPR (PALcode) */
1612#if defined (CONFIG_USER_ONLY)
1613 goto invalid_opc;
1614#else
1615 if (!ctx->pal_mode)
1616 goto invalid_opc;
3761035f
AJ		 1617 if (ra != 31)
1618 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
1619 else
1620 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 1621 gen_op_mtpr(insn & 0xFF);
1622 ret = 2;
1623 break;
1624#endif
1625 case 0x1E:
1626 /* HW_REI (PALcode) */
1627#if defined (CONFIG_USER_ONLY)
1628 goto invalid_opc;
1629#else
1630 if (!ctx->pal_mode)
1631 goto invalid_opc;
1632 if (rb == 31) {
1633 /* "Old" alpha */
1634 gen_op_hw_rei();
1635 } else {
3761035f
AJ		 1636 if (ra != 31)
1637 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1638 else
1639 tcg_gen_movi_i64(cpu_T[0], 0);
1640 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
4c9649a9
JM		 1641 gen_op_addq();
1642 gen_op_hw_ret();
1643 }
1644 ret = 2;
1645 break;
1646#endif
1647 case 0x1F:
1648 /* HW_ST (PALcode) */
1649#if defined (CONFIG_USER_ONLY)
1650 goto invalid_opc;
1651#else
1652 if (!ctx->pal_mode)
1653 goto invalid_opc;
3761035f
AJ		 1654 if (ra != 31)
1655 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1656 else
1657 tcg_gen_movi_i64(cpu_T[0], 0);
1658 tcg_gen_movi_i64(cpu_T[1], disp12);
4c9649a9 1659 gen_op_addq();
3761035f
AJ		 1660 if (ra != 31)
1661 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
1662 else
1663 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 1664 switch ((insn >> 12) & 0xF) {
1665 case 0x0:
1666 /* Longword physical access */
1667 gen_op_stl_raw();
1668 break;
1669 case 0x1:
1670 /* Quadword physical access */
1671 gen_op_stq_raw();
1672 break;
1673 case 0x2:
1674 /* Longword physical access with lock */
1675 gen_op_stl_c_raw();
1676 break;
1677 case 0x3:
1678 /* Quadword physical access with lock */
1679 gen_op_stq_c_raw();
1680 break;
1681 case 0x4:
1682 /* Longword virtual access */
1683 gen_op_st_phys_to_virt();
1684 gen_op_stl_raw();
1685 break;
1686 case 0x5:
1687 /* Quadword virtual access */
1688 gen_op_st_phys_to_virt();
1689 gen_op_stq_raw();
1690 break;
1691 case 0x6:
1692 /* Invalid */
1693 goto invalid_opc;
1694 case 0x7:
1695 /* Invalid */
1696 goto invalid_opc;
1697 case 0x8:
1698 /* Invalid */
1699 goto invalid_opc;
1700 case 0x9:
1701 /* Invalid */
1702 goto invalid_opc;
1703 case 0xA:
1704 /* Invalid */
1705 goto invalid_opc;
1706 case 0xB:
1707 /* Invalid */
1708 goto invalid_opc;
1709 case 0xC:
1710 /* Longword virtual access with alternate access mode */
1711 gen_op_set_alt_mode();
1712 gen_op_st_phys_to_virt();
1713 gen_op_ldl_raw();
1714 gen_op_restore_mode();
1715 break;
1716 case 0xD:
1717 /* Quadword virtual access with alternate access mode */
1718 gen_op_set_alt_mode();
1719 gen_op_st_phys_to_virt();
1720 gen_op_ldq_raw();
1721 gen_op_restore_mode();
1722 break;
1723 case 0xE:
1724 /* Invalid */
1725 goto invalid_opc;
1726 case 0xF:
1727 /* Invalid */
1728 goto invalid_opc;
1729 }
1730 ret = 2;
1731 break;
1732#endif
1733 case 0x20:
1734 /* LDF */
1735#if 0 // TODO
1736 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
1737#else
1738 goto invalid_opc;
1739#endif
1740 break;
1741 case 0x21:
1742 /* LDG */
1743#if 0 // TODO
1744 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
1745#else
1746 goto invalid_opc;
1747#endif
1748 break;
1749 case 0x22:
1750 /* LDS */
1751 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
1752 break;
1753 case 0x23:
1754 /* LDT */
1755 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
1756 break;
1757 case 0x24:
1758 /* STF */
1759#if 0 // TODO
1760 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
1761#else
1762 goto invalid_opc;
1763#endif
1764 break;
1765 case 0x25:
1766 /* STG */
1767#if 0 // TODO
1768 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
1769#else
1770 goto invalid_opc;
1771#endif
1772 break;
1773 case 0x26:
1774 /* STS */
1775 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
1776 break;
1777 case 0x27:
1778 /* STT */
1779 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
1780 break;
1781 case 0x28:
1782 /* LDL */
1783 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
1784 break;
1785 case 0x29:
1786 /* LDQ */
1787 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
1788 break;
1789 case 0x2A:
1790 /* LDL_L */
1791 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
1792 break;
1793 case 0x2B:
1794 /* LDQ_L */
1795 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
1796 break;
1797 case 0x2C:
1798 /* STL */
1799 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
1800 break;
1801 case 0x2D:
1802 /* STQ */
1803 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
1804 break;
1805 case 0x2E:
1806 /* STL_C */
1807 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
1808 break;
1809 case 0x2F:
1810 /* STQ_C */
1811 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
1812 break;
1813 case 0x30:
1814 /* BR */
3761035f
AJ		 1815 if (ra != 31)
1816 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1817 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 1818 ret = 1;
1819 break;
1820 case 0x31:
1821 /* FBEQ */
1822 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
1823 ret = 1;
1824 break;
1825 case 0x32:
1826 /* FBLT */
1827 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
1828 ret = 1;
1829 break;
1830 case 0x33:
1831 /* FBLE */
1832 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
1833 ret = 1;
1834 break;
1835 case 0x34:
1836 /* BSR */
3761035f
AJ		 1837 if (ra != 31)
1838 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1839 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 1840 ret = 1;
1841 break;
1842 case 0x35:
1843 /* FBNE */
1844 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
1845 ret = 1;
1846 break;
1847 case 0x36:
1848 /* FBGE */
1849 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
1850 ret = 1;
1851 break;
1852 case 0x37:
1853 /* FBGT */
1854 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
1855 ret = 1;
1856 break;
1857 case 0x38:
1858 /* BLBC */
1859 gen_bcond(ctx, &gen_op_cmplbc, ra, disp16);
1860 ret = 1;
1861 break;
1862 case 0x39:
1863 /* BEQ */
1864 gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16);
1865 ret = 1;
1866 break;
1867 case 0x3A:
1868 /* BLT */
1869 gen_bcond(ctx, &gen_op_cmpltz, ra, disp16);
1870 ret = 1;
1871 break;
1872 case 0x3B:
1873 /* BLE */
1874 gen_bcond(ctx, &gen_op_cmplez, ra, disp16);
1875 ret = 1;
1876 break;
1877 case 0x3C:
1878 /* BLBS */
1879 gen_bcond(ctx, &gen_op_cmplbs, ra, disp16);
1880 ret = 1;
1881 break;
1882 case 0x3D:
1883 /* BNE */
1884 gen_bcond(ctx, &gen_op_cmpnez, ra, disp16);
1885 ret = 1;
1886 break;
1887 case 0x3E:
1888 /* BGE */
1889 gen_bcond(ctx, &gen_op_cmpgez, ra, disp16);
1890 ret = 1;
1891 break;
1892 case 0x3F:
1893 /* BGT */
1894 gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16);
1895 ret = 1;
1896 break;
1897 invalid_opc:
1898 gen_invalid(ctx);
1899 ret = 3;
1900 break;
1901 }
1902
1903 return ret;
1904}
1905
2cfc5f17
TS		 1906static always_inline void gen_intermediate_code_internal (CPUState *env,
1907 TranslationBlock *tb,
1908 int search_pc)
4c9649a9
JM		 1909{
1910#if defined ALPHA_DEBUG_DISAS
1911 static int insn_count;
1912#endif
1913 DisasContext ctx, *ctxp = &ctx;
1914 target_ulong pc_start;
1915 uint32_t insn;
1916 uint16_t *gen_opc_end;
1917 int j, lj = -1;
1918 int ret;
2e70f6ef
PB		 1919 int num_insns;
1920 int max_insns;
4c9649a9
JM		 1921
1922 pc_start = tb->pc;
4c9649a9 1923 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4c9649a9
JM		 1924 ctx.pc = pc_start;
1925 ctx.amask = env->amask;
1926#if defined (CONFIG_USER_ONLY)
1927 ctx.mem_idx = 0;
1928#else
1929 ctx.mem_idx = ((env->ps >> 3) & 3);
1930 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
1931#endif
2e70f6ef
PB		 1932 num_insns = 0;
1933 max_insns = tb->cflags & CF_COUNT_MASK;
1934 if (max_insns == 0)
1935 max_insns = CF_COUNT_MASK;
1936
1937 gen_icount_start();
4c9649a9
JM		 1938 for (ret = 0; ret == 0;) {
1939 if (env->nb_breakpoints > 0) {
1940 for(j = 0; j < env->nb_breakpoints; j++) {
1941 if (env->breakpoints[j] == ctx.pc) {
1942 gen_excp(&ctx, EXCP_DEBUG, 0);
1943 break;
1944 }
1945 }
1946 }
1947 if (search_pc) {
1948 j = gen_opc_ptr - gen_opc_buf;
1949 if (lj < j) {
1950 lj++;
1951 while (lj < j)
1952 gen_opc_instr_start[lj++] = 0;
1953 gen_opc_pc[lj] = ctx.pc;
1954 gen_opc_instr_start[lj] = 1;
2e70f6ef 1955 gen_opc_icount[lj] = num_insns;
4c9649a9
JM		 1956 }
1957 }
2e70f6ef
PB		 1958 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1959 gen_io_start();
4c9649a9
JM		 1960#if defined ALPHA_DEBUG_DISAS
1961 insn_count++;
1962 if (logfile != NULL) {
e96efcfc
JM		 1963 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
1964 ctx.pc, ctx.mem_idx);
4c9649a9
JM		 1965 }
1966#endif
1967 insn = ldl_code(ctx.pc);
1968#if defined ALPHA_DEBUG_DISAS
1969 insn_count++;
1970 if (logfile != NULL) {
1971 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
1972 }
1973#endif
2e70f6ef 1974 num_insns++;
4c9649a9
JM		 1975 ctx.pc += 4;
1976 ret = translate_one(ctxp, insn);
1977 if (ret != 0)
1978 break;
1979 /* if we reach a page boundary or are single stepping, stop
1980 * generation
1981 */
1982 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 1983 (env->singlestep_enabled) ||
1984 num_insns >= max_insns) {
4c9649a9
JM		 1985 break;
1986 }
1987#if defined (DO_SINGLE_STEP)
1988 break;
1989#endif
1990 }
1991 if (ret != 1 && ret != 3) {
496cb5b9 1992 tcg_gen_movi_i64(cpu_pc, ctx.pc);
4c9649a9 1993 }
4c9649a9 1994#if defined (DO_TB_FLUSH)
496cb5b9 1995 tcg_gen_helper_0_0(helper_tb_flush);
4c9649a9 1996#endif
2e70f6ef
PB		 1997 if (tb->cflags & CF_LAST_IO)
1998 gen_io_end();
4c9649a9 1999 /* Generate the return instruction */
57fec1fe 2000 tcg_gen_exit_tb(0);
2e70f6ef 2001 gen_icount_end(tb, num_insns);
4c9649a9
JM		 2002 *gen_opc_ptr = INDEX_op_end;
2003 if (search_pc) {
2004 j = gen_opc_ptr - gen_opc_buf;
2005 lj++;
2006 while (lj <= j)
2007 gen_opc_instr_start[lj++] = 0;
4c9649a9
JM		 2008 } else {
2009 tb->size = ctx.pc - pc_start;
2e70f6ef 2010 tb->icount = num_insns;
4c9649a9
JM		 2011 }
2012#if defined ALPHA_DEBUG_DISAS
2013 if (loglevel & CPU_LOG_TB_CPU) {
2014 cpu_dump_state(env, logfile, fprintf, 0);
2015 }
2016 if (loglevel & CPU_LOG_TB_IN_ASM) {
2017 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2018 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2019 fprintf(logfile, "\n");
2020 }
4c9649a9 2021#endif
4c9649a9
JM		 2022}
2023
2cfc5f17 2024void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2025{
2cfc5f17 2026 gen_intermediate_code_internal(env, tb, 0);
4c9649a9
JM		 2027}
2028
2cfc5f17 2029void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2030{
2cfc5f17 2031 gen_intermediate_code_internal(env, tb, 1);
4c9649a9
JM		 2032}
2033
aaed909a 2034CPUAlphaState * cpu_alpha_init (const char *cpu_model)
4c9649a9
JM		 2035{
2036 CPUAlphaState *env;
2037 uint64_t hwpcb;
2038
2039 env = qemu_mallocz(sizeof(CPUAlphaState));
2040 if (!env)
2041 return NULL;
2042 cpu_exec_init(env);
2e70f6ef 2043 alpha_translate_init();
4c9649a9
JM		 2044 tlb_flush(env, 1);
2045 /* XXX: should not be hardcoded */
2046 env->implver = IMPLVER_2106x;
2047 env->ps = 0x1F00;
2048#if defined (CONFIG_USER_ONLY)
2049 env->ps |= 1 << 3;
2050#endif
2051 pal_init(env);
2052 /* Initialize IPR */
2053 hwpcb = env->ipr[IPR_PCBB];
2054 env->ipr[IPR_ASN] = 0;
2055 env->ipr[IPR_ASTEN] = 0;
2056 env->ipr[IPR_ASTSR] = 0;
2057 env->ipr[IPR_DATFX] = 0;
2058 /* XXX: fix this */
2059 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2060 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2061 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2062 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2063 env->ipr[IPR_FEN] = 0;
2064 env->ipr[IPR_IPL] = 31;
2065 env->ipr[IPR_MCES] = 0;
2066 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2067 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2068 env->ipr[IPR_SISR] = 0;
2069 env->ipr[IPR_VIRBND] = -1ULL;
2070
2071 return env;
2072}
aaed909a 2073
d2856f1a
AJ		 2074void gen_pc_load(CPUState *env, TranslationBlock *tb,
2075 unsigned long searched_pc, int pc_pos, void *puc)
2076{
2077 env->pc = gen_opc_pc[pc_pos];
2078}
Qemu copy for testing