]>
Commit | Line | Data |
---|---|---|
dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
dec9c2d4 | 22 | #include "qemu-common.h" |
3c30dd5a PM |
23 | #if !defined(CONFIG_USER_ONLY) |
24 | #include "hw/loader.h" | |
25 | #endif | |
34f90529 | 26 | #include "sysemu.h" |
dec9c2d4 | 27 | |
4b6a83fb PM |
28 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
29 | { | |
30 | /* Reset a single ARMCPRegInfo register */ | |
31 | ARMCPRegInfo *ri = value; | |
32 | ARMCPU *cpu = opaque; | |
33 | ||
34 | if (ri->type & ARM_CP_SPECIAL) { | |
35 | return; | |
36 | } | |
37 | ||
38 | if (ri->resetfn) { | |
39 | ri->resetfn(&cpu->env, ri); | |
40 | return; | |
41 | } | |
42 | ||
43 | /* A zero offset is never possible as it would be regs[0] | |
44 | * so we use it to indicate that reset is being handled elsewhere. | |
45 | * This is basically only used for fields in non-core coprocessors | |
46 | * (like the pxa2xx ones). | |
47 | */ | |
48 | if (!ri->fieldoffset) { | |
49 | return; | |
50 | } | |
51 | ||
52 | if (ri->type & ARM_CP_64BIT) { | |
53 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
54 | } else { | |
55 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
56 | } | |
57 | } | |
58 | ||
dec9c2d4 AF |
59 | /* CPUClass::reset() */ |
60 | static void arm_cpu_reset(CPUState *s) | |
61 | { | |
62 | ARMCPU *cpu = ARM_CPU(s); | |
63 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 64 | CPUARMState *env = &cpu->env; |
3c30dd5a PM |
65 | |
66 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
67 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
68 | log_cpu_state(env, 0); | |
69 | } | |
dec9c2d4 AF |
70 | |
71 | acc->parent_reset(s); | |
72 | ||
3c30dd5a | 73 | memset(env, 0, offsetof(CPUARMState, breakpoints)); |
4b6a83fb | 74 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
75 | env->cp15.c0_cpuid = cpu->midr; |
76 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; | |
77 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
78 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
79 | env->cp15.c0_cachetype = cpu->ctr; | |
80 | env->cp15.c1_sys = cpu->reset_sctlr; | |
81 | env->cp15.c0_c1[0] = cpu->id_pfr0; | |
82 | env->cp15.c0_c1[1] = cpu->id_pfr1; | |
83 | env->cp15.c0_c1[2] = cpu->id_dfr0; | |
84 | env->cp15.c0_c1[3] = cpu->id_afr0; | |
85 | env->cp15.c0_c1[4] = cpu->id_mmfr0; | |
86 | env->cp15.c0_c1[5] = cpu->id_mmfr1; | |
87 | env->cp15.c0_c1[6] = cpu->id_mmfr2; | |
88 | env->cp15.c0_c1[7] = cpu->id_mmfr3; | |
89 | env->cp15.c0_c2[0] = cpu->id_isar0; | |
90 | env->cp15.c0_c2[1] = cpu->id_isar1; | |
91 | env->cp15.c0_c2[2] = cpu->id_isar2; | |
92 | env->cp15.c0_c2[3] = cpu->id_isar3; | |
93 | env->cp15.c0_c2[4] = cpu->id_isar4; | |
94 | env->cp15.c0_c2[5] = cpu->id_isar5; | |
3c30dd5a PM |
95 | env->cp15.c0_clid = cpu->clidr; |
96 | memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); | |
97 | ||
98 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
99 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
100 | } | |
101 | ||
102 | #if defined(CONFIG_USER_ONLY) | |
103 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
104 | /* For user mode we must enable access to coprocessors */ | |
105 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
106 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
107 | env->cp15.c15_cpar = 3; | |
108 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
109 | env->cp15.c15_cpar = 1; | |
110 | } | |
111 | #else | |
112 | /* SVC mode with interrupts disabled. */ | |
113 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
114 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
115 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
116 | if (IS_M(env)) { | |
117 | uint32_t pc; | |
118 | uint8_t *rom; | |
119 | env->uncached_cpsr &= ~CPSR_I; | |
120 | rom = rom_ptr(0); | |
121 | if (rom) { | |
122 | /* We should really use ldl_phys here, in case the guest | |
123 | modified flash and reset itself. However images | |
124 | loaded via -kernel have not been copied yet, so load the | |
125 | values directly from there. */ | |
126 | env->regs[13] = ldl_p(rom); | |
127 | pc = ldl_p(rom + 4); | |
128 | env->thumb = pc & 1; | |
129 | env->regs[15] = pc & ~1; | |
130 | } | |
131 | } | |
132 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
3c30dd5a PM |
133 | #endif |
134 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
135 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
136 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
137 | set_float_detect_tininess(float_tininess_before_rounding, | |
138 | &env->vfp.fp_status); | |
139 | set_float_detect_tininess(float_tininess_before_rounding, | |
140 | &env->vfp.standard_fp_status); | |
141 | tlb_flush(env, 1); | |
142 | /* Reset is a state change for some CPUARMState fields which we | |
143 | * bake assumptions about into translated code, so we need to | |
144 | * tb_flush(). | |
145 | */ | |
146 | tb_flush(env); | |
dec9c2d4 AF |
147 | } |
148 | ||
581be094 PM |
149 | static inline void set_feature(CPUARMState *env, int feature) |
150 | { | |
151 | env->features |= 1u << feature; | |
152 | } | |
153 | ||
777dc784 PM |
154 | static void arm_cpu_initfn(Object *obj) |
155 | { | |
156 | ARMCPU *cpu = ARM_CPU(obj); | |
157 | ||
158 | cpu_exec_init(&cpu->env); | |
4b6a83fb PM |
159 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
160 | g_free, g_free); | |
161 | } | |
162 | ||
163 | static void arm_cpu_finalizefn(Object *obj) | |
164 | { | |
165 | ARMCPU *cpu = ARM_CPU(obj); | |
166 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
167 | } |
168 | ||
581be094 PM |
169 | void arm_cpu_realize(ARMCPU *cpu) |
170 | { | |
171 | /* This function is called by cpu_arm_init() because it | |
172 | * needs to do common actions based on feature bits, etc | |
173 | * that have been set by the subclass init functions. | |
174 | * When we have QOM realize support it should become | |
175 | * a true realize function instead. | |
176 | */ | |
177 | CPUARMState *env = &cpu->env; | |
178 | /* Some features automatically imply others: */ | |
179 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
180 | set_feature(env, ARM_FEATURE_VAPA); | |
181 | set_feature(env, ARM_FEATURE_THUMB2); | |
182 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
183 | set_feature(env, ARM_FEATURE_V6K); | |
184 | } else { | |
185 | set_feature(env, ARM_FEATURE_V6); | |
186 | } | |
187 | } | |
188 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
189 | set_feature(env, ARM_FEATURE_V6); | |
190 | set_feature(env, ARM_FEATURE_MVFR); | |
191 | } | |
192 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
193 | set_feature(env, ARM_FEATURE_V5); | |
194 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
195 | set_feature(env, ARM_FEATURE_AUXCR); | |
196 | } | |
197 | } | |
198 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
199 | set_feature(env, ARM_FEATURE_V4T); | |
200 | } | |
201 | if (arm_feature(env, ARM_FEATURE_M)) { | |
202 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
203 | } | |
204 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
205 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
206 | } | |
207 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
208 | set_feature(env, ARM_FEATURE_VFP3); | |
209 | } | |
210 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
211 | set_feature(env, ARM_FEATURE_VFP); | |
212 | } | |
2ceb98c0 PM |
213 | |
214 | register_cp_regs_for_features(cpu); | |
581be094 PM |
215 | } |
216 | ||
777dc784 PM |
217 | /* CPU models */ |
218 | ||
219 | static void arm926_initfn(Object *obj) | |
220 | { | |
221 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
222 | set_feature(&cpu->env, ARM_FEATURE_V5); |
223 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
224 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
225 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
777dc784 | 226 | cpu->midr = ARM_CPUID_ARM926; |
325b3cef | 227 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 228 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 229 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
230 | } |
231 | ||
232 | static void arm946_initfn(Object *obj) | |
233 | { | |
234 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
235 | set_feature(&cpu->env, ARM_FEATURE_V5); |
236 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 237 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 238 | cpu->midr = ARM_CPUID_ARM946; |
64e1671f | 239 | cpu->ctr = 0x0f004006; |
0ca7e01c | 240 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
241 | } |
242 | ||
243 | static void arm1026_initfn(Object *obj) | |
244 | { | |
245 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
246 | set_feature(&cpu->env, ARM_FEATURE_V5); |
247 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
248 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
249 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
250 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
777dc784 | 251 | cpu->midr = ARM_CPUID_ARM1026; |
325b3cef | 252 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 253 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 254 | cpu->reset_sctlr = 0x00090078; |
06d76f31 PM |
255 | { |
256 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
257 | ARMCPRegInfo ifar = { | |
258 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
259 | .access = PL1_RW, | |
260 | .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
261 | .resetvalue = 0 | |
262 | }; | |
263 | define_one_arm_cp_reg(cpu, &ifar); | |
264 | } | |
777dc784 PM |
265 | } |
266 | ||
267 | static void arm1136_r2_initfn(Object *obj) | |
268 | { | |
269 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
270 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
271 | * older core than plain "arm1136". In particular this does not | |
272 | * have the v6K features. | |
273 | * These ID register values are correct for 1136 but may be wrong | |
274 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
275 | * of the ID registers). | |
276 | */ | |
581be094 PM |
277 | set_feature(&cpu->env, ARM_FEATURE_V6); |
278 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
279 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
280 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
281 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
777dc784 | 282 | cpu->midr = ARM_CPUID_ARM1136_R2; |
325b3cef | 283 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
284 | cpu->mvfr0 = 0x11111111; |
285 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 286 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 287 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
288 | cpu->id_pfr0 = 0x111; |
289 | cpu->id_pfr1 = 0x1; | |
290 | cpu->id_dfr0 = 0x2; | |
291 | cpu->id_afr0 = 0x3; | |
292 | cpu->id_mmfr0 = 0x01130003; | |
293 | cpu->id_mmfr1 = 0x10030302; | |
294 | cpu->id_mmfr2 = 0x01222110; | |
295 | cpu->id_isar0 = 0x00140011; | |
296 | cpu->id_isar1 = 0x12002111; | |
297 | cpu->id_isar2 = 0x11231111; | |
298 | cpu->id_isar3 = 0x01102131; | |
299 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
300 | } |
301 | ||
302 | static void arm1136_initfn(Object *obj) | |
303 | { | |
304 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
305 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
306 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
307 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
308 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
309 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
310 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
777dc784 | 311 | cpu->midr = ARM_CPUID_ARM1136; |
325b3cef | 312 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
313 | cpu->mvfr0 = 0x11111111; |
314 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 315 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 316 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
317 | cpu->id_pfr0 = 0x111; |
318 | cpu->id_pfr1 = 0x1; | |
319 | cpu->id_dfr0 = 0x2; | |
320 | cpu->id_afr0 = 0x3; | |
321 | cpu->id_mmfr0 = 0x01130003; | |
322 | cpu->id_mmfr1 = 0x10030302; | |
323 | cpu->id_mmfr2 = 0x01222110; | |
324 | cpu->id_isar0 = 0x00140011; | |
325 | cpu->id_isar1 = 0x12002111; | |
326 | cpu->id_isar2 = 0x11231111; | |
327 | cpu->id_isar3 = 0x01102131; | |
328 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
329 | } |
330 | ||
331 | static void arm1176_initfn(Object *obj) | |
332 | { | |
333 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
334 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
335 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
336 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
337 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
338 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
339 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
777dc784 | 340 | cpu->midr = ARM_CPUID_ARM1176; |
325b3cef | 341 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
342 | cpu->mvfr0 = 0x11111111; |
343 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 344 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 345 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
346 | cpu->id_pfr0 = 0x111; |
347 | cpu->id_pfr1 = 0x11; | |
348 | cpu->id_dfr0 = 0x33; | |
349 | cpu->id_afr0 = 0; | |
350 | cpu->id_mmfr0 = 0x01130003; | |
351 | cpu->id_mmfr1 = 0x10030302; | |
352 | cpu->id_mmfr2 = 0x01222100; | |
353 | cpu->id_isar0 = 0x0140011; | |
354 | cpu->id_isar1 = 0x12002111; | |
355 | cpu->id_isar2 = 0x11231121; | |
356 | cpu->id_isar3 = 0x01102131; | |
357 | cpu->id_isar4 = 0x01141; | |
777dc784 PM |
358 | } |
359 | ||
360 | static void arm11mpcore_initfn(Object *obj) | |
361 | { | |
362 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
363 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
364 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
365 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 | 366 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 367 | cpu->midr = ARM_CPUID_ARM11MPCORE; |
325b3cef | 368 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
369 | cpu->mvfr0 = 0x11111111; |
370 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 371 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
372 | cpu->id_pfr0 = 0x111; |
373 | cpu->id_pfr1 = 0x1; | |
374 | cpu->id_dfr0 = 0; | |
375 | cpu->id_afr0 = 0x2; | |
376 | cpu->id_mmfr0 = 0x01100103; | |
377 | cpu->id_mmfr1 = 0x10020302; | |
378 | cpu->id_mmfr2 = 0x01222000; | |
379 | cpu->id_isar0 = 0x00100011; | |
380 | cpu->id_isar1 = 0x12002111; | |
381 | cpu->id_isar2 = 0x11221011; | |
382 | cpu->id_isar3 = 0x01102131; | |
383 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
384 | } |
385 | ||
386 | static void cortex_m3_initfn(Object *obj) | |
387 | { | |
388 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
389 | set_feature(&cpu->env, ARM_FEATURE_V7); |
390 | set_feature(&cpu->env, ARM_FEATURE_M); | |
777dc784 PM |
391 | cpu->midr = ARM_CPUID_CORTEXM3; |
392 | } | |
393 | ||
34f90529 PM |
394 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
395 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
396 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
397 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
398 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
399 | REGINFO_SENTINEL | |
400 | }; | |
401 | ||
777dc784 PM |
402 | static void cortex_a8_initfn(Object *obj) |
403 | { | |
404 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
405 | set_feature(&cpu->env, ARM_FEATURE_V7); |
406 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
407 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
408 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 409 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 410 | cpu->midr = ARM_CPUID_CORTEXA8; |
325b3cef | 411 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
412 | cpu->mvfr0 = 0x11110222; |
413 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 414 | cpu->ctr = 0x82048004; |
0ca7e01c | 415 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
416 | cpu->id_pfr0 = 0x1031; |
417 | cpu->id_pfr1 = 0x11; | |
418 | cpu->id_dfr0 = 0x400; | |
419 | cpu->id_afr0 = 0; | |
420 | cpu->id_mmfr0 = 0x31100003; | |
421 | cpu->id_mmfr1 = 0x20000000; | |
422 | cpu->id_mmfr2 = 0x01202000; | |
423 | cpu->id_mmfr3 = 0x11; | |
424 | cpu->id_isar0 = 0x00101111; | |
425 | cpu->id_isar1 = 0x12112111; | |
426 | cpu->id_isar2 = 0x21232031; | |
427 | cpu->id_isar3 = 0x11112131; | |
428 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
429 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
430 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
431 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
432 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
34f90529 | 433 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
434 | } |
435 | ||
1047b9d7 PM |
436 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
437 | /* power_control should be set to maximum latency. Again, | |
438 | * default to 0 and set by private hook | |
439 | */ | |
440 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
441 | .access = PL1_RW, .resetvalue = 0, | |
442 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
443 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
444 | .access = PL1_RW, .resetvalue = 0, | |
445 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
446 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
447 | .access = PL1_RW, .resetvalue = 0, | |
448 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
449 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
450 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
451 | /* TLB lockdown control */ | |
452 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
453 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
454 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
455 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
456 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
457 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
458 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
459 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
460 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
461 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
462 | REGINFO_SENTINEL | |
463 | }; | |
464 | ||
777dc784 PM |
465 | static void cortex_a9_initfn(Object *obj) |
466 | { | |
467 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
468 | set_feature(&cpu->env, ARM_FEATURE_V7); |
469 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
470 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
471 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
472 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
473 | /* Note that A9 supports the MP extensions even for | |
474 | * A9UP and single-core A9MP (which are both different | |
475 | * and valid configurations; we don't model A9UP). | |
476 | */ | |
477 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 | 478 | cpu->midr = ARM_CPUID_CORTEXA9; |
325b3cef | 479 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
480 | cpu->mvfr0 = 0x11110222; |
481 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 482 | cpu->ctr = 0x80038003; |
0ca7e01c | 483 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
484 | cpu->id_pfr0 = 0x1031; |
485 | cpu->id_pfr1 = 0x11; | |
486 | cpu->id_dfr0 = 0x000; | |
487 | cpu->id_afr0 = 0; | |
488 | cpu->id_mmfr0 = 0x00100103; | |
489 | cpu->id_mmfr1 = 0x20000000; | |
490 | cpu->id_mmfr2 = 0x01230000; | |
491 | cpu->id_mmfr3 = 0x00002111; | |
492 | cpu->id_isar0 = 0x00101111; | |
493 | cpu->id_isar1 = 0x13112111; | |
494 | cpu->id_isar2 = 0x21232041; | |
495 | cpu->id_isar3 = 0x11112131; | |
496 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
497 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
498 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
499 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
1047b9d7 PM |
500 | { |
501 | ARMCPRegInfo cbar = { | |
502 | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, | |
503 | .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
504 | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) | |
505 | }; | |
506 | define_one_arm_cp_reg(cpu, &cbar); | |
507 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); | |
508 | } | |
777dc784 PM |
509 | } |
510 | ||
34f90529 PM |
511 | #ifndef CONFIG_USER_ONLY |
512 | static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
513 | uint64_t *value) | |
514 | { | |
515 | /* Linux wants the number of processors from here. | |
516 | * Might as well set the interrupt-controller bit too. | |
517 | */ | |
518 | *value = ((smp_cpus - 1) << 24) | (1 << 23); | |
519 | return 0; | |
520 | } | |
521 | #endif | |
522 | ||
523 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
524 | #ifndef CONFIG_USER_ONLY | |
525 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
526 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
527 | .writefn = arm_cp_write_ignore, }, | |
528 | #endif | |
529 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
530 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
531 | REGINFO_SENTINEL | |
532 | }; | |
533 | ||
777dc784 PM |
534 | static void cortex_a15_initfn(Object *obj) |
535 | { | |
536 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
537 | set_feature(&cpu->env, ARM_FEATURE_V7); |
538 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
539 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
540 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
541 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
542 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
543 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
544 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
c4804214 | 545 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 546 | cpu->midr = ARM_CPUID_CORTEXA15; |
325b3cef | 547 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
548 | cpu->mvfr0 = 0x10110222; |
549 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 550 | cpu->ctr = 0x8444c004; |
0ca7e01c | 551 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
552 | cpu->id_pfr0 = 0x00001131; |
553 | cpu->id_pfr1 = 0x00011011; | |
554 | cpu->id_dfr0 = 0x02010555; | |
555 | cpu->id_afr0 = 0x00000000; | |
556 | cpu->id_mmfr0 = 0x10201105; | |
557 | cpu->id_mmfr1 = 0x20000000; | |
558 | cpu->id_mmfr2 = 0x01240000; | |
559 | cpu->id_mmfr3 = 0x02102211; | |
560 | cpu->id_isar0 = 0x02101110; | |
561 | cpu->id_isar1 = 0x13112111; | |
562 | cpu->id_isar2 = 0x21232041; | |
563 | cpu->id_isar3 = 0x11112131; | |
564 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
565 | cpu->clidr = 0x0a200023; |
566 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
567 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
568 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 569 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
570 | } |
571 | ||
572 | static void ti925t_initfn(Object *obj) | |
573 | { | |
574 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
575 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
576 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 577 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 578 | cpu->ctr = 0x5109149; |
0ca7e01c | 579 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
580 | } |
581 | ||
582 | static void sa1100_initfn(Object *obj) | |
583 | { | |
584 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 585 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 586 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 587 | cpu->midr = ARM_CPUID_SA1100; |
0ca7e01c | 588 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
589 | } |
590 | ||
591 | static void sa1110_initfn(Object *obj) | |
592 | { | |
593 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 594 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 595 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
777dc784 | 596 | cpu->midr = ARM_CPUID_SA1110; |
0ca7e01c | 597 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
598 | } |
599 | ||
600 | static void pxa250_initfn(Object *obj) | |
601 | { | |
602 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
603 | set_feature(&cpu->env, ARM_FEATURE_V5); |
604 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 605 | cpu->midr = ARM_CPUID_PXA250; |
64e1671f | 606 | cpu->ctr = 0xd172172; |
0ca7e01c | 607 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
608 | } |
609 | ||
610 | static void pxa255_initfn(Object *obj) | |
611 | { | |
612 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
613 | set_feature(&cpu->env, ARM_FEATURE_V5); |
614 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 615 | cpu->midr = ARM_CPUID_PXA255; |
64e1671f | 616 | cpu->ctr = 0xd172172; |
0ca7e01c | 617 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
618 | } |
619 | ||
620 | static void pxa260_initfn(Object *obj) | |
621 | { | |
622 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
623 | set_feature(&cpu->env, ARM_FEATURE_V5); |
624 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 625 | cpu->midr = ARM_CPUID_PXA260; |
64e1671f | 626 | cpu->ctr = 0xd172172; |
0ca7e01c | 627 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
628 | } |
629 | ||
630 | static void pxa261_initfn(Object *obj) | |
631 | { | |
632 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
633 | set_feature(&cpu->env, ARM_FEATURE_V5); |
634 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 635 | cpu->midr = ARM_CPUID_PXA261; |
64e1671f | 636 | cpu->ctr = 0xd172172; |
0ca7e01c | 637 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
638 | } |
639 | ||
640 | static void pxa262_initfn(Object *obj) | |
641 | { | |
642 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
643 | set_feature(&cpu->env, ARM_FEATURE_V5); |
644 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 645 | cpu->midr = ARM_CPUID_PXA262; |
64e1671f | 646 | cpu->ctr = 0xd172172; |
0ca7e01c | 647 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
648 | } |
649 | ||
650 | static void pxa270a0_initfn(Object *obj) | |
651 | { | |
652 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
653 | set_feature(&cpu->env, ARM_FEATURE_V5); |
654 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
655 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 656 | cpu->midr = ARM_CPUID_PXA270_A0; |
64e1671f | 657 | cpu->ctr = 0xd172172; |
0ca7e01c | 658 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
659 | } |
660 | ||
661 | static void pxa270a1_initfn(Object *obj) | |
662 | { | |
663 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
664 | set_feature(&cpu->env, ARM_FEATURE_V5); |
665 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
666 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 667 | cpu->midr = ARM_CPUID_PXA270_A1; |
64e1671f | 668 | cpu->ctr = 0xd172172; |
0ca7e01c | 669 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
670 | } |
671 | ||
672 | static void pxa270b0_initfn(Object *obj) | |
673 | { | |
674 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
675 | set_feature(&cpu->env, ARM_FEATURE_V5); |
676 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
677 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 678 | cpu->midr = ARM_CPUID_PXA270_B0; |
64e1671f | 679 | cpu->ctr = 0xd172172; |
0ca7e01c | 680 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
681 | } |
682 | ||
683 | static void pxa270b1_initfn(Object *obj) | |
684 | { | |
685 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
686 | set_feature(&cpu->env, ARM_FEATURE_V5); |
687 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
688 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 689 | cpu->midr = ARM_CPUID_PXA270_B1; |
64e1671f | 690 | cpu->ctr = 0xd172172; |
0ca7e01c | 691 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
692 | } |
693 | ||
694 | static void pxa270c0_initfn(Object *obj) | |
695 | { | |
696 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
697 | set_feature(&cpu->env, ARM_FEATURE_V5); |
698 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
699 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 700 | cpu->midr = ARM_CPUID_PXA270_C0; |
64e1671f | 701 | cpu->ctr = 0xd172172; |
0ca7e01c | 702 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
703 | } |
704 | ||
705 | static void pxa270c5_initfn(Object *obj) | |
706 | { | |
707 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
708 | set_feature(&cpu->env, ARM_FEATURE_V5); |
709 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
710 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 711 | cpu->midr = ARM_CPUID_PXA270_C5; |
64e1671f | 712 | cpu->ctr = 0xd172172; |
0ca7e01c | 713 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
714 | } |
715 | ||
716 | static void arm_any_initfn(Object *obj) | |
717 | { | |
718 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
719 | set_feature(&cpu->env, ARM_FEATURE_V7); |
720 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
721 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
722 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
723 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
724 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
725 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 PM |
726 | cpu->midr = ARM_CPUID_ANY; |
727 | } | |
728 | ||
729 | typedef struct ARMCPUInfo { | |
730 | const char *name; | |
731 | void (*initfn)(Object *obj); | |
732 | } ARMCPUInfo; | |
733 | ||
734 | static const ARMCPUInfo arm_cpus[] = { | |
735 | { .name = "arm926", .initfn = arm926_initfn }, | |
736 | { .name = "arm946", .initfn = arm946_initfn }, | |
737 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
738 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
739 | * older core than plain "arm1136". In particular this does not | |
740 | * have the v6K features. | |
741 | */ | |
742 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
743 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
744 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
745 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
746 | { .name = "cortex-m3", .initfn = cortex_m3_initfn }, | |
747 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | |
748 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
749 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
750 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
751 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
752 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
753 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
754 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
755 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
756 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
757 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
758 | /* "pxa270" is an alias for "pxa270-a0" */ | |
759 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
760 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
761 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
762 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
763 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
764 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
765 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
766 | { .name = "any", .initfn = arm_any_initfn }, | |
767 | }; | |
768 | ||
dec9c2d4 AF |
769 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
770 | { | |
771 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
772 | CPUClass *cc = CPU_CLASS(acc); | |
773 | ||
774 | acc->parent_reset = cc->reset; | |
775 | cc->reset = arm_cpu_reset; | |
776 | } | |
777 | ||
777dc784 PM |
778 | static void cpu_register(const ARMCPUInfo *info) |
779 | { | |
780 | TypeInfo type_info = { | |
781 | .name = info->name, | |
782 | .parent = TYPE_ARM_CPU, | |
783 | .instance_size = sizeof(ARMCPU), | |
784 | .instance_init = info->initfn, | |
785 | .class_size = sizeof(ARMCPUClass), | |
786 | }; | |
787 | ||
788 | type_register_static(&type_info); | |
789 | } | |
790 | ||
dec9c2d4 AF |
791 | static const TypeInfo arm_cpu_type_info = { |
792 | .name = TYPE_ARM_CPU, | |
793 | .parent = TYPE_CPU, | |
794 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 795 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 796 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 797 | .abstract = true, |
dec9c2d4 AF |
798 | .class_size = sizeof(ARMCPUClass), |
799 | .class_init = arm_cpu_class_init, | |
800 | }; | |
801 | ||
802 | static void arm_cpu_register_types(void) | |
803 | { | |
777dc784 PM |
804 | int i; |
805 | ||
dec9c2d4 | 806 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
807 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
808 | cpu_register(&arm_cpus[i]); | |
809 | } | |
dec9c2d4 AF |
810 | } |
811 | ||
812 | type_init(arm_cpu_register_types) |