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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
dec9c2d4 | 22 | #include "qemu-common.h" |
3c30dd5a PM |
23 | #if !defined(CONFIG_USER_ONLY) |
24 | #include "hw/loader.h" | |
25 | #endif | |
dec9c2d4 | 26 | |
4b6a83fb PM |
27 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
28 | { | |
29 | /* Reset a single ARMCPRegInfo register */ | |
30 | ARMCPRegInfo *ri = value; | |
31 | ARMCPU *cpu = opaque; | |
32 | ||
33 | if (ri->type & ARM_CP_SPECIAL) { | |
34 | return; | |
35 | } | |
36 | ||
37 | if (ri->resetfn) { | |
38 | ri->resetfn(&cpu->env, ri); | |
39 | return; | |
40 | } | |
41 | ||
42 | /* A zero offset is never possible as it would be regs[0] | |
43 | * so we use it to indicate that reset is being handled elsewhere. | |
44 | * This is basically only used for fields in non-core coprocessors | |
45 | * (like the pxa2xx ones). | |
46 | */ | |
47 | if (!ri->fieldoffset) { | |
48 | return; | |
49 | } | |
50 | ||
51 | if (ri->type & ARM_CP_64BIT) { | |
52 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
53 | } else { | |
54 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
55 | } | |
56 | } | |
57 | ||
dec9c2d4 AF |
58 | /* CPUClass::reset() */ |
59 | static void arm_cpu_reset(CPUState *s) | |
60 | { | |
61 | ARMCPU *cpu = ARM_CPU(s); | |
62 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 63 | CPUARMState *env = &cpu->env; |
3c30dd5a PM |
64 | |
65 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
66 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
67 | log_cpu_state(env, 0); | |
68 | } | |
dec9c2d4 AF |
69 | |
70 | acc->parent_reset(s); | |
71 | ||
3c30dd5a | 72 | memset(env, 0, offsetof(CPUARMState, breakpoints)); |
4b6a83fb | 73 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
c5fad12f | 74 | env->cp15.c15_config_base_address = cpu->reset_cbar; |
3c30dd5a PM |
75 | env->cp15.c0_cpuid = cpu->midr; |
76 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; | |
77 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
78 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
79 | env->cp15.c0_cachetype = cpu->ctr; | |
80 | env->cp15.c1_sys = cpu->reset_sctlr; | |
81 | env->cp15.c0_c1[0] = cpu->id_pfr0; | |
82 | env->cp15.c0_c1[1] = cpu->id_pfr1; | |
83 | env->cp15.c0_c1[2] = cpu->id_dfr0; | |
84 | env->cp15.c0_c1[3] = cpu->id_afr0; | |
85 | env->cp15.c0_c1[4] = cpu->id_mmfr0; | |
86 | env->cp15.c0_c1[5] = cpu->id_mmfr1; | |
87 | env->cp15.c0_c1[6] = cpu->id_mmfr2; | |
88 | env->cp15.c0_c1[7] = cpu->id_mmfr3; | |
89 | env->cp15.c0_c2[0] = cpu->id_isar0; | |
90 | env->cp15.c0_c2[1] = cpu->id_isar1; | |
91 | env->cp15.c0_c2[2] = cpu->id_isar2; | |
92 | env->cp15.c0_c2[3] = cpu->id_isar3; | |
93 | env->cp15.c0_c2[4] = cpu->id_isar4; | |
94 | env->cp15.c0_c2[5] = cpu->id_isar5; | |
95 | env->cp15.c15_i_min = 0xff0; | |
96 | env->cp15.c0_clid = cpu->clidr; | |
97 | memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); | |
98 | ||
99 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
100 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
101 | } | |
102 | ||
103 | #if defined(CONFIG_USER_ONLY) | |
104 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
105 | /* For user mode we must enable access to coprocessors */ | |
106 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
107 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
108 | env->cp15.c15_cpar = 3; | |
109 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
110 | env->cp15.c15_cpar = 1; | |
111 | } | |
112 | #else | |
113 | /* SVC mode with interrupts disabled. */ | |
114 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
115 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
116 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
117 | if (IS_M(env)) { | |
118 | uint32_t pc; | |
119 | uint8_t *rom; | |
120 | env->uncached_cpsr &= ~CPSR_I; | |
121 | rom = rom_ptr(0); | |
122 | if (rom) { | |
123 | /* We should really use ldl_phys here, in case the guest | |
124 | modified flash and reset itself. However images | |
125 | loaded via -kernel have not been copied yet, so load the | |
126 | values directly from there. */ | |
127 | env->regs[13] = ldl_p(rom); | |
128 | pc = ldl_p(rom + 4); | |
129 | env->thumb = pc & 1; | |
130 | env->regs[15] = pc & ~1; | |
131 | } | |
132 | } | |
133 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
3c30dd5a PM |
134 | #endif |
135 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
136 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
137 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
138 | set_float_detect_tininess(float_tininess_before_rounding, | |
139 | &env->vfp.fp_status); | |
140 | set_float_detect_tininess(float_tininess_before_rounding, | |
141 | &env->vfp.standard_fp_status); | |
142 | tlb_flush(env, 1); | |
143 | /* Reset is a state change for some CPUARMState fields which we | |
144 | * bake assumptions about into translated code, so we need to | |
145 | * tb_flush(). | |
146 | */ | |
147 | tb_flush(env); | |
dec9c2d4 AF |
148 | } |
149 | ||
581be094 PM |
150 | static inline void set_feature(CPUARMState *env, int feature) |
151 | { | |
152 | env->features |= 1u << feature; | |
153 | } | |
154 | ||
777dc784 PM |
155 | static void arm_cpu_initfn(Object *obj) |
156 | { | |
157 | ARMCPU *cpu = ARM_CPU(obj); | |
158 | ||
159 | cpu_exec_init(&cpu->env); | |
4b6a83fb PM |
160 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
161 | g_free, g_free); | |
162 | } | |
163 | ||
164 | static void arm_cpu_finalizefn(Object *obj) | |
165 | { | |
166 | ARMCPU *cpu = ARM_CPU(obj); | |
167 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
168 | } |
169 | ||
581be094 PM |
170 | void arm_cpu_realize(ARMCPU *cpu) |
171 | { | |
172 | /* This function is called by cpu_arm_init() because it | |
173 | * needs to do common actions based on feature bits, etc | |
174 | * that have been set by the subclass init functions. | |
175 | * When we have QOM realize support it should become | |
176 | * a true realize function instead. | |
177 | */ | |
178 | CPUARMState *env = &cpu->env; | |
179 | /* Some features automatically imply others: */ | |
180 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
181 | set_feature(env, ARM_FEATURE_VAPA); | |
182 | set_feature(env, ARM_FEATURE_THUMB2); | |
183 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
184 | set_feature(env, ARM_FEATURE_V6K); | |
185 | } else { | |
186 | set_feature(env, ARM_FEATURE_V6); | |
187 | } | |
188 | } | |
189 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
190 | set_feature(env, ARM_FEATURE_V6); | |
191 | set_feature(env, ARM_FEATURE_MVFR); | |
192 | } | |
193 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
194 | set_feature(env, ARM_FEATURE_V5); | |
195 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
196 | set_feature(env, ARM_FEATURE_AUXCR); | |
197 | } | |
198 | } | |
199 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
200 | set_feature(env, ARM_FEATURE_V4T); | |
201 | } | |
202 | if (arm_feature(env, ARM_FEATURE_M)) { | |
203 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
204 | } | |
205 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
206 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
207 | } | |
208 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
209 | set_feature(env, ARM_FEATURE_VFP3); | |
210 | } | |
211 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
212 | set_feature(env, ARM_FEATURE_VFP); | |
213 | } | |
2ceb98c0 PM |
214 | |
215 | register_cp_regs_for_features(cpu); | |
581be094 PM |
216 | } |
217 | ||
777dc784 PM |
218 | /* CPU models */ |
219 | ||
220 | static void arm926_initfn(Object *obj) | |
221 | { | |
222 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
223 | set_feature(&cpu->env, ARM_FEATURE_V5); |
224 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 225 | cpu->midr = ARM_CPUID_ARM926; |
325b3cef | 226 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 227 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 228 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
229 | } |
230 | ||
231 | static void arm946_initfn(Object *obj) | |
232 | { | |
233 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
234 | set_feature(&cpu->env, ARM_FEATURE_V5); |
235 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
777dc784 | 236 | cpu->midr = ARM_CPUID_ARM946; |
64e1671f | 237 | cpu->ctr = 0x0f004006; |
0ca7e01c | 238 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
239 | } |
240 | ||
241 | static void arm1026_initfn(Object *obj) | |
242 | { | |
243 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
244 | set_feature(&cpu->env, ARM_FEATURE_V5); |
245 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
246 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
777dc784 | 247 | cpu->midr = ARM_CPUID_ARM1026; |
325b3cef | 248 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 249 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 250 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
251 | } |
252 | ||
253 | static void arm1136_r2_initfn(Object *obj) | |
254 | { | |
255 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
256 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
257 | * older core than plain "arm1136". In particular this does not | |
258 | * have the v6K features. | |
259 | * These ID register values are correct for 1136 but may be wrong | |
260 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
261 | * of the ID registers). | |
262 | */ | |
581be094 PM |
263 | set_feature(&cpu->env, ARM_FEATURE_V6); |
264 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 265 | cpu->midr = ARM_CPUID_ARM1136_R2; |
325b3cef | 266 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
267 | cpu->mvfr0 = 0x11111111; |
268 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 269 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 270 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
271 | cpu->id_pfr0 = 0x111; |
272 | cpu->id_pfr1 = 0x1; | |
273 | cpu->id_dfr0 = 0x2; | |
274 | cpu->id_afr0 = 0x3; | |
275 | cpu->id_mmfr0 = 0x01130003; | |
276 | cpu->id_mmfr1 = 0x10030302; | |
277 | cpu->id_mmfr2 = 0x01222110; | |
278 | cpu->id_isar0 = 0x00140011; | |
279 | cpu->id_isar1 = 0x12002111; | |
280 | cpu->id_isar2 = 0x11231111; | |
281 | cpu->id_isar3 = 0x01102131; | |
282 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
283 | } |
284 | ||
285 | static void arm1136_initfn(Object *obj) | |
286 | { | |
287 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
288 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
289 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
290 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 291 | cpu->midr = ARM_CPUID_ARM1136; |
325b3cef | 292 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
293 | cpu->mvfr0 = 0x11111111; |
294 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 295 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 296 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
297 | cpu->id_pfr0 = 0x111; |
298 | cpu->id_pfr1 = 0x1; | |
299 | cpu->id_dfr0 = 0x2; | |
300 | cpu->id_afr0 = 0x3; | |
301 | cpu->id_mmfr0 = 0x01130003; | |
302 | cpu->id_mmfr1 = 0x10030302; | |
303 | cpu->id_mmfr2 = 0x01222110; | |
304 | cpu->id_isar0 = 0x00140011; | |
305 | cpu->id_isar1 = 0x12002111; | |
306 | cpu->id_isar2 = 0x11231111; | |
307 | cpu->id_isar3 = 0x01102131; | |
308 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
309 | } |
310 | ||
311 | static void arm1176_initfn(Object *obj) | |
312 | { | |
313 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
314 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
315 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
316 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
777dc784 | 317 | cpu->midr = ARM_CPUID_ARM1176; |
325b3cef | 318 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
319 | cpu->mvfr0 = 0x11111111; |
320 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 321 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 322 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
323 | cpu->id_pfr0 = 0x111; |
324 | cpu->id_pfr1 = 0x11; | |
325 | cpu->id_dfr0 = 0x33; | |
326 | cpu->id_afr0 = 0; | |
327 | cpu->id_mmfr0 = 0x01130003; | |
328 | cpu->id_mmfr1 = 0x10030302; | |
329 | cpu->id_mmfr2 = 0x01222100; | |
330 | cpu->id_isar0 = 0x0140011; | |
331 | cpu->id_isar1 = 0x12002111; | |
332 | cpu->id_isar2 = 0x11231121; | |
333 | cpu->id_isar3 = 0x01102131; | |
334 | cpu->id_isar4 = 0x01141; | |
777dc784 PM |
335 | } |
336 | ||
337 | static void arm11mpcore_initfn(Object *obj) | |
338 | { | |
339 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
340 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
341 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
342 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
777dc784 | 343 | cpu->midr = ARM_CPUID_ARM11MPCORE; |
325b3cef | 344 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
345 | cpu->mvfr0 = 0x11111111; |
346 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 347 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
348 | cpu->id_pfr0 = 0x111; |
349 | cpu->id_pfr1 = 0x1; | |
350 | cpu->id_dfr0 = 0; | |
351 | cpu->id_afr0 = 0x2; | |
352 | cpu->id_mmfr0 = 0x01100103; | |
353 | cpu->id_mmfr1 = 0x10020302; | |
354 | cpu->id_mmfr2 = 0x01222000; | |
355 | cpu->id_isar0 = 0x00100011; | |
356 | cpu->id_isar1 = 0x12002111; | |
357 | cpu->id_isar2 = 0x11221011; | |
358 | cpu->id_isar3 = 0x01102131; | |
359 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
360 | } |
361 | ||
362 | static void cortex_m3_initfn(Object *obj) | |
363 | { | |
364 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
365 | set_feature(&cpu->env, ARM_FEATURE_V7); |
366 | set_feature(&cpu->env, ARM_FEATURE_M); | |
777dc784 PM |
367 | cpu->midr = ARM_CPUID_CORTEXM3; |
368 | } | |
369 | ||
370 | static void cortex_a8_initfn(Object *obj) | |
371 | { | |
372 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
373 | set_feature(&cpu->env, ARM_FEATURE_V7); |
374 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
375 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
376 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
777dc784 | 377 | cpu->midr = ARM_CPUID_CORTEXA8; |
325b3cef | 378 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
379 | cpu->mvfr0 = 0x11110222; |
380 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 381 | cpu->ctr = 0x82048004; |
0ca7e01c | 382 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
383 | cpu->id_pfr0 = 0x1031; |
384 | cpu->id_pfr1 = 0x11; | |
385 | cpu->id_dfr0 = 0x400; | |
386 | cpu->id_afr0 = 0; | |
387 | cpu->id_mmfr0 = 0x31100003; | |
388 | cpu->id_mmfr1 = 0x20000000; | |
389 | cpu->id_mmfr2 = 0x01202000; | |
390 | cpu->id_mmfr3 = 0x11; | |
391 | cpu->id_isar0 = 0x00101111; | |
392 | cpu->id_isar1 = 0x12112111; | |
393 | cpu->id_isar2 = 0x21232031; | |
394 | cpu->id_isar3 = 0x11112131; | |
395 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
396 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
397 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
398 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
399 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
777dc784 PM |
400 | } |
401 | ||
402 | static void cortex_a9_initfn(Object *obj) | |
403 | { | |
404 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
405 | set_feature(&cpu->env, ARM_FEATURE_V7); |
406 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
407 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
408 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
409 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
410 | /* Note that A9 supports the MP extensions even for | |
411 | * A9UP and single-core A9MP (which are both different | |
412 | * and valid configurations; we don't model A9UP). | |
413 | */ | |
414 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 | 415 | cpu->midr = ARM_CPUID_CORTEXA9; |
325b3cef | 416 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
417 | cpu->mvfr0 = 0x11110222; |
418 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 419 | cpu->ctr = 0x80038003; |
0ca7e01c | 420 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
421 | cpu->id_pfr0 = 0x1031; |
422 | cpu->id_pfr1 = 0x11; | |
423 | cpu->id_dfr0 = 0x000; | |
424 | cpu->id_afr0 = 0; | |
425 | cpu->id_mmfr0 = 0x00100103; | |
426 | cpu->id_mmfr1 = 0x20000000; | |
427 | cpu->id_mmfr2 = 0x01230000; | |
428 | cpu->id_mmfr3 = 0x00002111; | |
429 | cpu->id_isar0 = 0x00101111; | |
430 | cpu->id_isar1 = 0x13112111; | |
431 | cpu->id_isar2 = 0x21232041; | |
432 | cpu->id_isar3 = 0x11112131; | |
433 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
434 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
435 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
436 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
777dc784 PM |
437 | } |
438 | ||
439 | static void cortex_a15_initfn(Object *obj) | |
440 | { | |
441 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
442 | set_feature(&cpu->env, ARM_FEATURE_V7); |
443 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
444 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
445 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
446 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
447 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
448 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
449 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
777dc784 | 450 | cpu->midr = ARM_CPUID_CORTEXA15; |
325b3cef | 451 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
452 | cpu->mvfr0 = 0x10110222; |
453 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 454 | cpu->ctr = 0x8444c004; |
0ca7e01c | 455 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
456 | cpu->id_pfr0 = 0x00001131; |
457 | cpu->id_pfr1 = 0x00011011; | |
458 | cpu->id_dfr0 = 0x02010555; | |
459 | cpu->id_afr0 = 0x00000000; | |
460 | cpu->id_mmfr0 = 0x10201105; | |
461 | cpu->id_mmfr1 = 0x20000000; | |
462 | cpu->id_mmfr2 = 0x01240000; | |
463 | cpu->id_mmfr3 = 0x02102211; | |
464 | cpu->id_isar0 = 0x02101110; | |
465 | cpu->id_isar1 = 0x13112111; | |
466 | cpu->id_isar2 = 0x21232041; | |
467 | cpu->id_isar3 = 0x11112131; | |
468 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
469 | cpu->clidr = 0x0a200023; |
470 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
471 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
472 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
777dc784 PM |
473 | } |
474 | ||
475 | static void ti925t_initfn(Object *obj) | |
476 | { | |
477 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
478 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
479 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 480 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 481 | cpu->ctr = 0x5109149; |
0ca7e01c | 482 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
483 | } |
484 | ||
485 | static void sa1100_initfn(Object *obj) | |
486 | { | |
487 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 488 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
777dc784 | 489 | cpu->midr = ARM_CPUID_SA1100; |
0ca7e01c | 490 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
491 | } |
492 | ||
493 | static void sa1110_initfn(Object *obj) | |
494 | { | |
495 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 496 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
777dc784 | 497 | cpu->midr = ARM_CPUID_SA1110; |
0ca7e01c | 498 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
499 | } |
500 | ||
501 | static void pxa250_initfn(Object *obj) | |
502 | { | |
503 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
504 | set_feature(&cpu->env, ARM_FEATURE_V5); |
505 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 506 | cpu->midr = ARM_CPUID_PXA250; |
64e1671f | 507 | cpu->ctr = 0xd172172; |
0ca7e01c | 508 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
509 | } |
510 | ||
511 | static void pxa255_initfn(Object *obj) | |
512 | { | |
513 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
514 | set_feature(&cpu->env, ARM_FEATURE_V5); |
515 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 516 | cpu->midr = ARM_CPUID_PXA255; |
64e1671f | 517 | cpu->ctr = 0xd172172; |
0ca7e01c | 518 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
519 | } |
520 | ||
521 | static void pxa260_initfn(Object *obj) | |
522 | { | |
523 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
524 | set_feature(&cpu->env, ARM_FEATURE_V5); |
525 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 526 | cpu->midr = ARM_CPUID_PXA260; |
64e1671f | 527 | cpu->ctr = 0xd172172; |
0ca7e01c | 528 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
529 | } |
530 | ||
531 | static void pxa261_initfn(Object *obj) | |
532 | { | |
533 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
534 | set_feature(&cpu->env, ARM_FEATURE_V5); |
535 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 536 | cpu->midr = ARM_CPUID_PXA261; |
64e1671f | 537 | cpu->ctr = 0xd172172; |
0ca7e01c | 538 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
539 | } |
540 | ||
541 | static void pxa262_initfn(Object *obj) | |
542 | { | |
543 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
544 | set_feature(&cpu->env, ARM_FEATURE_V5); |
545 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 546 | cpu->midr = ARM_CPUID_PXA262; |
64e1671f | 547 | cpu->ctr = 0xd172172; |
0ca7e01c | 548 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
549 | } |
550 | ||
551 | static void pxa270a0_initfn(Object *obj) | |
552 | { | |
553 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
554 | set_feature(&cpu->env, ARM_FEATURE_V5); |
555 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
556 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 557 | cpu->midr = ARM_CPUID_PXA270_A0; |
64e1671f | 558 | cpu->ctr = 0xd172172; |
0ca7e01c | 559 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
560 | } |
561 | ||
562 | static void pxa270a1_initfn(Object *obj) | |
563 | { | |
564 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
565 | set_feature(&cpu->env, ARM_FEATURE_V5); |
566 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
567 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 568 | cpu->midr = ARM_CPUID_PXA270_A1; |
64e1671f | 569 | cpu->ctr = 0xd172172; |
0ca7e01c | 570 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
571 | } |
572 | ||
573 | static void pxa270b0_initfn(Object *obj) | |
574 | { | |
575 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
576 | set_feature(&cpu->env, ARM_FEATURE_V5); |
577 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
578 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 579 | cpu->midr = ARM_CPUID_PXA270_B0; |
64e1671f | 580 | cpu->ctr = 0xd172172; |
0ca7e01c | 581 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
582 | } |
583 | ||
584 | static void pxa270b1_initfn(Object *obj) | |
585 | { | |
586 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
587 | set_feature(&cpu->env, ARM_FEATURE_V5); |
588 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
589 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 590 | cpu->midr = ARM_CPUID_PXA270_B1; |
64e1671f | 591 | cpu->ctr = 0xd172172; |
0ca7e01c | 592 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
593 | } |
594 | ||
595 | static void pxa270c0_initfn(Object *obj) | |
596 | { | |
597 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
598 | set_feature(&cpu->env, ARM_FEATURE_V5); |
599 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
600 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 601 | cpu->midr = ARM_CPUID_PXA270_C0; |
64e1671f | 602 | cpu->ctr = 0xd172172; |
0ca7e01c | 603 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
604 | } |
605 | ||
606 | static void pxa270c5_initfn(Object *obj) | |
607 | { | |
608 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
609 | set_feature(&cpu->env, ARM_FEATURE_V5); |
610 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
611 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 612 | cpu->midr = ARM_CPUID_PXA270_C5; |
64e1671f | 613 | cpu->ctr = 0xd172172; |
0ca7e01c | 614 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
615 | } |
616 | ||
617 | static void arm_any_initfn(Object *obj) | |
618 | { | |
619 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
620 | set_feature(&cpu->env, ARM_FEATURE_V7); |
621 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
622 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
623 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
624 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
625 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
626 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 PM |
627 | cpu->midr = ARM_CPUID_ANY; |
628 | } | |
629 | ||
630 | typedef struct ARMCPUInfo { | |
631 | const char *name; | |
632 | void (*initfn)(Object *obj); | |
633 | } ARMCPUInfo; | |
634 | ||
635 | static const ARMCPUInfo arm_cpus[] = { | |
636 | { .name = "arm926", .initfn = arm926_initfn }, | |
637 | { .name = "arm946", .initfn = arm946_initfn }, | |
638 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
639 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
640 | * older core than plain "arm1136". In particular this does not | |
641 | * have the v6K features. | |
642 | */ | |
643 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
644 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
645 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
646 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
647 | { .name = "cortex-m3", .initfn = cortex_m3_initfn }, | |
648 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | |
649 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
650 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
651 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
652 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
653 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
654 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
655 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
656 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
657 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
658 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
659 | /* "pxa270" is an alias for "pxa270-a0" */ | |
660 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
661 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
662 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
663 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
664 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
665 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
666 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
667 | { .name = "any", .initfn = arm_any_initfn }, | |
668 | }; | |
669 | ||
dec9c2d4 AF |
670 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
671 | { | |
672 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
673 | CPUClass *cc = CPU_CLASS(acc); | |
674 | ||
675 | acc->parent_reset = cc->reset; | |
676 | cc->reset = arm_cpu_reset; | |
677 | } | |
678 | ||
777dc784 PM |
679 | static void cpu_register(const ARMCPUInfo *info) |
680 | { | |
681 | TypeInfo type_info = { | |
682 | .name = info->name, | |
683 | .parent = TYPE_ARM_CPU, | |
684 | .instance_size = sizeof(ARMCPU), | |
685 | .instance_init = info->initfn, | |
686 | .class_size = sizeof(ARMCPUClass), | |
687 | }; | |
688 | ||
689 | type_register_static(&type_info); | |
690 | } | |
691 | ||
dec9c2d4 AF |
692 | static const TypeInfo arm_cpu_type_info = { |
693 | .name = TYPE_ARM_CPU, | |
694 | .parent = TYPE_CPU, | |
695 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 696 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 697 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 698 | .abstract = true, |
dec9c2d4 AF |
699 | .class_size = sizeof(ARMCPUClass), |
700 | .class_init = arm_cpu_class_init, | |
701 | }; | |
702 | ||
703 | static void arm_cpu_register_types(void) | |
704 | { | |
777dc784 PM |
705 | int i; |
706 | ||
dec9c2d4 | 707 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
708 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
709 | cpu_register(&arm_cpus[i]); | |
710 | } | |
dec9c2d4 AF |
711 | } |
712 | ||
713 | type_init(arm_cpu_register_types) |