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cpu: Move cpu_index field to CPUState
[qemu.git] / target-arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
778c3a06 21#include "cpu.h"
dec9c2d4 22#include "qemu-common.h"
3c30dd5a
PM		 23#if !defined(CONFIG_USER_ONLY)
24#include "hw/loader.h"
25#endif
9c17d615 26#include "sysemu/sysemu.h"
dec9c2d4 27
4b6a83fb
PM		 28static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
29{
30 /* Reset a single ARMCPRegInfo register */
31 ARMCPRegInfo *ri = value;
32 ARMCPU *cpu = opaque;
33
34 if (ri->type & ARM_CP_SPECIAL) {
35 return;
36 }
37
38 if (ri->resetfn) {
39 ri->resetfn(&cpu->env, ri);
40 return;
41 }
42
43 /* A zero offset is never possible as it would be regs[0]
44 * so we use it to indicate that reset is being handled elsewhere.
45 * This is basically only used for fields in non-core coprocessors
46 * (like the pxa2xx ones).
47 */
48 if (!ri->fieldoffset) {
49 return;
50 }
51
52 if (ri->type & ARM_CP_64BIT) {
53 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
54 } else {
55 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
56 }
57}
58
dec9c2d4
AF		 59/* CPUClass::reset() */
60static void arm_cpu_reset(CPUState *s)
61{
62 ARMCPU *cpu = ARM_CPU(s);
63 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a 64 CPUARMState *env = &cpu->env;
3c30dd5a
PM		 65
66 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 67 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
3c30dd5a
PM		 68 log_cpu_state(env, 0);
69 }
dec9c2d4
AF		 70
71 acc->parent_reset(s);
72
3c30dd5a 73 memset(env, 0, offsetof(CPUARMState, breakpoints));
4b6a83fb 74 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
3c30dd5a
PM		 75 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
76 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
77 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
3c30dd5a
PM		 78
79 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
80 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
81 }
82
83#if defined(CONFIG_USER_ONLY)
84 env->uncached_cpsr = ARM_CPU_MODE_USR;
85 /* For user mode we must enable access to coprocessors */
86 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
87 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
88 env->cp15.c15_cpar = 3;
89 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
90 env->cp15.c15_cpar = 1;
91 }
92#else
93 /* SVC mode with interrupts disabled. */
94 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
95 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
96 clear at reset. Initial SP and PC are loaded from ROM. */
97 if (IS_M(env)) {
98 uint32_t pc;
99 uint8_t *rom;
100 env->uncached_cpsr &= ~CPSR_I;
101 rom = rom_ptr(0);
102 if (rom) {
103 /* We should really use ldl_phys here, in case the guest
104 modified flash and reset itself. However images
105 loaded via -kernel have not been copied yet, so load the
106 values directly from there. */
107 env->regs[13] = ldl_p(rom);
108 pc = ldl_p(rom + 4);
109 env->thumb = pc & 1;
110 env->regs[15] = pc & ~1;
111 }
112 }
113 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
3c30dd5a
PM		 114#endif
115 set_flush_to_zero(1, &env->vfp.standard_fp_status);
116 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
117 set_default_nan_mode(1, &env->vfp.standard_fp_status);
118 set_float_detect_tininess(float_tininess_before_rounding,
119 &env->vfp.fp_status);
120 set_float_detect_tininess(float_tininess_before_rounding,
121 &env->vfp.standard_fp_status);
122 tlb_flush(env, 1);
123 /* Reset is a state change for some CPUARMState fields which we
124 * bake assumptions about into translated code, so we need to
125 * tb_flush().
126 */
127 tb_flush(env);
dec9c2d4
AF		 128}
129
581be094
PM		 130static inline void set_feature(CPUARMState *env, int feature)
131{
918f5dca 132 env->features |= 1ULL << feature;
581be094
PM		 133}
134
777dc784
PM		 135static void arm_cpu_initfn(Object *obj)
136{
137 ARMCPU *cpu = ARM_CPU(obj);
138
139 cpu_exec_init(&cpu->env);
4b6a83fb
PM		 140 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
141 g_free, g_free);
142}
143
144static void arm_cpu_finalizefn(Object *obj)
145{
146 ARMCPU *cpu = ARM_CPU(obj);
147 g_hash_table_destroy(cpu->cp_regs);
777dc784
PM		 148}
149
581be094
PM		 150void arm_cpu_realize(ARMCPU *cpu)
151{
152 /* This function is called by cpu_arm_init() because it
153 * needs to do common actions based on feature bits, etc
154 * that have been set by the subclass init functions.
155 * When we have QOM realize support it should become
156 * a true realize function instead.
157 */
158 CPUARMState *env = &cpu->env;
159 /* Some features automatically imply others: */
160 if (arm_feature(env, ARM_FEATURE_V7)) {
161 set_feature(env, ARM_FEATURE_VAPA);
162 set_feature(env, ARM_FEATURE_THUMB2);
81bdde9d 163 set_feature(env, ARM_FEATURE_MPIDR);
581be094
PM		 164 if (!arm_feature(env, ARM_FEATURE_M)) {
165 set_feature(env, ARM_FEATURE_V6K);
166 } else {
167 set_feature(env, ARM_FEATURE_V6);
168 }
169 }
170 if (arm_feature(env, ARM_FEATURE_V6K)) {
171 set_feature(env, ARM_FEATURE_V6);
172 set_feature(env, ARM_FEATURE_MVFR);
173 }
174 if (arm_feature(env, ARM_FEATURE_V6)) {
175 set_feature(env, ARM_FEATURE_V5);
176 if (!arm_feature(env, ARM_FEATURE_M)) {
177 set_feature(env, ARM_FEATURE_AUXCR);
178 }
179 }
180 if (arm_feature(env, ARM_FEATURE_V5)) {
181 set_feature(env, ARM_FEATURE_V4T);
182 }
183 if (arm_feature(env, ARM_FEATURE_M)) {
184 set_feature(env, ARM_FEATURE_THUMB_DIV);
185 }
186 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
187 set_feature(env, ARM_FEATURE_THUMB_DIV);
188 }
189 if (arm_feature(env, ARM_FEATURE_VFP4)) {
190 set_feature(env, ARM_FEATURE_VFP3);
191 }
192 if (arm_feature(env, ARM_FEATURE_VFP3)) {
193 set_feature(env, ARM_FEATURE_VFP);
194 }
de9b05b8
PM		 195 if (arm_feature(env, ARM_FEATURE_LPAE)) {
196 set_feature(env, ARM_FEATURE_PXN);
197 }
2ceb98c0
PM		 198
199 register_cp_regs_for_features(cpu);
581be094
PM		 200}
201
777dc784
PM		 202/* CPU models */
203
204static void arm926_initfn(Object *obj)
205{
206 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 207 set_feature(&cpu->env, ARM_FEATURE_V5);
208 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 209 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
210 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 211 cpu->midr = 0x41069265;
325b3cef 212 cpu->reset_fpsid = 0x41011090;
64e1671f 213 cpu->ctr = 0x1dd20d2;
0ca7e01c 214 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 215}
216
217static void arm946_initfn(Object *obj)
218{
219 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 220 set_feature(&cpu->env, ARM_FEATURE_V5);
221 set_feature(&cpu->env, ARM_FEATURE_MPU);
c4804214 222 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 223 cpu->midr = 0x41059461;
64e1671f 224 cpu->ctr = 0x0f004006;
0ca7e01c 225 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 226}
227
228static void arm1026_initfn(Object *obj)
229{
230 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 231 set_feature(&cpu->env, ARM_FEATURE_V5);
232 set_feature(&cpu->env, ARM_FEATURE_VFP);
233 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
c4804214
PM		 234 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
235 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 236 cpu->midr = 0x4106a262;
325b3cef 237 cpu->reset_fpsid = 0x410110a0;
64e1671f 238 cpu->ctr = 0x1dd20d2;
0ca7e01c 239 cpu->reset_sctlr = 0x00090078;
2771db27 240 cpu->reset_auxcr = 1;
06d76f31
PM		 241 {
242 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
243 ARMCPRegInfo ifar = {
244 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
245 .access = PL1_RW,
246 .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
247 .resetvalue = 0
248 };
249 define_one_arm_cp_reg(cpu, &ifar);
250 }
777dc784
PM		 251}
252
253static void arm1136_r2_initfn(Object *obj)
254{
255 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 256 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
257 * older core than plain "arm1136". In particular this does not
258 * have the v6K features.
259 * These ID register values are correct for 1136 but may be wrong
260 * for 1136_r2 (in particular r0p2 does not actually implement most
261 * of the ID registers).
262 */
581be094
PM		 263 set_feature(&cpu->env, ARM_FEATURE_V6);
264 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 265 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
266 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
267 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 268 cpu->midr = 0x4107b362;
325b3cef 269 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 270 cpu->mvfr0 = 0x11111111;
271 cpu->mvfr1 = 0x00000000;
64e1671f 272 cpu->ctr = 0x1dd20d2;
0ca7e01c 273 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 274 cpu->id_pfr0 = 0x111;
275 cpu->id_pfr1 = 0x1;
276 cpu->id_dfr0 = 0x2;
277 cpu->id_afr0 = 0x3;
278 cpu->id_mmfr0 = 0x01130003;
279 cpu->id_mmfr1 = 0x10030302;
280 cpu->id_mmfr2 = 0x01222110;
281 cpu->id_isar0 = 0x00140011;
282 cpu->id_isar1 = 0x12002111;
283 cpu->id_isar2 = 0x11231111;
284 cpu->id_isar3 = 0x01102131;
285 cpu->id_isar4 = 0x141;
2771db27 286 cpu->reset_auxcr = 7;
777dc784
PM		 287}
288
289static void arm1136_initfn(Object *obj)
290{
291 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 292 set_feature(&cpu->env, ARM_FEATURE_V6K);
293 set_feature(&cpu->env, ARM_FEATURE_V6);
294 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 295 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
296 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
297 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 298 cpu->midr = 0x4117b363;
325b3cef 299 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 300 cpu->mvfr0 = 0x11111111;
301 cpu->mvfr1 = 0x00000000;
64e1671f 302 cpu->ctr = 0x1dd20d2;
0ca7e01c 303 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 304 cpu->id_pfr0 = 0x111;
305 cpu->id_pfr1 = 0x1;
306 cpu->id_dfr0 = 0x2;
307 cpu->id_afr0 = 0x3;
308 cpu->id_mmfr0 = 0x01130003;
309 cpu->id_mmfr1 = 0x10030302;
310 cpu->id_mmfr2 = 0x01222110;
311 cpu->id_isar0 = 0x00140011;
312 cpu->id_isar1 = 0x12002111;
313 cpu->id_isar2 = 0x11231111;
314 cpu->id_isar3 = 0x01102131;
315 cpu->id_isar4 = 0x141;
2771db27 316 cpu->reset_auxcr = 7;
777dc784
PM		 317}
318
319static void arm1176_initfn(Object *obj)
320{
321 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 322 set_feature(&cpu->env, ARM_FEATURE_V6K);
323 set_feature(&cpu->env, ARM_FEATURE_VFP);
324 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214
PM		 325 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
326 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
327 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 328 cpu->midr = 0x410fb767;
325b3cef 329 cpu->reset_fpsid = 0x410120b5;
bd35c355
PM		 330 cpu->mvfr0 = 0x11111111;
331 cpu->mvfr1 = 0x00000000;
64e1671f 332 cpu->ctr = 0x1dd20d2;
0ca7e01c 333 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 334 cpu->id_pfr0 = 0x111;
335 cpu->id_pfr1 = 0x11;
336 cpu->id_dfr0 = 0x33;
337 cpu->id_afr0 = 0;
338 cpu->id_mmfr0 = 0x01130003;
339 cpu->id_mmfr1 = 0x10030302;
340 cpu->id_mmfr2 = 0x01222100;
341 cpu->id_isar0 = 0x0140011;
342 cpu->id_isar1 = 0x12002111;
343 cpu->id_isar2 = 0x11231121;
344 cpu->id_isar3 = 0x01102131;
345 cpu->id_isar4 = 0x01141;
2771db27 346 cpu->reset_auxcr = 7;
777dc784
PM		 347}
348
349static void arm11mpcore_initfn(Object *obj)
350{
351 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 352 set_feature(&cpu->env, ARM_FEATURE_V6K);
353 set_feature(&cpu->env, ARM_FEATURE_VFP);
354 set_feature(&cpu->env, ARM_FEATURE_VAPA);
81bdde9d 355 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
c4804214 356 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 357 cpu->midr = 0x410fb022;
325b3cef 358 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 359 cpu->mvfr0 = 0x11111111;
360 cpu->mvfr1 = 0x00000000;
200bf596 361 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2e4d7e3e
PM		 362 cpu->id_pfr0 = 0x111;
363 cpu->id_pfr1 = 0x1;
364 cpu->id_dfr0 = 0;
365 cpu->id_afr0 = 0x2;
366 cpu->id_mmfr0 = 0x01100103;
367 cpu->id_mmfr1 = 0x10020302;
368 cpu->id_mmfr2 = 0x01222000;
369 cpu->id_isar0 = 0x00100011;
370 cpu->id_isar1 = 0x12002111;
371 cpu->id_isar2 = 0x11221011;
372 cpu->id_isar3 = 0x01102131;
373 cpu->id_isar4 = 0x141;
2771db27 374 cpu->reset_auxcr = 1;
777dc784
PM		 375}
376
377static void cortex_m3_initfn(Object *obj)
378{
379 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 380 set_feature(&cpu->env, ARM_FEATURE_V7);
381 set_feature(&cpu->env, ARM_FEATURE_M);
b2d06f96 382 cpu->midr = 0x410fc231;
777dc784
PM		 383}
384
34f90529
PM		 385static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
386 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
387 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
388 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
389 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
390 REGINFO_SENTINEL
391};
392
777dc784
PM		 393static void cortex_a8_initfn(Object *obj)
394{
395 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 396 set_feature(&cpu->env, ARM_FEATURE_V7);
397 set_feature(&cpu->env, ARM_FEATURE_VFP3);
398 set_feature(&cpu->env, ARM_FEATURE_NEON);
399 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c4804214 400 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 401 cpu->midr = 0x410fc080;
325b3cef 402 cpu->reset_fpsid = 0x410330c0;
bd35c355
PM		 403 cpu->mvfr0 = 0x11110222;
404 cpu->mvfr1 = 0x00011100;
64e1671f 405 cpu->ctr = 0x82048004;
0ca7e01c 406 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 407 cpu->id_pfr0 = 0x1031;
408 cpu->id_pfr1 = 0x11;
409 cpu->id_dfr0 = 0x400;
410 cpu->id_afr0 = 0;
411 cpu->id_mmfr0 = 0x31100003;
412 cpu->id_mmfr1 = 0x20000000;
413 cpu->id_mmfr2 = 0x01202000;
414 cpu->id_mmfr3 = 0x11;
415 cpu->id_isar0 = 0x00101111;
416 cpu->id_isar1 = 0x12112111;
417 cpu->id_isar2 = 0x21232031;
418 cpu->id_isar3 = 0x11112131;
419 cpu->id_isar4 = 0x00111142;
85df3786
PM		 420 cpu->clidr = (1 << 27) | (2 << 24) | 3;
421 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
422 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
423 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2771db27 424 cpu->reset_auxcr = 2;
34f90529 425 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
777dc784
PM		 426}
427
1047b9d7
PM		 428static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
429 /* power_control should be set to maximum latency. Again,
430 * default to 0 and set by private hook
431 */
432 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
433 .access = PL1_RW, .resetvalue = 0,
434 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
435 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
436 .access = PL1_RW, .resetvalue = 0,
437 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
438 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
439 .access = PL1_RW, .resetvalue = 0,
440 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
441 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
442 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
443 /* TLB lockdown control */
444 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
445 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
446 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
447 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
448 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
449 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
450 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
451 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
452 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
453 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
454 REGINFO_SENTINEL
455};
456
777dc784
PM		 457static void cortex_a9_initfn(Object *obj)
458{
459 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 460 set_feature(&cpu->env, ARM_FEATURE_V7);
461 set_feature(&cpu->env, ARM_FEATURE_VFP3);
462 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
463 set_feature(&cpu->env, ARM_FEATURE_NEON);
464 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
465 /* Note that A9 supports the MP extensions even for
466 * A9UP and single-core A9MP (which are both different
467 * and valid configurations; we don't model A9UP).
468 */
469 set_feature(&cpu->env, ARM_FEATURE_V7MP);
b2d06f96 470 cpu->midr = 0x410fc090;
325b3cef 471 cpu->reset_fpsid = 0x41033090;
bd35c355
PM		 472 cpu->mvfr0 = 0x11110222;
473 cpu->mvfr1 = 0x01111111;
64e1671f 474 cpu->ctr = 0x80038003;
0ca7e01c 475 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 476 cpu->id_pfr0 = 0x1031;
477 cpu->id_pfr1 = 0x11;
478 cpu->id_dfr0 = 0x000;
479 cpu->id_afr0 = 0;
480 cpu->id_mmfr0 = 0x00100103;
481 cpu->id_mmfr1 = 0x20000000;
482 cpu->id_mmfr2 = 0x01230000;
483 cpu->id_mmfr3 = 0x00002111;
484 cpu->id_isar0 = 0x00101111;
485 cpu->id_isar1 = 0x13112111;
486 cpu->id_isar2 = 0x21232041;
487 cpu->id_isar3 = 0x11112131;
488 cpu->id_isar4 = 0x00111142;
85df3786
PM		 489 cpu->clidr = (1 << 27) | (1 << 24) | 3;
490 cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
491 cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
1047b9d7
PM		 492 {
493 ARMCPRegInfo cbar = {
494 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4,
495 .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
496 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
497 };
498 define_one_arm_cp_reg(cpu, &cbar);
499 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
500 }
777dc784
PM		 501}
502
34f90529
PM		 503#ifndef CONFIG_USER_ONLY
504static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
505 uint64_t *value)
506{
507 /* Linux wants the number of processors from here.
508 * Might as well set the interrupt-controller bit too.
509 */
510 *value = ((smp_cpus - 1) << 24) | (1 << 23);
511 return 0;
512}
513#endif
514
515static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
516#ifndef CONFIG_USER_ONLY
517 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
518 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
519 .writefn = arm_cp_write_ignore, },
520#endif
521 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
522 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
523 REGINFO_SENTINEL
524};
525
777dc784
PM		 526static void cortex_a15_initfn(Object *obj)
527{
528 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 529 set_feature(&cpu->env, ARM_FEATURE_V7);
530 set_feature(&cpu->env, ARM_FEATURE_VFP4);
531 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
532 set_feature(&cpu->env, ARM_FEATURE_NEON);
533 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
534 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
535 set_feature(&cpu->env, ARM_FEATURE_V7MP);
536 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
c4804214 537 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
de9b05b8 538 set_feature(&cpu->env, ARM_FEATURE_LPAE);
b2d06f96 539 cpu->midr = 0x412fc0f1;
325b3cef 540 cpu->reset_fpsid = 0x410430f0;
bd35c355
PM		 541 cpu->mvfr0 = 0x10110222;
542 cpu->mvfr1 = 0x11111111;
64e1671f 543 cpu->ctr = 0x8444c004;
0ca7e01c 544 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 545 cpu->id_pfr0 = 0x00001131;
546 cpu->id_pfr1 = 0x00011011;
547 cpu->id_dfr0 = 0x02010555;
548 cpu->id_afr0 = 0x00000000;
549 cpu->id_mmfr0 = 0x10201105;
550 cpu->id_mmfr1 = 0x20000000;
551 cpu->id_mmfr2 = 0x01240000;
552 cpu->id_mmfr3 = 0x02102211;
553 cpu->id_isar0 = 0x02101110;
554 cpu->id_isar1 = 0x13112111;
555 cpu->id_isar2 = 0x21232041;
556 cpu->id_isar3 = 0x11112131;
557 cpu->id_isar4 = 0x10011142;
85df3786
PM		 558 cpu->clidr = 0x0a200023;
559 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
560 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
561 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
34f90529 562 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
777dc784
PM		 563}
564
565static void ti925t_initfn(Object *obj)
566{
567 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 568 set_feature(&cpu->env, ARM_FEATURE_V4T);
569 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 570 cpu->midr = ARM_CPUID_TI925T;
64e1671f 571 cpu->ctr = 0x5109149;
0ca7e01c 572 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 573}
574
575static void sa1100_initfn(Object *obj)
576{
577 ARMCPU *cpu = ARM_CPU(obj);
581be094 578 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 579 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 580 cpu->midr = 0x4401A11B;
0ca7e01c 581 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 582}
583
584static void sa1110_initfn(Object *obj)
585{
586 ARMCPU *cpu = ARM_CPU(obj);
581be094 587 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 588 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 589 cpu->midr = 0x6901B119;
0ca7e01c 590 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 591}
592
593static void pxa250_initfn(Object *obj)
594{
595 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 596 set_feature(&cpu->env, ARM_FEATURE_V5);
597 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 598 cpu->midr = 0x69052100;
64e1671f 599 cpu->ctr = 0xd172172;
0ca7e01c 600 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 601}
602
603static void pxa255_initfn(Object *obj)
604{
605 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 606 set_feature(&cpu->env, ARM_FEATURE_V5);
607 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 608 cpu->midr = 0x69052d00;
64e1671f 609 cpu->ctr = 0xd172172;
0ca7e01c 610 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 611}
612
613static void pxa260_initfn(Object *obj)
614{
615 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 616 set_feature(&cpu->env, ARM_FEATURE_V5);
617 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 618 cpu->midr = 0x69052903;
64e1671f 619 cpu->ctr = 0xd172172;
0ca7e01c 620 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 621}
622
623static void pxa261_initfn(Object *obj)
624{
625 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 626 set_feature(&cpu->env, ARM_FEATURE_V5);
627 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 628 cpu->midr = 0x69052d05;
64e1671f 629 cpu->ctr = 0xd172172;
0ca7e01c 630 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 631}
632
633static void pxa262_initfn(Object *obj)
634{
635 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 636 set_feature(&cpu->env, ARM_FEATURE_V5);
637 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 638 cpu->midr = 0x69052d06;
64e1671f 639 cpu->ctr = 0xd172172;
0ca7e01c 640 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 641}
642
643static void pxa270a0_initfn(Object *obj)
644{
645 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 646 set_feature(&cpu->env, ARM_FEATURE_V5);
647 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
648 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 649 cpu->midr = 0x69054110;
64e1671f 650 cpu->ctr = 0xd172172;
0ca7e01c 651 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 652}
653
654static void pxa270a1_initfn(Object *obj)
655{
656 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 657 set_feature(&cpu->env, ARM_FEATURE_V5);
658 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
659 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 660 cpu->midr = 0x69054111;
64e1671f 661 cpu->ctr = 0xd172172;
0ca7e01c 662 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 663}
664
665static void pxa270b0_initfn(Object *obj)
666{
667 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 668 set_feature(&cpu->env, ARM_FEATURE_V5);
669 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
670 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 671 cpu->midr = 0x69054112;
64e1671f 672 cpu->ctr = 0xd172172;
0ca7e01c 673 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 674}
675
676static void pxa270b1_initfn(Object *obj)
677{
678 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 679 set_feature(&cpu->env, ARM_FEATURE_V5);
680 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
681 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 682 cpu->midr = 0x69054113;
64e1671f 683 cpu->ctr = 0xd172172;
0ca7e01c 684 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 685}
686
687static void pxa270c0_initfn(Object *obj)
688{
689 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 690 set_feature(&cpu->env, ARM_FEATURE_V5);
691 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
692 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 693 cpu->midr = 0x69054114;
64e1671f 694 cpu->ctr = 0xd172172;
0ca7e01c 695 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 696}
697
698static void pxa270c5_initfn(Object *obj)
699{
700 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 701 set_feature(&cpu->env, ARM_FEATURE_V5);
702 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
703 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 704 cpu->midr = 0x69054117;
64e1671f 705 cpu->ctr = 0xd172172;
0ca7e01c 706 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 707}
708
709static void arm_any_initfn(Object *obj)
710{
711 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 712 set_feature(&cpu->env, ARM_FEATURE_V7);
713 set_feature(&cpu->env, ARM_FEATURE_VFP4);
714 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
715 set_feature(&cpu->env, ARM_FEATURE_NEON);
716 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
717 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
718 set_feature(&cpu->env, ARM_FEATURE_V7MP);
b2d06f96 719 cpu->midr = 0xffffffff;
777dc784
PM		 720}
721
722typedef struct ARMCPUInfo {
723 const char *name;
724 void (*initfn)(Object *obj);
725} ARMCPUInfo;
726
727static const ARMCPUInfo arm_cpus[] = {
728 { .name = "arm926", .initfn = arm926_initfn },
729 { .name = "arm946", .initfn = arm946_initfn },
730 { .name = "arm1026", .initfn = arm1026_initfn },
731 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
732 * older core than plain "arm1136". In particular this does not
733 * have the v6K features.
734 */
735 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
736 { .name = "arm1136", .initfn = arm1136_initfn },
737 { .name = "arm1176", .initfn = arm1176_initfn },
738 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
739 { .name = "cortex-m3", .initfn = cortex_m3_initfn },
740 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
741 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
742 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
743 { .name = "ti925t", .initfn = ti925t_initfn },
744 { .name = "sa1100", .initfn = sa1100_initfn },
745 { .name = "sa1110", .initfn = sa1110_initfn },
746 { .name = "pxa250", .initfn = pxa250_initfn },
747 { .name = "pxa255", .initfn = pxa255_initfn },
748 { .name = "pxa260", .initfn = pxa260_initfn },
749 { .name = "pxa261", .initfn = pxa261_initfn },
750 { .name = "pxa262", .initfn = pxa262_initfn },
751 /* "pxa270" is an alias for "pxa270-a0" */
752 { .name = "pxa270", .initfn = pxa270a0_initfn },
753 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
754 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
755 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
756 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
757 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
758 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
759 { .name = "any", .initfn = arm_any_initfn },
760};
761
dec9c2d4
AF		 762static void arm_cpu_class_init(ObjectClass *oc, void *data)
763{
764 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
765 CPUClass *cc = CPU_CLASS(acc);
766
767 acc->parent_reset = cc->reset;
768 cc->reset = arm_cpu_reset;
769}
770
777dc784
PM		 771static void cpu_register(const ARMCPUInfo *info)
772{
773 TypeInfo type_info = {
774 .name = info->name,
775 .parent = TYPE_ARM_CPU,
776 .instance_size = sizeof(ARMCPU),
777 .instance_init = info->initfn,
778 .class_size = sizeof(ARMCPUClass),
779 };
780
918fd083 781 type_register(&type_info);
777dc784
PM		 782}
783
dec9c2d4
AF		 784static const TypeInfo arm_cpu_type_info = {
785 .name = TYPE_ARM_CPU,
786 .parent = TYPE_CPU,
787 .instance_size = sizeof(ARMCPU),
777dc784 788 .instance_init = arm_cpu_initfn,
4b6a83fb 789 .instance_finalize = arm_cpu_finalizefn,
777dc784 790 .abstract = true,
dec9c2d4
AF		 791 .class_size = sizeof(ARMCPUClass),
792 .class_init = arm_cpu_class_init,
793};
794
795static void arm_cpu_register_types(void)
796{
777dc784
PM		 797 int i;
798
dec9c2d4 799 type_register_static(&arm_cpu_type_info);
777dc784
PM		 800 for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
801 cpu_register(&arm_cpus[i]);
802 }
dec9c2d4
AF		 803}
804
805type_init(arm_cpu_register_types)
Qemu copy for testing