]>
Commit | Line | Data |
---|---|---|
dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
21 | #include "cpu-qom.h" | |
22 | #include "qemu-common.h" | |
23 | ||
24 | /* CPUClass::reset() */ | |
25 | static void arm_cpu_reset(CPUState *s) | |
26 | { | |
27 | ARMCPU *cpu = ARM_CPU(s); | |
28 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
29 | ||
30 | acc->parent_reset(s); | |
31 | ||
32 | /* TODO Inline the current contents of cpu_state_reset(), | |
33 | once cpu_reset_model_id() is eliminated. */ | |
34 | cpu_state_reset(&cpu->env); | |
35 | } | |
36 | ||
581be094 PM |
37 | static inline void set_feature(CPUARMState *env, int feature) |
38 | { | |
39 | env->features |= 1u << feature; | |
40 | } | |
41 | ||
777dc784 PM |
42 | static void arm_cpu_initfn(Object *obj) |
43 | { | |
44 | ARMCPU *cpu = ARM_CPU(obj); | |
45 | ||
46 | cpu_exec_init(&cpu->env); | |
47 | } | |
48 | ||
581be094 PM |
49 | void arm_cpu_realize(ARMCPU *cpu) |
50 | { | |
51 | /* This function is called by cpu_arm_init() because it | |
52 | * needs to do common actions based on feature bits, etc | |
53 | * that have been set by the subclass init functions. | |
54 | * When we have QOM realize support it should become | |
55 | * a true realize function instead. | |
56 | */ | |
57 | CPUARMState *env = &cpu->env; | |
58 | /* Some features automatically imply others: */ | |
59 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
60 | set_feature(env, ARM_FEATURE_VAPA); | |
61 | set_feature(env, ARM_FEATURE_THUMB2); | |
62 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
63 | set_feature(env, ARM_FEATURE_V6K); | |
64 | } else { | |
65 | set_feature(env, ARM_FEATURE_V6); | |
66 | } | |
67 | } | |
68 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
69 | set_feature(env, ARM_FEATURE_V6); | |
70 | set_feature(env, ARM_FEATURE_MVFR); | |
71 | } | |
72 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
73 | set_feature(env, ARM_FEATURE_V5); | |
74 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
75 | set_feature(env, ARM_FEATURE_AUXCR); | |
76 | } | |
77 | } | |
78 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
79 | set_feature(env, ARM_FEATURE_V4T); | |
80 | } | |
81 | if (arm_feature(env, ARM_FEATURE_M)) { | |
82 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
83 | } | |
84 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
85 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
86 | } | |
87 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
88 | set_feature(env, ARM_FEATURE_VFP3); | |
89 | } | |
90 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
91 | set_feature(env, ARM_FEATURE_VFP); | |
92 | } | |
93 | } | |
94 | ||
777dc784 PM |
95 | /* CPU models */ |
96 | ||
97 | static void arm926_initfn(Object *obj) | |
98 | { | |
99 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
100 | set_feature(&cpu->env, ARM_FEATURE_V5); |
101 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 102 | cpu->midr = ARM_CPUID_ARM926; |
325b3cef | 103 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 104 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 105 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
106 | } |
107 | ||
108 | static void arm946_initfn(Object *obj) | |
109 | { | |
110 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
111 | set_feature(&cpu->env, ARM_FEATURE_V5); |
112 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
777dc784 | 113 | cpu->midr = ARM_CPUID_ARM946; |
64e1671f | 114 | cpu->ctr = 0x0f004006; |
0ca7e01c | 115 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
116 | } |
117 | ||
118 | static void arm1026_initfn(Object *obj) | |
119 | { | |
120 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
121 | set_feature(&cpu->env, ARM_FEATURE_V5); |
122 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
123 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
777dc784 | 124 | cpu->midr = ARM_CPUID_ARM1026; |
325b3cef | 125 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 126 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 127 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
128 | } |
129 | ||
130 | static void arm1136_r2_initfn(Object *obj) | |
131 | { | |
132 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
133 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
134 | * older core than plain "arm1136". In particular this does not | |
135 | * have the v6K features. | |
136 | * These ID register values are correct for 1136 but may be wrong | |
137 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
138 | * of the ID registers). | |
139 | */ | |
581be094 PM |
140 | set_feature(&cpu->env, ARM_FEATURE_V6); |
141 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 142 | cpu->midr = ARM_CPUID_ARM1136_R2; |
325b3cef | 143 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
144 | cpu->mvfr0 = 0x11111111; |
145 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 146 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 147 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
148 | cpu->id_pfr0 = 0x111; |
149 | cpu->id_pfr1 = 0x1; | |
150 | cpu->id_dfr0 = 0x2; | |
151 | cpu->id_afr0 = 0x3; | |
152 | cpu->id_mmfr0 = 0x01130003; | |
153 | cpu->id_mmfr1 = 0x10030302; | |
154 | cpu->id_mmfr2 = 0x01222110; | |
155 | cpu->id_isar0 = 0x00140011; | |
156 | cpu->id_isar1 = 0x12002111; | |
157 | cpu->id_isar2 = 0x11231111; | |
158 | cpu->id_isar3 = 0x01102131; | |
159 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
160 | } |
161 | ||
162 | static void arm1136_initfn(Object *obj) | |
163 | { | |
164 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
165 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
166 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
167 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
777dc784 | 168 | cpu->midr = ARM_CPUID_ARM1136; |
325b3cef | 169 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
170 | cpu->mvfr0 = 0x11111111; |
171 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 172 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 173 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
174 | cpu->id_pfr0 = 0x111; |
175 | cpu->id_pfr1 = 0x1; | |
176 | cpu->id_dfr0 = 0x2; | |
177 | cpu->id_afr0 = 0x3; | |
178 | cpu->id_mmfr0 = 0x01130003; | |
179 | cpu->id_mmfr1 = 0x10030302; | |
180 | cpu->id_mmfr2 = 0x01222110; | |
181 | cpu->id_isar0 = 0x00140011; | |
182 | cpu->id_isar1 = 0x12002111; | |
183 | cpu->id_isar2 = 0x11231111; | |
184 | cpu->id_isar3 = 0x01102131; | |
185 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
186 | } |
187 | ||
188 | static void arm1176_initfn(Object *obj) | |
189 | { | |
190 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
191 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
192 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
193 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
777dc784 | 194 | cpu->midr = ARM_CPUID_ARM1176; |
325b3cef | 195 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
196 | cpu->mvfr0 = 0x11111111; |
197 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 198 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 199 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
200 | cpu->id_pfr0 = 0x111; |
201 | cpu->id_pfr1 = 0x11; | |
202 | cpu->id_dfr0 = 0x33; | |
203 | cpu->id_afr0 = 0; | |
204 | cpu->id_mmfr0 = 0x01130003; | |
205 | cpu->id_mmfr1 = 0x10030302; | |
206 | cpu->id_mmfr2 = 0x01222100; | |
207 | cpu->id_isar0 = 0x0140011; | |
208 | cpu->id_isar1 = 0x12002111; | |
209 | cpu->id_isar2 = 0x11231121; | |
210 | cpu->id_isar3 = 0x01102131; | |
211 | cpu->id_isar4 = 0x01141; | |
777dc784 PM |
212 | } |
213 | ||
214 | static void arm11mpcore_initfn(Object *obj) | |
215 | { | |
216 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
217 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
218 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
219 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
777dc784 | 220 | cpu->midr = ARM_CPUID_ARM11MPCORE; |
325b3cef | 221 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
222 | cpu->mvfr0 = 0x11111111; |
223 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 224 | cpu->ctr = 0x1dd20d2; |
2e4d7e3e PM |
225 | cpu->id_pfr0 = 0x111; |
226 | cpu->id_pfr1 = 0x1; | |
227 | cpu->id_dfr0 = 0; | |
228 | cpu->id_afr0 = 0x2; | |
229 | cpu->id_mmfr0 = 0x01100103; | |
230 | cpu->id_mmfr1 = 0x10020302; | |
231 | cpu->id_mmfr2 = 0x01222000; | |
232 | cpu->id_isar0 = 0x00100011; | |
233 | cpu->id_isar1 = 0x12002111; | |
234 | cpu->id_isar2 = 0x11221011; | |
235 | cpu->id_isar3 = 0x01102131; | |
236 | cpu->id_isar4 = 0x141; | |
777dc784 PM |
237 | } |
238 | ||
239 | static void cortex_m3_initfn(Object *obj) | |
240 | { | |
241 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
242 | set_feature(&cpu->env, ARM_FEATURE_V7); |
243 | set_feature(&cpu->env, ARM_FEATURE_M); | |
777dc784 PM |
244 | cpu->midr = ARM_CPUID_CORTEXM3; |
245 | } | |
246 | ||
247 | static void cortex_a8_initfn(Object *obj) | |
248 | { | |
249 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
250 | set_feature(&cpu->env, ARM_FEATURE_V7); |
251 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
252 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
253 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
777dc784 | 254 | cpu->midr = ARM_CPUID_CORTEXA8; |
325b3cef | 255 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
256 | cpu->mvfr0 = 0x11110222; |
257 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 258 | cpu->ctr = 0x82048004; |
0ca7e01c | 259 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
260 | cpu->id_pfr0 = 0x1031; |
261 | cpu->id_pfr1 = 0x11; | |
262 | cpu->id_dfr0 = 0x400; | |
263 | cpu->id_afr0 = 0; | |
264 | cpu->id_mmfr0 = 0x31100003; | |
265 | cpu->id_mmfr1 = 0x20000000; | |
266 | cpu->id_mmfr2 = 0x01202000; | |
267 | cpu->id_mmfr3 = 0x11; | |
268 | cpu->id_isar0 = 0x00101111; | |
269 | cpu->id_isar1 = 0x12112111; | |
270 | cpu->id_isar2 = 0x21232031; | |
271 | cpu->id_isar3 = 0x11112131; | |
272 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
273 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
274 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
275 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
276 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
777dc784 PM |
277 | } |
278 | ||
279 | static void cortex_a9_initfn(Object *obj) | |
280 | { | |
281 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
282 | set_feature(&cpu->env, ARM_FEATURE_V7); |
283 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
284 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
285 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
286 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
287 | /* Note that A9 supports the MP extensions even for | |
288 | * A9UP and single-core A9MP (which are both different | |
289 | * and valid configurations; we don't model A9UP). | |
290 | */ | |
291 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 | 292 | cpu->midr = ARM_CPUID_CORTEXA9; |
325b3cef | 293 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
294 | cpu->mvfr0 = 0x11110222; |
295 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 296 | cpu->ctr = 0x80038003; |
0ca7e01c | 297 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
298 | cpu->id_pfr0 = 0x1031; |
299 | cpu->id_pfr1 = 0x11; | |
300 | cpu->id_dfr0 = 0x000; | |
301 | cpu->id_afr0 = 0; | |
302 | cpu->id_mmfr0 = 0x00100103; | |
303 | cpu->id_mmfr1 = 0x20000000; | |
304 | cpu->id_mmfr2 = 0x01230000; | |
305 | cpu->id_mmfr3 = 0x00002111; | |
306 | cpu->id_isar0 = 0x00101111; | |
307 | cpu->id_isar1 = 0x13112111; | |
308 | cpu->id_isar2 = 0x21232041; | |
309 | cpu->id_isar3 = 0x11112131; | |
310 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
311 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
312 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
313 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
777dc784 PM |
314 | } |
315 | ||
316 | static void cortex_a15_initfn(Object *obj) | |
317 | { | |
318 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
319 | set_feature(&cpu->env, ARM_FEATURE_V7); |
320 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
321 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
322 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
323 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
324 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
325 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
326 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
777dc784 | 327 | cpu->midr = ARM_CPUID_CORTEXA15; |
325b3cef | 328 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
329 | cpu->mvfr0 = 0x10110222; |
330 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 331 | cpu->ctr = 0x8444c004; |
0ca7e01c | 332 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
333 | cpu->id_pfr0 = 0x00001131; |
334 | cpu->id_pfr1 = 0x00011011; | |
335 | cpu->id_dfr0 = 0x02010555; | |
336 | cpu->id_afr0 = 0x00000000; | |
337 | cpu->id_mmfr0 = 0x10201105; | |
338 | cpu->id_mmfr1 = 0x20000000; | |
339 | cpu->id_mmfr2 = 0x01240000; | |
340 | cpu->id_mmfr3 = 0x02102211; | |
341 | cpu->id_isar0 = 0x02101110; | |
342 | cpu->id_isar1 = 0x13112111; | |
343 | cpu->id_isar2 = 0x21232041; | |
344 | cpu->id_isar3 = 0x11112131; | |
345 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
346 | cpu->clidr = 0x0a200023; |
347 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
348 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
349 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
777dc784 PM |
350 | } |
351 | ||
352 | static void ti925t_initfn(Object *obj) | |
353 | { | |
354 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
355 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
356 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 357 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 358 | cpu->ctr = 0x5109149; |
0ca7e01c | 359 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
360 | } |
361 | ||
362 | static void sa1100_initfn(Object *obj) | |
363 | { | |
364 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 365 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
777dc784 | 366 | cpu->midr = ARM_CPUID_SA1100; |
0ca7e01c | 367 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
368 | } |
369 | ||
370 | static void sa1110_initfn(Object *obj) | |
371 | { | |
372 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 373 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
777dc784 | 374 | cpu->midr = ARM_CPUID_SA1110; |
0ca7e01c | 375 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
376 | } |
377 | ||
378 | static void pxa250_initfn(Object *obj) | |
379 | { | |
380 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
381 | set_feature(&cpu->env, ARM_FEATURE_V5); |
382 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 383 | cpu->midr = ARM_CPUID_PXA250; |
64e1671f | 384 | cpu->ctr = 0xd172172; |
0ca7e01c | 385 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
386 | } |
387 | ||
388 | static void pxa255_initfn(Object *obj) | |
389 | { | |
390 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
391 | set_feature(&cpu->env, ARM_FEATURE_V5); |
392 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 393 | cpu->midr = ARM_CPUID_PXA255; |
64e1671f | 394 | cpu->ctr = 0xd172172; |
0ca7e01c | 395 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
396 | } |
397 | ||
398 | static void pxa260_initfn(Object *obj) | |
399 | { | |
400 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
401 | set_feature(&cpu->env, ARM_FEATURE_V5); |
402 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 403 | cpu->midr = ARM_CPUID_PXA260; |
64e1671f | 404 | cpu->ctr = 0xd172172; |
0ca7e01c | 405 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
406 | } |
407 | ||
408 | static void pxa261_initfn(Object *obj) | |
409 | { | |
410 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
411 | set_feature(&cpu->env, ARM_FEATURE_V5); |
412 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 413 | cpu->midr = ARM_CPUID_PXA261; |
64e1671f | 414 | cpu->ctr = 0xd172172; |
0ca7e01c | 415 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
416 | } |
417 | ||
418 | static void pxa262_initfn(Object *obj) | |
419 | { | |
420 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
421 | set_feature(&cpu->env, ARM_FEATURE_V5); |
422 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
777dc784 | 423 | cpu->midr = ARM_CPUID_PXA262; |
64e1671f | 424 | cpu->ctr = 0xd172172; |
0ca7e01c | 425 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
426 | } |
427 | ||
428 | static void pxa270a0_initfn(Object *obj) | |
429 | { | |
430 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
431 | set_feature(&cpu->env, ARM_FEATURE_V5); |
432 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
433 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 434 | cpu->midr = ARM_CPUID_PXA270_A0; |
64e1671f | 435 | cpu->ctr = 0xd172172; |
0ca7e01c | 436 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
437 | } |
438 | ||
439 | static void pxa270a1_initfn(Object *obj) | |
440 | { | |
441 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
442 | set_feature(&cpu->env, ARM_FEATURE_V5); |
443 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
444 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 445 | cpu->midr = ARM_CPUID_PXA270_A1; |
64e1671f | 446 | cpu->ctr = 0xd172172; |
0ca7e01c | 447 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
448 | } |
449 | ||
450 | static void pxa270b0_initfn(Object *obj) | |
451 | { | |
452 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
453 | set_feature(&cpu->env, ARM_FEATURE_V5); |
454 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
455 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 456 | cpu->midr = ARM_CPUID_PXA270_B0; |
64e1671f | 457 | cpu->ctr = 0xd172172; |
0ca7e01c | 458 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
459 | } |
460 | ||
461 | static void pxa270b1_initfn(Object *obj) | |
462 | { | |
463 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
464 | set_feature(&cpu->env, ARM_FEATURE_V5); |
465 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
466 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 467 | cpu->midr = ARM_CPUID_PXA270_B1; |
64e1671f | 468 | cpu->ctr = 0xd172172; |
0ca7e01c | 469 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
470 | } |
471 | ||
472 | static void pxa270c0_initfn(Object *obj) | |
473 | { | |
474 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
475 | set_feature(&cpu->env, ARM_FEATURE_V5); |
476 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
477 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 478 | cpu->midr = ARM_CPUID_PXA270_C0; |
64e1671f | 479 | cpu->ctr = 0xd172172; |
0ca7e01c | 480 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
481 | } |
482 | ||
483 | static void pxa270c5_initfn(Object *obj) | |
484 | { | |
485 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
486 | set_feature(&cpu->env, ARM_FEATURE_V5); |
487 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
488 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
777dc784 | 489 | cpu->midr = ARM_CPUID_PXA270_C5; |
64e1671f | 490 | cpu->ctr = 0xd172172; |
0ca7e01c | 491 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
492 | } |
493 | ||
494 | static void arm_any_initfn(Object *obj) | |
495 | { | |
496 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
497 | set_feature(&cpu->env, ARM_FEATURE_V7); |
498 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
499 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
500 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
501 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
502 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
503 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
777dc784 PM |
504 | cpu->midr = ARM_CPUID_ANY; |
505 | } | |
506 | ||
507 | typedef struct ARMCPUInfo { | |
508 | const char *name; | |
509 | void (*initfn)(Object *obj); | |
510 | } ARMCPUInfo; | |
511 | ||
512 | static const ARMCPUInfo arm_cpus[] = { | |
513 | { .name = "arm926", .initfn = arm926_initfn }, | |
514 | { .name = "arm946", .initfn = arm946_initfn }, | |
515 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
516 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
517 | * older core than plain "arm1136". In particular this does not | |
518 | * have the v6K features. | |
519 | */ | |
520 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
521 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
522 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
523 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
524 | { .name = "cortex-m3", .initfn = cortex_m3_initfn }, | |
525 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | |
526 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
527 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
528 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
529 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
530 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
531 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
532 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
533 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
534 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
535 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
536 | /* "pxa270" is an alias for "pxa270-a0" */ | |
537 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
538 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
539 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
540 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
541 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
542 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
543 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
544 | { .name = "any", .initfn = arm_any_initfn }, | |
545 | }; | |
546 | ||
dec9c2d4 AF |
547 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
548 | { | |
549 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
550 | CPUClass *cc = CPU_CLASS(acc); | |
551 | ||
552 | acc->parent_reset = cc->reset; | |
553 | cc->reset = arm_cpu_reset; | |
554 | } | |
555 | ||
777dc784 PM |
556 | static void cpu_register(const ARMCPUInfo *info) |
557 | { | |
558 | TypeInfo type_info = { | |
559 | .name = info->name, | |
560 | .parent = TYPE_ARM_CPU, | |
561 | .instance_size = sizeof(ARMCPU), | |
562 | .instance_init = info->initfn, | |
563 | .class_size = sizeof(ARMCPUClass), | |
564 | }; | |
565 | ||
566 | type_register_static(&type_info); | |
567 | } | |
568 | ||
dec9c2d4 AF |
569 | static const TypeInfo arm_cpu_type_info = { |
570 | .name = TYPE_ARM_CPU, | |
571 | .parent = TYPE_CPU, | |
572 | .instance_size = sizeof(ARMCPU), | |
777dc784 PM |
573 | .instance_init = arm_cpu_initfn, |
574 | .abstract = true, | |
dec9c2d4 AF |
575 | .class_size = sizeof(ARMCPUClass), |
576 | .class_init = arm_cpu_class_init, | |
577 | }; | |
578 | ||
579 | static void arm_cpu_register_types(void) | |
580 | { | |
777dc784 PM |
581 | int i; |
582 | ||
dec9c2d4 | 583 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
584 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
585 | cpu_register(&arm_cpus[i]); | |
586 | } | |
dec9c2d4 AF |
587 | } |
588 | ||
589 | type_init(arm_cpu_register_types) |