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target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
[qemu.git] / target-arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
778c3a06 21#include "cpu.h"
dec9c2d4 22#include "qemu-common.h"
3c30dd5a
PM		 23#if !defined(CONFIG_USER_ONLY)
24#include "hw/loader.h"
25#endif
9c17d615 26#include "sysemu/sysemu.h"
dec9c2d4 27
4b6a83fb
PM		 28static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
29{
30 /* Reset a single ARMCPRegInfo register */
31 ARMCPRegInfo *ri = value;
32 ARMCPU *cpu = opaque;
33
34 if (ri->type & ARM_CP_SPECIAL) {
35 return;
36 }
37
38 if (ri->resetfn) {
39 ri->resetfn(&cpu->env, ri);
40 return;
41 }
42
43 /* A zero offset is never possible as it would be regs[0]
44 * so we use it to indicate that reset is being handled elsewhere.
45 * This is basically only used for fields in non-core coprocessors
46 * (like the pxa2xx ones).
47 */
48 if (!ri->fieldoffset) {
49 return;
50 }
51
52 if (ri->type & ARM_CP_64BIT) {
53 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
54 } else {
55 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
56 }
57}
58
dec9c2d4
AF		 59/* CPUClass::reset() */
60static void arm_cpu_reset(CPUState *s)
61{
62 ARMCPU *cpu = ARM_CPU(s);
63 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a 64 CPUARMState *env = &cpu->env;
3c30dd5a
PM		 65
66 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 67 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
3c30dd5a
PM		 68 log_cpu_state(env, 0);
69 }
dec9c2d4
AF		 70
71 acc->parent_reset(s);
72
3c30dd5a 73 memset(env, 0, offsetof(CPUARMState, breakpoints));
4b6a83fb 74 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
3c30dd5a
PM		 75 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
76 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
77 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
3c30dd5a
PM		 78
79 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
80 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
81 }
82
83#if defined(CONFIG_USER_ONLY)
84 env->uncached_cpsr = ARM_CPU_MODE_USR;
85 /* For user mode we must enable access to coprocessors */
86 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
87 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
88 env->cp15.c15_cpar = 3;
89 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
90 env->cp15.c15_cpar = 1;
91 }
92#else
93 /* SVC mode with interrupts disabled. */
94 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
95 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
96 clear at reset. Initial SP and PC are loaded from ROM. */
97 if (IS_M(env)) {
98 uint32_t pc;
99 uint8_t *rom;
100 env->uncached_cpsr &= ~CPSR_I;
101 rom = rom_ptr(0);
102 if (rom) {
103 /* We should really use ldl_phys here, in case the guest
104 modified flash and reset itself. However images
105 loaded via -kernel have not been copied yet, so load the
106 values directly from there. */
107 env->regs[13] = ldl_p(rom);
108 pc = ldl_p(rom + 4);
109 env->thumb = pc & 1;
110 env->regs[15] = pc & ~1;
111 }
112 }
113 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
3c30dd5a
PM		 114#endif
115 set_flush_to_zero(1, &env->vfp.standard_fp_status);
116 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
117 set_default_nan_mode(1, &env->vfp.standard_fp_status);
118 set_float_detect_tininess(float_tininess_before_rounding,
119 &env->vfp.fp_status);
120 set_float_detect_tininess(float_tininess_before_rounding,
121 &env->vfp.standard_fp_status);
122 tlb_flush(env, 1);
123 /* Reset is a state change for some CPUARMState fields which we
124 * bake assumptions about into translated code, so we need to
125 * tb_flush().
126 */
127 tb_flush(env);
dec9c2d4
AF		 128}
129
581be094
PM		 130static inline void set_feature(CPUARMState *env, int feature)
131{
918f5dca 132 env->features |= 1ULL << feature;
581be094
PM		 133}
134
777dc784
PM		 135static void arm_cpu_initfn(Object *obj)
136{
137 ARMCPU *cpu = ARM_CPU(obj);
138
139 cpu_exec_init(&cpu->env);
4b6a83fb
PM		 140 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
141 g_free, g_free);
142}
143
144static void arm_cpu_finalizefn(Object *obj)
145{
146 ARMCPU *cpu = ARM_CPU(obj);
147 g_hash_table_destroy(cpu->cp_regs);
777dc784
PM		 148}
149
581be094
PM		 150void arm_cpu_realize(ARMCPU *cpu)
151{
152 /* This function is called by cpu_arm_init() because it
153 * needs to do common actions based on feature bits, etc
154 * that have been set by the subclass init functions.
155 * When we have QOM realize support it should become
156 * a true realize function instead.
157 */
158 CPUARMState *env = &cpu->env;
159 /* Some features automatically imply others: */
160 if (arm_feature(env, ARM_FEATURE_V7)) {
161 set_feature(env, ARM_FEATURE_VAPA);
162 set_feature(env, ARM_FEATURE_THUMB2);
81bdde9d 163 set_feature(env, ARM_FEATURE_MPIDR);
581be094
PM		 164 if (!arm_feature(env, ARM_FEATURE_M)) {
165 set_feature(env, ARM_FEATURE_V6K);
166 } else {
167 set_feature(env, ARM_FEATURE_V6);
168 }
169 }
170 if (arm_feature(env, ARM_FEATURE_V6K)) {
171 set_feature(env, ARM_FEATURE_V6);
172 set_feature(env, ARM_FEATURE_MVFR);
173 }
174 if (arm_feature(env, ARM_FEATURE_V6)) {
175 set_feature(env, ARM_FEATURE_V5);
176 if (!arm_feature(env, ARM_FEATURE_M)) {
177 set_feature(env, ARM_FEATURE_AUXCR);
178 }
179 }
180 if (arm_feature(env, ARM_FEATURE_V5)) {
181 set_feature(env, ARM_FEATURE_V4T);
182 }
183 if (arm_feature(env, ARM_FEATURE_M)) {
184 set_feature(env, ARM_FEATURE_THUMB_DIV);
185 }
186 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
187 set_feature(env, ARM_FEATURE_THUMB_DIV);
188 }
189 if (arm_feature(env, ARM_FEATURE_VFP4)) {
190 set_feature(env, ARM_FEATURE_VFP3);
191 }
192 if (arm_feature(env, ARM_FEATURE_VFP3)) {
193 set_feature(env, ARM_FEATURE_VFP);
194 }
de9b05b8
PM		 195 if (arm_feature(env, ARM_FEATURE_LPAE)) {
196 set_feature(env, ARM_FEATURE_PXN);
197 }
2ceb98c0
PM		 198
199 register_cp_regs_for_features(cpu);
581be094
PM		 200}
201
777dc784
PM		 202/* CPU models */
203
5900d6b2
AF		 204static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
205{
206 ObjectClass *oc;
207
208 if (!cpu_model) {
209 return NULL;
210 }
211
212 oc = object_class_by_name(cpu_model);
245fb54d
AF		 213 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
214 object_class_is_abstract(oc)) {
5900d6b2
AF		 215 return NULL;
216 }
217 return oc;
218}
219
777dc784
PM		 220static void arm926_initfn(Object *obj)
221{
222 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 223 set_feature(&cpu->env, ARM_FEATURE_V5);
224 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 225 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
226 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 227 cpu->midr = 0x41069265;
325b3cef 228 cpu->reset_fpsid = 0x41011090;
64e1671f 229 cpu->ctr = 0x1dd20d2;
0ca7e01c 230 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 231}
232
233static void arm946_initfn(Object *obj)
234{
235 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 236 set_feature(&cpu->env, ARM_FEATURE_V5);
237 set_feature(&cpu->env, ARM_FEATURE_MPU);
c4804214 238 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 239 cpu->midr = 0x41059461;
64e1671f 240 cpu->ctr = 0x0f004006;
0ca7e01c 241 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 242}
243
244static void arm1026_initfn(Object *obj)
245{
246 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 247 set_feature(&cpu->env, ARM_FEATURE_V5);
248 set_feature(&cpu->env, ARM_FEATURE_VFP);
249 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
c4804214
PM		 250 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
251 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 252 cpu->midr = 0x4106a262;
325b3cef 253 cpu->reset_fpsid = 0x410110a0;
64e1671f 254 cpu->ctr = 0x1dd20d2;
0ca7e01c 255 cpu->reset_sctlr = 0x00090078;
2771db27 256 cpu->reset_auxcr = 1;
06d76f31
PM		 257 {
258 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
259 ARMCPRegInfo ifar = {
260 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
261 .access = PL1_RW,
262 .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
263 .resetvalue = 0
264 };
265 define_one_arm_cp_reg(cpu, &ifar);
266 }
777dc784
PM		 267}
268
269static void arm1136_r2_initfn(Object *obj)
270{
271 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 272 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
273 * older core than plain "arm1136". In particular this does not
274 * have the v6K features.
275 * These ID register values are correct for 1136 but may be wrong
276 * for 1136_r2 (in particular r0p2 does not actually implement most
277 * of the ID registers).
278 */
581be094
PM		 279 set_feature(&cpu->env, ARM_FEATURE_V6);
280 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 281 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
282 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
283 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 284 cpu->midr = 0x4107b362;
325b3cef 285 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 286 cpu->mvfr0 = 0x11111111;
287 cpu->mvfr1 = 0x00000000;
64e1671f 288 cpu->ctr = 0x1dd20d2;
0ca7e01c 289 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 290 cpu->id_pfr0 = 0x111;
291 cpu->id_pfr1 = 0x1;
292 cpu->id_dfr0 = 0x2;
293 cpu->id_afr0 = 0x3;
294 cpu->id_mmfr0 = 0x01130003;
295 cpu->id_mmfr1 = 0x10030302;
296 cpu->id_mmfr2 = 0x01222110;
297 cpu->id_isar0 = 0x00140011;
298 cpu->id_isar1 = 0x12002111;
299 cpu->id_isar2 = 0x11231111;
300 cpu->id_isar3 = 0x01102131;
301 cpu->id_isar4 = 0x141;
2771db27 302 cpu->reset_auxcr = 7;
777dc784
PM		 303}
304
305static void arm1136_initfn(Object *obj)
306{
307 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 308 set_feature(&cpu->env, ARM_FEATURE_V6K);
309 set_feature(&cpu->env, ARM_FEATURE_V6);
310 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 311 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
312 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
313 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 314 cpu->midr = 0x4117b363;
325b3cef 315 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 316 cpu->mvfr0 = 0x11111111;
317 cpu->mvfr1 = 0x00000000;
64e1671f 318 cpu->ctr = 0x1dd20d2;
0ca7e01c 319 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 320 cpu->id_pfr0 = 0x111;
321 cpu->id_pfr1 = 0x1;
322 cpu->id_dfr0 = 0x2;
323 cpu->id_afr0 = 0x3;
324 cpu->id_mmfr0 = 0x01130003;
325 cpu->id_mmfr1 = 0x10030302;
326 cpu->id_mmfr2 = 0x01222110;
327 cpu->id_isar0 = 0x00140011;
328 cpu->id_isar1 = 0x12002111;
329 cpu->id_isar2 = 0x11231111;
330 cpu->id_isar3 = 0x01102131;
331 cpu->id_isar4 = 0x141;
2771db27 332 cpu->reset_auxcr = 7;
777dc784
PM		 333}
334
335static void arm1176_initfn(Object *obj)
336{
337 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 338 set_feature(&cpu->env, ARM_FEATURE_V6K);
339 set_feature(&cpu->env, ARM_FEATURE_VFP);
340 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214
PM		 341 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
342 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
343 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 344 cpu->midr = 0x410fb767;
325b3cef 345 cpu->reset_fpsid = 0x410120b5;
bd35c355
PM		 346 cpu->mvfr0 = 0x11111111;
347 cpu->mvfr1 = 0x00000000;
64e1671f 348 cpu->ctr = 0x1dd20d2;
0ca7e01c 349 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 350 cpu->id_pfr0 = 0x111;
351 cpu->id_pfr1 = 0x11;
352 cpu->id_dfr0 = 0x33;
353 cpu->id_afr0 = 0;
354 cpu->id_mmfr0 = 0x01130003;
355 cpu->id_mmfr1 = 0x10030302;
356 cpu->id_mmfr2 = 0x01222100;
357 cpu->id_isar0 = 0x0140011;
358 cpu->id_isar1 = 0x12002111;
359 cpu->id_isar2 = 0x11231121;
360 cpu->id_isar3 = 0x01102131;
361 cpu->id_isar4 = 0x01141;
2771db27 362 cpu->reset_auxcr = 7;
777dc784
PM		 363}
364
365static void arm11mpcore_initfn(Object *obj)
366{
367 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 368 set_feature(&cpu->env, ARM_FEATURE_V6K);
369 set_feature(&cpu->env, ARM_FEATURE_VFP);
370 set_feature(&cpu->env, ARM_FEATURE_VAPA);
81bdde9d 371 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
c4804214 372 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 373 cpu->midr = 0x410fb022;
325b3cef 374 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 375 cpu->mvfr0 = 0x11111111;
376 cpu->mvfr1 = 0x00000000;
200bf596 377 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2e4d7e3e
PM		 378 cpu->id_pfr0 = 0x111;
379 cpu->id_pfr1 = 0x1;
380 cpu->id_dfr0 = 0;
381 cpu->id_afr0 = 0x2;
382 cpu->id_mmfr0 = 0x01100103;
383 cpu->id_mmfr1 = 0x10020302;
384 cpu->id_mmfr2 = 0x01222000;
385 cpu->id_isar0 = 0x00100011;
386 cpu->id_isar1 = 0x12002111;
387 cpu->id_isar2 = 0x11221011;
388 cpu->id_isar3 = 0x01102131;
389 cpu->id_isar4 = 0x141;
2771db27 390 cpu->reset_auxcr = 1;
777dc784
PM		 391}
392
393static void cortex_m3_initfn(Object *obj)
394{
395 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 396 set_feature(&cpu->env, ARM_FEATURE_V7);
397 set_feature(&cpu->env, ARM_FEATURE_M);
b2d06f96 398 cpu->midr = 0x410fc231;
777dc784
PM		 399}
400
34f90529
PM		 401static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
402 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
403 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
404 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
405 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
406 REGINFO_SENTINEL
407};
408
777dc784
PM		 409static void cortex_a8_initfn(Object *obj)
410{
411 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 412 set_feature(&cpu->env, ARM_FEATURE_V7);
413 set_feature(&cpu->env, ARM_FEATURE_VFP3);
414 set_feature(&cpu->env, ARM_FEATURE_NEON);
415 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c4804214 416 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 417 cpu->midr = 0x410fc080;
325b3cef 418 cpu->reset_fpsid = 0x410330c0;
bd35c355
PM		 419 cpu->mvfr0 = 0x11110222;
420 cpu->mvfr1 = 0x00011100;
64e1671f 421 cpu->ctr = 0x82048004;
0ca7e01c 422 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 423 cpu->id_pfr0 = 0x1031;
424 cpu->id_pfr1 = 0x11;
425 cpu->id_dfr0 = 0x400;
426 cpu->id_afr0 = 0;
427 cpu->id_mmfr0 = 0x31100003;
428 cpu->id_mmfr1 = 0x20000000;
429 cpu->id_mmfr2 = 0x01202000;
430 cpu->id_mmfr3 = 0x11;
431 cpu->id_isar0 = 0x00101111;
432 cpu->id_isar1 = 0x12112111;
433 cpu->id_isar2 = 0x21232031;
434 cpu->id_isar3 = 0x11112131;
435 cpu->id_isar4 = 0x00111142;
85df3786
PM		 436 cpu->clidr = (1 << 27) | (2 << 24) | 3;
437 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
438 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
439 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2771db27 440 cpu->reset_auxcr = 2;
34f90529 441 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
777dc784
PM		 442}
443
1047b9d7
PM		 444static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
445 /* power_control should be set to maximum latency. Again,
446 * default to 0 and set by private hook
447 */
448 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
449 .access = PL1_RW, .resetvalue = 0,
450 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
451 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
452 .access = PL1_RW, .resetvalue = 0,
453 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
454 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
455 .access = PL1_RW, .resetvalue = 0,
456 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
457 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
458 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
459 /* TLB lockdown control */
460 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
461 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
462 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
463 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
464 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
465 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
466 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
467 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
468 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
469 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
470 REGINFO_SENTINEL
471};
472
777dc784
PM		 473static void cortex_a9_initfn(Object *obj)
474{
475 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 476 set_feature(&cpu->env, ARM_FEATURE_V7);
477 set_feature(&cpu->env, ARM_FEATURE_VFP3);
478 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
479 set_feature(&cpu->env, ARM_FEATURE_NEON);
480 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
481 /* Note that A9 supports the MP extensions even for
482 * A9UP and single-core A9MP (which are both different
483 * and valid configurations; we don't model A9UP).
484 */
485 set_feature(&cpu->env, ARM_FEATURE_V7MP);
b2d06f96 486 cpu->midr = 0x410fc090;
325b3cef 487 cpu->reset_fpsid = 0x41033090;
bd35c355
PM		 488 cpu->mvfr0 = 0x11110222;
489 cpu->mvfr1 = 0x01111111;
64e1671f 490 cpu->ctr = 0x80038003;
0ca7e01c 491 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 492 cpu->id_pfr0 = 0x1031;
493 cpu->id_pfr1 = 0x11;
494 cpu->id_dfr0 = 0x000;
495 cpu->id_afr0 = 0;
496 cpu->id_mmfr0 = 0x00100103;
497 cpu->id_mmfr1 = 0x20000000;
498 cpu->id_mmfr2 = 0x01230000;
499 cpu->id_mmfr3 = 0x00002111;
500 cpu->id_isar0 = 0x00101111;
501 cpu->id_isar1 = 0x13112111;
502 cpu->id_isar2 = 0x21232041;
503 cpu->id_isar3 = 0x11112131;
504 cpu->id_isar4 = 0x00111142;
85df3786
PM		 505 cpu->clidr = (1 << 27) | (1 << 24) | 3;
506 cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
507 cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
1047b9d7
PM		 508 {
509 ARMCPRegInfo cbar = {
510 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4,
511 .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
512 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
513 };
514 define_one_arm_cp_reg(cpu, &cbar);
515 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
516 }
777dc784
PM		 517}
518
34f90529
PM		 519#ifndef CONFIG_USER_ONLY
520static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
521 uint64_t *value)
522{
523 /* Linux wants the number of processors from here.
524 * Might as well set the interrupt-controller bit too.
525 */
526 *value = ((smp_cpus - 1) << 24) | (1 << 23);
527 return 0;
528}
529#endif
530
531static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
532#ifndef CONFIG_USER_ONLY
533 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
534 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
535 .writefn = arm_cp_write_ignore, },
536#endif
537 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
538 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
539 REGINFO_SENTINEL
540};
541
777dc784
PM		 542static void cortex_a15_initfn(Object *obj)
543{
544 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 545 set_feature(&cpu->env, ARM_FEATURE_V7);
546 set_feature(&cpu->env, ARM_FEATURE_VFP4);
547 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
548 set_feature(&cpu->env, ARM_FEATURE_NEON);
549 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
550 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
551 set_feature(&cpu->env, ARM_FEATURE_V7MP);
552 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
c4804214 553 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
de9b05b8 554 set_feature(&cpu->env, ARM_FEATURE_LPAE);
b2d06f96 555 cpu->midr = 0x412fc0f1;
325b3cef 556 cpu->reset_fpsid = 0x410430f0;
bd35c355
PM		 557 cpu->mvfr0 = 0x10110222;
558 cpu->mvfr1 = 0x11111111;
64e1671f 559 cpu->ctr = 0x8444c004;
0ca7e01c 560 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 561 cpu->id_pfr0 = 0x00001131;
562 cpu->id_pfr1 = 0x00011011;
563 cpu->id_dfr0 = 0x02010555;
564 cpu->id_afr0 = 0x00000000;
565 cpu->id_mmfr0 = 0x10201105;
566 cpu->id_mmfr1 = 0x20000000;
567 cpu->id_mmfr2 = 0x01240000;
568 cpu->id_mmfr3 = 0x02102211;
569 cpu->id_isar0 = 0x02101110;
570 cpu->id_isar1 = 0x13112111;
571 cpu->id_isar2 = 0x21232041;
572 cpu->id_isar3 = 0x11112131;
573 cpu->id_isar4 = 0x10011142;
85df3786
PM		 574 cpu->clidr = 0x0a200023;
575 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
576 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
577 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
34f90529 578 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
777dc784
PM		 579}
580
581static void ti925t_initfn(Object *obj)
582{
583 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 584 set_feature(&cpu->env, ARM_FEATURE_V4T);
585 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 586 cpu->midr = ARM_CPUID_TI925T;
64e1671f 587 cpu->ctr = 0x5109149;
0ca7e01c 588 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 589}
590
591static void sa1100_initfn(Object *obj)
592{
593 ARMCPU *cpu = ARM_CPU(obj);
581be094 594 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 595 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 596 cpu->midr = 0x4401A11B;
0ca7e01c 597 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 598}
599
600static void sa1110_initfn(Object *obj)
601{
602 ARMCPU *cpu = ARM_CPU(obj);
581be094 603 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 604 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 605 cpu->midr = 0x6901B119;
0ca7e01c 606 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 607}
608
609static void pxa250_initfn(Object *obj)
610{
611 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 612 set_feature(&cpu->env, ARM_FEATURE_V5);
613 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 614 cpu->midr = 0x69052100;
64e1671f 615 cpu->ctr = 0xd172172;
0ca7e01c 616 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 617}
618
619static void pxa255_initfn(Object *obj)
620{
621 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 622 set_feature(&cpu->env, ARM_FEATURE_V5);
623 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 624 cpu->midr = 0x69052d00;
64e1671f 625 cpu->ctr = 0xd172172;
0ca7e01c 626 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 627}
628
629static void pxa260_initfn(Object *obj)
630{
631 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 632 set_feature(&cpu->env, ARM_FEATURE_V5);
633 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 634 cpu->midr = 0x69052903;
64e1671f 635 cpu->ctr = 0xd172172;
0ca7e01c 636 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 637}
638
639static void pxa261_initfn(Object *obj)
640{
641 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 642 set_feature(&cpu->env, ARM_FEATURE_V5);
643 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 644 cpu->midr = 0x69052d05;
64e1671f 645 cpu->ctr = 0xd172172;
0ca7e01c 646 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 647}
648
649static void pxa262_initfn(Object *obj)
650{
651 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 652 set_feature(&cpu->env, ARM_FEATURE_V5);
653 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 654 cpu->midr = 0x69052d06;
64e1671f 655 cpu->ctr = 0xd172172;
0ca7e01c 656 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 657}
658
659static void pxa270a0_initfn(Object *obj)
660{
661 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 662 set_feature(&cpu->env, ARM_FEATURE_V5);
663 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
664 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 665 cpu->midr = 0x69054110;
64e1671f 666 cpu->ctr = 0xd172172;
0ca7e01c 667 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 668}
669
670static void pxa270a1_initfn(Object *obj)
671{
672 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 673 set_feature(&cpu->env, ARM_FEATURE_V5);
674 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
675 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 676 cpu->midr = 0x69054111;
64e1671f 677 cpu->ctr = 0xd172172;
0ca7e01c 678 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 679}
680
681static void pxa270b0_initfn(Object *obj)
682{
683 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 684 set_feature(&cpu->env, ARM_FEATURE_V5);
685 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
686 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 687 cpu->midr = 0x69054112;
64e1671f 688 cpu->ctr = 0xd172172;
0ca7e01c 689 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 690}
691
692static void pxa270b1_initfn(Object *obj)
693{
694 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 695 set_feature(&cpu->env, ARM_FEATURE_V5);
696 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
697 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 698 cpu->midr = 0x69054113;
64e1671f 699 cpu->ctr = 0xd172172;
0ca7e01c 700 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 701}
702
703static void pxa270c0_initfn(Object *obj)
704{
705 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 706 set_feature(&cpu->env, ARM_FEATURE_V5);
707 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
708 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 709 cpu->midr = 0x69054114;
64e1671f 710 cpu->ctr = 0xd172172;
0ca7e01c 711 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 712}
713
714static void pxa270c5_initfn(Object *obj)
715{
716 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 717 set_feature(&cpu->env, ARM_FEATURE_V5);
718 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
719 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 720 cpu->midr = 0x69054117;
64e1671f 721 cpu->ctr = 0xd172172;
0ca7e01c 722 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 723}
724
725static void arm_any_initfn(Object *obj)
726{
727 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 728 set_feature(&cpu->env, ARM_FEATURE_V7);
729 set_feature(&cpu->env, ARM_FEATURE_VFP4);
730 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
731 set_feature(&cpu->env, ARM_FEATURE_NEON);
732 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
733 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
734 set_feature(&cpu->env, ARM_FEATURE_V7MP);
b2d06f96 735 cpu->midr = 0xffffffff;
777dc784
PM		 736}
737
738typedef struct ARMCPUInfo {
739 const char *name;
740 void (*initfn)(Object *obj);
741} ARMCPUInfo;
742
743static const ARMCPUInfo arm_cpus[] = {
744 { .name = "arm926", .initfn = arm926_initfn },
745 { .name = "arm946", .initfn = arm946_initfn },
746 { .name = "arm1026", .initfn = arm1026_initfn },
747 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
748 * older core than plain "arm1136". In particular this does not
749 * have the v6K features.
750 */
751 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
752 { .name = "arm1136", .initfn = arm1136_initfn },
753 { .name = "arm1176", .initfn = arm1176_initfn },
754 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
755 { .name = "cortex-m3", .initfn = cortex_m3_initfn },
756 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
757 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
758 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
759 { .name = "ti925t", .initfn = ti925t_initfn },
760 { .name = "sa1100", .initfn = sa1100_initfn },
761 { .name = "sa1110", .initfn = sa1110_initfn },
762 { .name = "pxa250", .initfn = pxa250_initfn },
763 { .name = "pxa255", .initfn = pxa255_initfn },
764 { .name = "pxa260", .initfn = pxa260_initfn },
765 { .name = "pxa261", .initfn = pxa261_initfn },
766 { .name = "pxa262", .initfn = pxa262_initfn },
767 /* "pxa270" is an alias for "pxa270-a0" */
768 { .name = "pxa270", .initfn = pxa270a0_initfn },
769 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
770 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
771 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
772 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
773 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
774 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
775 { .name = "any", .initfn = arm_any_initfn },
776};
777
dec9c2d4
AF		 778static void arm_cpu_class_init(ObjectClass *oc, void *data)
779{
780 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
781 CPUClass *cc = CPU_CLASS(acc);
782
783 acc->parent_reset = cc->reset;
784 cc->reset = arm_cpu_reset;
5900d6b2
AF		 785
786 cc->class_by_name = arm_cpu_class_by_name;
dec9c2d4
AF		 787}
788
777dc784
PM		 789static void cpu_register(const ARMCPUInfo *info)
790{
791 TypeInfo type_info = {
792 .name = info->name,
793 .parent = TYPE_ARM_CPU,
794 .instance_size = sizeof(ARMCPU),
795 .instance_init = info->initfn,
796 .class_size = sizeof(ARMCPUClass),
797 };
798
918fd083 799 type_register(&type_info);
777dc784
PM		 800}
801
dec9c2d4
AF		 802static const TypeInfo arm_cpu_type_info = {
803 .name = TYPE_ARM_CPU,
804 .parent = TYPE_CPU,
805 .instance_size = sizeof(ARMCPU),
777dc784 806 .instance_init = arm_cpu_initfn,
4b6a83fb 807 .instance_finalize = arm_cpu_finalizefn,
777dc784 808 .abstract = true,
dec9c2d4
AF		 809 .class_size = sizeof(ARMCPUClass),
810 .class_init = arm_cpu_class_init,
811};
812
813static void arm_cpu_register_types(void)
814{
777dc784
PM		 815 int i;
816
dec9c2d4 817 type_register_static(&arm_cpu_type_info);
777dc784
PM		 818 for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
819 cpu_register(&arm_cpus[i]);
820 }
dec9c2d4
AF		 821}
822
823type_init(arm_cpu_register_types)
Qemu copy for testing