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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3cf1e035 FB |
22 | #define TARGET_LONG_BITS 32 |
23 | ||
9042c0e2 TS |
24 | #define ELF_MACHINE EM_ARM |
25 | ||
c2764719 PB |
26 | #define CPUState struct CPUARMState |
27 | ||
2c0262af FB |
28 | #include "cpu-defs.h" |
29 | ||
53cd6637 FB |
30 | #include "softfloat.h" |
31 | ||
1fddef4b FB |
32 | #define TARGET_HAS_ICE 1 |
33 | ||
b8a9e8f1 FB |
34 | #define EXCP_UDEF 1 /* undefined instruction */ |
35 | #define EXCP_SWI 2 /* software interrupt */ | |
36 | #define EXCP_PREFETCH_ABORT 3 | |
37 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
38 | #define EXCP_IRQ 5 |
39 | #define EXCP_FIQ 6 | |
06c949e6 | 40 | #define EXCP_BKPT 7 |
9ee6e8bb | 41 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 42 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
9ee6e8bb PB |
43 | |
44 | #define ARMV7M_EXCP_RESET 1 | |
45 | #define ARMV7M_EXCP_NMI 2 | |
46 | #define ARMV7M_EXCP_HARD 3 | |
47 | #define ARMV7M_EXCP_MEM 4 | |
48 | #define ARMV7M_EXCP_BUS 5 | |
49 | #define ARMV7M_EXCP_USAGE 6 | |
50 | #define ARMV7M_EXCP_SVC 11 | |
51 | #define ARMV7M_EXCP_DEBUG 12 | |
52 | #define ARMV7M_EXCP_PENDSV 14 | |
53 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 54 | |
c1713132 AZ |
55 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
56 | int srcreg, int operand, uint32_t value); | |
57 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
58 | int dstreg, int operand); | |
59 | ||
f93eb9ff AZ |
60 | struct arm_boot_info; |
61 | ||
6ebbf390 JM |
62 | #define NB_MMU_MODES 2 |
63 | ||
b7bcbe95 FB |
64 | /* We currently assume float and double are IEEE single and double |
65 | precision respectively. | |
66 | Doing runtime conversions is tricky because VFP registers may contain | |
67 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
68 | s<2n> maps to the least significant half of d<n> |
69 | s<2n+1> maps to the most significant half of d<n> | |
70 | */ | |
b7bcbe95 | 71 | |
2c0262af | 72 | typedef struct CPUARMState { |
b5ff1b31 | 73 | /* Regs for current mode. */ |
2c0262af | 74 | uint32_t regs[16]; |
b5ff1b31 | 75 | /* Frequently accessed CPSR bits are stored separately for efficiently. |
d37aca66 | 76 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
77 | the whole CPSR. */ |
78 | uint32_t uncached_cpsr; | |
79 | uint32_t spsr; | |
80 | ||
81 | /* Banked registers. */ | |
82 | uint32_t banked_spsr[6]; | |
83 | uint32_t banked_r13[6]; | |
84 | uint32_t banked_r14[6]; | |
3b46e624 | 85 | |
b5ff1b31 FB |
86 | /* These hold r8-r12. */ |
87 | uint32_t usr_regs[5]; | |
88 | uint32_t fiq_regs[5]; | |
3b46e624 | 89 | |
2c0262af FB |
90 | /* cpsr flag cache for faster execution */ |
91 | uint32_t CF; /* 0 or 1 */ | |
92 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
93 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
94 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 95 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 96 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 97 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 98 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
2c0262af | 99 | |
b5ff1b31 FB |
100 | /* System control coprocessor (cp15) */ |
101 | struct { | |
40f137e1 | 102 | uint32_t c0_cpuid; |
c1713132 | 103 | uint32_t c0_cachetype; |
a49ea279 PB |
104 | uint32_t c0_ccsid[16]; /* Cache size. */ |
105 | uint32_t c0_clid; /* Cache level. */ | |
106 | uint32_t c0_cssel; /* Cache size selection. */ | |
9ee6e8bb PB |
107 | uint32_t c0_c1[8]; /* Feature registers. */ |
108 | uint32_t c0_c2[8]; /* Instruction set registers. */ | |
b5ff1b31 FB |
109 | uint32_t c1_sys; /* System control register. */ |
110 | uint32_t c1_coproc; /* Coprocessor access register. */ | |
610c3c8a | 111 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
9ee6e8bb PB |
112 | uint32_t c2_base0; /* MMU translation table base 0. */ |
113 | uint32_t c2_base1; /* MMU translation table base 1. */ | |
b2fa1797 PB |
114 | uint32_t c2_control; /* MMU translation table base control. */ |
115 | uint32_t c2_mask; /* MMU translation table base selection mask. */ | |
116 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
117 | uint32_t c2_data; /* MPU data cachable bits. */ |
118 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
119 | uint32_t c3; /* MMU domain access control register | |
120 | MPU write buffer control. */ | |
b5ff1b31 FB |
121 | uint32_t c5_insn; /* Fault status registers. */ |
122 | uint32_t c5_data; | |
ce819861 | 123 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b5ff1b31 FB |
124 | uint32_t c6_insn; /* Fault address registers. */ |
125 | uint32_t c6_data; | |
126 | uint32_t c9_insn; /* Cache lockdown registers. */ | |
127 | uint32_t c9_data; | |
128 | uint32_t c13_fcse; /* FCSE PID. */ | |
129 | uint32_t c13_context; /* Context ID. */ | |
9ee6e8bb PB |
130 | uint32_t c13_tls1; /* User RW Thread register. */ |
131 | uint32_t c13_tls2; /* User RO Thread register. */ | |
132 | uint32_t c13_tls3; /* Privileged Thread register. */ | |
c1713132 | 133 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
134 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
135 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
136 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
137 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
b5ff1b31 | 138 | } cp15; |
40f137e1 | 139 | |
9ee6e8bb PB |
140 | struct { |
141 | uint32_t other_sp; | |
142 | uint32_t vecbase; | |
143 | uint32_t basepri; | |
144 | uint32_t control; | |
145 | int current_sp; | |
146 | int exception; | |
147 | int pending_exception; | |
148 | void *nvic; | |
149 | } v7m; | |
150 | ||
c1713132 AZ |
151 | /* Coprocessor IO used by peripherals */ |
152 | struct { | |
153 | ARMReadCPFunc *cp_read; | |
154 | ARMWriteCPFunc *cp_write; | |
155 | void *opaque; | |
156 | } cp[15]; | |
157 | ||
fe1479c3 PB |
158 | /* Thumb-2 EE state. */ |
159 | uint32_t teecr; | |
160 | uint32_t teehbr; | |
161 | ||
40f137e1 PB |
162 | /* Internal CPU feature flags. */ |
163 | uint32_t features; | |
164 | ||
9ee6e8bb PB |
165 | /* Callback for vectored interrupt controller. */ |
166 | int (*get_irq_vector)(struct CPUARMState *); | |
167 | void *irq_opaque; | |
168 | ||
b7bcbe95 FB |
169 | /* VFP coprocessor state. */ |
170 | struct { | |
9ee6e8bb | 171 | float64 regs[32]; |
b7bcbe95 | 172 | |
40f137e1 | 173 | uint32_t xregs[16]; |
b7bcbe95 FB |
174 | /* We store these fpcsr fields separately for convenience. */ |
175 | int vec_len; | |
176 | int vec_stride; | |
177 | ||
9ee6e8bb PB |
178 | /* scratch space when Tn are not sufficient. */ |
179 | uint32_t scratch[8]; | |
3b46e624 | 180 | |
53cd6637 | 181 | float_status fp_status; |
b7bcbe95 | 182 | } vfp; |
9ee6e8bb PB |
183 | #if defined(CONFIG_USER_ONLY) |
184 | struct mmon_state *mmon_entry; | |
185 | #else | |
186 | uint32_t mmon_addr; | |
187 | #endif | |
b7bcbe95 | 188 | |
18c9b560 AZ |
189 | /* iwMMXt coprocessor state. */ |
190 | struct { | |
191 | uint64_t regs[16]; | |
192 | uint64_t val; | |
193 | ||
194 | uint32_t cregs[16]; | |
195 | } iwmmxt; | |
196 | ||
ce4defa0 PB |
197 | #if defined(CONFIG_USER_ONLY) |
198 | /* For usermode syscall translation. */ | |
199 | int eabi; | |
200 | #endif | |
201 | ||
a316d335 FB |
202 | CPU_COMMON |
203 | ||
9d551997 | 204 | /* These fields after the common ones so they are preserved on reset. */ |
f93eb9ff | 205 | struct arm_boot_info *boot_info; |
2c0262af FB |
206 | } CPUARMState; |
207 | ||
aaed909a | 208 | CPUARMState *cpu_arm_init(const char *cpu_model); |
b26eefb6 | 209 | void arm_translate_init(void); |
2c0262af FB |
210 | int cpu_arm_exec(CPUARMState *s); |
211 | void cpu_arm_close(CPUARMState *s); | |
b5ff1b31 FB |
212 | void do_interrupt(CPUARMState *); |
213 | void switch_mode(CPUARMState *, int); | |
9ee6e8bb | 214 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 215 | |
2c0262af FB |
216 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
217 | signal handlers to inform the virtual CPU of exceptions. non zero | |
218 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 219 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 220 | void *puc); |
84a031c6 AJ |
221 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
222 | int mmu_idx, int is_softmuu); | |
0b5c1ce8 | 223 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
2c0262af | 224 | |
9ee6e8bb PB |
225 | void cpu_lock(void); |
226 | void cpu_unlock(void); | |
fbb4a2e3 PB |
227 | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
228 | { | |
229 | env->cp15.c13_tls2 = newtls; | |
230 | } | |
9ee6e8bb | 231 | |
b5ff1b31 FB |
232 | #define CPSR_M (0x1f) |
233 | #define CPSR_T (1 << 5) | |
234 | #define CPSR_F (1 << 6) | |
235 | #define CPSR_I (1 << 7) | |
236 | #define CPSR_A (1 << 8) | |
237 | #define CPSR_E (1 << 9) | |
238 | #define CPSR_IT_2_7 (0xfc00) | |
9ee6e8bb PB |
239 | #define CPSR_GE (0xf << 16) |
240 | #define CPSR_RESERVED (0xf << 20) | |
b5ff1b31 FB |
241 | #define CPSR_J (1 << 24) |
242 | #define CPSR_IT_0_1 (3 << 25) | |
243 | #define CPSR_Q (1 << 27) | |
9ee6e8bb PB |
244 | #define CPSR_V (1 << 28) |
245 | #define CPSR_C (1 << 29) | |
246 | #define CPSR_Z (1 << 30) | |
247 | #define CPSR_N (1 << 31) | |
248 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) | |
249 | ||
250 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
251 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) | |
252 | /* Bits writable in user mode. */ | |
253 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
254 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
255 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) | |
b5ff1b31 | 256 | |
b5ff1b31 | 257 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
258 | uint32_t cpsr_read(CPUARMState *env); |
259 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
260 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
261 | |
262 | /* Return the current xPSR value. */ | |
263 | static inline uint32_t xpsr_read(CPUARMState *env) | |
264 | { | |
265 | int ZF; | |
6fbe23d5 PB |
266 | ZF = (env->ZF == 0); |
267 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
268 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
269 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
270 | | ((env->condexec_bits & 0xfc) << 8) | |
271 | | env->v7m.exception; | |
b5ff1b31 FB |
272 | } |
273 | ||
9ee6e8bb PB |
274 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
275 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
276 | { | |
9ee6e8bb | 277 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
278 | env->ZF = (~val) & CPSR_Z; |
279 | env->NF = val; | |
9ee6e8bb PB |
280 | env->CF = (val >> 29) & 1; |
281 | env->VF = (val << 3) & 0x80000000; | |
282 | } | |
283 | if (mask & CPSR_Q) | |
284 | env->QF = ((val & CPSR_Q) != 0); | |
285 | if (mask & (1 << 24)) | |
286 | env->thumb = ((val & (1 << 24)) != 0); | |
287 | if (mask & CPSR_IT_0_1) { | |
288 | env->condexec_bits &= ~3; | |
289 | env->condexec_bits |= (val >> 25) & 3; | |
290 | } | |
291 | if (mask & CPSR_IT_2_7) { | |
292 | env->condexec_bits &= 3; | |
293 | env->condexec_bits |= (val >> 8) & 0xfc; | |
294 | } | |
295 | if (mask & 0x1ff) { | |
296 | env->v7m.exception = val & 0x1ff; | |
297 | } | |
298 | } | |
299 | ||
b5ff1b31 FB |
300 | enum arm_cpu_mode { |
301 | ARM_CPU_MODE_USR = 0x10, | |
302 | ARM_CPU_MODE_FIQ = 0x11, | |
303 | ARM_CPU_MODE_IRQ = 0x12, | |
304 | ARM_CPU_MODE_SVC = 0x13, | |
305 | ARM_CPU_MODE_ABT = 0x17, | |
306 | ARM_CPU_MODE_UND = 0x1b, | |
307 | ARM_CPU_MODE_SYS = 0x1f | |
308 | }; | |
309 | ||
40f137e1 PB |
310 | /* VFP system registers. */ |
311 | #define ARM_VFP_FPSID 0 | |
312 | #define ARM_VFP_FPSCR 1 | |
9ee6e8bb PB |
313 | #define ARM_VFP_MVFR1 6 |
314 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
315 | #define ARM_VFP_FPEXC 8 |
316 | #define ARM_VFP_FPINST 9 | |
317 | #define ARM_VFP_FPINST2 10 | |
318 | ||
18c9b560 AZ |
319 | /* iwMMXt coprocessor control registers. */ |
320 | #define ARM_IWMMXT_wCID 0 | |
321 | #define ARM_IWMMXT_wCon 1 | |
322 | #define ARM_IWMMXT_wCSSF 2 | |
323 | #define ARM_IWMMXT_wCASF 3 | |
324 | #define ARM_IWMMXT_wCGR0 8 | |
325 | #define ARM_IWMMXT_wCGR1 9 | |
326 | #define ARM_IWMMXT_wCGR2 10 | |
327 | #define ARM_IWMMXT_wCGR3 11 | |
328 | ||
40f137e1 PB |
329 | enum arm_features { |
330 | ARM_FEATURE_VFP, | |
c1713132 AZ |
331 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
332 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 333 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
334 | ARM_FEATURE_V6, |
335 | ARM_FEATURE_V6K, | |
336 | ARM_FEATURE_V7, | |
337 | ARM_FEATURE_THUMB2, | |
c3d2689d | 338 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb PB |
339 | ARM_FEATURE_VFP3, |
340 | ARM_FEATURE_NEON, | |
341 | ARM_FEATURE_DIV, | |
342 | ARM_FEATURE_M, /* Microcontroller profile. */ | |
fe1479c3 PB |
343 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
344 | ARM_FEATURE_THUMB2EE | |
40f137e1 PB |
345 | }; |
346 | ||
347 | static inline int arm_feature(CPUARMState *env, int feature) | |
348 | { | |
349 | return (env->features & (1u << feature)) != 0; | |
350 | } | |
351 | ||
c732abe2 | 352 | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
40f137e1 | 353 | |
9ee6e8bb PB |
354 | /* Interface between CPU and Interrupt controller. */ |
355 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
356 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
357 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
358 | ||
c1713132 AZ |
359 | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
360 | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, | |
361 | void *opaque); | |
362 | ||
9ee6e8bb PB |
363 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
364 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
365 | conventional cores (ie. Application or Realtime profile). */ | |
366 | ||
367 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
368 | #define ARM_CPUID(env) (env->cp15.c0_cpuid) | |
369 | ||
370 | #define ARM_CPUID_ARM1026 0x4106a262 | |
371 | #define ARM_CPUID_ARM926 0x41069265 | |
372 | #define ARM_CPUID_ARM946 0x41059461 | |
373 | #define ARM_CPUID_TI915T 0x54029152 | |
374 | #define ARM_CPUID_TI925T 0x54029252 | |
375 | #define ARM_CPUID_PXA250 0x69052100 | |
376 | #define ARM_CPUID_PXA255 0x69052d00 | |
377 | #define ARM_CPUID_PXA260 0x69052903 | |
378 | #define ARM_CPUID_PXA261 0x69052d05 | |
379 | #define ARM_CPUID_PXA262 0x69052d06 | |
380 | #define ARM_CPUID_PXA270 0x69054110 | |
381 | #define ARM_CPUID_PXA270_A0 0x69054110 | |
382 | #define ARM_CPUID_PXA270_A1 0x69054111 | |
383 | #define ARM_CPUID_PXA270_B0 0x69054112 | |
384 | #define ARM_CPUID_PXA270_B1 0x69054113 | |
385 | #define ARM_CPUID_PXA270_C0 0x69054114 | |
386 | #define ARM_CPUID_PXA270_C5 0x69054117 | |
387 | #define ARM_CPUID_ARM1136 0x4117b363 | |
827df9f3 | 388 | #define ARM_CPUID_ARM1136_R2 0x4107b362 |
9ee6e8bb PB |
389 | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
390 | #define ARM_CPUID_CORTEXA8 0x410fc080 | |
391 | #define ARM_CPUID_CORTEXM3 0x410fc231 | |
392 | #define ARM_CPUID_ANY 0xffffffff | |
40f137e1 | 393 | |
b5ff1b31 | 394 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 395 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
396 | #else |
397 | /* The ARM MMU allows 1k pages. */ | |
398 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 399 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
400 | #define TARGET_PAGE_BITS 10 |
401 | #endif | |
9467d44c | 402 | |
9467d44c TS |
403 | #define cpu_init cpu_arm_init |
404 | #define cpu_exec cpu_arm_exec | |
405 | #define cpu_gen_code cpu_arm_gen_code | |
406 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 407 | #define cpu_list arm_cpu_list |
9467d44c | 408 | |
ffe47d33 | 409 | #define CPU_SAVE_VERSION 2 |
9ee6e8bb | 410 | |
6ebbf390 JM |
411 | /* MMU modes definitions */ |
412 | #define MMU_MODE0_SUFFIX _kernel | |
413 | #define MMU_MODE1_SUFFIX _user | |
414 | #define MMU_USER_IDX 1 | |
415 | static inline int cpu_mmu_index (CPUState *env) | |
416 | { | |
417 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; | |
418 | } | |
419 | ||
6e68e076 PB |
420 | #if defined(CONFIG_USER_ONLY) |
421 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
422 | { | |
f8ed7070 | 423 | if (newsp) |
6e68e076 PB |
424 | env->regs[13] = newsp; |
425 | env->regs[0] = 0; | |
426 | } | |
427 | #endif | |
428 | ||
2c0262af | 429 | #include "cpu-all.h" |
622ed360 AL |
430 | #include "exec-all.h" |
431 | ||
432 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
433 | { | |
434 | env->regs[15] = tb->pc; | |
435 | } | |
2c0262af | 436 | |
6b917547 AL |
437 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
438 | target_ulong *cs_base, int *flags) | |
439 | { | |
440 | *pc = env->regs[15]; | |
441 | *cs_base = 0; | |
442 | *flags = env->thumb | (env->vfp.vec_len << 1) | |
443 | | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); | |
444 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) | |
445 | *flags |= (1 << 6); | |
446 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) | |
447 | *flags |= (1 << 7); | |
448 | } | |
449 | ||
2c0262af | 450 | #endif |