[qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7
#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */

#define ARMV7M_EXCP_RESET   1
#define ARMV7M_EXCP_NMI     2
#define ARMV7M_EXCP_HARD    3
#define ARMV7M_EXCP_MEM     4
#define ARMV7M_EXCP_BUS     5
#define ARMV7M_EXCP_USAGE   6
#define ARMV7M_EXCP_SVC     11
#define ARMV7M_EXCP_DEBUG   12
#define ARMV7M_EXCP_PENDSV  14
#define ARMV7M_EXCP_SYSTICK 15

typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

struct arm_boot_info;

#define NB_MMU_MODES 2

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];

    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];

    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NF; /* N is bit 31. All other bits are undefined.  */
    uint32_t ZF; /* Z set if zero.  */
    uint32_t QF; /* 0 or 1 */
    uint32_t GE; /* cpsr[19:16] */
    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c0_c1[8]; /* Feature registers.  */
        uint32_t c0_c2[8]; /* Instruction set registers.  */
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base0; /* MMU translation table base 0.  */
        uint32_t c2_base1; /* MMU translation table base 1.  */
        uint32_t c2_control; /* MMU translation table base control.  */
        uint32_t c2_mask; /* MMU translation table base selection mask.  */
        uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c13_tls1; /* User RW Thread register.  */
        uint32_t c13_tls2; /* User RO Thread register.  */
        uint32_t c13_tls3; /* Privileged Thread register.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    struct {
        uint32_t other_sp;
        uint32_t vecbase;
        uint32_t basepri;
        uint32_t control;
        int current_sp;
        int exception;
        int pending_exception;
        void *nvic;
    } v7m;

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* Callback for vectored interrupt controller.  */
    int (*get_irq_vector)(struct CPUARMState *);
    void *irq_opaque;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[32];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* scratch space when Tn are not sufficient.  */
        uint32_t scratch[8];

        float_status fp_status;
    } vfp;
#if defined(CONFIG_USER_ONLY)
    struct mmon_state *mmon_entry;
#else
    uint32_t mmon_addr;
#endif

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */
    struct arm_boot_info *boot_info;
} CPUARMState;

CPUARMState *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);

void cpu_lock(void);
void cpu_unlock(void);
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
  env->cp15.c13_tls2 = newtls;
}

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
#define CPSR_GE (0xf << 16)
#define CPSR_RESERVED (0xf << 20)
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_V (1 << 28)
#define CPSR_C (1 << 29)
#define CPSR_Z (1 << 30)
#define CPSR_N (1 << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
/* Bits writable in user mode.  */
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)

/* Return the current CPSR value.  */
uint32_t cpsr_read(CPUARMState *env);
/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);

/* Return the current xPSR value.  */
static inline uint32_t xpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->ZF == 0);
    return (env->NF & 0x80000000) | (ZF << 30)
        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | env->v7m.exception;
}

/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & (1 << 24))
        env->thumb = ((val & (1 << 24)) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & 0x1ff) {
        env->v7m.exception = val & 0x1ff;
    }
}

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_MVFR1   6
#define ARM_VFP_MVFR0   7
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_V6,
    ARM_FEATURE_V6K,
    ARM_FEATURE_V7,
    ARM_FEATURE_THUMB2,
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_VFP3,
    ARM_FEATURE_NEON,
    ARM_FEATURE_DIV,
    ARM_FEATURE_M, /* Microcontroller profile.  */
    ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

/* Interface between CPU and Interrupt controller.  */
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
   conventional cores (ie. Application or Realtime profile).  */

#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
#define ARM_CPUID(env) (env->cp15.c0_cpuid)

#define ARM_CPUID_ARM1026     0x4106a262
#define ARM_CPUID_ARM926      0x41069265
#define ARM_CPUID_ARM946      0x41059461
#define ARM_CPUID_TI915T      0x54029152
#define ARM_CPUID_TI925T      0x54029252
#define ARM_CPUID_PXA250      0x69052100
#define ARM_CPUID_PXA255      0x69052d00
#define ARM_CPUID_PXA260      0x69052903
#define ARM_CPUID_PXA261      0x69052d05
#define ARM_CPUID_PXA262      0x69052d06
#define ARM_CPUID_PXA270      0x69054110
#define ARM_CPUID_PXA270_A0   0x69054110
#define ARM_CPUID_PXA270_A1   0x69054111
#define ARM_CPUID_PXA270_B0   0x69054112
#define ARM_CPUID_PXA270_B1   0x69054113
#define ARM_CPUID_PXA270_C0   0x69054114
#define ARM_CPUID_PXA270_C5   0x69054117
#define ARM_CPUID_ARM1136     0x4117b363
#define ARM_CPUID_ARM1136_R2  0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8    0x410fc080
#define ARM_CPUID_CORTEXM3    0x410fc231
#define ARM_CPUID_ANY         0xffffffff

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define CPUState CPUARMState
#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

#define CPU_SAVE_VERSION 1

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regs[13] = newsp;
    env->regs[0] = 0;
}
#endif

#define CPU_PC_FROM_TB(env, tb) env->regs[15] = tb->pc

#include "cpu-all.h"

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_ARM_H
	21	#define CPU_ARM_H
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
9042c0e2 TS	25	#define ELF_MACHINE EM_ARM
9042c0e2 TS	26
2c0262af FB	27	#include "cpu-defs.h"
2c0262af FB	28
53cd6637 FB	29	#include "softfloat.h"
53cd6637 FB	30
1fddef4b FB	31	#define TARGET_HAS_ICE 1
1fddef4b FB	32
b8a9e8f1 FB	33	#define EXCP_UDEF 1 /* undefined instruction */
	34	#define EXCP_SWI 2 /* software interrupt */
	35	#define EXCP_PREFETCH_ABORT 3
	36	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	37	#define EXCP_IRQ 5
b5ff1b31 FB	38	#define EXCP_FIQ 6
06c949e6	39	#define EXCP_BKPT 7
9ee6e8bb	40	#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
fbb4a2e3	41	#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
9ee6e8bb PB	42
	43	#define ARMV7M_EXCP_RESET 1
	44	#define ARMV7M_EXCP_NMI 2
	45	#define ARMV7M_EXCP_HARD 3
	46	#define ARMV7M_EXCP_MEM 4
	47	#define ARMV7M_EXCP_BUS 5
	48	#define ARMV7M_EXCP_USAGE 6
	49	#define ARMV7M_EXCP_SVC 11
	50	#define ARMV7M_EXCP_DEBUG 12
	51	#define ARMV7M_EXCP_PENDSV 14
	52	#define ARMV7M_EXCP_SYSTICK 15
2c0262af	53
c1713132 AZ	54	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	55	int srcreg, int operand, uint32_t value);
	56	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	57	int dstreg, int operand);
	58
f93eb9ff AZ	59	struct arm_boot_info;
f93eb9ff AZ	60
6ebbf390 JM	61	#define NB_MMU_MODES 2
6ebbf390 JM	62
b7bcbe95 FB	63	/* We currently assume float and double are IEEE single and double
	64	precision respectively.
	65	Doing runtime conversions is tricky because VFP registers may contain
	66	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	67	s<2n> maps to the least significant half of d<n>
	68	s<2n+1> maps to the most significant half of d<n>
	69	*/
b7bcbe95	70
2c0262af	71	typedef struct CPUARMState {
b5ff1b31	72	/* Regs for current mode. */
2c0262af	73	uint32_t regs[16];
b5ff1b31	74	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	75	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	76	the whole CPSR. */
	77	uint32_t uncached_cpsr;
	78	uint32_t spsr;
	79
	80	/* Banked registers. */
	81	uint32_t banked_spsr[6];
	82	uint32_t banked_r13[6];
	83	uint32_t banked_r14[6];
3b46e624	84
b5ff1b31 FB	85	/* These hold r8-r12. */
	86	uint32_t usr_regs[5];
	87	uint32_t fiq_regs[5];
3b46e624	88
2c0262af FB	89	/* cpsr flag cache for faster execution */
	90	uint32_t CF; /* 0 or 1 */
	91	uint32_t VF; /* V is the bit 31. All other bits are undefined */
6fbe23d5 PB	92	uint32_t NF; /* N is bit 31. All other bits are undefined. */
6fbe23d5 PB	93	uint32_t ZF; /* Z set if zero. */
99c475ab	94	uint32_t QF; /* 0 or 1 */
9ee6e8bb	95	uint32_t GE; /* cpsr[19:16] */
b26eefb6	96	uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
9ee6e8bb	97	uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
2c0262af	98
b5ff1b31 FB	99	/* System control coprocessor (cp15) */
b5ff1b31 FB	100	struct {
40f137e1	101	uint32_t c0_cpuid;
c1713132	102	uint32_t c0_cachetype;
9ee6e8bb PB	103	uint32_t c0_c1[8]; /* Feature registers. */
9ee6e8bb PB	104	uint32_t c0_c2[8]; /* Instruction set registers. */
b5ff1b31 FB	105	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	106	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	107	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
9ee6e8bb PB	108	uint32_t c2_base0; /* MMU translation table base 0. */
9ee6e8bb PB	109	uint32_t c2_base1; /* MMU translation table base 1. */
b2fa1797 PB	110	uint32_t c2_control; /* MMU translation table base control. */
	111	uint32_t c2_mask; /* MMU translation table base selection mask. */
	112	uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
ce819861 PB	113	uint32_t c2_data; /* MPU data cachable bits. */
	114	uint32_t c2_insn; /* MPU instruction cachable bits. */
	115	uint32_t c3; /* MMU domain access control register
	116	MPU write buffer control. */
b5ff1b31 FB	117	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	118	uint32_t c5_data;
ce819861	119	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	120	uint32_t c6_insn; /* Fault address registers. */
	121	uint32_t c6_data;
	122	uint32_t c9_insn; /* Cache lockdown registers. */
	123	uint32_t c9_data;
	124	uint32_t c13_fcse; /* FCSE PID. */
	125	uint32_t c13_context; /* Context ID. */
9ee6e8bb PB	126	uint32_t c13_tls1; /* User RW Thread register. */
	127	uint32_t c13_tls2; /* User RO Thread register. */
	128	uint32_t c13_tls3; /* Privileged Thread register. */
c1713132	129	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	130	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	131	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	132	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	133	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	134	} cp15;
40f137e1	135
9ee6e8bb PB	136	struct {
	137	uint32_t other_sp;
	138	uint32_t vecbase;
	139	uint32_t basepri;
	140	uint32_t control;
	141	int current_sp;
	142	int exception;
	143	int pending_exception;
	144	void *nvic;
	145	} v7m;
	146
c1713132 AZ	147	/* Coprocessor IO used by peripherals */
	148	struct {
	149	ARMReadCPFunc *cp_read;
	150	ARMWriteCPFunc *cp_write;
	151	void *opaque;
	152	} cp[15];
	153
40f137e1 PB	154	/* Internal CPU feature flags. */
	155	uint32_t features;
	156
9ee6e8bb PB	157	/* Callback for vectored interrupt controller. */
	158	int (get_irq_vector)(struct CPUARMState );
	159	void *irq_opaque;
	160
b7bcbe95 FB	161	/* VFP coprocessor state. */
b7bcbe95 FB	162	struct {
9ee6e8bb	163	float64 regs[32];
b7bcbe95	164
40f137e1	165	uint32_t xregs[16];
b7bcbe95 FB	166	/* We store these fpcsr fields separately for convenience. */
	167	int vec_len;
	168	int vec_stride;
	169
9ee6e8bb PB	170	/* scratch space when Tn are not sufficient. */
9ee6e8bb PB	171	uint32_t scratch[8];
3b46e624	172
53cd6637	173	float_status fp_status;
b7bcbe95	174	} vfp;
9ee6e8bb PB	175	#if defined(CONFIG_USER_ONLY)
	176	struct mmon_state *mmon_entry;
	177	#else
	178	uint32_t mmon_addr;
	179	#endif
b7bcbe95	180
18c9b560 AZ	181	/* iwMMXt coprocessor state. */
	182	struct {
	183	uint64_t regs[16];
	184	uint64_t val;
	185
	186	uint32_t cregs[16];
	187	} iwmmxt;
	188
ce4defa0 PB	189	#if defined(CONFIG_USER_ONLY)
	190	/* For usermode syscall translation. */
	191	int eabi;
	192	#endif
	193
a316d335 FB	194	CPU_COMMON
a316d335 FB	195
9d551997	196	/* These fields after the common ones so they are preserved on reset. */
f93eb9ff	197	struct arm_boot_info *boot_info;
2c0262af FB	198	} CPUARMState;
2c0262af FB	199
aaed909a	200	CPUARMState cpu_arm_init(const char cpu_model);
b26eefb6	201	void arm_translate_init(void);
2c0262af FB	202	int cpu_arm_exec(CPUARMState *s);
2c0262af FB	203	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	204	void do_interrupt(CPUARMState *);
b5ff1b31 FB	205	void switch_mode(CPUARMState *, int);
9ee6e8bb	206	uint32_t do_arm_semihosting(CPUARMState *env);
b5ff1b31	207
2c0262af FB	208	/* you can call this signal handler from your SIGBUS and SIGSEGV
	209	signal handlers to inform the virtual CPU of exceptions. non zero
	210	is returned if the signal was handled by the virtual CPU. */
5fafdf24	211	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af FB	212	void *puc);
2c0262af FB	213
9ee6e8bb PB	214	void cpu_lock(void);
9ee6e8bb PB	215	void cpu_unlock(void);
fbb4a2e3 PB	216	static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
	217	{
	218	env->cp15.c13_tls2 = newtls;
	219	}
9ee6e8bb	220
b5ff1b31 FB	221	#define CPSR_M (0x1f)
	222	#define CPSR_T (1 << 5)
	223	#define CPSR_F (1 << 6)
	224	#define CPSR_I (1 << 7)
	225	#define CPSR_A (1 << 8)
	226	#define CPSR_E (1 << 9)
	227	#define CPSR_IT_2_7 (0xfc00)
9ee6e8bb PB	228	#define CPSR_GE (0xf << 16)
9ee6e8bb PB	229	#define CPSR_RESERVED (0xf << 20)
b5ff1b31 FB	230	#define CPSR_J (1 << 24)
	231	#define CPSR_IT_0_1 (3 << 25)
	232	#define CPSR_Q (1 << 27)
9ee6e8bb PB	233	#define CPSR_V (1 << 28)
	234	#define CPSR_C (1 << 29)
	235	#define CPSR_Z (1 << 30)
	236	#define CPSR_N (1 << 31)
	237	#define CPSR_NZCV (CPSR_N \| CPSR_Z \| CPSR_C \| CPSR_V)
	238
	239	#define CPSR_IT (CPSR_IT_0_1 \| CPSR_IT_2_7)
	240	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_GE \| CPSR_IT \| CPSR_Q \| CPSR_NZCV)
	241	/* Bits writable in user mode. */
	242	#define CPSR_USER (CPSR_NZCV \| CPSR_Q \| CPSR_GE)
	243	/* Execution state bits. MRS read as zero, MSR writes ignored. */
	244	#define CPSR_EXEC (CPSR_T \| CPSR_IT \| CPSR_J)
b5ff1b31	245
b5ff1b31	246	/* Return the current CPSR value. */
2f4a40e5 AZ	247	uint32_t cpsr_read(CPUARMState *env);
	248	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	249	void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
9ee6e8bb PB	250
	251	/* Return the current xPSR value. */
	252	static inline uint32_t xpsr_read(CPUARMState *env)
	253	{
	254	int ZF;
6fbe23d5 PB	255	ZF = (env->ZF == 0);
6fbe23d5 PB	256	return (env->NF & 0x80000000) \| (ZF << 30)
9ee6e8bb PB	257	\| (env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	258	\| (env->thumb << 24) \| ((env->condexec_bits & 3) << 25)
	259	\| ((env->condexec_bits & 0xfc) << 8)
	260	\| env->v7m.exception;
b5ff1b31 FB	261	}
b5ff1b31 FB	262
9ee6e8bb PB	263	/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
	264	static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	265	{
9ee6e8bb	266	if (mask & CPSR_NZCV) {
6fbe23d5 PB	267	env->ZF = (~val) & CPSR_Z;
6fbe23d5 PB	268	env->NF = val;
9ee6e8bb PB	269	env->CF = (val >> 29) & 1;
	270	env->VF = (val << 3) & 0x80000000;
	271	}
	272	if (mask & CPSR_Q)
	273	env->QF = ((val & CPSR_Q) != 0);
	274	if (mask & (1 << 24))
	275	env->thumb = ((val & (1 << 24)) != 0);
	276	if (mask & CPSR_IT_0_1) {
	277	env->condexec_bits &= ~3;
	278	env->condexec_bits \|= (val >> 25) & 3;
	279	}
	280	if (mask & CPSR_IT_2_7) {
	281	env->condexec_bits &= 3;
	282	env->condexec_bits \|= (val >> 8) & 0xfc;
	283	}
	284	if (mask & 0x1ff) {
	285	env->v7m.exception = val & 0x1ff;
	286	}
	287	}
	288
b5ff1b31 FB	289	enum arm_cpu_mode {
	290	ARM_CPU_MODE_USR = 0x10,
	291	ARM_CPU_MODE_FIQ = 0x11,
	292	ARM_CPU_MODE_IRQ = 0x12,
	293	ARM_CPU_MODE_SVC = 0x13,
	294	ARM_CPU_MODE_ABT = 0x17,
	295	ARM_CPU_MODE_UND = 0x1b,
	296	ARM_CPU_MODE_SYS = 0x1f
	297	};
	298
40f137e1 PB	299	/* VFP system registers. */
	300	#define ARM_VFP_FPSID 0
	301	#define ARM_VFP_FPSCR 1
9ee6e8bb PB	302	#define ARM_VFP_MVFR1 6
9ee6e8bb PB	303	#define ARM_VFP_MVFR0 7
40f137e1 PB	304	#define ARM_VFP_FPEXC 8
	305	#define ARM_VFP_FPINST 9
	306	#define ARM_VFP_FPINST2 10
	307
18c9b560 AZ	308	/* iwMMXt coprocessor control registers. */
	309	#define ARM_IWMMXT_wCID 0
	310	#define ARM_IWMMXT_wCon 1
	311	#define ARM_IWMMXT_wCSSF 2
	312	#define ARM_IWMMXT_wCASF 3
	313	#define ARM_IWMMXT_wCGR0 8
	314	#define ARM_IWMMXT_wCGR1 9
	315	#define ARM_IWMMXT_wCGR2 10
	316	#define ARM_IWMMXT_wCGR3 11
	317
40f137e1 PB	318	enum arm_features {
40f137e1 PB	319	ARM_FEATURE_VFP,
c1713132 AZ	320	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	321	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	322	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
9ee6e8bb PB	323	ARM_FEATURE_V6,
	324	ARM_FEATURE_V6K,
	325	ARM_FEATURE_V7,
	326	ARM_FEATURE_THUMB2,
c3d2689d	327	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
9ee6e8bb PB	328	ARM_FEATURE_VFP3,
	329	ARM_FEATURE_NEON,
	330	ARM_FEATURE_DIV,
	331	ARM_FEATURE_M, /* Microcontroller profile. */
c3d2689d	332	ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
40f137e1 PB	333	};
	334
	335	static inline int arm_feature(CPUARMState *env, int feature)
	336	{
	337	return (env->features & (1u << feature)) != 0;
	338	}
	339
c732abe2	340	void arm_cpu_list(FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
40f137e1	341
9ee6e8bb PB	342	/* Interface between CPU and Interrupt controller. */
	343	void armv7m_nvic_set_pending(void *opaque, int irq);
	344	int armv7m_nvic_acknowledge_irq(void *opaque);
	345	void armv7m_nvic_complete_irq(void *opaque, int irq);
	346
c1713132 AZ	347	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	348	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	349	void *opaque);
	350
9ee6e8bb PB	351	/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
	352	Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
	353	conventional cores (ie. Application or Realtime profile). */
	354
	355	#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
	356	#define ARM_CPUID(env) (env->cp15.c0_cpuid)
	357
	358	#define ARM_CPUID_ARM1026 0x4106a262
	359	#define ARM_CPUID_ARM926 0x41069265
	360	#define ARM_CPUID_ARM946 0x41059461
	361	#define ARM_CPUID_TI915T 0x54029152
	362	#define ARM_CPUID_TI925T 0x54029252
	363	#define ARM_CPUID_PXA250 0x69052100
	364	#define ARM_CPUID_PXA255 0x69052d00
	365	#define ARM_CPUID_PXA260 0x69052903
	366	#define ARM_CPUID_PXA261 0x69052d05
	367	#define ARM_CPUID_PXA262 0x69052d06
	368	#define ARM_CPUID_PXA270 0x69054110
	369	#define ARM_CPUID_PXA270_A0 0x69054110
	370	#define ARM_CPUID_PXA270_A1 0x69054111
	371	#define ARM_CPUID_PXA270_B0 0x69054112
	372	#define ARM_CPUID_PXA270_B1 0x69054113
	373	#define ARM_CPUID_PXA270_C0 0x69054114
	374	#define ARM_CPUID_PXA270_C5 0x69054117
	375	#define ARM_CPUID_ARM1136 0x4117b363
827df9f3	376	#define ARM_CPUID_ARM1136_R2 0x4107b362
9ee6e8bb PB	377	#define ARM_CPUID_ARM11MPCORE 0x410fb022
	378	#define ARM_CPUID_CORTEXA8 0x410fc080
	379	#define ARM_CPUID_CORTEXM3 0x410fc231
	380	#define ARM_CPUID_ANY 0xffffffff
40f137e1	381
b5ff1b31	382	#if defined(CONFIG_USER_ONLY)
2c0262af	383	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	384	#else
	385	/* The ARM MMU allows 1k pages. */
	386	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	387	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	388	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	389	#endif
9467d44c TS	390
	391	#define CPUState CPUARMState
	392	#define cpu_init cpu_arm_init
	393	#define cpu_exec cpu_arm_exec
	394	#define cpu_gen_code cpu_arm_gen_code
	395	#define cpu_signal_handler cpu_arm_signal_handler
c732abe2	396	#define cpu_list arm_cpu_list
9467d44c	397
b3c7724c	398	#define CPU_SAVE_VERSION 1
9ee6e8bb	399
6ebbf390 JM	400	/* MMU modes definitions */
	401	#define MMU_MODE0_SUFFIX _kernel
	402	#define MMU_MODE1_SUFFIX _user
	403	#define MMU_USER_IDX 1
	404	static inline int cpu_mmu_index (CPUState *env)
	405	{
	406	return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
	407	}
	408
6e68e076 PB	409	#if defined(CONFIG_USER_ONLY)
	410	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	411	{
f8ed7070	412	if (newsp)
6e68e076 PB	413	env->regs[13] = newsp;
	414	env->regs[0] = 0;
	415	}
	416	#endif
	417
2e70f6ef PB	418	#define CPU_PC_FROM_TB(env, tb) env->regs[15] = tb->pc
2e70f6ef PB	419
2c0262af FB	420	#include "cpu-all.h"
	421
	422	#endif