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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3cf1e035 FB |
22 | #define TARGET_LONG_BITS 32 |
23 | ||
9042c0e2 TS |
24 | #define ELF_MACHINE EM_ARM |
25 | ||
9349b4f9 | 26 | #define CPUArchState struct CPUARMState |
c2764719 | 27 | |
9a78eead SW |
28 | #include "config.h" |
29 | #include "qemu-common.h" | |
2c0262af FB |
30 | #include "cpu-defs.h" |
31 | ||
53cd6637 FB |
32 | #include "softfloat.h" |
33 | ||
1fddef4b FB |
34 | #define TARGET_HAS_ICE 1 |
35 | ||
b8a9e8f1 FB |
36 | #define EXCP_UDEF 1 /* undefined instruction */ |
37 | #define EXCP_SWI 2 /* software interrupt */ | |
38 | #define EXCP_PREFETCH_ABORT 3 | |
39 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
40 | #define EXCP_IRQ 5 |
41 | #define EXCP_FIQ 6 | |
06c949e6 | 42 | #define EXCP_BKPT 7 |
9ee6e8bb | 43 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 44 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
426f5abc | 45 | #define EXCP_STREX 10 |
9ee6e8bb PB |
46 | |
47 | #define ARMV7M_EXCP_RESET 1 | |
48 | #define ARMV7M_EXCP_NMI 2 | |
49 | #define ARMV7M_EXCP_HARD 3 | |
50 | #define ARMV7M_EXCP_MEM 4 | |
51 | #define ARMV7M_EXCP_BUS 5 | |
52 | #define ARMV7M_EXCP_USAGE 6 | |
53 | #define ARMV7M_EXCP_SVC 11 | |
54 | #define ARMV7M_EXCP_DEBUG 12 | |
55 | #define ARMV7M_EXCP_PENDSV 14 | |
56 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 57 | |
403946c0 RH |
58 | /* ARM-specific interrupt pending bits. */ |
59 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
60 | ||
61 | ||
c1713132 AZ |
62 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
63 | int srcreg, int operand, uint32_t value); | |
64 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
65 | int dstreg, int operand); | |
66 | ||
f93eb9ff AZ |
67 | struct arm_boot_info; |
68 | ||
6ebbf390 JM |
69 | #define NB_MMU_MODES 2 |
70 | ||
b7bcbe95 FB |
71 | /* We currently assume float and double are IEEE single and double |
72 | precision respectively. | |
73 | Doing runtime conversions is tricky because VFP registers may contain | |
74 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
75 | s<2n> maps to the least significant half of d<n> |
76 | s<2n+1> maps to the most significant half of d<n> | |
77 | */ | |
b7bcbe95 | 78 | |
2c0262af | 79 | typedef struct CPUARMState { |
b5ff1b31 | 80 | /* Regs for current mode. */ |
2c0262af | 81 | uint32_t regs[16]; |
b5ff1b31 | 82 | /* Frequently accessed CPSR bits are stored separately for efficiently. |
d37aca66 | 83 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
84 | the whole CPSR. */ |
85 | uint32_t uncached_cpsr; | |
86 | uint32_t spsr; | |
87 | ||
88 | /* Banked registers. */ | |
89 | uint32_t banked_spsr[6]; | |
90 | uint32_t banked_r13[6]; | |
91 | uint32_t banked_r14[6]; | |
3b46e624 | 92 | |
b5ff1b31 FB |
93 | /* These hold r8-r12. */ |
94 | uint32_t usr_regs[5]; | |
95 | uint32_t fiq_regs[5]; | |
3b46e624 | 96 | |
2c0262af FB |
97 | /* cpsr flag cache for faster execution */ |
98 | uint32_t CF; /* 0 or 1 */ | |
99 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
100 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
101 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 102 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 103 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 104 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 105 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
2c0262af | 106 | |
b5ff1b31 FB |
107 | /* System control coprocessor (cp15) */ |
108 | struct { | |
40f137e1 | 109 | uint32_t c0_cpuid; |
c1713132 | 110 | uint32_t c0_cachetype; |
a49ea279 | 111 | uint32_t c0_cssel; /* Cache size selection. */ |
b5ff1b31 FB |
112 | uint32_t c1_sys; /* System control register. */ |
113 | uint32_t c1_coproc; /* Coprocessor access register. */ | |
610c3c8a | 114 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
2be27624 | 115 | uint32_t c1_scr; /* secure config register. */ |
9ee6e8bb PB |
116 | uint32_t c2_base0; /* MMU translation table base 0. */ |
117 | uint32_t c2_base1; /* MMU translation table base 1. */ | |
b2fa1797 PB |
118 | uint32_t c2_control; /* MMU translation table base control. */ |
119 | uint32_t c2_mask; /* MMU translation table base selection mask. */ | |
120 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
121 | uint32_t c2_data; /* MPU data cachable bits. */ |
122 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
123 | uint32_t c3; /* MMU domain access control register | |
124 | MPU write buffer control. */ | |
b5ff1b31 FB |
125 | uint32_t c5_insn; /* Fault status registers. */ |
126 | uint32_t c5_data; | |
ce819861 | 127 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b5ff1b31 FB |
128 | uint32_t c6_insn; /* Fault address registers. */ |
129 | uint32_t c6_data; | |
f8bf8606 | 130 | uint32_t c7_par; /* Translation result. */ |
b5ff1b31 FB |
131 | uint32_t c9_insn; /* Cache lockdown registers. */ |
132 | uint32_t c9_data; | |
74594c9d PM |
133 | uint32_t c9_pmcr; /* performance monitor control register */ |
134 | uint32_t c9_pmcnten; /* perf monitor counter enables */ | |
135 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | |
136 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | |
137 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | |
138 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | |
b5ff1b31 FB |
139 | uint32_t c13_fcse; /* FCSE PID. */ |
140 | uint32_t c13_context; /* Context ID. */ | |
9ee6e8bb PB |
141 | uint32_t c13_tls1; /* User RW Thread register. */ |
142 | uint32_t c13_tls2; /* User RO Thread register. */ | |
143 | uint32_t c13_tls3; /* Privileged Thread register. */ | |
c1713132 | 144 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
145 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
146 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
147 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
148 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
149 | uint32_t c15_config_base_address; /* SCU base address. */ |
150 | uint32_t c15_diagnostic; /* diagnostic register */ | |
151 | uint32_t c15_power_diagnostic; | |
152 | uint32_t c15_power_control; /* power control */ | |
b5ff1b31 | 153 | } cp15; |
40f137e1 | 154 | |
9ee6e8bb PB |
155 | struct { |
156 | uint32_t other_sp; | |
157 | uint32_t vecbase; | |
158 | uint32_t basepri; | |
159 | uint32_t control; | |
160 | int current_sp; | |
161 | int exception; | |
162 | int pending_exception; | |
9ee6e8bb PB |
163 | } v7m; |
164 | ||
fe1479c3 PB |
165 | /* Thumb-2 EE state. */ |
166 | uint32_t teecr; | |
167 | uint32_t teehbr; | |
168 | ||
b7bcbe95 FB |
169 | /* VFP coprocessor state. */ |
170 | struct { | |
9ee6e8bb | 171 | float64 regs[32]; |
b7bcbe95 | 172 | |
40f137e1 | 173 | uint32_t xregs[16]; |
b7bcbe95 FB |
174 | /* We store these fpcsr fields separately for convenience. */ |
175 | int vec_len; | |
176 | int vec_stride; | |
177 | ||
9ee6e8bb PB |
178 | /* scratch space when Tn are not sufficient. */ |
179 | uint32_t scratch[8]; | |
3b46e624 | 180 | |
3a492f3a PM |
181 | /* fp_status is the "normal" fp status. standard_fp_status retains |
182 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
183 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
184 | * any operations (generally Neon) which the architecture defines | |
185 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
186 | * | |
187 | * To avoid having to transfer exception bits around, we simply | |
188 | * say that the FPSCR cumulative exception flags are the logical | |
189 | * OR of the flags in the two fp statuses. This relies on the | |
190 | * only thing which needs to read the exception flags being | |
191 | * an explicit FPSCR read. | |
192 | */ | |
53cd6637 | 193 | float_status fp_status; |
3a492f3a | 194 | float_status standard_fp_status; |
b7bcbe95 | 195 | } vfp; |
426f5abc PB |
196 | uint32_t exclusive_addr; |
197 | uint32_t exclusive_val; | |
198 | uint32_t exclusive_high; | |
9ee6e8bb | 199 | #if defined(CONFIG_USER_ONLY) |
426f5abc PB |
200 | uint32_t exclusive_test; |
201 | uint32_t exclusive_info; | |
9ee6e8bb | 202 | #endif |
b7bcbe95 | 203 | |
18c9b560 AZ |
204 | /* iwMMXt coprocessor state. */ |
205 | struct { | |
206 | uint64_t regs[16]; | |
207 | uint64_t val; | |
208 | ||
209 | uint32_t cregs[16]; | |
210 | } iwmmxt; | |
211 | ||
d8fd2954 PB |
212 | /* For mixed endian mode. */ |
213 | bool bswap_code; | |
214 | ||
ce4defa0 PB |
215 | #if defined(CONFIG_USER_ONLY) |
216 | /* For usermode syscall translation. */ | |
217 | int eabi; | |
218 | #endif | |
219 | ||
a316d335 FB |
220 | CPU_COMMON |
221 | ||
9d551997 | 222 | /* These fields after the common ones so they are preserved on reset. */ |
9ba8c3f4 | 223 | |
581be094 PM |
224 | /* Internal CPU feature flags. */ |
225 | uint32_t features; | |
226 | ||
983fe826 | 227 | void *nvic; |
462a8bc6 | 228 | const struct arm_boot_info *boot_info; |
2c0262af FB |
229 | } CPUARMState; |
230 | ||
778c3a06 AF |
231 | #include "cpu-qom.h" |
232 | ||
233 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
b26eefb6 | 234 | void arm_translate_init(void); |
2c0262af | 235 | int cpu_arm_exec(CPUARMState *s); |
b5ff1b31 FB |
236 | void do_interrupt(CPUARMState *); |
237 | void switch_mode(CPUARMState *, int); | |
9ee6e8bb | 238 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 239 | |
2c0262af FB |
240 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
241 | signal handlers to inform the virtual CPU of exceptions. non zero | |
242 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 243 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 244 | void *puc); |
84a031c6 | 245 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
97b348e7 | 246 | int mmu_idx); |
0b5c1ce8 | 247 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
2c0262af | 248 | |
fbb4a2e3 PB |
249 | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
250 | { | |
251 | env->cp15.c13_tls2 = newtls; | |
252 | } | |
9ee6e8bb | 253 | |
b5ff1b31 FB |
254 | #define CPSR_M (0x1f) |
255 | #define CPSR_T (1 << 5) | |
256 | #define CPSR_F (1 << 6) | |
257 | #define CPSR_I (1 << 7) | |
258 | #define CPSR_A (1 << 8) | |
259 | #define CPSR_E (1 << 9) | |
260 | #define CPSR_IT_2_7 (0xfc00) | |
9ee6e8bb PB |
261 | #define CPSR_GE (0xf << 16) |
262 | #define CPSR_RESERVED (0xf << 20) | |
b5ff1b31 FB |
263 | #define CPSR_J (1 << 24) |
264 | #define CPSR_IT_0_1 (3 << 25) | |
265 | #define CPSR_Q (1 << 27) | |
9ee6e8bb PB |
266 | #define CPSR_V (1 << 28) |
267 | #define CPSR_C (1 << 29) | |
268 | #define CPSR_Z (1 << 30) | |
269 | #define CPSR_N (1 << 31) | |
270 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) | |
271 | ||
272 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
273 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) | |
274 | /* Bits writable in user mode. */ | |
275 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
276 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
277 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) | |
b5ff1b31 | 278 | |
b5ff1b31 | 279 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
280 | uint32_t cpsr_read(CPUARMState *env); |
281 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
282 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
283 | |
284 | /* Return the current xPSR value. */ | |
285 | static inline uint32_t xpsr_read(CPUARMState *env) | |
286 | { | |
287 | int ZF; | |
6fbe23d5 PB |
288 | ZF = (env->ZF == 0); |
289 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
290 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
291 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
292 | | ((env->condexec_bits & 0xfc) << 8) | |
293 | | env->v7m.exception; | |
b5ff1b31 FB |
294 | } |
295 | ||
9ee6e8bb PB |
296 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
297 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
298 | { | |
9ee6e8bb | 299 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
300 | env->ZF = (~val) & CPSR_Z; |
301 | env->NF = val; | |
9ee6e8bb PB |
302 | env->CF = (val >> 29) & 1; |
303 | env->VF = (val << 3) & 0x80000000; | |
304 | } | |
305 | if (mask & CPSR_Q) | |
306 | env->QF = ((val & CPSR_Q) != 0); | |
307 | if (mask & (1 << 24)) | |
308 | env->thumb = ((val & (1 << 24)) != 0); | |
309 | if (mask & CPSR_IT_0_1) { | |
310 | env->condexec_bits &= ~3; | |
311 | env->condexec_bits |= (val >> 25) & 3; | |
312 | } | |
313 | if (mask & CPSR_IT_2_7) { | |
314 | env->condexec_bits &= 3; | |
315 | env->condexec_bits |= (val >> 8) & 0xfc; | |
316 | } | |
317 | if (mask & 0x1ff) { | |
318 | env->v7m.exception = val & 0x1ff; | |
319 | } | |
320 | } | |
321 | ||
01653295 PM |
322 | /* Return the current FPSCR value. */ |
323 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
324 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
325 | ||
b5ff1b31 FB |
326 | enum arm_cpu_mode { |
327 | ARM_CPU_MODE_USR = 0x10, | |
328 | ARM_CPU_MODE_FIQ = 0x11, | |
329 | ARM_CPU_MODE_IRQ = 0x12, | |
330 | ARM_CPU_MODE_SVC = 0x13, | |
331 | ARM_CPU_MODE_ABT = 0x17, | |
332 | ARM_CPU_MODE_UND = 0x1b, | |
333 | ARM_CPU_MODE_SYS = 0x1f | |
334 | }; | |
335 | ||
40f137e1 PB |
336 | /* VFP system registers. */ |
337 | #define ARM_VFP_FPSID 0 | |
338 | #define ARM_VFP_FPSCR 1 | |
9ee6e8bb PB |
339 | #define ARM_VFP_MVFR1 6 |
340 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
341 | #define ARM_VFP_FPEXC 8 |
342 | #define ARM_VFP_FPINST 9 | |
343 | #define ARM_VFP_FPINST2 10 | |
344 | ||
18c9b560 AZ |
345 | /* iwMMXt coprocessor control registers. */ |
346 | #define ARM_IWMMXT_wCID 0 | |
347 | #define ARM_IWMMXT_wCon 1 | |
348 | #define ARM_IWMMXT_wCSSF 2 | |
349 | #define ARM_IWMMXT_wCASF 3 | |
350 | #define ARM_IWMMXT_wCGR0 8 | |
351 | #define ARM_IWMMXT_wCGR1 9 | |
352 | #define ARM_IWMMXT_wCGR2 10 | |
353 | #define ARM_IWMMXT_wCGR3 11 | |
354 | ||
ce854d7c BC |
355 | /* If adding a feature bit which corresponds to a Linux ELF |
356 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
357 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
358 | */ | |
40f137e1 PB |
359 | enum arm_features { |
360 | ARM_FEATURE_VFP, | |
c1713132 AZ |
361 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
362 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 363 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
364 | ARM_FEATURE_V6, |
365 | ARM_FEATURE_V6K, | |
366 | ARM_FEATURE_V7, | |
367 | ARM_FEATURE_THUMB2, | |
c3d2689d | 368 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb | 369 | ARM_FEATURE_VFP3, |
60011498 | 370 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 371 | ARM_FEATURE_NEON, |
47789990 | 372 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 373 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 374 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 375 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
376 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
377 | ARM_FEATURE_V4T, | |
378 | ARM_FEATURE_V5, | |
5bc95aa2 | 379 | ARM_FEATURE_STRONGARM, |
906879a9 | 380 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 381 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 382 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 383 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 384 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 385 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
386 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
387 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
388 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 389 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
40f137e1 PB |
390 | }; |
391 | ||
392 | static inline int arm_feature(CPUARMState *env, int feature) | |
393 | { | |
394 | return (env->features & (1u << feature)) != 0; | |
395 | } | |
396 | ||
9a78eead | 397 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
40f137e1 | 398 | |
9ee6e8bb PB |
399 | /* Interface between CPU and Interrupt controller. */ |
400 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
401 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
402 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
403 | ||
4b6a83fb PM |
404 | /* Interface for defining coprocessor registers. |
405 | * Registers are defined in tables of arm_cp_reginfo structs | |
406 | * which are passed to define_arm_cp_regs(). | |
407 | */ | |
408 | ||
409 | /* When looking up a coprocessor register we look for it | |
410 | * via an integer which encodes all of: | |
411 | * coprocessor number | |
412 | * Crn, Crm, opc1, opc2 fields | |
413 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
414 | * or via MRRC/MCRR?) | |
415 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | |
416 | * (In this case crn and opc2 should be zero.) | |
417 | */ | |
418 | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ | |
419 | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ | |
420 | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
421 | ||
422 | #define DECODE_CPREG_CRN(enc) (((enc) >> 7) & 0xf) | |
423 | ||
424 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | |
425 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
426 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
427 | * TCG can assume the value to be constant (ie load at translate time) | |
428 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
429 | * indicates that the TB should not be ended after a write to this register | |
430 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
431 | * a register definition to override a previous definition for the | |
432 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
433 | * old must have the OVERRIDE bit set. | |
434 | */ | |
435 | #define ARM_CP_SPECIAL 1 | |
436 | #define ARM_CP_CONST 2 | |
437 | #define ARM_CP_64BIT 4 | |
438 | #define ARM_CP_SUPPRESS_TB_END 8 | |
439 | #define ARM_CP_OVERRIDE 16 | |
440 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) | |
441 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
442 | #define ARM_LAST_SPECIAL ARM_CP_WFI | |
443 | /* Used only as a terminator for ARMCPRegInfo lists */ | |
444 | #define ARM_CP_SENTINEL 0xffff | |
445 | /* Mask of only the flag bits in a type field */ | |
446 | #define ARM_CP_FLAG_MASK 0x1f | |
447 | ||
448 | /* Return true if cptype is a valid type field. This is used to try to | |
449 | * catch errors where the sentinel has been accidentally left off the end | |
450 | * of a list of registers. | |
451 | */ | |
452 | static inline bool cptype_valid(int cptype) | |
453 | { | |
454 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
455 | || ((cptype & ARM_CP_SPECIAL) && | |
456 | (cptype <= ARM_LAST_SPECIAL)); | |
457 | } | |
458 | ||
459 | /* Access rights: | |
460 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
461 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
462 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
463 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
464 | * If a register is accessible in one privilege level it's always accessible | |
465 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
466 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
467 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
468 | * terminology a little and call this PL3. | |
469 | * | |
470 | * If access permissions for a register are more complex than can be | |
471 | * described with these bits, then use a laxer set of restrictions, and | |
472 | * do the more restrictive/complex check inside a helper function. | |
473 | */ | |
474 | #define PL3_R 0x80 | |
475 | #define PL3_W 0x40 | |
476 | #define PL2_R (0x20 | PL3_R) | |
477 | #define PL2_W (0x10 | PL3_W) | |
478 | #define PL1_R (0x08 | PL2_R) | |
479 | #define PL1_W (0x04 | PL2_W) | |
480 | #define PL0_R (0x02 | PL1_R) | |
481 | #define PL0_W (0x01 | PL1_W) | |
482 | ||
483 | #define PL3_RW (PL3_R | PL3_W) | |
484 | #define PL2_RW (PL2_R | PL2_W) | |
485 | #define PL1_RW (PL1_R | PL1_W) | |
486 | #define PL0_RW (PL0_R | PL0_W) | |
487 | ||
488 | static inline int arm_current_pl(CPUARMState *env) | |
489 | { | |
490 | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { | |
491 | return 0; | |
492 | } | |
493 | /* We don't currently implement the Virtualization or TrustZone | |
494 | * extensions, so PL2 and PL3 don't exist for us. | |
495 | */ | |
496 | return 1; | |
497 | } | |
498 | ||
499 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
500 | ||
501 | /* Access functions for coprocessor registers. These should return | |
502 | * 0 on success, or one of the EXCP_* constants if access should cause | |
503 | * an exception (in which case *value is not written). | |
504 | */ | |
505 | typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
506 | uint64_t *value); | |
507 | typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
508 | uint64_t value); | |
509 | /* Hook function for register reset */ | |
510 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
511 | ||
512 | #define CP_ANY 0xff | |
513 | ||
514 | /* Definition of an ARM coprocessor register */ | |
515 | struct ARMCPRegInfo { | |
516 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
517 | const char *name; | |
518 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
519 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
520 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
521 | * will be decoded to this register. The register read and write | |
522 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
523 | * used by the program, so it is possible to register a wildcard and | |
524 | * then behave differently on read/write if necessary. | |
525 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
526 | * must both be zero. | |
527 | */ | |
528 | uint8_t cp; | |
529 | uint8_t crn; | |
530 | uint8_t crm; | |
531 | uint8_t opc1; | |
532 | uint8_t opc2; | |
533 | /* Register type: ARM_CP_* bits/values */ | |
534 | int type; | |
535 | /* Access rights: PL*_[RW] */ | |
536 | int access; | |
537 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | |
538 | * this register was defined: can be used to hand data through to the | |
539 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
540 | */ | |
541 | void *opaque; | |
542 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
543 | * fieldoffset is non-zero, the reset value of the register. | |
544 | */ | |
545 | uint64_t resetvalue; | |
546 | /* Offset of the field in CPUARMState for this register. This is not | |
547 | * needed if either: | |
548 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | |
549 | * 2. both readfn and writefn are specified | |
550 | */ | |
551 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
552 | /* Function for handling reads of this register. If NULL, then reads | |
553 | * will be done by loading from the offset into CPUARMState specified | |
554 | * by fieldoffset. | |
555 | */ | |
556 | CPReadFn *readfn; | |
557 | /* Function for handling writes of this register. If NULL, then writes | |
558 | * will be done by writing to the offset into CPUARMState specified | |
559 | * by fieldoffset. | |
560 | */ | |
561 | CPWriteFn *writefn; | |
562 | /* Function for resetting the register. If NULL, then reset will be done | |
563 | * by writing resetvalue to the field specified in fieldoffset. If | |
564 | * fieldoffset is 0 then no reset will be done. | |
565 | */ | |
566 | CPResetFn *resetfn; | |
567 | }; | |
568 | ||
569 | /* Macros which are lvalues for the field in CPUARMState for the | |
570 | * ARMCPRegInfo *ri. | |
571 | */ | |
572 | #define CPREG_FIELD32(env, ri) \ | |
573 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
574 | #define CPREG_FIELD64(env, ri) \ | |
575 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
576 | ||
577 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
578 | ||
579 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
580 | const ARMCPRegInfo *regs, void *opaque); | |
581 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
582 | const ARMCPRegInfo *regs, void *opaque); | |
583 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
584 | { | |
585 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
586 | } | |
587 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
588 | { | |
589 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
590 | } | |
591 | const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp); | |
592 | ||
593 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
594 | int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | |
595 | uint64_t value); | |
596 | /* CPReadFn that can be used for read-as-zero behaviour */ | |
597 | int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); | |
598 | ||
599 | static inline bool cp_access_ok(CPUARMState *env, | |
600 | const ARMCPRegInfo *ri, int isread) | |
601 | { | |
602 | return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; | |
603 | } | |
604 | ||
9ee6e8bb PB |
605 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
606 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
607 | conventional cores (ie. Application or Realtime profile). */ | |
608 | ||
609 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
610 | #define ARM_CPUID(env) (env->cp15.c0_cpuid) | |
611 | ||
612 | #define ARM_CPUID_ARM1026 0x4106a262 | |
613 | #define ARM_CPUID_ARM926 0x41069265 | |
614 | #define ARM_CPUID_ARM946 0x41059461 | |
615 | #define ARM_CPUID_TI915T 0x54029152 | |
616 | #define ARM_CPUID_TI925T 0x54029252 | |
5bc95aa2 DES |
617 | #define ARM_CPUID_SA1100 0x4401A11B |
618 | #define ARM_CPUID_SA1110 0x6901B119 | |
9ee6e8bb PB |
619 | #define ARM_CPUID_PXA250 0x69052100 |
620 | #define ARM_CPUID_PXA255 0x69052d00 | |
621 | #define ARM_CPUID_PXA260 0x69052903 | |
622 | #define ARM_CPUID_PXA261 0x69052d05 | |
623 | #define ARM_CPUID_PXA262 0x69052d06 | |
624 | #define ARM_CPUID_PXA270 0x69054110 | |
625 | #define ARM_CPUID_PXA270_A0 0x69054110 | |
626 | #define ARM_CPUID_PXA270_A1 0x69054111 | |
627 | #define ARM_CPUID_PXA270_B0 0x69054112 | |
628 | #define ARM_CPUID_PXA270_B1 0x69054113 | |
629 | #define ARM_CPUID_PXA270_C0 0x69054114 | |
630 | #define ARM_CPUID_PXA270_C5 0x69054117 | |
631 | #define ARM_CPUID_ARM1136 0x4117b363 | |
827df9f3 | 632 | #define ARM_CPUID_ARM1136_R2 0x4107b362 |
7807eed9 | 633 | #define ARM_CPUID_ARM1176 0x410fb767 |
9ee6e8bb PB |
634 | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
635 | #define ARM_CPUID_CORTEXA8 0x410fc080 | |
10055562 | 636 | #define ARM_CPUID_CORTEXA9 0x410fc090 |
0b03bdfc | 637 | #define ARM_CPUID_CORTEXA15 0x412fc0f1 |
9ee6e8bb PB |
638 | #define ARM_CPUID_CORTEXM3 0x410fc231 |
639 | #define ARM_CPUID_ANY 0xffffffff | |
40f137e1 | 640 | |
b5ff1b31 | 641 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 642 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
643 | #else |
644 | /* The ARM MMU allows 1k pages. */ | |
645 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 646 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
647 | #define TARGET_PAGE_BITS 10 |
648 | #endif | |
9467d44c | 649 | |
52705890 RH |
650 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
651 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
652 | ||
ad37ad5b PM |
653 | static inline CPUARMState *cpu_init(const char *cpu_model) |
654 | { | |
655 | ARMCPU *cpu = cpu_arm_init(cpu_model); | |
656 | if (cpu) { | |
657 | return &cpu->env; | |
658 | } | |
659 | return NULL; | |
660 | } | |
661 | ||
9467d44c TS |
662 | #define cpu_exec cpu_arm_exec |
663 | #define cpu_gen_code cpu_arm_gen_code | |
664 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 665 | #define cpu_list arm_cpu_list |
9467d44c | 666 | |
2be27624 | 667 | #define CPU_SAVE_VERSION 6 |
9ee6e8bb | 668 | |
6ebbf390 JM |
669 | /* MMU modes definitions */ |
670 | #define MMU_MODE0_SUFFIX _kernel | |
671 | #define MMU_MODE1_SUFFIX _user | |
672 | #define MMU_USER_IDX 1 | |
0ecb72a5 | 673 | static inline int cpu_mmu_index (CPUARMState *env) |
6ebbf390 JM |
674 | { |
675 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; | |
676 | } | |
677 | ||
6e68e076 | 678 | #if defined(CONFIG_USER_ONLY) |
0ecb72a5 | 679 | static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) |
6e68e076 | 680 | { |
f8ed7070 | 681 | if (newsp) |
6e68e076 PB |
682 | env->regs[13] = newsp; |
683 | env->regs[0] = 0; | |
684 | } | |
685 | #endif | |
686 | ||
2c0262af | 687 | #include "cpu-all.h" |
622ed360 | 688 | |
a1705768 PM |
689 | /* Bit usage in the TB flags field: */ |
690 | #define ARM_TBFLAG_THUMB_SHIFT 0 | |
691 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
692 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
693 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
694 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
695 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
696 | #define ARM_TBFLAG_PRIV_SHIFT 6 | |
697 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) | |
698 | #define ARM_TBFLAG_VFPEN_SHIFT 7 | |
699 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
700 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
701 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
702 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
703 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
704 | /* Bits 31..17 are currently unused. */ | |
a1705768 PM |
705 | |
706 | /* some convenience accessor macros */ | |
707 | #define ARM_TBFLAG_THUMB(F) \ | |
708 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
709 | #define ARM_TBFLAG_VECLEN(F) \ | |
710 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
711 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
712 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
713 | #define ARM_TBFLAG_PRIV(F) \ | |
714 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) | |
715 | #define ARM_TBFLAG_VFPEN(F) \ | |
716 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
717 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
718 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
719 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
720 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
a1705768 | 721 | |
0ecb72a5 | 722 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
6b917547 AL |
723 | target_ulong *cs_base, int *flags) |
724 | { | |
05ed9a99 | 725 | int privmode; |
6b917547 AL |
726 | *pc = env->regs[15]; |
727 | *cs_base = 0; | |
a1705768 PM |
728 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
729 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
730 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
d8fd2954 PB |
731 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) |
732 | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); | |
05ed9a99 PM |
733 | if (arm_feature(env, ARM_FEATURE_M)) { |
734 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
735 | } else { | |
736 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; | |
737 | } | |
738 | if (privmode) { | |
a1705768 PM |
739 | *flags |= ARM_TBFLAG_PRIV_MASK; |
740 | } | |
741 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { | |
742 | *flags |= ARM_TBFLAG_VFPEN_MASK; | |
743 | } | |
6b917547 AL |
744 | } |
745 | ||
0ecb72a5 | 746 | static inline bool cpu_has_work(CPUARMState *env) |
f081c76c BS |
747 | { |
748 | return env->interrupt_request & | |
749 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
750 | } | |
751 | ||
752 | #include "exec-all.h" | |
753 | ||
0ecb72a5 | 754 | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
f081c76c BS |
755 | { |
756 | env->regs[15] = tb->pc; | |
757 | } | |
758 | ||
d8fd2954 PB |
759 | /* Load an instruction and return it in the standard little-endian order */ |
760 | static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap) | |
761 | { | |
762 | uint32_t insn = ldl_code(addr); | |
763 | if (do_swap) { | |
764 | return bswap32(insn); | |
765 | } | |
766 | return insn; | |
767 | } | |
768 | ||
769 | /* Ditto, for a halfword (Thumb) instruction */ | |
770 | static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap) | |
771 | { | |
772 | uint16_t insn = lduw_code(addr); | |
773 | if (do_swap) { | |
774 | return bswap16(insn); | |
775 | } | |
776 | return insn; | |
777 | } | |
778 | ||
2c0262af | 779 | #endif |