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2c0262af FB |
1 | /* |
2 | * ARM execution defines | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
8294eba1 | 20 | #include "config.h" |
2c0262af FB |
21 | #include "dyngen-exec.h" |
22 | ||
23 | register struct CPUARMState *env asm(AREG0); | |
24 | register uint32_t T0 asm(AREG1); | |
25 | register uint32_t T1 asm(AREG2); | |
26 | register uint32_t T2 asm(AREG3); | |
27 | ||
b7bcbe95 FB |
28 | /* TODO: Put these in FP regs on targets that have such things. */ |
29 | /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */ | |
30 | #define FT0s env->vfp.tmp0s | |
31 | #define FT1s env->vfp.tmp1s | |
32 | #define FT0d env->vfp.tmp0d | |
33 | #define FT1d env->vfp.tmp1d | |
34 | ||
18c9b560 AZ |
35 | #define M0 env->iwmmxt.val |
36 | ||
2c0262af FB |
37 | #include "cpu.h" |
38 | #include "exec-all.h" | |
39 | ||
0d1a29f9 FB |
40 | static inline void env_to_regs(void) |
41 | { | |
42 | } | |
43 | ||
44 | static inline void regs_to_env(void) | |
45 | { | |
46 | } | |
b8a9e8f1 FB |
47 | |
48 | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
49 | int is_user, int is_softmmu); | |
b7bcbe95 | 50 | |
bfed01fc TS |
51 | static inline int cpu_halted(CPUState *env) { |
52 | if (!env->halted) | |
53 | return 0; | |
54 | /* An interrupt wakes the CPU even if the I and F CPSR bits are | |
55 | set. We use EXITTB to silently wake CPU without causing an | |
56 | actual interrupt. */ | |
57 | if (env->interrupt_request & | |
58 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) { | |
59 | env->halted = 0; | |
60 | return 0; | |
61 | } | |
62 | return EXCP_HALTED; | |
63 | } | |
64 | ||
b5ff1b31 FB |
65 | #if !defined(CONFIG_USER_ONLY) |
66 | #include "softmmu_exec.h" | |
67 | #endif | |
68 | ||
b7bcbe95 FB |
69 | /* In op_helper.c */ |
70 | ||
71 | void cpu_lock(void); | |
72 | void cpu_unlock(void); | |
c1713132 AZ |
73 | void helper_set_cp(CPUState *, uint32_t, uint32_t); |
74 | uint32_t helper_get_cp(CPUState *, uint32_t); | |
b5ff1b31 FB |
75 | void helper_set_cp15(CPUState *, uint32_t, uint32_t); |
76 | uint32_t helper_get_cp15(CPUState *, uint32_t); | |
77 | ||
b7bcbe95 FB |
78 | void cpu_loop_exit(void); |
79 | ||
80 | void raise_exception(int); | |
81 | ||
82 | void do_vfp_abss(void); | |
83 | void do_vfp_absd(void); | |
84 | void do_vfp_negs(void); | |
85 | void do_vfp_negd(void); | |
86 | void do_vfp_sqrts(void); | |
87 | void do_vfp_sqrtd(void); | |
88 | void do_vfp_cmps(void); | |
89 | void do_vfp_cmpd(void); | |
90 | void do_vfp_cmpes(void); | |
91 | void do_vfp_cmped(void); | |
92 | void do_vfp_set_fpscr(void); | |
93 | void do_vfp_get_fpscr(void); | |
a9049a07 | 94 |