[qemu.git] / target-arm / machine.c

#include "hw/hw.h"
#include "hw/boards.h"

static bool vfp_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_VFP);
}

static const VMStateDescription vmstate_vfp = {
    .name = "cpu/vfp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
        VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
        /* TODO: Should use proper FPSCR access functions.  */
        VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
        VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool iwmmxt_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_IWMMXT);
}

static const VMStateDescription vmstate_iwmmxt = {
    .name = "cpu/iwmmxt",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
        VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
        VMSTATE_END_OF_LIST()
    }
};

static bool m_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_M);
}

const VMStateDescription vmstate_m = {
    .name = "cpu/m",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
        VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
        VMSTATE_UINT32(env.v7m.control, ARMCPU),
        VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
        VMSTATE_INT32(env.v7m.exception, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool thumb2ee_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_THUMB2EE);
}

static const VMStateDescription vmstate_thumb2ee = {
    .name = "cpu/thumb2ee",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.teecr, ARMCPU),
        VMSTATE_UINT32(env.teehbr, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    /* Avoid mode switch when restoring CPSR */
    env->uncached_cpsr = val & CPSR_M;
    cpsr_write(env, val, 0xffffffff);
    return 0;
}

static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    qemu_put_be32(f, cpsr_read(env));
}

static const VMStateInfo vmstate_cpsr = {
    .name = "cpsr",
    .get = get_cpsr,
    .put = put_cpsr,
};

const VMStateDescription vmstate_arm_cpu = {
    .name = "cpu",
    .version_id = 11,
    .minimum_version_id = 11,
    .minimum_version_id_old = 11,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
        {
            .name = "cpsr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_cpsr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_UINT32(env.spsr, ARMCPU),
        VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
        VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
        VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
        VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
        VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
        VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
        VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
        VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
        VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
        VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
        VMSTATE_UINT32(env.cp15.c3, ARMCPU),
        VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
        VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
        VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
        VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
        VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
        VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
        VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
        VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
        VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
        VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
        VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
        VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
        VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_ticonfig, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_i_max, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_i_min, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_threadid, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
        VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
        VMSTATE_UINT32(env.exclusive_addr, ARMCPU),
        VMSTATE_UINT32(env.exclusive_val, ARMCPU),
        VMSTATE_UINT32(env.exclusive_high, ARMCPU),
        VMSTATE_UINT64(env.features, ARMCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection[]) {
        {
            .vmsd = &vmstate_vfp,
            .needed = vfp_needed,
        } , {
            .vmsd = &vmstate_iwmmxt,
            .needed = iwmmxt_needed,
        } , {
            .vmsd = &vmstate_m,
            .needed = m_needed,
        } , {
            .vmsd = &vmstate_thumb2ee,
            .needed = thumb2ee_needed,
        } , {
            /* empty */
        }
    }
};
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3
3cc1d208	4	static bool vfp_needed(void *opaque)
8dd3dca3	5	{
3cc1d208 JQ	6	ARMCPU *cpu = opaque;
3cc1d208 JQ	7	CPUARMState *env = &cpu->env;
8dd3dca3	8
3cc1d208 JQ	9	return arm_feature(env, ARM_FEATURE_VFP);
3cc1d208 JQ	10	}
8dd3dca3	11
3cc1d208 JQ	12	static const VMStateDescription vmstate_vfp = {
	13	.name = "cpu/vfp",
	14	.version_id = 1,
	15	.minimum_version_id = 1,
	16	.minimum_version_id_old = 1,
	17	.fields = (VMStateField[]) {
	18	VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
	19	VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
8dd3dca3	20	/* TODO: Should use proper FPSCR access functions. */
3cc1d208 JQ	21	VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
	22	VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
	23	VMSTATE_END_OF_LIST()
8dd3dca3	24	}
3cc1d208	25	};
8dd3dca3	26
3cc1d208 JQ	27	static bool iwmmxt_needed(void *opaque)
	28	{
	29	ARMCPU *cpu = opaque;
	30	CPUARMState *env = &cpu->env;
8dd3dca3	31
3cc1d208 JQ	32	return arm_feature(env, ARM_FEATURE_IWMMXT);
3cc1d208 JQ	33	}
ffe47d33	34
3cc1d208 JQ	35	static const VMStateDescription vmstate_iwmmxt = {
	36	.name = "cpu/iwmmxt",
	37	.version_id = 1,
	38	.minimum_version_id = 1,
	39	.minimum_version_id_old = 1,
	40	.fields = (VMStateField[]) {
	41	VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
	42	VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
	43	VMSTATE_END_OF_LIST()
ffe47d33	44	}
3cc1d208 JQ	45	};
	46
	47	static bool m_needed(void *opaque)
	48	{
	49	ARMCPU *cpu = opaque;
	50	CPUARMState *env = &cpu->env;
	51
	52	return arm_feature(env, ARM_FEATURE_M);
8dd3dca3 AJ	53	}
8dd3dca3 AJ	54
3cc1d208 JQ	55	const VMStateDescription vmstate_m = {
	56	.name = "cpu/m",
	57	.version_id = 1,
	58	.minimum_version_id = 1,
	59	.minimum_version_id_old = 1,
	60	.fields = (VMStateField[]) {
	61	VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
	62	VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
	63	VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
	64	VMSTATE_UINT32(env.v7m.control, ARMCPU),
	65	VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
	66	VMSTATE_INT32(env.v7m.exception, ARMCPU),
	67	VMSTATE_END_OF_LIST()
	68	}
	69	};
	70
	71	static bool thumb2ee_needed(void *opaque)
8dd3dca3	72	{
3cc1d208 JQ	73	ARMCPU *cpu = opaque;
3cc1d208 JQ	74	CPUARMState *env = &cpu->env;
8dd3dca3	75
3cc1d208 JQ	76	return arm_feature(env, ARM_FEATURE_THUMB2EE);
3cc1d208 JQ	77	}
8dd3dca3	78
3cc1d208 JQ	79	static const VMStateDescription vmstate_thumb2ee = {
	80	.name = "cpu/thumb2ee",
	81	.version_id = 1,
	82	.minimum_version_id = 1,
	83	.minimum_version_id_old = 1,
	84	.fields = (VMStateField[]) {
	85	VMSTATE_UINT32(env.teecr, ARMCPU),
	86	VMSTATE_UINT32(env.teehbr, ARMCPU),
	87	VMSTATE_END_OF_LIST()
8dd3dca3	88	}
3cc1d208 JQ	89	};
	90
	91	static int get_cpsr(QEMUFile f, void opaque, size_t size)
	92	{
	93	ARMCPU *cpu = opaque;
	94	CPUARMState *env = &cpu->env;
	95	uint32_t val = qemu_get_be32(f);
	96
	97	/* Avoid mode switch when restoring CPSR */
ffe47d33 PB	98	env->uncached_cpsr = val & CPSR_M;
ffe47d33 PB	99	cpsr_write(env, val, 0xffffffff);
3cc1d208 JQ	100	return 0;
3cc1d208 JQ	101	}
8dd3dca3	102
3cc1d208 JQ	103	static void put_cpsr(QEMUFile f, void opaque, size_t size)
	104	{
	105	ARMCPU *cpu = opaque;
	106	CPUARMState *env = &cpu->env;
8dd3dca3	107
3cc1d208 JQ	108	qemu_put_be32(f, cpsr_read(env));
3cc1d208 JQ	109	}
8dd3dca3	110
3cc1d208 JQ	111	static const VMStateInfo vmstate_cpsr = {
	112	.name = "cpsr",
	113	.get = get_cpsr,
	114	.put = put_cpsr,
	115	};
	116
	117	const VMStateDescription vmstate_arm_cpu = {
	118	.name = "cpu",
602131e9 PM	119	.version_id = 11,
	120	.minimum_version_id = 11,
	121	.minimum_version_id_old = 11,
3cc1d208 JQ	122	.fields = (VMStateField[]) {
	123	VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
	124	{
	125	.name = "cpsr",
	126	.version_id = 0,
	127	.size = sizeof(uint32_t),
	128	.info = &vmstate_cpsr,
	129	.flags = VMS_SINGLE,
	130	.offset = 0,
	131	},
	132	VMSTATE_UINT32(env.spsr, ARMCPU),
	133	VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
	134	VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
	135	VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
	136	VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
	137	VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
	138	VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
	139	VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
	140	VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
	141	VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
	142	VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
	143	VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
	144	VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
	145	VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
	146	VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
	147	VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
	148	VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
	149	VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
	150	VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
	151	VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
	152	VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
	153	VMSTATE_UINT32(env.cp15.c3, ARMCPU),
	154	VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
	155	VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
	156	VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
	157	VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
	158	VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
	159	VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
	160	VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
	161	VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
	162	VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
	163	VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
	164	VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
	165	VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
	166	VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
	167	VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
	168	VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
	169	VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
	170	VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
	171	VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
	172	VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
	173	VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
	174	VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
602131e9 PM	175	VMSTATE_UINT32(env.cp15.c15_ticonfig, ARMCPU),
	176	VMSTATE_UINT32(env.cp15.c15_i_max, ARMCPU),
	177	VMSTATE_UINT32(env.cp15.c15_i_min, ARMCPU),
	178	VMSTATE_UINT32(env.cp15.c15_threadid, ARMCPU),
3cc1d208 JQ	179	VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
	180	VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
	181	VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
602131e9 PM	182	VMSTATE_UINT32(env.exclusive_addr, ARMCPU),
	183	VMSTATE_UINT32(env.exclusive_val, ARMCPU),
	184	VMSTATE_UINT32(env.exclusive_high, ARMCPU),
3cc1d208 JQ	185	VMSTATE_UINT64(env.features, ARMCPU),
	186	VMSTATE_END_OF_LIST()
	187	},
	188	.subsections = (VMStateSubsection[]) {
	189	{
	190	.vmsd = &vmstate_vfp,
	191	.needed = vfp_needed,
	192	} , {
	193	.vmsd = &vmstate_iwmmxt,
	194	.needed = iwmmxt_needed,
	195	} , {
	196	.vmsd = &vmstate_m,
	197	.needed = m_needed,
	198	} , {
	199	.vmsd = &vmstate_thumb2ee,
	200	.needed = thumb2ee_needed,
	201	} , {
	202	/* empty */
	203	}
ffe47d33	204	}
3cc1d208	205	};